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Merge branch 'wl12xx-next' into for-linville
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ti / wl18xx / main.c
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25 #include <linux/firmware.h>
26
27 #include "../wlcore/wlcore.h"
28 #include "../wlcore/debug.h"
29 #include "../wlcore/io.h"
30 #include "../wlcore/acx.h"
31 #include "../wlcore/tx.h"
32 #include "../wlcore/rx.h"
33 #include "../wlcore/boot.h"
34
35 #include "reg.h"
36 #include "conf.h"
37 #include "cmd.h"
38 #include "acx.h"
39 #include "tx.h"
40 #include "wl18xx.h"
41 #include "io.h"
42 #include "scan.h"
43 #include "event.h"
44 #include "debugfs.h"
45
46 #define WL18XX_RX_CHECKSUM_MASK 0x40
47
48 static char *ht_mode_param = NULL;
49 static char *board_type_param = NULL;
50 static bool checksum_param = false;
51 static int num_rx_desc_param = -1;
52
53 /* phy paramters */
54 static int dc2dc_param = -1;
55 static int n_antennas_2_param = -1;
56 static int n_antennas_5_param = -1;
57 static int low_band_component_param = -1;
58 static int low_band_component_type_param = -1;
59 static int high_band_component_param = -1;
60 static int high_band_component_type_param = -1;
61 static int pwr_limit_reference_11_abg_param = -1;
62
63 static const u8 wl18xx_rate_to_idx_2ghz[] = {
64 /* MCS rates are used only with 11n */
65 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
66 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
67 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
68 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
69 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
70 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
71 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
72 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
73 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
74 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
75 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
76 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
77 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
78 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
79 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
80 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
81
82 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
83 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
84 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
85 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
86
87 /* TI-specific rate */
88 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
89
90 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
91 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
92 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
93 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
94 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
95 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
96 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
97 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
98 };
99
100 static const u8 wl18xx_rate_to_idx_5ghz[] = {
101 /* MCS rates are used only with 11n */
102 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
103 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
104 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
105 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
106 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
107 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
108 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
109 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
110 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
111 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
112 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
113 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
114 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
115 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
116 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
117 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
118
119 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
120 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
121 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
122 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
123
124 /* TI-specific rate */
125 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
126
127 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
128 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
129 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
130 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
131 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
132 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
133 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
134 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
135 };
136
137 static const u8 *wl18xx_band_rate_to_idx[] = {
138 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
139 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
140 };
141
142 enum wl18xx_hw_rates {
143 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
144 WL18XX_CONF_HW_RXTX_RATE_MCS14,
145 WL18XX_CONF_HW_RXTX_RATE_MCS13,
146 WL18XX_CONF_HW_RXTX_RATE_MCS12,
147 WL18XX_CONF_HW_RXTX_RATE_MCS11,
148 WL18XX_CONF_HW_RXTX_RATE_MCS10,
149 WL18XX_CONF_HW_RXTX_RATE_MCS9,
150 WL18XX_CONF_HW_RXTX_RATE_MCS8,
151 WL18XX_CONF_HW_RXTX_RATE_MCS7,
152 WL18XX_CONF_HW_RXTX_RATE_MCS6,
153 WL18XX_CONF_HW_RXTX_RATE_MCS5,
154 WL18XX_CONF_HW_RXTX_RATE_MCS4,
155 WL18XX_CONF_HW_RXTX_RATE_MCS3,
156 WL18XX_CONF_HW_RXTX_RATE_MCS2,
157 WL18XX_CONF_HW_RXTX_RATE_MCS1,
158 WL18XX_CONF_HW_RXTX_RATE_MCS0,
159 WL18XX_CONF_HW_RXTX_RATE_54,
160 WL18XX_CONF_HW_RXTX_RATE_48,
161 WL18XX_CONF_HW_RXTX_RATE_36,
162 WL18XX_CONF_HW_RXTX_RATE_24,
163 WL18XX_CONF_HW_RXTX_RATE_22,
164 WL18XX_CONF_HW_RXTX_RATE_18,
165 WL18XX_CONF_HW_RXTX_RATE_12,
166 WL18XX_CONF_HW_RXTX_RATE_11,
167 WL18XX_CONF_HW_RXTX_RATE_9,
168 WL18XX_CONF_HW_RXTX_RATE_6,
169 WL18XX_CONF_HW_RXTX_RATE_5_5,
170 WL18XX_CONF_HW_RXTX_RATE_2,
171 WL18XX_CONF_HW_RXTX_RATE_1,
172 WL18XX_CONF_HW_RXTX_RATE_MAX,
173 };
174
175 static struct wlcore_conf wl18xx_conf = {
176 .sg = {
177 .params = {
178 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
179 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
180 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
181 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
182 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
183 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
184 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
185 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
186 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
187 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
188 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
189 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
190 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
191 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
192 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
193 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
194 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
195 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
196 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
197 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
198 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
199 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
200 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
201 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
202 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
203 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
204 /* active scan params */
205 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
206 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
207 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
208 /* passive scan params */
209 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
210 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
211 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
212 /* passive scan in dual antenna params */
213 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
214 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
215 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
216 /* general params */
217 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
218 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
219 [CONF_SG_BEACON_MISS_PERCENT] = 60,
220 [CONF_SG_DHCP_TIME] = 5000,
221 [CONF_SG_RXT] = 1200,
222 [CONF_SG_TXT] = 1000,
223 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
224 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
225 [CONF_SG_HV3_MAX_SERVED] = 6,
226 [CONF_SG_PS_POLL_TIMEOUT] = 10,
227 [CONF_SG_UPSD_TIMEOUT] = 10,
228 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
229 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
230 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
231 /* AP params */
232 [CONF_AP_BEACON_MISS_TX] = 3,
233 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
234 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
235 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
236 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
237 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
238 /* CTS Diluting params */
239 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
240 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
241 },
242 .state = CONF_SG_PROTECTIVE,
243 },
244 .rx = {
245 .rx_msdu_life_time = 512000,
246 .packet_detection_threshold = 0,
247 .ps_poll_timeout = 15,
248 .upsd_timeout = 15,
249 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
250 .rx_cca_threshold = 0,
251 .irq_blk_threshold = 0xFFFF,
252 .irq_pkt_threshold = 0,
253 .irq_timeout = 600,
254 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
255 },
256 .tx = {
257 .tx_energy_detection = 0,
258 .sta_rc_conf = {
259 .enabled_rates = 0,
260 .short_retry_limit = 10,
261 .long_retry_limit = 10,
262 .aflags = 0,
263 },
264 .ac_conf_count = 4,
265 .ac_conf = {
266 [CONF_TX_AC_BE] = {
267 .ac = CONF_TX_AC_BE,
268 .cw_min = 15,
269 .cw_max = 63,
270 .aifsn = 3,
271 .tx_op_limit = 0,
272 },
273 [CONF_TX_AC_BK] = {
274 .ac = CONF_TX_AC_BK,
275 .cw_min = 15,
276 .cw_max = 63,
277 .aifsn = 7,
278 .tx_op_limit = 0,
279 },
280 [CONF_TX_AC_VI] = {
281 .ac = CONF_TX_AC_VI,
282 .cw_min = 15,
283 .cw_max = 63,
284 .aifsn = CONF_TX_AIFS_PIFS,
285 .tx_op_limit = 3008,
286 },
287 [CONF_TX_AC_VO] = {
288 .ac = CONF_TX_AC_VO,
289 .cw_min = 15,
290 .cw_max = 63,
291 .aifsn = CONF_TX_AIFS_PIFS,
292 .tx_op_limit = 1504,
293 },
294 },
295 .max_tx_retries = 100,
296 .ap_aging_period = 300,
297 .tid_conf_count = 4,
298 .tid_conf = {
299 [CONF_TX_AC_BE] = {
300 .queue_id = CONF_TX_AC_BE,
301 .channel_type = CONF_CHANNEL_TYPE_EDCF,
302 .tsid = CONF_TX_AC_BE,
303 .ps_scheme = CONF_PS_SCHEME_LEGACY,
304 .ack_policy = CONF_ACK_POLICY_LEGACY,
305 .apsd_conf = {0, 0},
306 },
307 [CONF_TX_AC_BK] = {
308 .queue_id = CONF_TX_AC_BK,
309 .channel_type = CONF_CHANNEL_TYPE_EDCF,
310 .tsid = CONF_TX_AC_BK,
311 .ps_scheme = CONF_PS_SCHEME_LEGACY,
312 .ack_policy = CONF_ACK_POLICY_LEGACY,
313 .apsd_conf = {0, 0},
314 },
315 [CONF_TX_AC_VI] = {
316 .queue_id = CONF_TX_AC_VI,
317 .channel_type = CONF_CHANNEL_TYPE_EDCF,
318 .tsid = CONF_TX_AC_VI,
319 .ps_scheme = CONF_PS_SCHEME_LEGACY,
320 .ack_policy = CONF_ACK_POLICY_LEGACY,
321 .apsd_conf = {0, 0},
322 },
323 [CONF_TX_AC_VO] = {
324 .queue_id = CONF_TX_AC_VO,
325 .channel_type = CONF_CHANNEL_TYPE_EDCF,
326 .tsid = CONF_TX_AC_VO,
327 .ps_scheme = CONF_PS_SCHEME_LEGACY,
328 .ack_policy = CONF_ACK_POLICY_LEGACY,
329 .apsd_conf = {0, 0},
330 },
331 },
332 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
333 .tx_compl_timeout = 350,
334 .tx_compl_threshold = 10,
335 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
336 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
337 .tmpl_short_retry_limit = 10,
338 .tmpl_long_retry_limit = 10,
339 .tx_watchdog_timeout = 5000,
340 .slow_link_thold = 3,
341 .fast_link_thold = 30,
342 },
343 .conn = {
344 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
345 .listen_interval = 1,
346 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
347 .suspend_listen_interval = 3,
348 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
349 .bcn_filt_ie_count = 3,
350 .bcn_filt_ie = {
351 [0] = {
352 .ie = WLAN_EID_CHANNEL_SWITCH,
353 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
354 },
355 [1] = {
356 .ie = WLAN_EID_HT_OPERATION,
357 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
358 },
359 [2] = {
360 .ie = WLAN_EID_ERP_INFO,
361 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
362 },
363 },
364 .synch_fail_thold = 12,
365 .bss_lose_timeout = 400,
366 .beacon_rx_timeout = 10000,
367 .broadcast_timeout = 20000,
368 .rx_broadcast_in_ps = 1,
369 .ps_poll_threshold = 10,
370 .bet_enable = CONF_BET_MODE_ENABLE,
371 .bet_max_consecutive = 50,
372 .psm_entry_retries = 8,
373 .psm_exit_retries = 16,
374 .psm_entry_nullfunc_retries = 3,
375 .dynamic_ps_timeout = 1500,
376 .forced_ps = false,
377 .keep_alive_interval = 55000,
378 .max_listen_interval = 20,
379 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
380 },
381 .itrim = {
382 .enable = false,
383 .timeout = 50000,
384 },
385 .pm_config = {
386 .host_clk_settling_time = 5000,
387 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
388 },
389 .roam_trigger = {
390 .trigger_pacing = 1,
391 .avg_weight_rssi_beacon = 20,
392 .avg_weight_rssi_data = 10,
393 .avg_weight_snr_beacon = 20,
394 .avg_weight_snr_data = 10,
395 },
396 .scan = {
397 .min_dwell_time_active = 7500,
398 .max_dwell_time_active = 30000,
399 .min_dwell_time_active_long = 25000,
400 .max_dwell_time_active_long = 50000,
401 .dwell_time_passive = 100000,
402 .dwell_time_dfs = 150000,
403 .num_probe_reqs = 2,
404 .split_scan_timeout = 50000,
405 },
406 .sched_scan = {
407 /*
408 * Values are in TU/1000 but since sched scan FW command
409 * params are in TUs rounding up may occur.
410 */
411 .base_dwell_time = 7500,
412 .max_dwell_time_delta = 22500,
413 /* based on 250bits per probe @1Mbps */
414 .dwell_time_delta_per_probe = 2000,
415 /* based on 250bits per probe @6Mbps (plus a bit more) */
416 .dwell_time_delta_per_probe_5 = 350,
417 .dwell_time_passive = 100000,
418 .dwell_time_dfs = 150000,
419 .num_probe_reqs = 2,
420 .rssi_threshold = -90,
421 .snr_threshold = 0,
422 },
423 .ht = {
424 .rx_ba_win_size = 32,
425 .tx_ba_win_size = 64,
426 .inactivity_timeout = 10000,
427 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
428 },
429 .mem = {
430 .num_stations = 1,
431 .ssid_profiles = 1,
432 .rx_block_num = 40,
433 .tx_min_block_num = 40,
434 .dynamic_memory = 1,
435 .min_req_tx_blocks = 45,
436 .min_req_rx_blocks = 22,
437 .tx_min = 27,
438 },
439 .fm_coex = {
440 .enable = true,
441 .swallow_period = 5,
442 .n_divider_fref_set_1 = 0xff, /* default */
443 .n_divider_fref_set_2 = 12,
444 .m_divider_fref_set_1 = 0xffff,
445 .m_divider_fref_set_2 = 148, /* default */
446 .coex_pll_stabilization_time = 0xffffffff, /* default */
447 .ldo_stabilization_time = 0xffff, /* default */
448 .fm_disturbed_band_margin = 0xff, /* default */
449 .swallow_clk_diff = 0xff, /* default */
450 },
451 .rx_streaming = {
452 .duration = 150,
453 .queues = 0x1,
454 .interval = 20,
455 .always = 0,
456 },
457 .fwlog = {
458 .mode = WL12XX_FWLOG_ON_DEMAND,
459 .mem_blocks = 2,
460 .severity = 0,
461 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
462 .output = WL12XX_FWLOG_OUTPUT_HOST,
463 .threshold = 0,
464 },
465 .rate = {
466 .rate_retry_score = 32000,
467 .per_add = 8192,
468 .per_th1 = 2048,
469 .per_th2 = 4096,
470 .max_per = 8100,
471 .inverse_curiosity_factor = 5,
472 .tx_fail_low_th = 4,
473 .tx_fail_high_th = 10,
474 .per_alpha_shift = 4,
475 .per_add_shift = 13,
476 .per_beta1_shift = 10,
477 .per_beta2_shift = 8,
478 .rate_check_up = 2,
479 .rate_check_down = 12,
480 .rate_retry_policy = {
481 0x00, 0x00, 0x00, 0x00, 0x00,
482 0x00, 0x00, 0x00, 0x00, 0x00,
483 0x00, 0x00, 0x00,
484 },
485 },
486 .hangover = {
487 .recover_time = 0,
488 .hangover_period = 20,
489 .dynamic_mode = 1,
490 .early_termination_mode = 1,
491 .max_period = 20,
492 .min_period = 1,
493 .increase_delta = 1,
494 .decrease_delta = 2,
495 .quiet_time = 4,
496 .increase_time = 1,
497 .window_size = 16,
498 },
499 .recovery = {
500 .bug_on_recovery = 0,
501 .no_recovery = 0,
502 },
503 };
504
505 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
506 .ht = {
507 .mode = HT_MODE_DEFAULT,
508 },
509 .phy = {
510 .phy_standalone = 0x00,
511 .primary_clock_setting_time = 0x05,
512 .clock_valid_on_wake_up = 0x00,
513 .secondary_clock_setting_time = 0x05,
514 .board_type = BOARD_TYPE_HDK_18XX,
515 .auto_detect = 0x00,
516 .dedicated_fem = FEM_NONE,
517 .low_band_component = COMPONENT_3_WAY_SWITCH,
518 .low_band_component_type = 0x04,
519 .high_band_component = COMPONENT_2_WAY_SWITCH,
520 .high_band_component_type = 0x09,
521 .tcxo_ldo_voltage = 0x00,
522 .xtal_itrim_val = 0x04,
523 .srf_state = 0x00,
524 .io_configuration = 0x01,
525 .sdio_configuration = 0x00,
526 .settings = 0x00,
527 .enable_clpc = 0x00,
528 .enable_tx_low_pwr_on_siso_rdl = 0x00,
529 .rx_profile = 0x00,
530 .pwr_limit_reference_11_abg = 0x64,
531 .per_chan_pwr_limit_arr_11abg = {
532 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
533 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
534 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
535 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
536 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
537 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
538 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
539 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
540 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
541 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
542 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
543 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
544 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
545 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
546 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
547 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
548 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
549 .pwr_limit_reference_11p = 0x64,
550 .per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
551 0xff, 0xff, 0xff },
552 .psat = 0,
553 .low_power_val = 0x08,
554 .med_power_val = 0x12,
555 .high_power_val = 0x18,
556 .low_power_val_2nd = 0x05,
557 .med_power_val_2nd = 0x0a,
558 .high_power_val_2nd = 0x14,
559 .external_pa_dc2dc = 0,
560 .number_of_assembled_ant2_4 = 2,
561 .number_of_assembled_ant5 = 1,
562 .tx_rf_margin = 1,
563 },
564 };
565
566 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
567 [PART_TOP_PRCM_ELP_SOC] = {
568 .mem = { .start = 0x00A02000, .size = 0x00010000 },
569 .reg = { .start = 0x00807000, .size = 0x00005000 },
570 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
571 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
572 },
573 [PART_DOWN] = {
574 .mem = { .start = 0x00000000, .size = 0x00014000 },
575 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
576 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
577 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
578 },
579 [PART_BOOT] = {
580 .mem = { .start = 0x00700000, .size = 0x0000030c },
581 .reg = { .start = 0x00802000, .size = 0x00014578 },
582 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
583 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
584 },
585 [PART_WORK] = {
586 .mem = { .start = 0x00800000, .size = 0x000050FC },
587 .reg = { .start = 0x00B00404, .size = 0x00001000 },
588 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
589 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
590 },
591 [PART_PHY_INIT] = {
592 .mem = { .start = 0x80926000,
593 .size = sizeof(struct wl18xx_mac_and_phy_params) },
594 .reg = { .start = 0x00000000, .size = 0x00000000 },
595 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
596 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
597 },
598 };
599
600 static const int wl18xx_rtable[REG_TABLE_LEN] = {
601 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
602 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
603 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
604 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
605 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
606 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
607 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
608 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
609 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
610 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
611
612 /* data access memory addresses, used with partition translation */
613 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
614 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
615
616 /* raw data access memory addresses */
617 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
618 };
619
620 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
621 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
622 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
623 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
624 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
625 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
626 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
627 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
628 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
629 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
630 };
631
632 /* TODO: maybe move to a new header file? */
633 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-2.bin"
634
635 static int wl18xx_identify_chip(struct wl1271 *wl)
636 {
637 int ret = 0;
638
639 switch (wl->chip.id) {
640 case CHIP_ID_185x_PG20:
641 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
642 wl->chip.id);
643 wl->sr_fw_name = WL18XX_FW_NAME;
644 /* wl18xx uses the same firmware for PLT */
645 wl->plt_fw_name = WL18XX_FW_NAME;
646 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
647 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
648 WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
649 WLCORE_QUIRK_TX_PAD_LAST_FRAME |
650 WLCORE_QUIRK_REGDOMAIN_CONF |
651 WLCORE_QUIRK_DUAL_PROBE_TMPL;
652
653 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
654 WL18XX_IFTYPE_VER, WL18XX_MAJOR_VER,
655 WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
656 /* there's no separate multi-role FW */
657 0, 0, 0, 0);
658 break;
659 case CHIP_ID_185x_PG10:
660 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
661 wl->chip.id);
662 ret = -ENODEV;
663 goto out;
664
665 default:
666 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
667 ret = -ENODEV;
668 goto out;
669 }
670
671 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
672 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
673 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
674 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
675 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
676 out:
677 return ret;
678 }
679
680 static int wl18xx_set_clk(struct wl1271 *wl)
681 {
682 u16 clk_freq;
683 int ret;
684
685 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
686 if (ret < 0)
687 goto out;
688
689 /* TODO: PG2: apparently we need to read the clk type */
690
691 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
692 if (ret < 0)
693 goto out;
694
695 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
696 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
697 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
698 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
699
700 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
701 wl18xx_clk_table[clk_freq].n);
702 if (ret < 0)
703 goto out;
704
705 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
706 wl18xx_clk_table[clk_freq].m);
707 if (ret < 0)
708 goto out;
709
710 if (wl18xx_clk_table[clk_freq].swallow) {
711 /* first the 16 lower bits */
712 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
713 wl18xx_clk_table[clk_freq].q &
714 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
715 if (ret < 0)
716 goto out;
717
718 /* then the 16 higher bits, masked out */
719 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
720 (wl18xx_clk_table[clk_freq].q >> 16) &
721 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
722 if (ret < 0)
723 goto out;
724
725 /* first the 16 lower bits */
726 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
727 wl18xx_clk_table[clk_freq].p &
728 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
729 if (ret < 0)
730 goto out;
731
732 /* then the 16 higher bits, masked out */
733 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
734 (wl18xx_clk_table[clk_freq].p >> 16) &
735 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
736 } else {
737 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
738 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
739 }
740
741 out:
742 return ret;
743 }
744
745 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
746 {
747 int ret;
748
749 /* disable Rx/Tx */
750 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
751 if (ret < 0)
752 goto out;
753
754 /* disable auto calibration on start*/
755 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
756
757 out:
758 return ret;
759 }
760
761 static int wl18xx_pre_boot(struct wl1271 *wl)
762 {
763 int ret;
764
765 ret = wl18xx_set_clk(wl);
766 if (ret < 0)
767 goto out;
768
769 /* Continue the ELP wake up sequence */
770 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
771 if (ret < 0)
772 goto out;
773
774 udelay(500);
775
776 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
777 if (ret < 0)
778 goto out;
779
780 /* Disable interrupts */
781 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
782 if (ret < 0)
783 goto out;
784
785 ret = wl18xx_boot_soft_reset(wl);
786
787 out:
788 return ret;
789 }
790
791 static int wl18xx_pre_upload(struct wl1271 *wl)
792 {
793 u32 tmp;
794 int ret;
795
796 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
797 if (ret < 0)
798 goto out;
799
800 /* TODO: check if this is all needed */
801 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
802 if (ret < 0)
803 goto out;
804
805 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
806 if (ret < 0)
807 goto out;
808
809 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
810
811 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
812
813 out:
814 return ret;
815 }
816
817 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
818 {
819 struct wl18xx_priv *priv = wl->priv;
820 struct wl18xx_mac_and_phy_params *params;
821 int ret;
822
823 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
824 if (!params) {
825 ret = -ENOMEM;
826 goto out;
827 }
828
829 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
830 if (ret < 0)
831 goto out;
832
833 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
834 sizeof(*params), false);
835
836 out:
837 kfree(params);
838 return ret;
839 }
840
841 static int wl18xx_enable_interrupts(struct wl1271 *wl)
842 {
843 u32 event_mask, intr_mask;
844 int ret;
845
846 event_mask = WL18XX_ACX_EVENTS_VECTOR;
847 intr_mask = WL18XX_INTR_MASK;
848
849 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
850 if (ret < 0)
851 goto out;
852
853 wlcore_enable_interrupts(wl);
854
855 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
856 WL1271_ACX_INTR_ALL & ~intr_mask);
857 if (ret < 0)
858 goto disable_interrupts;
859
860 return ret;
861
862 disable_interrupts:
863 wlcore_disable_interrupts(wl);
864
865 out:
866 return ret;
867 }
868
869 static int wl18xx_boot(struct wl1271 *wl)
870 {
871 int ret;
872
873 ret = wl18xx_pre_boot(wl);
874 if (ret < 0)
875 goto out;
876
877 ret = wl18xx_pre_upload(wl);
878 if (ret < 0)
879 goto out;
880
881 ret = wlcore_boot_upload_firmware(wl);
882 if (ret < 0)
883 goto out;
884
885 ret = wl18xx_set_mac_and_phy(wl);
886 if (ret < 0)
887 goto out;
888
889 wl->event_mask = BSS_LOSS_EVENT_ID |
890 SCAN_COMPLETE_EVENT_ID |
891 RSSI_SNR_TRIGGER_0_EVENT_ID |
892 PERIODIC_SCAN_COMPLETE_EVENT_ID |
893 PERIODIC_SCAN_REPORT_EVENT_ID |
894 DUMMY_PACKET_EVENT_ID |
895 PEER_REMOVE_COMPLETE_EVENT_ID |
896 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
897 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
898 INACTIVE_STA_EVENT_ID |
899 MAX_TX_FAILURE_EVENT_ID |
900 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
901 DFS_CHANNELS_CONFIG_COMPLETE_EVENT;
902
903 ret = wlcore_boot_run_firmware(wl);
904 if (ret < 0)
905 goto out;
906
907 ret = wl18xx_enable_interrupts(wl);
908
909 out:
910 return ret;
911 }
912
913 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
914 void *buf, size_t len)
915 {
916 struct wl18xx_priv *priv = wl->priv;
917
918 memcpy(priv->cmd_buf, buf, len);
919 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
920
921 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
922 WL18XX_CMD_MAX_SIZE, false);
923 }
924
925 static int wl18xx_ack_event(struct wl1271 *wl)
926 {
927 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
928 WL18XX_INTR_TRIG_EVENT_ACK);
929 }
930
931 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
932 {
933 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
934 return (len + blk_size - 1) / blk_size + spare_blks;
935 }
936
937 static void
938 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
939 u32 blks, u32 spare_blks)
940 {
941 desc->wl18xx_mem.total_mem_blocks = blks;
942 }
943
944 static void
945 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
946 struct sk_buff *skb)
947 {
948 desc->length = cpu_to_le16(skb->len);
949
950 /* if only the last frame is to be padded, we unset this bit on Tx */
951 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
952 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
953 else
954 desc->wl18xx_mem.ctrl = 0;
955
956 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
957 "len: %d life: %d mem: %d", desc->hlid,
958 le16_to_cpu(desc->length),
959 le16_to_cpu(desc->life_time),
960 desc->wl18xx_mem.total_mem_blocks);
961 }
962
963 static enum wl_rx_buf_align
964 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
965 {
966 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
967 return WLCORE_RX_BUF_PADDED;
968
969 return WLCORE_RX_BUF_ALIGNED;
970 }
971
972 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
973 u32 data_len)
974 {
975 struct wl1271_rx_descriptor *desc = rx_data;
976
977 /* invalid packet */
978 if (data_len < sizeof(*desc))
979 return 0;
980
981 return data_len - sizeof(*desc);
982 }
983
984 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
985 {
986 wl18xx_tx_immediate_complete(wl);
987 }
988
989 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
990 {
991 int ret;
992 u32 sdio_align_size = 0;
993 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
994 HOST_IF_CFG_ADD_RX_ALIGNMENT;
995
996 /* Enable Tx SDIO padding */
997 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
998 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
999 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1000 }
1001
1002 /* Enable Rx SDIO padding */
1003 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1004 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1005 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1006 }
1007
1008 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1009 sdio_align_size, extra_mem_blk,
1010 WL18XX_HOST_IF_LEN_SIZE_FIELD);
1011 if (ret < 0)
1012 return ret;
1013
1014 return 0;
1015 }
1016
1017 static int wl18xx_hw_init(struct wl1271 *wl)
1018 {
1019 int ret;
1020 struct wl18xx_priv *priv = wl->priv;
1021
1022 /* (re)init private structures. Relevant on recovery as well. */
1023 priv->last_fw_rls_idx = 0;
1024 priv->extra_spare_key_count = 0;
1025
1026 /* set the default amount of spare blocks in the bitmap */
1027 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1028 if (ret < 0)
1029 return ret;
1030
1031 if (checksum_param) {
1032 ret = wl18xx_acx_set_checksum_state(wl);
1033 if (ret != 0)
1034 return ret;
1035 }
1036
1037 return ret;
1038 }
1039
1040 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1041 struct wl1271_tx_hw_descr *desc,
1042 struct sk_buff *skb)
1043 {
1044 u32 ip_hdr_offset;
1045 struct iphdr *ip_hdr;
1046
1047 if (!checksum_param) {
1048 desc->wl18xx_checksum_data = 0;
1049 return;
1050 }
1051
1052 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1053 desc->wl18xx_checksum_data = 0;
1054 return;
1055 }
1056
1057 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1058 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1059 desc->wl18xx_checksum_data = 0;
1060 return;
1061 }
1062
1063 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1064
1065 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1066 ip_hdr = (void *)skb_network_header(skb);
1067 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1068 }
1069
1070 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1071 struct wl1271_rx_descriptor *desc,
1072 struct sk_buff *skb)
1073 {
1074 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1075 skb->ip_summed = CHECKSUM_UNNECESSARY;
1076 }
1077
1078 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1079 {
1080 struct wl18xx_priv *priv = wl->priv;
1081
1082 /* only support MIMO with multiple antennas, and when SISO
1083 * is not forced through config
1084 */
1085 return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) &&
1086 (priv->conf.ht.mode != HT_MODE_WIDE) &&
1087 (priv->conf.ht.mode != HT_MODE_SISO20);
1088 }
1089
1090 /*
1091 * TODO: instead of having these two functions to get the rate mask,
1092 * we should modify the wlvif->rate_set instead
1093 */
1094 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1095 struct wl12xx_vif *wlvif)
1096 {
1097 u32 hw_rate_set = wlvif->rate_set;
1098
1099 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1100 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1101 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1102 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1103
1104 /* we don't support MIMO in wide-channel mode */
1105 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1106 } else if (wl18xx_is_mimo_supported(wl)) {
1107 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1108 hw_rate_set |= CONF_TX_MIMO_RATES;
1109 }
1110
1111 return hw_rate_set;
1112 }
1113
1114 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1115 struct wl12xx_vif *wlvif)
1116 {
1117 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1118 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1119 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1120
1121 /* sanity check - we don't support this */
1122 if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ))
1123 return 0;
1124
1125 return CONF_TX_RATE_USE_WIDE_CHAN;
1126 } else if (wl18xx_is_mimo_supported(wl) &&
1127 wlvif->band == IEEE80211_BAND_2GHZ) {
1128 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1129 /*
1130 * we don't care about HT channel here - if a peer doesn't
1131 * support MIMO, we won't enable it in its rates
1132 */
1133 return CONF_TX_MIMO_RATES;
1134 } else {
1135 return 0;
1136 }
1137 }
1138
1139 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1140 {
1141 u32 fuse;
1142 int ret;
1143
1144 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1145 if (ret < 0)
1146 goto out;
1147
1148 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1149 if (ret < 0)
1150 goto out;
1151
1152 if (ver)
1153 *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1154
1155 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1156
1157 out:
1158 return ret;
1159 }
1160
1161 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1162 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1163 {
1164 struct wl18xx_priv *priv = wl->priv;
1165 struct wlcore_conf_file *conf_file;
1166 const struct firmware *fw;
1167 int ret;
1168
1169 ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1170 if (ret < 0) {
1171 wl1271_error("could not get configuration binary %s: %d",
1172 WL18XX_CONF_FILE_NAME, ret);
1173 goto out_fallback;
1174 }
1175
1176 if (fw->size != WL18XX_CONF_SIZE) {
1177 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1178 WL18XX_CONF_SIZE, fw->size);
1179 ret = -EINVAL;
1180 goto out;
1181 }
1182
1183 conf_file = (struct wlcore_conf_file *) fw->data;
1184
1185 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1186 wl1271_error("configuration binary file magic number mismatch, "
1187 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1188 conf_file->header.magic);
1189 ret = -EINVAL;
1190 goto out;
1191 }
1192
1193 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1194 wl1271_error("configuration binary file version not supported, "
1195 "expected 0x%08x got 0x%08x",
1196 WL18XX_CONF_VERSION, conf_file->header.version);
1197 ret = -EINVAL;
1198 goto out;
1199 }
1200
1201 memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1202 memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1203
1204 goto out;
1205
1206 out_fallback:
1207 wl1271_warning("falling back to default config");
1208
1209 /* apply driver default configuration */
1210 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1211 /* apply default private configuration */
1212 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1213
1214 /* For now we just fallback */
1215 return 0;
1216
1217 out:
1218 release_firmware(fw);
1219 return ret;
1220 }
1221
1222 static int wl18xx_plt_init(struct wl1271 *wl)
1223 {
1224 int ret;
1225
1226 /* calibrator based auto/fem detect not supported for 18xx */
1227 if (wl->plt_mode == PLT_FEM_DETECT) {
1228 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1229 return -EINVAL;
1230 }
1231
1232 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1233 if (ret < 0)
1234 return ret;
1235
1236 return wl->ops->boot(wl);
1237 }
1238
1239 static int wl18xx_get_mac(struct wl1271 *wl)
1240 {
1241 u32 mac1, mac2;
1242 int ret;
1243
1244 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1245 if (ret < 0)
1246 goto out;
1247
1248 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1249 if (ret < 0)
1250 goto out;
1251
1252 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1253 if (ret < 0)
1254 goto out;
1255
1256 /* these are the two parts of the BD_ADDR */
1257 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1258 ((mac1 & 0xff000000) >> 24);
1259 wl->fuse_nic_addr = (mac1 & 0xffffff);
1260
1261 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1262
1263 out:
1264 return ret;
1265 }
1266
1267 static int wl18xx_handle_static_data(struct wl1271 *wl,
1268 struct wl1271_static_data *static_data)
1269 {
1270 struct wl18xx_static_data_priv *static_data_priv =
1271 (struct wl18xx_static_data_priv *) static_data->priv;
1272
1273 strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1274 sizeof(wl->chip.phy_fw_ver_str));
1275
1276 /* make sure the string is NULL-terminated */
1277 wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1278
1279 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1280
1281 return 0;
1282 }
1283
1284 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1285 {
1286 struct wl18xx_priv *priv = wl->priv;
1287
1288 /* If we have keys requiring extra spare, indulge them */
1289 if (priv->extra_spare_key_count)
1290 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1291
1292 return WL18XX_TX_HW_BLOCK_SPARE;
1293 }
1294
1295 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1296 struct ieee80211_vif *vif,
1297 struct ieee80211_sta *sta,
1298 struct ieee80211_key_conf *key_conf)
1299 {
1300 struct wl18xx_priv *priv = wl->priv;
1301 bool change_spare = false, special_enc;
1302 int ret;
1303
1304 wl1271_debug(DEBUG_CRYPT, "extra spare keys before: %d",
1305 priv->extra_spare_key_count);
1306
1307 special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1308 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP;
1309
1310 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1311 if (ret < 0)
1312 goto out;
1313
1314 /*
1315 * when adding the first or removing the last GEM/TKIP key,
1316 * we have to adjust the number of spare blocks.
1317 */
1318 if (special_enc) {
1319 if (cmd == SET_KEY) {
1320 /* first key */
1321 change_spare = (priv->extra_spare_key_count == 0);
1322 priv->extra_spare_key_count++;
1323 } else if (cmd == DISABLE_KEY) {
1324 /* last key */
1325 change_spare = (priv->extra_spare_key_count == 1);
1326 priv->extra_spare_key_count--;
1327 }
1328 }
1329
1330 wl1271_debug(DEBUG_CRYPT, "extra spare keys after: %d",
1331 priv->extra_spare_key_count);
1332
1333 if (!change_spare)
1334 goto out;
1335
1336 /* key is now set, change the spare blocks */
1337 if (priv->extra_spare_key_count)
1338 ret = wl18xx_set_host_cfg_bitmap(wl,
1339 WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1340 else
1341 ret = wl18xx_set_host_cfg_bitmap(wl,
1342 WL18XX_TX_HW_BLOCK_SPARE);
1343
1344 out:
1345 return ret;
1346 }
1347
1348 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1349 u32 buf_offset, u32 last_len)
1350 {
1351 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1352 struct wl1271_tx_hw_descr *last_desc;
1353
1354 /* get the last TX HW descriptor written to the aggr buf */
1355 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1356 buf_offset - last_len);
1357
1358 /* the last frame is padded up to an SDIO block */
1359 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1360 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1361 }
1362
1363 /* no modifications */
1364 return buf_offset;
1365 }
1366
1367 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1368 struct wl12xx_vif *wlvif,
1369 struct ieee80211_sta *sta,
1370 u32 changed)
1371 {
1372 bool wide = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1373
1374 wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1375
1376 if (!(changed & IEEE80211_RC_BW_CHANGED))
1377 return;
1378
1379 mutex_lock(&wl->mutex);
1380
1381 /* sanity */
1382 if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
1383 goto out;
1384
1385 /* ignore the change before association */
1386 if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
1387 goto out;
1388
1389 /*
1390 * If we started out as wide, we can change the operation mode. If we
1391 * thought this was a 20mhz AP, we have to reconnect
1392 */
1393 if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1394 wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1395 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1396 else
1397 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
1398
1399 out:
1400 mutex_unlock(&wl->mutex);
1401 }
1402
1403 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1404 struct ieee80211_sta_ht_cap *ht_cap,
1405 bool allow_ht_operation,
1406 u32 rate_set, u8 hlid)
1407 {
1408 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1409 rate_set, hlid);
1410 }
1411
1412 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1413 struct wl1271_link *lnk)
1414 {
1415 u8 thold;
1416 struct wl18xx_fw_status_priv *status_priv =
1417 (struct wl18xx_fw_status_priv *)wl->fw_status_2->priv;
1418 u32 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1419
1420 /* suspended links are never high priority */
1421 if (test_bit(hlid, (unsigned long *)&suspend_bitmap))
1422 return false;
1423
1424 /* the priority thresholds are taken from FW */
1425 if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map) &&
1426 !test_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map))
1427 thold = status_priv->tx_fast_link_prio_threshold;
1428 else
1429 thold = status_priv->tx_slow_link_prio_threshold;
1430
1431 return lnk->allocated_pkts < thold;
1432 }
1433
1434 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1435 struct wl1271_link *lnk)
1436 {
1437 u8 thold;
1438 struct wl18xx_fw_status_priv *status_priv =
1439 (struct wl18xx_fw_status_priv *)wl->fw_status_2->priv;
1440 u32 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1441
1442 if (test_bit(hlid, (unsigned long *)&suspend_bitmap))
1443 thold = status_priv->tx_suspend_threshold;
1444 else if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map) &&
1445 !test_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map))
1446 thold = status_priv->tx_fast_stop_threshold;
1447 else
1448 thold = status_priv->tx_slow_stop_threshold;
1449
1450 return lnk->allocated_pkts < thold;
1451 }
1452
1453 static int wl18xx_setup(struct wl1271 *wl);
1454
1455 static struct wlcore_ops wl18xx_ops = {
1456 .setup = wl18xx_setup,
1457 .identify_chip = wl18xx_identify_chip,
1458 .boot = wl18xx_boot,
1459 .plt_init = wl18xx_plt_init,
1460 .trigger_cmd = wl18xx_trigger_cmd,
1461 .ack_event = wl18xx_ack_event,
1462 .wait_for_event = wl18xx_wait_for_event,
1463 .process_mailbox_events = wl18xx_process_mailbox_events,
1464 .calc_tx_blocks = wl18xx_calc_tx_blocks,
1465 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1466 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1467 .get_rx_buf_align = wl18xx_get_rx_buf_align,
1468 .get_rx_packet_len = wl18xx_get_rx_packet_len,
1469 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1470 .tx_delayed_compl = NULL,
1471 .hw_init = wl18xx_hw_init,
1472 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1473 .get_pg_ver = wl18xx_get_pg_ver,
1474 .set_rx_csum = wl18xx_set_rx_csum,
1475 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1476 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1477 .get_mac = wl18xx_get_mac,
1478 .debugfs_init = wl18xx_debugfs_add_files,
1479 .scan_start = wl18xx_scan_start,
1480 .scan_stop = wl18xx_scan_stop,
1481 .sched_scan_start = wl18xx_sched_scan_start,
1482 .sched_scan_stop = wl18xx_scan_sched_scan_stop,
1483 .handle_static_data = wl18xx_handle_static_data,
1484 .get_spare_blocks = wl18xx_get_spare_blocks,
1485 .set_key = wl18xx_set_key,
1486 .channel_switch = wl18xx_cmd_channel_switch,
1487 .pre_pkt_send = wl18xx_pre_pkt_send,
1488 .sta_rc_update = wl18xx_sta_rc_update,
1489 .set_peer_cap = wl18xx_set_peer_cap,
1490 .lnk_high_prio = wl18xx_lnk_high_prio,
1491 .lnk_low_prio = wl18xx_lnk_low_prio,
1492 };
1493
1494 /* HT cap appropriate for wide channels in 2Ghz */
1495 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1496 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1497 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1498 IEEE80211_HT_CAP_GRN_FLD,
1499 .ht_supported = true,
1500 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1501 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1502 .mcs = {
1503 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1504 .rx_highest = cpu_to_le16(150),
1505 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1506 },
1507 };
1508
1509 /* HT cap appropriate for wide channels in 5Ghz */
1510 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1511 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1512 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1513 IEEE80211_HT_CAP_GRN_FLD,
1514 .ht_supported = true,
1515 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1516 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1517 .mcs = {
1518 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1519 .rx_highest = cpu_to_le16(150),
1520 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1521 },
1522 };
1523
1524 /* HT cap appropriate for SISO 20 */
1525 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1526 .cap = IEEE80211_HT_CAP_SGI_20 |
1527 IEEE80211_HT_CAP_GRN_FLD,
1528 .ht_supported = true,
1529 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1530 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1531 .mcs = {
1532 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1533 .rx_highest = cpu_to_le16(72),
1534 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1535 },
1536 };
1537
1538 /* HT cap appropriate for MIMO rates in 20mhz channel */
1539 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1540 .cap = IEEE80211_HT_CAP_SGI_20 |
1541 IEEE80211_HT_CAP_GRN_FLD,
1542 .ht_supported = true,
1543 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1544 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1545 .mcs = {
1546 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1547 .rx_highest = cpu_to_le16(144),
1548 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1549 },
1550 };
1551
1552 static int wl18xx_setup(struct wl1271 *wl)
1553 {
1554 struct wl18xx_priv *priv = wl->priv;
1555 int ret;
1556
1557 wl->rtable = wl18xx_rtable;
1558 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1559 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
1560 wl->num_channels = 2;
1561 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1562 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1563 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1564 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1565 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1566 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1567 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1568
1569 if (num_rx_desc_param != -1)
1570 wl->num_rx_desc = num_rx_desc_param;
1571
1572 ret = wl18xx_conf_init(wl, wl->dev);
1573 if (ret < 0)
1574 return ret;
1575
1576 /* If the module param is set, update it in conf */
1577 if (board_type_param) {
1578 if (!strcmp(board_type_param, "fpga")) {
1579 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1580 } else if (!strcmp(board_type_param, "hdk")) {
1581 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1582 } else if (!strcmp(board_type_param, "dvp")) {
1583 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1584 } else if (!strcmp(board_type_param, "evb")) {
1585 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1586 } else if (!strcmp(board_type_param, "com8")) {
1587 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1588 } else {
1589 wl1271_error("invalid board type '%s'",
1590 board_type_param);
1591 return -EINVAL;
1592 }
1593 }
1594
1595 if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1596 wl1271_error("invalid board type '%d'",
1597 priv->conf.phy.board_type);
1598 return -EINVAL;
1599 }
1600
1601 if (low_band_component_param != -1)
1602 priv->conf.phy.low_band_component = low_band_component_param;
1603 if (low_band_component_type_param != -1)
1604 priv->conf.phy.low_band_component_type =
1605 low_band_component_type_param;
1606 if (high_band_component_param != -1)
1607 priv->conf.phy.high_band_component = high_band_component_param;
1608 if (high_band_component_type_param != -1)
1609 priv->conf.phy.high_band_component_type =
1610 high_band_component_type_param;
1611 if (pwr_limit_reference_11_abg_param != -1)
1612 priv->conf.phy.pwr_limit_reference_11_abg =
1613 pwr_limit_reference_11_abg_param;
1614 if (n_antennas_2_param != -1)
1615 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1616 if (n_antennas_5_param != -1)
1617 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1618 if (dc2dc_param != -1)
1619 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1620
1621 if (ht_mode_param) {
1622 if (!strcmp(ht_mode_param, "default"))
1623 priv->conf.ht.mode = HT_MODE_DEFAULT;
1624 else if (!strcmp(ht_mode_param, "wide"))
1625 priv->conf.ht.mode = HT_MODE_WIDE;
1626 else if (!strcmp(ht_mode_param, "siso20"))
1627 priv->conf.ht.mode = HT_MODE_SISO20;
1628 else {
1629 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1630 return -EINVAL;
1631 }
1632 }
1633
1634 if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
1635 /*
1636 * Only support mimo with multiple antennas. Fall back to
1637 * siso40.
1638 */
1639 if (wl18xx_is_mimo_supported(wl))
1640 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1641 &wl18xx_mimo_ht_cap_2ghz);
1642 else
1643 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1644 &wl18xx_siso40_ht_cap_2ghz);
1645
1646 /* 5Ghz is always wide */
1647 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1648 &wl18xx_siso40_ht_cap_5ghz);
1649 } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
1650 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1651 &wl18xx_siso40_ht_cap_2ghz);
1652 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1653 &wl18xx_siso40_ht_cap_5ghz);
1654 } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
1655 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1656 &wl18xx_siso20_ht_cap);
1657 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1658 &wl18xx_siso20_ht_cap);
1659 }
1660
1661 if (!checksum_param) {
1662 wl18xx_ops.set_rx_csum = NULL;
1663 wl18xx_ops.init_vif = NULL;
1664 }
1665
1666 /* Enable 11a Band only if we have 5G antennas */
1667 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1668
1669 return 0;
1670 }
1671
1672 static int wl18xx_probe(struct platform_device *pdev)
1673 {
1674 struct wl1271 *wl;
1675 struct ieee80211_hw *hw;
1676 int ret;
1677
1678 hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
1679 WL18XX_AGGR_BUFFER_SIZE,
1680 sizeof(struct wl18xx_event_mailbox));
1681 if (IS_ERR(hw)) {
1682 wl1271_error("can't allocate hw");
1683 ret = PTR_ERR(hw);
1684 goto out;
1685 }
1686
1687 wl = hw->priv;
1688 wl->ops = &wl18xx_ops;
1689 wl->ptable = wl18xx_ptable;
1690 ret = wlcore_probe(wl, pdev);
1691 if (ret)
1692 goto out_free;
1693
1694 return ret;
1695
1696 out_free:
1697 wlcore_free_hw(wl);
1698 out:
1699 return ret;
1700 }
1701
1702 static const struct platform_device_id wl18xx_id_table[] = {
1703 { "wl18xx", 0 },
1704 { } /* Terminating Entry */
1705 };
1706 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1707
1708 static struct platform_driver wl18xx_driver = {
1709 .probe = wl18xx_probe,
1710 .remove = wlcore_remove,
1711 .id_table = wl18xx_id_table,
1712 .driver = {
1713 .name = "wl18xx_driver",
1714 .owner = THIS_MODULE,
1715 }
1716 };
1717
1718 module_platform_driver(wl18xx_driver);
1719 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1720 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1721
1722 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1723 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1724 "dvp");
1725
1726 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1727 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1728
1729 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1730 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1731
1732 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1733 MODULE_PARM_DESC(n_antennas_2,
1734 "Number of installed 2.4GHz antennas: 1 (default) or 2");
1735
1736 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1737 MODULE_PARM_DESC(n_antennas_5,
1738 "Number of installed 5GHz antennas: 1 (default) or 2");
1739
1740 module_param_named(low_band_component, low_band_component_param, int,
1741 S_IRUSR);
1742 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1743 "(default is 0x01)");
1744
1745 module_param_named(low_band_component_type, low_band_component_type_param,
1746 int, S_IRUSR);
1747 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1748 "(default is 0x05 or 0x06 depending on the board_type)");
1749
1750 module_param_named(high_band_component, high_band_component_param, int,
1751 S_IRUSR);
1752 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1753 "(default is 0x01)");
1754
1755 module_param_named(high_band_component_type, high_band_component_type_param,
1756 int, S_IRUSR);
1757 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1758 "(default is 0x09)");
1759
1760 module_param_named(pwr_limit_reference_11_abg,
1761 pwr_limit_reference_11_abg_param, int, S_IRUSR);
1762 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1763 "(default is 0xc8)");
1764
1765 module_param_named(num_rx_desc,
1766 num_rx_desc_param, int, S_IRUSR);
1767 MODULE_PARM_DESC(num_rx_desc_param,
1768 "Number of Rx descriptors: u8 (default is 32)");
1769
1770 MODULE_LICENSE("GPL v2");
1771 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1772 MODULE_FIRMWARE(WL18XX_FW_NAME);
kernel source for telekom puls (alcatel/mediatek)