projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rtl818x / rtl8180_dev.c
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <net/mac80211.h>
25
26 #include "rtl8180.h"
27 #include "rtl8180_rtl8225.h"
28 #include "rtl8180_sa2400.h"
29 #include "rtl8180_max2820.h"
30 #include "rtl8180_grf5101.h"
31
32 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
33 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
34 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
35 MODULE_LICENSE("GPL");
36
37 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
38 /* rtl8185 */
39 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
40 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
42
43 /* rtl8180 */
44 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
45 { PCI_DEVICE(0x1799, 0x6001) },
46 { PCI_DEVICE(0x1799, 0x6020) },
47 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
48 { }
49 };
50
51 MODULE_DEVICE_TABLE(pci, rtl8180_table);
52
53 static const struct ieee80211_rate rtl818x_rates[] = {
54 { .bitrate = 10, .hw_value = 0, },
55 { .bitrate = 20, .hw_value = 1, },
56 { .bitrate = 55, .hw_value = 2, },
57 { .bitrate = 110, .hw_value = 3, },
58 { .bitrate = 60, .hw_value = 4, },
59 { .bitrate = 90, .hw_value = 5, },
60 { .bitrate = 120, .hw_value = 6, },
61 { .bitrate = 180, .hw_value = 7, },
62 { .bitrate = 240, .hw_value = 8, },
63 { .bitrate = 360, .hw_value = 9, },
64 { .bitrate = 480, .hw_value = 10, },
65 { .bitrate = 540, .hw_value = 11, },
66 };
67
68 static const struct ieee80211_channel rtl818x_channels[] = {
69 { .center_freq = 2412 },
70 { .center_freq = 2417 },
71 { .center_freq = 2422 },
72 { .center_freq = 2427 },
73 { .center_freq = 2432 },
74 { .center_freq = 2437 },
75 { .center_freq = 2442 },
76 { .center_freq = 2447 },
77 { .center_freq = 2452 },
78 { .center_freq = 2457 },
79 { .center_freq = 2462 },
80 { .center_freq = 2467 },
81 { .center_freq = 2472 },
82 { .center_freq = 2484 },
83 };
84
85
86 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
87 {
88 struct rtl8180_priv *priv = dev->priv;
89 int i = 10;
90 u32 buf;
91
92 buf = (data << 8) | addr;
93
94 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
95 while (i--) {
96 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
97 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
98 return;
99 }
100 }
101
102 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
103 {
104 struct rtl8180_priv *priv = dev->priv;
105 unsigned int count = 32;
106
107 while (count--) {
108 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
109 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
110 u32 flags = le32_to_cpu(entry->flags);
111
112 if (flags & RTL818X_RX_DESC_FLAG_OWN)
113 return;
114
115 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
116 RTL818X_RX_DESC_FLAG_FOF |
117 RTL818X_RX_DESC_FLAG_RX_ERR)))
118 goto done;
119 else {
120 u32 flags2 = le32_to_cpu(entry->flags2);
121 struct ieee80211_rx_status rx_status = {0};
122 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
123
124 if (unlikely(!new_skb))
125 goto done;
126
127 pci_unmap_single(priv->pdev,
128 *((dma_addr_t *)skb->cb),
129 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
130 skb_put(skb, flags & 0xFFF);
131
132 rx_status.antenna = (flags2 >> 15) & 1;
133 /* TODO: improve signal/rssi reporting */
134 rx_status.signal = (flags2 >> 8) & 0x7F;
135 /* XXX: is this correct? */
136 rx_status.rate_idx = (flags >> 20) & 0xF;
137 rx_status.freq = dev->conf.channel->center_freq;
138 rx_status.band = dev->conf.channel->band;
139 rx_status.mactime = le64_to_cpu(entry->tsft);
140 rx_status.flag |= RX_FLAG_TSFT;
141 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
142 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
143
144 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
145 ieee80211_rx_irqsafe(dev, skb);
146
147 skb = new_skb;
148 priv->rx_buf[priv->rx_idx] = skb;
149 *((dma_addr_t *) skb->cb) =
150 pci_map_single(priv->pdev, skb_tail_pointer(skb),
151 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
152 }
153
154 done:
155 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
156 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
157 MAX_RX_SIZE);
158 if (priv->rx_idx == 31)
159 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
160 priv->rx_idx = (priv->rx_idx + 1) % 32;
161 }
162 }
163
164 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
165 {
166 struct rtl8180_priv *priv = dev->priv;
167 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
168
169 while (skb_queue_len(&ring->queue)) {
170 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
171 struct sk_buff *skb;
172 struct ieee80211_tx_info *info;
173 u32 flags = le32_to_cpu(entry->flags);
174
175 if (flags & RTL818X_TX_DESC_FLAG_OWN)
176 return;
177
178 ring->idx = (ring->idx + 1) % ring->entries;
179 skb = __skb_dequeue(&ring->queue);
180 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
181 skb->len, PCI_DMA_TODEVICE);
182
183 info = IEEE80211_SKB_CB(skb);
184 ieee80211_tx_info_clear_status(info);
185
186 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
187 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
188 info->flags |= IEEE80211_TX_STAT_ACK;
189
190 info->status.rates[0].count = (flags & 0xFF) + 1;
191 info->status.rates[1].idx = -1;
192
193 ieee80211_tx_status_irqsafe(dev, skb);
194 if (ring->entries - skb_queue_len(&ring->queue) == 2)
195 ieee80211_wake_queue(dev, prio);
196 }
197 }
198
199 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
200 {
201 struct ieee80211_hw *dev = dev_id;
202 struct rtl8180_priv *priv = dev->priv;
203 u16 reg;
204
205 spin_lock(&priv->lock);
206 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
207 if (unlikely(reg == 0xFFFF)) {
208 spin_unlock(&priv->lock);
209 return IRQ_HANDLED;
210 }
211
212 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
213
214 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
215 rtl8180_handle_tx(dev, 3);
216
217 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
218 rtl8180_handle_tx(dev, 2);
219
220 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
221 rtl8180_handle_tx(dev, 1);
222
223 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
224 rtl8180_handle_tx(dev, 0);
225
226 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
227 rtl8180_handle_rx(dev);
228
229 spin_unlock(&priv->lock);
230
231 return IRQ_HANDLED;
232 }
233
234 static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
235 {
236 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
237 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
238 struct rtl8180_priv *priv = dev->priv;
239 struct rtl8180_tx_ring *ring;
240 struct rtl8180_tx_desc *entry;
241 unsigned long flags;
242 unsigned int idx, prio;
243 dma_addr_t mapping;
244 u32 tx_flags;
245 u8 rc_flags;
246 u16 plcp_len = 0;
247 __le16 rts_duration = 0;
248
249 prio = skb_get_queue_mapping(skb);
250 ring = &priv->tx_ring[prio];
251
252 mapping = pci_map_single(priv->pdev, skb->data,
253 skb->len, PCI_DMA_TODEVICE);
254
255 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
256 RTL818X_TX_DESC_FLAG_LS |
257 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
258 skb->len;
259
260 if (priv->r8185)
261 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
262 RTL818X_TX_DESC_FLAG_NO_ENC;
263
264 rc_flags = info->control.rates[0].flags;
265 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
266 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
267 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
268 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
269 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
270 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
271 }
272
273 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
274 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
275 info);
276
277 if (!priv->r8185) {
278 unsigned int remainder;
279
280 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
281 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
282 remainder = (16 * (skb->len + 4)) %
283 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
284 if (remainder <= 6)
285 plcp_len |= 1 << 15;
286 }
287
288 spin_lock_irqsave(&priv->lock, flags);
289
290 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
291 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
292 priv->seqno += 0x10;
293 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
294 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
295 }
296
297 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
298 entry = &ring->desc[idx];
299
300 entry->rts_duration = rts_duration;
301 entry->plcp_len = cpu_to_le16(plcp_len);
302 entry->tx_buf = cpu_to_le32(mapping);
303 entry->frame_len = cpu_to_le32(skb->len);
304 entry->flags2 = info->control.rates[1].idx >= 0 ?
305 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
306 entry->retry_limit = info->control.rates[0].count;
307 entry->flags = cpu_to_le32(tx_flags);
308 __skb_queue_tail(&ring->queue, skb);
309 if (ring->entries - skb_queue_len(&ring->queue) < 2)
310 ieee80211_stop_queue(dev, prio);
311
312 spin_unlock_irqrestore(&priv->lock, flags);
313
314 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
315
316 return 0;
317 }
318
319 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
320 {
321 u8 reg;
322
323 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
324 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
325 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
326 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
327 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
328 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
329 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
330 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
331 }
332
333 static int rtl8180_init_hw(struct ieee80211_hw *dev)
334 {
335 struct rtl8180_priv *priv = dev->priv;
336 u16 reg;
337
338 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
339 rtl818x_ioread8(priv, &priv->map->CMD);
340 msleep(10);
341
342 /* reset */
343 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
344 rtl818x_ioread8(priv, &priv->map->CMD);
345
346 reg = rtl818x_ioread8(priv, &priv->map->CMD);
347 reg &= (1 << 1);
348 reg |= RTL818X_CMD_RESET;
349 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
350 rtl818x_ioread8(priv, &priv->map->CMD);
351 msleep(200);
352
353 /* check success of reset */
354 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
355 printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy));
356 return -ETIMEDOUT;
357 }
358
359 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
360 rtl818x_ioread8(priv, &priv->map->CMD);
361 msleep(200);
362
363 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
364 /* For cardbus */
365 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
366 reg |= 1 << 1;
367 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
368 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
369 reg |= (1 << 15) | (1 << 14) | (1 << 4);
370 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
371 }
372
373 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
374
375 if (!priv->r8185)
376 rtl8180_set_anaparam(priv, priv->anaparam);
377
378 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
379 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
380 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
381 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
382 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
383
384 /* TODO: necessary? specs indicate not */
385 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
386 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
387 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
388 if (priv->r8185) {
389 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
390 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
391 }
392 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
393
394 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
395
396 /* TODO: turn off hw wep on rtl8180 */
397
398 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
399
400 if (priv->r8185) {
401 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
402 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
403 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
404
405 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
406
407 /* TODO: set ClkRun enable? necessary? */
408 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
409 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
410 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
411 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
412 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
413 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
414 } else {
415 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
416 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
417
418 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
419 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
420 }
421
422 priv->rf->init(dev);
423 if (priv->r8185)
424 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
425 return 0;
426 }
427
428 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
429 {
430 struct rtl8180_priv *priv = dev->priv;
431 struct rtl8180_rx_desc *entry;
432 int i;
433
434 priv->rx_ring = pci_alloc_consistent(priv->pdev,
435 sizeof(*priv->rx_ring) * 32,
436 &priv->rx_ring_dma);
437
438 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
439 printk(KERN_ERR "%s: Cannot allocate RX ring\n",
440 wiphy_name(dev->wiphy));
441 return -ENOMEM;
442 }
443
444 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
445 priv->rx_idx = 0;
446
447 for (i = 0; i < 32; i++) {
448 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
449 dma_addr_t *mapping;
450 entry = &priv->rx_ring[i];
451 if (!skb)
452 return 0;
453
454 priv->rx_buf[i] = skb;
455 mapping = (dma_addr_t *)skb->cb;
456 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
457 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
458 entry->rx_buf = cpu_to_le32(*mapping);
459 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
460 MAX_RX_SIZE);
461 }
462 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
463 return 0;
464 }
465
466 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
467 {
468 struct rtl8180_priv *priv = dev->priv;
469 int i;
470
471 for (i = 0; i < 32; i++) {
472 struct sk_buff *skb = priv->rx_buf[i];
473 if (!skb)
474 continue;
475
476 pci_unmap_single(priv->pdev,
477 *((dma_addr_t *)skb->cb),
478 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
479 kfree_skb(skb);
480 }
481
482 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
483 priv->rx_ring, priv->rx_ring_dma);
484 priv->rx_ring = NULL;
485 }
486
487 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
488 unsigned int prio, unsigned int entries)
489 {
490 struct rtl8180_priv *priv = dev->priv;
491 struct rtl8180_tx_desc *ring;
492 dma_addr_t dma;
493 int i;
494
495 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
496 if (!ring || (unsigned long)ring & 0xFF) {
497 printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n",
498 wiphy_name(dev->wiphy), prio);
499 return -ENOMEM;
500 }
501
502 memset(ring, 0, sizeof(*ring)*entries);
503 priv->tx_ring[prio].desc = ring;
504 priv->tx_ring[prio].dma = dma;
505 priv->tx_ring[prio].idx = 0;
506 priv->tx_ring[prio].entries = entries;
507 skb_queue_head_init(&priv->tx_ring[prio].queue);
508
509 for (i = 0; i < entries; i++)
510 ring[i].next_tx_desc =
511 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
512
513 return 0;
514 }
515
516 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
517 {
518 struct rtl8180_priv *priv = dev->priv;
519 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
520
521 while (skb_queue_len(&ring->queue)) {
522 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
523 struct sk_buff *skb = __skb_dequeue(&ring->queue);
524
525 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
526 skb->len, PCI_DMA_TODEVICE);
527 kfree_skb(skb);
528 ring->idx = (ring->idx + 1) % ring->entries;
529 }
530
531 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
532 ring->desc, ring->dma);
533 ring->desc = NULL;
534 }
535
536 static int rtl8180_start(struct ieee80211_hw *dev)
537 {
538 struct rtl8180_priv *priv = dev->priv;
539 int ret, i;
540 u32 reg;
541
542 ret = rtl8180_init_rx_ring(dev);
543 if (ret)
544 return ret;
545
546 for (i = 0; i < 4; i++)
547 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
548 goto err_free_rings;
549
550 ret = rtl8180_init_hw(dev);
551 if (ret)
552 goto err_free_rings;
553
554 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
555 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
556 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
557 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
558 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
559
560 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
561 IRQF_SHARED, KBUILD_MODNAME, dev);
562 if (ret) {
563 printk(KERN_ERR "%s: failed to register IRQ handler\n",
564 wiphy_name(dev->wiphy));
565 goto err_free_rings;
566 }
567
568 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
569
570 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
571 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
572
573 reg = RTL818X_RX_CONF_ONLYERLPKT |
574 RTL818X_RX_CONF_RX_AUTORESETPHY |
575 RTL818X_RX_CONF_MGMT |
576 RTL818X_RX_CONF_DATA |
577 (7 << 8 /* MAX RX DMA */) |
578 RTL818X_RX_CONF_BROADCAST |
579 RTL818X_RX_CONF_NICMAC;
580
581 if (priv->r8185)
582 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
583 else {
584 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
585 ? RTL818X_RX_CONF_CSDM1 : 0;
586 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
587 ? RTL818X_RX_CONF_CSDM2 : 0;
588 }
589
590 priv->rx_conf = reg;
591 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
592
593 if (priv->r8185) {
594 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
595 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
596 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
597 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
598
599 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
600 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
601 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
602 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
603 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
604
605 /* disable early TX */
606 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
607 }
608
609 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
610 reg |= (6 << 21 /* MAX TX DMA */) |
611 RTL818X_TX_CONF_NO_ICV;
612
613 if (priv->r8185)
614 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
615 else
616 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
617
618 /* different meaning, same value on both rtl8185 and rtl8180 */
619 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
620
621 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
622
623 reg = rtl818x_ioread8(priv, &priv->map->CMD);
624 reg |= RTL818X_CMD_RX_ENABLE;
625 reg |= RTL818X_CMD_TX_ENABLE;
626 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
627
628 return 0;
629
630 err_free_rings:
631 rtl8180_free_rx_ring(dev);
632 for (i = 0; i < 4; i++)
633 if (priv->tx_ring[i].desc)
634 rtl8180_free_tx_ring(dev, i);
635
636 return ret;
637 }
638
639 static void rtl8180_stop(struct ieee80211_hw *dev)
640 {
641 struct rtl8180_priv *priv = dev->priv;
642 u8 reg;
643 int i;
644
645 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
646
647 reg = rtl818x_ioread8(priv, &priv->map->CMD);
648 reg &= ~RTL818X_CMD_TX_ENABLE;
649 reg &= ~RTL818X_CMD_RX_ENABLE;
650 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
651
652 priv->rf->stop(dev);
653
654 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
655 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
656 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
657 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
658
659 free_irq(priv->pdev->irq, dev);
660
661 rtl8180_free_rx_ring(dev);
662 for (i = 0; i < 4; i++)
663 rtl8180_free_tx_ring(dev, i);
664 }
665
666 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev)
667 {
668 struct rtl8180_priv *priv = dev->priv;
669
670 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
671 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
672 }
673
674 void rtl8180_beacon_work(struct work_struct *work)
675 {
676 struct rtl8180_vif *vif_priv =
677 container_of(work, struct rtl8180_vif, beacon_work.work);
678 struct ieee80211_vif *vif =
679 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
680 struct ieee80211_hw *dev = vif_priv->dev;
681 struct ieee80211_mgmt *mgmt;
682 struct sk_buff *skb;
683 int err = 0;
684
685 /* don't overflow the tx ring */
686 if (ieee80211_queue_stopped(dev, 0))
687 goto resched;
688
689 /* grab a fresh beacon */
690 skb = ieee80211_beacon_get(dev, vif);
691
692 /*
693 * update beacon timestamp w/ TSF value
694 * TODO: make hardware update beacon timestamp
695 */
696 mgmt = (struct ieee80211_mgmt *)skb->data;
697 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev));
698
699 /* TODO: use actual beacon queue */
700 skb_set_queue_mapping(skb, 0);
701
702 err = rtl8180_tx(dev, skb);
703 WARN_ON(err);
704
705 resched:
706 /*
707 * schedule next beacon
708 * TODO: use hardware support for beacon timing
709 */
710 schedule_delayed_work(&vif_priv->beacon_work,
711 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
712 }
713
714 static int rtl8180_add_interface(struct ieee80211_hw *dev,
715 struct ieee80211_vif *vif)
716 {
717 struct rtl8180_priv *priv = dev->priv;
718 struct rtl8180_vif *vif_priv;
719
720 /*
721 * We only support one active interface at a time.
722 */
723 if (priv->vif)
724 return -EBUSY;
725
726 switch (vif->type) {
727 case NL80211_IFTYPE_STATION:
728 case NL80211_IFTYPE_ADHOC:
729 break;
730 default:
731 return -EOPNOTSUPP;
732 }
733
734 priv->vif = vif;
735
736 /* Initialize driver private area */
737 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
738 vif_priv->dev = dev;
739 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
740 vif_priv->enable_beacon = false;
741
742 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
743 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
744 le32_to_cpu(*(__le32 *)vif->addr));
745 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
746 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
747 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
748
749 return 0;
750 }
751
752 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
753 struct ieee80211_vif *vif)
754 {
755 struct rtl8180_priv *priv = dev->priv;
756 priv->vif = NULL;
757 }
758
759 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
760 {
761 struct rtl8180_priv *priv = dev->priv;
762 struct ieee80211_conf *conf = &dev->conf;
763
764 priv->rf->set_chan(dev, conf);
765
766 return 0;
767 }
768
769 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
770 struct ieee80211_vif *vif,
771 struct ieee80211_bss_conf *info,
772 u32 changed)
773 {
774 struct rtl8180_priv *priv = dev->priv;
775 struct rtl8180_vif *vif_priv;
776 int i;
777
778 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
779
780 if (changed & BSS_CHANGED_BSSID) {
781 for (i = 0; i < ETH_ALEN; i++)
782 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
783 info->bssid[i]);
784
785 if (is_valid_ether_addr(info->bssid))
786 rtl818x_iowrite8(priv, &priv->map->MSR,
787 RTL818X_MSR_INFRA);
788 else
789 rtl818x_iowrite8(priv, &priv->map->MSR,
790 RTL818X_MSR_NO_LINK);
791 }
792
793 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
794 priv->rf->conf_erp(dev, info);
795
796 if (changed & BSS_CHANGED_BEACON_ENABLED)
797 vif_priv->enable_beacon = info->enable_beacon;
798
799 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
800 cancel_delayed_work_sync(&vif_priv->beacon_work);
801 if (vif_priv->enable_beacon)
802 schedule_work(&vif_priv->beacon_work.work);
803 }
804 }
805
806 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
807 struct netdev_hw_addr_list *mc_list)
808 {
809 return netdev_hw_addr_list_count(mc_list);
810 }
811
812 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
813 unsigned int changed_flags,
814 unsigned int *total_flags,
815 u64 multicast)
816 {
817 struct rtl8180_priv *priv = dev->priv;
818
819 if (changed_flags & FIF_FCSFAIL)
820 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
821 if (changed_flags & FIF_CONTROL)
822 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
823 if (changed_flags & FIF_OTHER_BSS)
824 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
825 if (*total_flags & FIF_ALLMULTI || multicast > 0)
826 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
827 else
828 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
829
830 *total_flags = 0;
831
832 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
833 *total_flags |= FIF_FCSFAIL;
834 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
835 *total_flags |= FIF_CONTROL;
836 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
837 *total_flags |= FIF_OTHER_BSS;
838 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
839 *total_flags |= FIF_ALLMULTI;
840
841 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
842 }
843
844 static const struct ieee80211_ops rtl8180_ops = {
845 .tx = rtl8180_tx,
846 .start = rtl8180_start,
847 .stop = rtl8180_stop,
848 .add_interface = rtl8180_add_interface,
849 .remove_interface = rtl8180_remove_interface,
850 .config = rtl8180_config,
851 .bss_info_changed = rtl8180_bss_info_changed,
852 .prepare_multicast = rtl8180_prepare_multicast,
853 .configure_filter = rtl8180_configure_filter,
854 .get_tsf = rtl8180_get_tsf,
855 };
856
857 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
858 {
859 struct ieee80211_hw *dev = eeprom->data;
860 struct rtl8180_priv *priv = dev->priv;
861 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
862
863 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
864 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
865 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
866 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
867 }
868
869 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
870 {
871 struct ieee80211_hw *dev = eeprom->data;
872 struct rtl8180_priv *priv = dev->priv;
873 u8 reg = 2 << 6;
874
875 if (eeprom->reg_data_in)
876 reg |= RTL818X_EEPROM_CMD_WRITE;
877 if (eeprom->reg_data_out)
878 reg |= RTL818X_EEPROM_CMD_READ;
879 if (eeprom->reg_data_clock)
880 reg |= RTL818X_EEPROM_CMD_CK;
881 if (eeprom->reg_chip_select)
882 reg |= RTL818X_EEPROM_CMD_CS;
883
884 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
885 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
886 udelay(10);
887 }
888
889 static int __devinit rtl8180_probe(struct pci_dev *pdev,
890 const struct pci_device_id *id)
891 {
892 struct ieee80211_hw *dev;
893 struct rtl8180_priv *priv;
894 unsigned long mem_addr, mem_len;
895 unsigned int io_addr, io_len;
896 int err, i;
897 struct eeprom_93cx6 eeprom;
898 const char *chip_name, *rf_name = NULL;
899 u32 reg;
900 u16 eeprom_val;
901 u8 mac_addr[ETH_ALEN];
902
903 err = pci_enable_device(pdev);
904 if (err) {
905 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
906 pci_name(pdev));
907 return err;
908 }
909
910 err = pci_request_regions(pdev, KBUILD_MODNAME);
911 if (err) {
912 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
913 pci_name(pdev));
914 return err;
915 }
916
917 io_addr = pci_resource_start(pdev, 0);
918 io_len = pci_resource_len(pdev, 0);
919 mem_addr = pci_resource_start(pdev, 1);
920 mem_len = pci_resource_len(pdev, 1);
921
922 if (mem_len < sizeof(struct rtl818x_csr) ||
923 io_len < sizeof(struct rtl818x_csr)) {
924 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
925 pci_name(pdev));
926 err = -ENOMEM;
927 goto err_free_reg;
928 }
929
930 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
931 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
932 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
933 pci_name(pdev));
934 goto err_free_reg;
935 }
936
937 pci_set_master(pdev);
938
939 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
940 if (!dev) {
941 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
942 pci_name(pdev));
943 err = -ENOMEM;
944 goto err_free_reg;
945 }
946
947 priv = dev->priv;
948 priv->pdev = pdev;
949
950 dev->max_rates = 2;
951 SET_IEEE80211_DEV(dev, &pdev->dev);
952 pci_set_drvdata(pdev, dev);
953
954 priv->map = pci_iomap(pdev, 1, mem_len);
955 if (!priv->map)
956 priv->map = pci_iomap(pdev, 0, io_len);
957
958 if (!priv->map) {
959 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
960 pci_name(pdev));
961 goto err_free_dev;
962 }
963
964 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
965 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
966
967 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
968 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
969
970 priv->band.band = IEEE80211_BAND_2GHZ;
971 priv->band.channels = priv->channels;
972 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
973 priv->band.bitrates = priv->rates;
974 priv->band.n_bitrates = 4;
975 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
976
977 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
978 IEEE80211_HW_RX_INCLUDES_FCS |
979 IEEE80211_HW_SIGNAL_UNSPEC;
980 dev->vif_data_size = sizeof(struct rtl8180_vif);
981 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
982 BIT(NL80211_IFTYPE_ADHOC);
983 dev->queues = 1;
984 dev->max_signal = 65;
985
986 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
987 reg &= RTL818X_TX_CONF_HWVER_MASK;
988 switch (reg) {
989 case RTL818X_TX_CONF_R8180_ABCD:
990 chip_name = "RTL8180";
991 break;
992 case RTL818X_TX_CONF_R8180_F:
993 chip_name = "RTL8180vF";
994 break;
995 case RTL818X_TX_CONF_R8185_ABC:
996 chip_name = "RTL8185";
997 break;
998 case RTL818X_TX_CONF_R8185_D:
999 chip_name = "RTL8185vD";
1000 break;
1001 default:
1002 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1003 pci_name(pdev), reg >> 25);
1004 goto err_iounmap;
1005 }
1006
1007 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1008 if (priv->r8185) {
1009 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1010 pci_try_set_mwi(pdev);
1011 }
1012
1013 eeprom.data = dev;
1014 eeprom.register_read = rtl8180_eeprom_register_read;
1015 eeprom.register_write = rtl8180_eeprom_register_write;
1016 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1017 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1018 else
1019 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1020
1021 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1022 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1023 udelay(10);
1024
1025 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1026 eeprom_val &= 0xFF;
1027 switch (eeprom_val) {
1028 case 1: rf_name = "Intersil";
1029 break;
1030 case 2: rf_name = "RFMD";
1031 break;
1032 case 3: priv->rf = &sa2400_rf_ops;
1033 break;
1034 case 4: priv->rf = &max2820_rf_ops;
1035 break;
1036 case 5: priv->rf = &grf5101_rf_ops;
1037 break;
1038 case 9: priv->rf = rtl8180_detect_rf(dev);
1039 break;
1040 case 10:
1041 rf_name = "RTL8255";
1042 break;
1043 default:
1044 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1045 pci_name(pdev), eeprom_val);
1046 goto err_iounmap;
1047 }
1048
1049 if (!priv->rf) {
1050 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1051 pci_name(pdev), rf_name);
1052 goto err_iounmap;
1053 }
1054
1055 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1056 priv->csthreshold = eeprom_val >> 8;
1057 if (!priv->r8185) {
1058 __le32 anaparam;
1059 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1060 priv->anaparam = le32_to_cpu(anaparam);
1061 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1062 }
1063
1064 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1065 if (!is_valid_ether_addr(mac_addr)) {
1066 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1067 " randomly generated MAC addr\n", pci_name(pdev));
1068 random_ether_addr(mac_addr);
1069 }
1070 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1071
1072 /* CCK TX power */
1073 for (i = 0; i < 14; i += 2) {
1074 u16 txpwr;
1075 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1076 priv->channels[i].hw_value = txpwr & 0xFF;
1077 priv->channels[i + 1].hw_value = txpwr >> 8;
1078 }
1079
1080 /* OFDM TX power */
1081 if (priv->r8185) {
1082 for (i = 0; i < 14; i += 2) {
1083 u16 txpwr;
1084 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1085 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1086 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1087 }
1088 }
1089
1090 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1091
1092 spin_lock_init(&priv->lock);
1093
1094 err = ieee80211_register_hw(dev);
1095 if (err) {
1096 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1097 pci_name(pdev));
1098 goto err_iounmap;
1099 }
1100
1101 printk(KERN_INFO "%s: hwaddr %pM, %s + %s\n",
1102 wiphy_name(dev->wiphy), mac_addr,
1103 chip_name, priv->rf->name);
1104
1105 return 0;
1106
1107 err_iounmap:
1108 iounmap(priv->map);
1109
1110 err_free_dev:
1111 pci_set_drvdata(pdev, NULL);
1112 ieee80211_free_hw(dev);
1113
1114 err_free_reg:
1115 pci_release_regions(pdev);
1116 pci_disable_device(pdev);
1117 return err;
1118 }
1119
1120 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1121 {
1122 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1123 struct rtl8180_priv *priv;
1124
1125 if (!dev)
1126 return;
1127
1128 ieee80211_unregister_hw(dev);
1129
1130 priv = dev->priv;
1131
1132 pci_iounmap(pdev, priv->map);
1133 pci_release_regions(pdev);
1134 pci_disable_device(pdev);
1135 ieee80211_free_hw(dev);
1136 }
1137
1138 #ifdef CONFIG_PM
1139 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1140 {
1141 pci_save_state(pdev);
1142 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1143 return 0;
1144 }
1145
1146 static int rtl8180_resume(struct pci_dev *pdev)
1147 {
1148 pci_set_power_state(pdev, PCI_D0);
1149 pci_restore_state(pdev);
1150 return 0;
1151 }
1152
1153 #endif /* CONFIG_PM */
1154
1155 static struct pci_driver rtl8180_driver = {
1156 .name = KBUILD_MODNAME,
1157 .id_table = rtl8180_table,
1158 .probe = rtl8180_probe,
1159 .remove = __devexit_p(rtl8180_remove),
1160 #ifdef CONFIG_PM
1161 .suspend = rtl8180_suspend,
1162 .resume = rtl8180_resume,
1163 #endif /* CONFIG_PM */
1164 };
1165
1166 static int __init rtl8180_init(void)
1167 {
1168 return pci_register_driver(&rtl8180_driver);
1169 }
1170
1171 static void __exit rtl8180_exit(void)
1172 {
1173 pci_unregister_driver(&rtl8180_driver);
1174 }
1175
1176 module_init(rtl8180_init);
1177 module_exit(rtl8180_exit);
kernel source for telekom puls (alcatel/mediatek)