1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
44 * mac80211 queues, ACs, hardware queues, FIFOs.
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
69 static const u8 tid_to_ac
[] = {
70 /* this matches the mac80211 numbers */
71 2, 3, 3, 2, 1, 1, 0, 0
74 static const u8 ac_to_fifo
[] = {
81 static inline int get_fifo_from_ac(u8 ac
)
83 return ac_to_fifo
[ac
];
86 static inline int get_ac_from_tid(u16 tid
)
88 if (likely(tid
< ARRAY_SIZE(tid_to_ac
)))
89 return tid_to_ac
[tid
];
91 /* no support for TIDs 8-15 yet */
95 static inline int get_fifo_from_tid(u16 tid
)
97 if (likely(tid
< ARRAY_SIZE(tid_to_ac
)))
98 return get_fifo_from_ac(tid_to_ac
[tid
]);
100 /* no support for TIDs 8-15 yet */
105 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
107 void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
108 struct iwl_tx_queue
*txq
,
111 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
112 int write_ptr
= txq
->q
.write_ptr
;
113 int txq_id
= txq
->q
.id
;
116 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
119 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
121 if (txq_id
!= IWL_CMD_QUEUE_NUM
) {
122 sta_id
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sta_id
;
123 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sec_ctl
;
125 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
129 case TX_CMD_SEC_TKIP
:
133 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
138 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
140 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
142 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
144 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
147 void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv
*priv
,
148 struct iwl_tx_queue
*txq
)
150 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
151 int txq_id
= txq
->q
.id
;
152 int read_ptr
= txq
->q
.read_ptr
;
156 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
158 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
159 sta_id
= txq
->cmd
[read_ptr
]->cmd
.tx
.sta_id
;
161 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
162 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
164 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
166 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
169 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv
*priv
, u16 ra_tid
,
176 scd_q2ratid
= ra_tid
& IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
178 tbl_dw_addr
= priv
->scd_base_addr
+
179 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id
);
181 tbl_dw
= iwl_read_targ_mem(priv
, tbl_dw_addr
);
184 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
186 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
188 iwl_write_targ_mem(priv
, tbl_dw_addr
, tbl_dw
);
193 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv
*priv
, u16 txq_id
)
195 /* Simply stop the queue, but don't change any configuration;
196 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
198 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id
),
199 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
200 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
203 void iwlagn_set_wr_ptrs(struct iwl_priv
*priv
,
204 int txq_id
, u32 index
)
206 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
207 (index
& 0xff) | (txq_id
<< 8));
208 iwl_write_prph(priv
, IWLAGN_SCD_QUEUE_RDPTR(txq_id
), index
);
211 void iwlagn_tx_queue_set_status(struct iwl_priv
*priv
,
212 struct iwl_tx_queue
*txq
,
213 int tx_fifo_id
, int scd_retry
)
215 int txq_id
= txq
->q
.id
;
216 int active
= test_bit(txq_id
, &priv
->txq_ctx_active_msk
) ? 1 : 0;
218 iwl_write_prph(priv
, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id
),
219 (active
<< IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
220 (tx_fifo_id
<< IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF
) |
221 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL
) |
222 IWLAGN_SCD_QUEUE_STTS_REG_MSK
);
224 txq
->sched_retry
= scd_retry
;
226 IWL_DEBUG_INFO(priv
, "%s %s Queue %d on FIFO %d\n",
227 active
? "Activate" : "Deactivate",
228 scd_retry
? "BA" : "AC/CMD", txq_id
, tx_fifo_id
);
231 int iwlagn_txq_agg_enable(struct iwl_priv
*priv
, int txq_id
,
232 int tx_fifo
, int sta_id
, int tid
, u16 ssn_idx
)
237 if ((IWLAGN_FIRST_AMPDU_QUEUE
> txq_id
) ||
238 (IWLAGN_FIRST_AMPDU_QUEUE
+ priv
->cfg
->num_of_ampdu_queues
241 "queue number out of range: %d, must be %d to %d\n",
242 txq_id
, IWLAGN_FIRST_AMPDU_QUEUE
,
243 IWLAGN_FIRST_AMPDU_QUEUE
+
244 priv
->cfg
->num_of_ampdu_queues
- 1);
248 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
250 /* Modify device's station table to Tx this TID */
251 iwl_sta_tx_modify_enable_tid(priv
, sta_id
, tid
);
253 spin_lock_irqsave(&priv
->lock
, flags
);
255 /* Stop this Tx queue before configuring it */
256 iwlagn_tx_queue_stop_scheduler(priv
, txq_id
);
258 /* Map receiver-address / traffic-ID to this queue */
259 iwlagn_tx_queue_set_q2ratid(priv
, ra_tid
, txq_id
);
261 /* Set this queue as a chain-building queue */
262 iwl_set_bits_prph(priv
, IWLAGN_SCD_QUEUECHAIN_SEL
, (1<<txq_id
));
264 /* enable aggregations for the queue */
265 iwl_set_bits_prph(priv
, IWLAGN_SCD_AGGR_SEL
, (1<<txq_id
));
267 /* Place first TFD at index corresponding to start sequence number.
268 * Assumes that ssn_idx is valid (!= 0xFFF) */
269 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
270 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
271 iwlagn_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
273 /* Set up Tx window size and frame limit for this queue */
274 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
275 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id
) +
278 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
279 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
281 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
282 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
284 iwl_set_bits_prph(priv
, IWLAGN_SCD_INTERRUPT_MASK
, (1 << txq_id
));
286 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
287 iwlagn_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 1);
289 spin_unlock_irqrestore(&priv
->lock
, flags
);
294 int iwlagn_txq_agg_disable(struct iwl_priv
*priv
, u16 txq_id
,
295 u16 ssn_idx
, u8 tx_fifo
)
297 if ((IWLAGN_FIRST_AMPDU_QUEUE
> txq_id
) ||
298 (IWLAGN_FIRST_AMPDU_QUEUE
+ priv
->cfg
->num_of_ampdu_queues
301 "queue number out of range: %d, must be %d to %d\n",
302 txq_id
, IWLAGN_FIRST_AMPDU_QUEUE
,
303 IWLAGN_FIRST_AMPDU_QUEUE
+
304 priv
->cfg
->num_of_ampdu_queues
- 1);
308 iwlagn_tx_queue_stop_scheduler(priv
, txq_id
);
310 iwl_clear_bits_prph(priv
, IWLAGN_SCD_AGGR_SEL
, (1 << txq_id
));
312 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
313 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
314 /* supposes that ssn_idx is valid (!= 0xFFF) */
315 iwlagn_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
317 iwl_clear_bits_prph(priv
, IWLAGN_SCD_INTERRUPT_MASK
, (1 << txq_id
));
318 iwl_txq_ctx_deactivate(priv
, txq_id
);
319 iwlagn_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 0);
325 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
326 * must be called under priv->lock and mac access
328 void iwlagn_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
330 iwl_write_prph(priv
, IWLAGN_SCD_TXFACT
, mask
);
333 static inline int get_queue_from_ac(u16 ac
)
339 * handle build REPLY_TX command notification.
341 static void iwlagn_tx_cmd_build_basic(struct iwl_priv
*priv
,
342 struct iwl_tx_cmd
*tx_cmd
,
343 struct ieee80211_tx_info
*info
,
344 struct ieee80211_hdr
*hdr
,
347 __le16 fc
= hdr
->frame_control
;
348 __le32 tx_flags
= tx_cmd
->tx_flags
;
350 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
351 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
352 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
353 if (ieee80211_is_mgmt(fc
))
354 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
355 if (ieee80211_is_probe_resp(fc
) &&
356 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
357 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
359 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
360 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
363 if (ieee80211_is_back_req(fc
))
364 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
367 tx_cmd
->sta_id
= std_id
;
368 if (ieee80211_has_morefrags(fc
))
369 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
371 if (ieee80211_is_data_qos(fc
)) {
372 u8
*qc
= ieee80211_get_qos_ctl(hdr
);
373 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
374 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
376 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
379 priv
->cfg
->ops
->utils
->rts_tx_cmd_flag(info
, &tx_flags
);
381 if ((tx_flags
& TX_CMD_FLG_RTS_MSK
) || (tx_flags
& TX_CMD_FLG_CTS_MSK
))
382 tx_flags
|= TX_CMD_FLG_FULL_TXOP_PROT_MSK
;
384 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
385 if (ieee80211_is_mgmt(fc
)) {
386 if (ieee80211_is_assoc_req(fc
) || ieee80211_is_reassoc_req(fc
))
387 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
389 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
391 tx_cmd
->timeout
.pm_frame_timeout
= 0;
394 tx_cmd
->driver_txop
= 0;
395 tx_cmd
->tx_flags
= tx_flags
;
396 tx_cmd
->next_frame_len
= 0;
399 #define RTS_DFAULT_RETRY_LIMIT 60
401 static void iwlagn_tx_cmd_build_rate(struct iwl_priv
*priv
,
402 struct iwl_tx_cmd
*tx_cmd
,
403 struct ieee80211_tx_info
*info
,
412 /* Set retry limit on DATA packets and Probe Responses*/
413 if (ieee80211_is_probe_resp(fc
))
414 data_retry_limit
= 3;
416 data_retry_limit
= IWLAGN_DEFAULT_TX_RETRY
;
417 tx_cmd
->data_retry_limit
= data_retry_limit
;
419 /* Set retry limit on RTS packets */
420 rts_retry_limit
= RTS_DFAULT_RETRY_LIMIT
;
421 if (data_retry_limit
< rts_retry_limit
)
422 rts_retry_limit
= data_retry_limit
;
423 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
425 /* DATA packets will use the uCode station table for rate/antenna
427 if (ieee80211_is_data(fc
)) {
428 tx_cmd
->initial_rate_index
= 0;
429 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
434 * If the current TX rate stored in mac80211 has the MCS bit set, it's
435 * not really a TX rate. Thus, we use the lowest supported rate for
436 * this band. Also use the lowest supported rate if the stored rate
439 rate_idx
= info
->control
.rates
[0].idx
;
440 if (info
->control
.rates
[0].flags
& IEEE80211_TX_RC_MCS
||
441 (rate_idx
< 0) || (rate_idx
> IWL_RATE_COUNT_LEGACY
))
442 rate_idx
= rate_lowest_index(&priv
->bands
[info
->band
],
444 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
445 if (info
->band
== IEEE80211_BAND_5GHZ
)
446 rate_idx
+= IWL_FIRST_OFDM_RATE
;
447 /* Get PLCP rate for tx_cmd->rate_n_flags */
448 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
449 /* Zero out flags for this packet */
452 /* Set CCK flag as needed */
453 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
454 rate_flags
|= RATE_MCS_CCK_MSK
;
456 /* Set up RTS and CTS flags for certain packets */
457 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
458 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
459 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
460 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
461 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
462 if (tx_cmd
->tx_flags
& TX_CMD_FLG_RTS_MSK
) {
463 tx_cmd
->tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
464 tx_cmd
->tx_flags
|= TX_CMD_FLG_CTS_MSK
;
471 /* Set up antennas */
472 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
);
473 rate_flags
|= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
475 /* Set the rate in the TX cmd */
476 tx_cmd
->rate_n_flags
= iwl_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
479 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
480 struct ieee80211_tx_info
*info
,
481 struct iwl_tx_cmd
*tx_cmd
,
482 struct sk_buff
*skb_frag
,
485 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
487 switch (keyconf
->alg
) {
489 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
490 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
491 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
492 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
493 IWL_DEBUG_TX(priv
, "tx_cmd with AES hwcrypto\n");
497 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
498 ieee80211_get_tkip_key(keyconf
, skb_frag
,
499 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
500 IWL_DEBUG_TX(priv
, "tx_cmd with tkip hwcrypto\n");
504 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
505 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
507 if (keyconf
->keylen
== WEP_KEY_LEN_128
)
508 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
510 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
512 IWL_DEBUG_TX(priv
, "Configuring packet for WEP encryption "
513 "with key %d\n", keyconf
->keyidx
);
517 IWL_ERR(priv
, "Unknown encode alg %d\n", keyconf
->alg
);
523 * start REPLY_TX command process
525 int iwlagn_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
527 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
528 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
529 struct ieee80211_sta
*sta
= info
->control
.sta
;
530 struct iwl_station_priv
*sta_priv
= NULL
;
531 struct iwl_tx_queue
*txq
;
533 struct iwl_device_cmd
*out_cmd
;
534 struct iwl_cmd_meta
*out_meta
;
535 struct iwl_tx_cmd
*tx_cmd
;
537 dma_addr_t phys_addr
;
538 dma_addr_t txcmd_phys
;
539 dma_addr_t scratch_phys
;
540 u16 len
, len_org
, firstlen
, secondlen
;
545 u8 wait_write_ptr
= 0;
550 spin_lock_irqsave(&priv
->lock
, flags
);
551 if (iwl_is_rfkill(priv
)) {
552 IWL_DEBUG_DROP(priv
, "Dropping - RF KILL\n");
556 fc
= hdr
->frame_control
;
558 #ifdef CONFIG_IWLWIFI_DEBUG
559 if (ieee80211_is_auth(fc
))
560 IWL_DEBUG_TX(priv
, "Sending AUTH frame\n");
561 else if (ieee80211_is_assoc_req(fc
))
562 IWL_DEBUG_TX(priv
, "Sending ASSOC frame\n");
563 else if (ieee80211_is_reassoc_req(fc
))
564 IWL_DEBUG_TX(priv
, "Sending REASSOC frame\n");
567 hdr_len
= ieee80211_hdrlen(fc
);
569 /* Find index into station table for destination station */
570 if (!info
->control
.sta
)
571 sta_id
= priv
->hw_params
.bcast_sta_id
;
573 sta_id
= iwl_sta_id(info
->control
.sta
);
574 if (sta_id
== IWL_INVALID_STATION
) {
575 IWL_DEBUG_DROP(priv
, "Dropping - INVALID STATION: %pM\n",
580 IWL_DEBUG_TX(priv
, "station Id %d\n", sta_id
);
583 sta_priv
= (void *)sta
->drv_priv
;
585 if (sta_priv
&& sta_id
!= priv
->hw_params
.bcast_sta_id
&&
587 WARN_ON(!(info
->flags
& IEEE80211_TX_CTL_PSPOLL_RESPONSE
));
589 * This sends an asynchronous command to the device,
590 * but we can rely on it being processed before the
591 * next frame is processed -- and the next frame to
592 * this station is the one that will consume this
594 * For now set the counter to just 1 since we do not
597 iwl_sta_modify_sleep_tx_count(priv
, sta_id
, 1);
600 txq_id
= get_queue_from_ac(skb_get_queue_mapping(skb
));
601 if (ieee80211_is_data_qos(fc
)) {
602 qc
= ieee80211_get_qos_ctl(hdr
);
603 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
604 if (unlikely(tid
>= MAX_TID_COUNT
))
606 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
;
607 seq_number
&= IEEE80211_SCTL_SEQ
;
608 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
609 cpu_to_le16(IEEE80211_SCTL_FRAG
);
610 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
612 /* aggregation is on for this <sta,tid> */
613 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
&&
614 priv
->stations
[sta_id
].tid
[tid
].agg
.state
== IWL_AGG_ON
) {
615 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
619 txq
= &priv
->txq
[txq_id
];
620 swq_id
= txq
->swq_id
;
623 if (unlikely(iwl_queue_space(q
) < q
->high_mark
))
626 if (ieee80211_is_data_qos(fc
))
627 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
629 /* Set up driver data for this TFD */
630 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
631 txq
->txb
[q
->write_ptr
].skb
[0] = skb
;
633 /* Set up first empty entry in queue's array of Tx/cmd buffers */
634 out_cmd
= txq
->cmd
[q
->write_ptr
];
635 out_meta
= &txq
->meta
[q
->write_ptr
];
636 tx_cmd
= &out_cmd
->cmd
.tx
;
637 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
638 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
641 * Set up the Tx-command (not MAC!) header.
642 * Store the chosen Tx queue and TFD index within the sequence field;
643 * after Tx, uCode's Tx response will return this value so driver can
644 * locate the frame within the tx queue and do post-tx processing.
646 out_cmd
->hdr
.cmd
= REPLY_TX
;
647 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
648 INDEX_TO_SEQ(q
->write_ptr
)));
650 /* Copy MAC header from skb into command buffer */
651 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
654 /* Total # bytes to be transmitted */
656 tx_cmd
->len
= cpu_to_le16(len
);
658 if (info
->control
.hw_key
)
659 iwlagn_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
661 /* TODO need this for burst mode later on */
662 iwlagn_tx_cmd_build_basic(priv
, tx_cmd
, info
, hdr
, sta_id
);
663 iwl_dbg_log_tx_data_frame(priv
, len
, hdr
);
665 iwlagn_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
);
667 iwl_update_stats(priv
, true, fc
, len
);
669 * Use the first empty entry in this queue's command buffer array
670 * to contain the Tx command and MAC header concatenated together
671 * (payload data will be in another buffer).
672 * Size of this varies, due to varying MAC header length.
673 * If end is not dword aligned, we'll have 2 extra bytes at the end
674 * of the MAC header (device reads on dword boundaries).
675 * We'll tell device about this padding later.
677 len
= sizeof(struct iwl_tx_cmd
) +
678 sizeof(struct iwl_cmd_header
) + hdr_len
;
681 firstlen
= len
= (len
+ 3) & ~3;
688 /* Tell NIC about any 2-byte padding after MAC header */
690 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
692 /* Physical address of this Tx command's header (not MAC header!),
693 * within command buffer array. */
694 txcmd_phys
= pci_map_single(priv
->pci_dev
,
696 PCI_DMA_BIDIRECTIONAL
);
697 pci_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
698 pci_unmap_len_set(out_meta
, len
, len
);
699 /* Add buffer containing Tx command and MAC(!) header to TFD's
701 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
702 txcmd_phys
, len
, 1, 0);
704 if (!ieee80211_has_morefrags(hdr
->frame_control
)) {
705 txq
->need_update
= 1;
707 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
710 txq
->need_update
= 0;
713 /* Set up TFD's 2nd entry to point directly to remainder of skb,
714 * if any (802.11 null frames have no payload). */
715 secondlen
= len
= skb
->len
- hdr_len
;
717 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
718 len
, PCI_DMA_TODEVICE
);
719 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
724 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
725 offsetof(struct iwl_tx_cmd
, scratch
);
727 len
= sizeof(struct iwl_tx_cmd
) +
728 sizeof(struct iwl_cmd_header
) + hdr_len
;
729 /* take back ownership of DMA buffer to enable update */
730 pci_dma_sync_single_for_cpu(priv
->pci_dev
, txcmd_phys
,
731 len
, PCI_DMA_BIDIRECTIONAL
);
732 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
733 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
735 IWL_DEBUG_TX(priv
, "sequence nr = 0X%x\n",
736 le16_to_cpu(out_cmd
->hdr
.sequence
));
737 IWL_DEBUG_TX(priv
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
738 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
739 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
741 /* Set up entry for this TFD in Tx byte-count array */
742 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
743 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
,
744 le16_to_cpu(tx_cmd
->len
));
746 pci_dma_sync_single_for_device(priv
->pci_dev
, txcmd_phys
,
747 len
, PCI_DMA_BIDIRECTIONAL
);
749 trace_iwlwifi_dev_tx(priv
,
750 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
751 sizeof(struct iwl_tfd
),
752 &out_cmd
->hdr
, firstlen
,
753 skb
->data
+ hdr_len
, secondlen
);
755 /* Tell device the write index *just past* this latest filled TFD */
756 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
757 iwl_txq_update_write_ptr(priv
, txq
);
758 spin_unlock_irqrestore(&priv
->lock
, flags
);
761 * At this point the frame is "transmitted" successfully
762 * and we will get a TX status notification eventually,
763 * regardless of the value of ret. "ret" only indicates
764 * whether or not we should update the write pointer.
767 /* avoid atomic ops if it isn't an associated client */
768 if (sta_priv
&& sta_priv
->client
)
769 atomic_inc(&sta_priv
->pending_frames
);
771 if ((iwl_queue_space(q
) < q
->high_mark
) && priv
->mac80211_registered
) {
772 if (wait_write_ptr
) {
773 spin_lock_irqsave(&priv
->lock
, flags
);
774 txq
->need_update
= 1;
775 iwl_txq_update_write_ptr(priv
, txq
);
776 spin_unlock_irqrestore(&priv
->lock
, flags
);
778 iwl_stop_queue(priv
, txq
->swq_id
);
785 spin_unlock_irqrestore(&priv
->lock
, flags
);
789 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv
*priv
,
790 struct iwl_dma_ptr
*ptr
, size_t size
)
792 ptr
->addr
= dma_alloc_coherent(&priv
->pci_dev
->dev
, size
, &ptr
->dma
,
800 static inline void iwlagn_free_dma_ptr(struct iwl_priv
*priv
,
801 struct iwl_dma_ptr
*ptr
)
803 if (unlikely(!ptr
->addr
))
806 dma_free_coherent(&priv
->pci_dev
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
807 memset(ptr
, 0, sizeof(*ptr
));
811 * iwlagn_hw_txq_ctx_free - Free TXQ Context
813 * Destroy all TX DMA queues and structures
815 void iwlagn_hw_txq_ctx_free(struct iwl_priv
*priv
)
821 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
822 if (txq_id
== IWL_CMD_QUEUE_NUM
)
823 iwl_cmd_queue_free(priv
);
825 iwl_tx_queue_free(priv
, txq_id
);
827 iwlagn_free_dma_ptr(priv
, &priv
->kw
);
829 iwlagn_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
831 /* free tx queue structure */
832 iwl_free_txq_mem(priv
);
836 * iwlagn_txq_ctx_alloc - allocate TX queue context
837 * Allocate all Tx DMA structures and initialize them
842 int iwlagn_txq_ctx_alloc(struct iwl_priv
*priv
)
845 int txq_id
, slots_num
;
848 /* Free all tx/cmd queues and keep-warm buffer */
849 iwlagn_hw_txq_ctx_free(priv
);
851 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->scd_bc_tbls
,
852 priv
->hw_params
.scd_bc_tbls_size
);
854 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
857 /* Alloc keep-warm buffer */
858 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
860 IWL_ERR(priv
, "Keep Warm allocation failed\n");
864 /* allocate tx queue structure */
865 ret
= iwl_alloc_txq_mem(priv
);
869 spin_lock_irqsave(&priv
->lock
, flags
);
871 /* Turn off all Tx DMA fifos */
872 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
874 /* Tell NIC where to find the "keep warm" buffer */
875 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
877 spin_unlock_irqrestore(&priv
->lock
, flags
);
879 /* Alloc and init all Tx queues, including the command queue (#4) */
880 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
881 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
882 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
883 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
886 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
894 iwlagn_hw_txq_ctx_free(priv
);
895 iwlagn_free_dma_ptr(priv
, &priv
->kw
);
897 iwlagn_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
902 void iwlagn_txq_ctx_reset(struct iwl_priv
*priv
)
904 int txq_id
, slots_num
;
907 spin_lock_irqsave(&priv
->lock
, flags
);
909 /* Turn off all Tx DMA fifos */
910 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
912 /* Tell NIC where to find the "keep warm" buffer */
913 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
915 spin_unlock_irqrestore(&priv
->lock
, flags
);
917 /* Alloc and init all Tx queues, including the command queue (#4) */
918 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
919 slots_num
= txq_id
== IWL_CMD_QUEUE_NUM
?
920 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
921 iwl_tx_queue_reset(priv
, &priv
->txq
[txq_id
], slots_num
, txq_id
);
926 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
928 void iwlagn_txq_ctx_stop(struct iwl_priv
*priv
)
933 /* Turn off all Tx DMA fifos */
934 spin_lock_irqsave(&priv
->lock
, flags
);
936 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
938 /* Stop each Tx DMA channel, and wait for it to be idle */
939 for (ch
= 0; ch
< priv
->hw_params
.dma_chnl_num
; ch
++) {
940 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
941 iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
942 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
945 spin_unlock_irqrestore(&priv
->lock
, flags
);
949 * Find first available (lowest unused) Tx Queue, mark it "active".
950 * Called only when finding queue for aggregation.
951 * Should never return anything < 7, because they should already
952 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
954 static int iwlagn_txq_ctx_activate_free(struct iwl_priv
*priv
)
958 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
959 if (!test_and_set_bit(txq_id
, &priv
->txq_ctx_active_msk
))
964 int iwlagn_tx_agg_start(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
,
965 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
)
972 struct iwl_tid_data
*tid_data
;
974 tx_fifo
= get_fifo_from_tid(tid
);
975 if (unlikely(tx_fifo
< 0))
978 IWL_WARN(priv
, "%s on ra = %pM tid = %d\n",
979 __func__
, sta
->addr
, tid
);
981 sta_id
= iwl_sta_id(sta
);
982 if (sta_id
== IWL_INVALID_STATION
) {
983 IWL_ERR(priv
, "Start AGG on invalid station\n");
986 if (unlikely(tid
>= MAX_TID_COUNT
))
989 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_OFF
) {
990 IWL_ERR(priv
, "Start AGG when state is not IWL_AGG_OFF !\n");
994 txq_id
= iwlagn_txq_ctx_activate_free(priv
);
996 IWL_ERR(priv
, "No free aggregation queue available\n");
1000 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1001 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1002 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1003 tid_data
->agg
.txq_id
= txq_id
;
1004 priv
->txq
[txq_id
].swq_id
= iwl_virtual_agg_queue_num(get_ac_from_tid(tid
), txq_id
);
1005 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1007 ret
= priv
->cfg
->ops
->lib
->txq_agg_enable(priv
, txq_id
, tx_fifo
,
1012 if (tid_data
->tfds_in_queue
== 0) {
1013 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1014 tid_data
->agg
.state
= IWL_AGG_ON
;
1015 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
1017 IWL_DEBUG_HT(priv
, "HW queue is NOT empty: %d packets in HW queue\n",
1018 tid_data
->tfds_in_queue
);
1019 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
1024 int iwlagn_tx_agg_stop(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
,
1025 struct ieee80211_sta
*sta
, u16 tid
)
1027 int tx_fifo_id
, txq_id
, sta_id
, ssn
= -1;
1028 struct iwl_tid_data
*tid_data
;
1029 int write_ptr
, read_ptr
;
1030 unsigned long flags
;
1032 tx_fifo_id
= get_fifo_from_tid(tid
);
1033 if (unlikely(tx_fifo_id
< 0))
1036 sta_id
= iwl_sta_id(sta
);
1038 if (sta_id
== IWL_INVALID_STATION
) {
1039 IWL_ERR(priv
, "Invalid station for AGG tid %d\n", tid
);
1043 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
==
1044 IWL_EMPTYING_HW_QUEUE_ADDBA
) {
1045 IWL_DEBUG_HT(priv
, "AGG stop before setup done\n");
1046 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
1047 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1051 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_ON
)
1052 IWL_WARN(priv
, "Stopping AGG while state not ON or starting\n");
1054 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1055 ssn
= (tid_data
->seq_number
& IEEE80211_SCTL_SEQ
) >> 4;
1056 txq_id
= tid_data
->agg
.txq_id
;
1057 write_ptr
= priv
->txq
[txq_id
].q
.write_ptr
;
1058 read_ptr
= priv
->txq
[txq_id
].q
.read_ptr
;
1060 /* The queue is not empty */
1061 if (write_ptr
!= read_ptr
) {
1062 IWL_DEBUG_HT(priv
, "Stopping a non empty AGG HW QUEUE\n");
1063 priv
->stations
[sta_id
].tid
[tid
].agg
.state
=
1064 IWL_EMPTYING_HW_QUEUE_DELBA
;
1068 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1069 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1071 spin_lock_irqsave(&priv
->lock
, flags
);
1073 * the only reason this call can fail is queue number out of range,
1074 * which can happen if uCode is reloaded and all the station
1075 * information are lost. if it is outside the range, there is no need
1076 * to deactivate the uCode queue, just return "success" to allow
1077 * mac80211 to clean up it own data.
1079 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
, ssn
,
1081 spin_unlock_irqrestore(&priv
->lock
, flags
);
1083 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
1088 int iwlagn_txq_check_empty(struct iwl_priv
*priv
,
1089 int sta_id
, u8 tid
, int txq_id
)
1091 struct iwl_queue
*q
= &priv
->txq
[txq_id
].q
;
1092 u8
*addr
= priv
->stations
[sta_id
].sta
.sta
.addr
;
1093 struct iwl_tid_data
*tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1095 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1096 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1097 /* We are reclaiming the last packet of the */
1098 /* aggregated HW queue */
1099 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1100 (q
->read_ptr
== q
->write_ptr
)) {
1101 u16 ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1102 int tx_fifo
= get_fifo_from_tid(tid
);
1103 IWL_DEBUG_HT(priv
, "HW queue empty: continue DELBA flow\n");
1104 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
,
1106 tid_data
->agg
.state
= IWL_AGG_OFF
;
1107 ieee80211_stop_tx_ba_cb_irqsafe(priv
->vif
, addr
, tid
);
1110 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1111 /* We are reclaiming the last packet of the queue */
1112 if (tid_data
->tfds_in_queue
== 0) {
1113 IWL_DEBUG_HT(priv
, "HW queue empty: continue ADDBA flow\n");
1114 tid_data
->agg
.state
= IWL_AGG_ON
;
1115 ieee80211_start_tx_ba_cb_irqsafe(priv
->vif
, addr
, tid
);
1122 static void iwlagn_tx_status(struct iwl_priv
*priv
, struct sk_buff
*skb
)
1124 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1125 struct ieee80211_sta
*sta
;
1126 struct iwl_station_priv
*sta_priv
;
1129 sta
= ieee80211_find_sta(priv
->vif
, hdr
->addr1
);
1131 sta_priv
= (void *)sta
->drv_priv
;
1132 /* avoid atomic ops if this isn't a client */
1133 if (sta_priv
->client
&&
1134 atomic_dec_return(&sta_priv
->pending_frames
) == 0)
1135 ieee80211_sta_block_awake(priv
->hw
, sta
, false);
1139 ieee80211_tx_status_irqsafe(priv
->hw
, skb
);
1142 int iwlagn_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1144 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1145 struct iwl_queue
*q
= &txq
->q
;
1146 struct iwl_tx_info
*tx_info
;
1148 struct ieee80211_hdr
*hdr
;
1150 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1151 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1152 "is out of range [0-%d] %d %d.\n", txq_id
,
1153 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1157 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
);
1158 q
->read_ptr
!= index
;
1159 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1161 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1162 iwlagn_tx_status(priv
, tx_info
->skb
[0]);
1164 hdr
= (struct ieee80211_hdr
*)tx_info
->skb
[0]->data
;
1165 if (hdr
&& ieee80211_is_data_qos(hdr
->frame_control
))
1167 tx_info
->skb
[0] = NULL
;
1169 if (priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl
)
1170 priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl(priv
, txq
);
1172 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
1178 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1180 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1181 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1183 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv
*priv
,
1184 struct iwl_ht_agg
*agg
,
1185 struct iwl_compressed_ba_resp
*ba_resp
)
1189 u16 seq_ctl
= le16_to_cpu(ba_resp
->seq_ctl
);
1190 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1193 struct ieee80211_tx_info
*info
;
1195 if (unlikely(!agg
->wait_for_ba
)) {
1196 IWL_ERR(priv
, "Received BA when not expected\n");
1200 /* Mark that the expected block-ack response arrived */
1201 agg
->wait_for_ba
= 0;
1202 IWL_DEBUG_TX_REPLY(priv
, "BA %d %d\n", agg
->start_idx
, ba_resp
->seq_ctl
);
1204 /* Calculate shift to align block-ack bits with our Tx window bits */
1205 sh
= agg
->start_idx
- SEQ_TO_INDEX(seq_ctl
>> 4);
1206 if (sh
< 0) /* tbw something is wrong with indices */
1209 /* don't use 64-bit values for now */
1210 bitmap
= le64_to_cpu(ba_resp
->bitmap
) >> sh
;
1212 if (agg
->frame_count
> (64 - sh
)) {
1213 IWL_DEBUG_TX_REPLY(priv
, "more frames than bitmap size");
1217 /* check for success or failure according to the
1218 * transmitted bitmap and block-ack bitmap */
1219 bitmap
&= agg
->bitmap
;
1221 /* For each frame attempted in aggregation,
1222 * update driver's record of tx frame's status. */
1223 for (i
= 0; i
< agg
->frame_count
; i
++) {
1224 ack
= bitmap
& (1ULL << i
);
1226 IWL_DEBUG_TX_REPLY(priv
, "%s ON i=%d idx=%d raw=%d\n",
1227 ack
? "ACK" : "NACK", i
, (agg
->start_idx
+ i
) & 0xff,
1228 agg
->start_idx
+ i
);
1231 info
= IEEE80211_SKB_CB(priv
->txq
[scd_flow
].txb
[agg
->start_idx
].skb
[0]);
1232 memset(&info
->status
, 0, sizeof(info
->status
));
1233 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1234 info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
1235 info
->status
.ampdu_ack_len
= successes
;
1236 info
->status
.ampdu_ack_map
= bitmap
;
1237 info
->status
.ampdu_len
= agg
->frame_count
;
1238 iwlagn_hwrate_to_tx_control(priv
, agg
->rate_n_flags
, info
);
1240 IWL_DEBUG_TX_REPLY(priv
, "Bitmap %llx\n", (unsigned long long)bitmap
);
1246 * translate ucode response to mac80211 tx status control values
1248 void iwlagn_hwrate_to_tx_control(struct iwl_priv
*priv
, u32 rate_n_flags
,
1249 struct ieee80211_tx_info
*info
)
1251 struct ieee80211_tx_rate
*r
= &info
->control
.rates
[0];
1253 info
->antenna_sel_tx
=
1254 ((rate_n_flags
& RATE_MCS_ANT_ABC_MSK
) >> RATE_MCS_ANT_POS
);
1255 if (rate_n_flags
& RATE_MCS_HT_MSK
)
1256 r
->flags
|= IEEE80211_TX_RC_MCS
;
1257 if (rate_n_flags
& RATE_MCS_GF_MSK
)
1258 r
->flags
|= IEEE80211_TX_RC_GREEN_FIELD
;
1259 if (rate_n_flags
& RATE_MCS_HT40_MSK
)
1260 r
->flags
|= IEEE80211_TX_RC_40_MHZ_WIDTH
;
1261 if (rate_n_flags
& RATE_MCS_DUP_MSK
)
1262 r
->flags
|= IEEE80211_TX_RC_DUP_DATA
;
1263 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
1264 r
->flags
|= IEEE80211_TX_RC_SHORT_GI
;
1265 r
->idx
= iwlagn_hwrate_to_mac80211_idx(rate_n_flags
, info
->band
);
1269 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1271 * Handles block-acknowledge notification from device, which reports success
1272 * of frames sent via aggregation.
1274 void iwlagn_rx_reply_compressed_ba(struct iwl_priv
*priv
,
1275 struct iwl_rx_mem_buffer
*rxb
)
1277 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1278 struct iwl_compressed_ba_resp
*ba_resp
= &pkt
->u
.compressed_ba
;
1279 struct iwl_tx_queue
*txq
= NULL
;
1280 struct iwl_ht_agg
*agg
;
1285 /* "flow" corresponds to Tx queue */
1286 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1288 /* "ssn" is start of block-ack Tx window, corresponds to index
1289 * (in Tx queue's circular buffer) of first TFD/frame in window */
1290 u16 ba_resp_scd_ssn
= le16_to_cpu(ba_resp
->scd_ssn
);
1292 if (scd_flow
>= priv
->hw_params
.max_txq_num
) {
1294 "BUG_ON scd_flow is bigger than number of queues\n");
1298 txq
= &priv
->txq
[scd_flow
];
1299 sta_id
= ba_resp
->sta_id
;
1301 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1303 /* Find index just before block-ack window */
1304 index
= iwl_queue_dec_wrap(ba_resp_scd_ssn
& 0xff, txq
->q
.n_bd
);
1306 /* TODO: Need to get this copy more safely - now good for debug */
1308 IWL_DEBUG_TX_REPLY(priv
, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1311 (u8
*) &ba_resp
->sta_addr_lo32
,
1313 IWL_DEBUG_TX_REPLY(priv
, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1314 "%d, scd_ssn = %d\n",
1317 (unsigned long long)le64_to_cpu(ba_resp
->bitmap
),
1320 IWL_DEBUG_TX_REPLY(priv
, "DAT start_idx = %d, bitmap = 0x%llx\n",
1322 (unsigned long long)agg
->bitmap
);
1324 /* Update driver's record of ACK vs. not for each frame in window */
1325 iwlagn_tx_status_reply_compressed_ba(priv
, agg
, ba_resp
);
1327 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1328 * block-ack window (we assume that they've been successfully
1329 * transmitted ... if not, it's too late anyway). */
1330 if (txq
->q
.read_ptr
!= (ba_resp_scd_ssn
& 0xff)) {
1331 /* calculate mac80211 ampdu sw queue to wake */
1332 int freed
= iwlagn_tx_queue_reclaim(priv
, scd_flow
, index
);
1333 iwl_free_tfds_in_queue(priv
, sta_id
, tid
, freed
);
1335 if ((iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1336 priv
->mac80211_registered
&&
1337 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
))
1338 iwl_wake_queue(priv
, txq
->swq_id
);
1340 iwlagn_txq_check_empty(priv
, sta_id
, tid
, scd_flow
);