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Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwlagn_tx_resp *tx_resp,
176 int txq_id, bool is_agg)
177 {
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195 }
196
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200 const char *iwl_get_agg_tx_fail_reason(u16 status)
201 {
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221 }
222 #endif /* CONFIG_IWLWIFI_DEBUG */
223
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
226 struct iwlagn_tx_resp *tx_resp,
227 int txq_id, u16 start_idx)
228 {
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
231 struct ieee80211_hdr *hdr = NULL;
232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
246 idx = start_idx;
247
248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
319 sh = idx - start;
320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
330 bitmap = bitmap << sh;
331 /* Now idx is the new start so sh = 0 */
332 sh = 0;
333 start = idx;
334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
346 sh = start - idx;
347 bitmap = bitmap << sh;
348 /* Now idx is the new start so sh = 0 */
349 start = idx;
350 sh = 0;
351 }
352 /* Sequence number start + sh was sent in this batch */
353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372 }
373
374 void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376 {
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
381 }
382 }
383
384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386 {
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
393 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
398 unsigned long flags;
399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
408 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
409 memset(&info->status, 0, sizeof(info->status));
410
411 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
412 IWLAGN_TX_RES_TID_POS;
413 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
414 IWLAGN_TX_RES_RA_POS;
415
416 spin_lock_irqsave(&priv->sta_lock, flags);
417 if (txq->sched_retry) {
418 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
419 struct iwl_ht_agg *agg;
420
421 agg = &priv->stations[sta_id].tid[tid].agg;
422 /*
423 * If the BT kill count is non-zero, we'll get this
424 * notification again.
425 */
426 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
427 priv->cfg->bt_params &&
428 priv->cfg->bt_params->advanced_bt_coexist) {
429 IWL_WARN(priv, "receive reply tx with bt_kill\n");
430 }
431 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
432
433 /* check if BAR is needed */
434 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
435 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
436
437 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
438 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
439 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
440 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
441 scd_ssn , index, txq_id, txq->swq_id);
442
443 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
444 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
445
446 if (priv->mac80211_registered &&
447 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
448 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
449 if (agg->state == IWL_AGG_OFF)
450 iwl_wake_queue(priv, txq_id);
451 else
452 iwl_wake_queue(priv, txq->swq_id);
453 }
454 }
455 } else {
456 BUG_ON(txq_id != txq->swq_id);
457 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
458 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
459 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
460
461 if (priv->mac80211_registered &&
462 (iwl_queue_space(&txq->q) > txq->q.low_mark))
463 iwl_wake_queue(priv, txq_id);
464 }
465
466 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
467
468 iwl_check_abort_status(priv, tx_resp->frame_count, status);
469 spin_unlock_irqrestore(&priv->sta_lock, flags);
470 }
471
472 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
473 {
474 /* init calibration handlers */
475 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
476 iwlagn_rx_calib_result;
477 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
478 iwlagn_rx_calib_complete;
479 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
480 }
481
482 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
483 {
484 /* in agn, the tx power calibration is done in uCode */
485 priv->disable_tx_power_cal = 1;
486 }
487
488 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
489 {
490 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
491 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
492 }
493
494 int iwlagn_send_tx_power(struct iwl_priv *priv)
495 {
496 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
497 u8 tx_ant_cfg_cmd;
498
499 /* half dBm need to multiply */
500 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
501
502 if (priv->tx_power_lmt_in_half_dbm &&
503 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
504 /*
505 * For the newer devices which using enhanced/extend tx power
506 * table in EEPROM, the format is in half dBm. driver need to
507 * convert to dBm format before report to mac80211.
508 * By doing so, there is a possibility of 1/2 dBm resolution
509 * lost. driver will perform "round-up" operation before
510 * reporting, but it will cause 1/2 dBm tx power over the
511 * regulatory limit. Perform the checking here, if the
512 * "tx_power_user_lmt" is higher than EEPROM value (in
513 * half-dBm format), lower the tx power based on EEPROM
514 */
515 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
516 }
517 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
518 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
519
520 if (IWL_UCODE_API(priv->ucode_ver) == 1)
521 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
522 else
523 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
524
525 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
526 sizeof(tx_power_cmd), &tx_power_cmd,
527 NULL);
528 }
529
530 void iwlagn_temperature(struct iwl_priv *priv)
531 {
532 /* store temperature from statistics (in Celsius) */
533 priv->temperature =
534 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
535 iwl_tt_handler(priv);
536 }
537
538 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
539 {
540 struct iwl_eeprom_calib_hdr {
541 u8 version;
542 u8 pa_type;
543 u16 voltage;
544 } *hdr;
545
546 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
547 EEPROM_CALIB_ALL);
548 return hdr->version;
549
550 }
551
552 /*
553 * EEPROM
554 */
555 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
556 {
557 u16 offset = 0;
558
559 if ((address & INDIRECT_ADDRESS) == 0)
560 return address;
561
562 switch (address & INDIRECT_TYPE_MSK) {
563 case INDIRECT_HOST:
564 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
565 break;
566 case INDIRECT_GENERAL:
567 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
568 break;
569 case INDIRECT_REGULATORY:
570 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
571 break;
572 case INDIRECT_CALIBRATION:
573 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
574 break;
575 case INDIRECT_PROCESS_ADJST:
576 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
577 break;
578 case INDIRECT_OTHERS:
579 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
580 break;
581 default:
582 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
583 address & INDIRECT_TYPE_MSK);
584 break;
585 }
586
587 /* translate the offset from words to byte */
588 return (address & ADDRESS_MSK) + (offset << 1);
589 }
590
591 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
592 size_t offset)
593 {
594 u32 address = eeprom_indirect_address(priv, offset);
595 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
596 return &priv->eeprom[address];
597 }
598
599 struct iwl_mod_params iwlagn_mod_params = {
600 .amsdu_size_8K = 1,
601 .restart_fw = 1,
602 /* the rest are 0 by default */
603 };
604
605 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
606 {
607 unsigned long flags;
608 int i;
609 spin_lock_irqsave(&rxq->lock, flags);
610 INIT_LIST_HEAD(&rxq->rx_free);
611 INIT_LIST_HEAD(&rxq->rx_used);
612 /* Fill the rx_used queue with _all_ of the Rx buffers */
613 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
614 /* In the reset function, these buffers may have been allocated
615 * to an SKB, so we need to unmap and free potential storage */
616 if (rxq->pool[i].page != NULL) {
617 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
618 PAGE_SIZE << priv->hw_params.rx_page_order,
619 PCI_DMA_FROMDEVICE);
620 __iwl_free_pages(priv, rxq->pool[i].page);
621 rxq->pool[i].page = NULL;
622 }
623 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
624 }
625
626 for (i = 0; i < RX_QUEUE_SIZE; i++)
627 rxq->queue[i] = NULL;
628
629 /* Set us so that we have processed and used all buffers, but have
630 * not restocked the Rx queue with fresh buffers */
631 rxq->read = rxq->write = 0;
632 rxq->write_actual = 0;
633 rxq->free_count = 0;
634 spin_unlock_irqrestore(&rxq->lock, flags);
635 }
636
637 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
638 {
639 u32 rb_size;
640 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
641 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
642
643 if (!priv->cfg->base_params->use_isr_legacy)
644 rb_timeout = RX_RB_TIMEOUT;
645
646 if (priv->cfg->mod_params->amsdu_size_8K)
647 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
648 else
649 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
650
651 /* Stop Rx DMA */
652 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
653
654 /* Reset driver's Rx queue write index */
655 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
656
657 /* Tell device where to find RBD circular buffer in DRAM */
658 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
659 (u32)(rxq->bd_dma >> 8));
660
661 /* Tell device where in DRAM to update its Rx status */
662 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
663 rxq->rb_stts_dma >> 4);
664
665 /* Enable Rx DMA
666 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
667 * the credit mechanism in 5000 HW RX FIFO
668 * Direct rx interrupts to hosts
669 * Rx buffer size 4 or 8k
670 * RB timeout 0x10
671 * 256 RBDs
672 */
673 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
674 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
675 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
676 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
677 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
678 rb_size|
679 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
680 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
681
682 /* Set interrupt coalescing timer to default (2048 usecs) */
683 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
684
685 return 0;
686 }
687
688 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
689 {
690 /*
691 * (for documentation purposes)
692 * to set power to V_AUX, do:
693
694 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
695 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
696 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
697 ~APMG_PS_CTRL_MSK_PWR_SRC);
698 */
699
700 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
701 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
702 ~APMG_PS_CTRL_MSK_PWR_SRC);
703 }
704
705 int iwlagn_hw_nic_init(struct iwl_priv *priv)
706 {
707 unsigned long flags;
708 struct iwl_rx_queue *rxq = &priv->rxq;
709 int ret;
710
711 /* nic_init */
712 spin_lock_irqsave(&priv->lock, flags);
713 priv->cfg->ops->lib->apm_ops.init(priv);
714
715 /* Set interrupt coalescing calibration timer to default (512 usecs) */
716 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
717
718 spin_unlock_irqrestore(&priv->lock, flags);
719
720 iwlagn_set_pwr_vmain(priv);
721
722 priv->cfg->ops->lib->apm_ops.config(priv);
723
724 /* Allocate the RX queue, or reset if it is already allocated */
725 if (!rxq->bd) {
726 ret = iwl_rx_queue_alloc(priv);
727 if (ret) {
728 IWL_ERR(priv, "Unable to initialize Rx queue\n");
729 return -ENOMEM;
730 }
731 } else
732 iwlagn_rx_queue_reset(priv, rxq);
733
734 iwlagn_rx_replenish(priv);
735
736 iwlagn_rx_init(priv, rxq);
737
738 spin_lock_irqsave(&priv->lock, flags);
739
740 rxq->need_update = 1;
741 iwl_rx_queue_update_write_ptr(priv, rxq);
742
743 spin_unlock_irqrestore(&priv->lock, flags);
744
745 /* Allocate or reset and init all Tx and Command queues */
746 if (!priv->txq) {
747 ret = iwlagn_txq_ctx_alloc(priv);
748 if (ret)
749 return ret;
750 } else
751 iwlagn_txq_ctx_reset(priv);
752
753 set_bit(STATUS_INIT, &priv->status);
754
755 return 0;
756 }
757
758 /**
759 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
760 */
761 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
762 dma_addr_t dma_addr)
763 {
764 return cpu_to_le32((u32)(dma_addr >> 8));
765 }
766
767 /**
768 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
769 *
770 * If there are slots in the RX queue that need to be restocked,
771 * and we have free pre-allocated buffers, fill the ranks as much
772 * as we can, pulling from rx_free.
773 *
774 * This moves the 'write' index forward to catch up with 'processed', and
775 * also updates the memory address in the firmware to reference the new
776 * target buffer.
777 */
778 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
779 {
780 struct iwl_rx_queue *rxq = &priv->rxq;
781 struct list_head *element;
782 struct iwl_rx_mem_buffer *rxb;
783 unsigned long flags;
784
785 spin_lock_irqsave(&rxq->lock, flags);
786 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
787 /* The overwritten rxb must be a used one */
788 rxb = rxq->queue[rxq->write];
789 BUG_ON(rxb && rxb->page);
790
791 /* Get next free Rx buffer, remove from free list */
792 element = rxq->rx_free.next;
793 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
794 list_del(element);
795
796 /* Point to Rx buffer via next RBD in circular buffer */
797 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
798 rxb->page_dma);
799 rxq->queue[rxq->write] = rxb;
800 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
801 rxq->free_count--;
802 }
803 spin_unlock_irqrestore(&rxq->lock, flags);
804 /* If the pre-allocated buffer pool is dropping low, schedule to
805 * refill it */
806 if (rxq->free_count <= RX_LOW_WATERMARK)
807 queue_work(priv->workqueue, &priv->rx_replenish);
808
809
810 /* If we've added more space for the firmware to place data, tell it.
811 * Increment device's write pointer in multiples of 8. */
812 if (rxq->write_actual != (rxq->write & ~0x7)) {
813 spin_lock_irqsave(&rxq->lock, flags);
814 rxq->need_update = 1;
815 spin_unlock_irqrestore(&rxq->lock, flags);
816 iwl_rx_queue_update_write_ptr(priv, rxq);
817 }
818 }
819
820 /**
821 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
822 *
823 * When moving to rx_free an SKB is allocated for the slot.
824 *
825 * Also restock the Rx queue via iwl_rx_queue_restock.
826 * This is called as a scheduled work item (except for during initialization)
827 */
828 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
829 {
830 struct iwl_rx_queue *rxq = &priv->rxq;
831 struct list_head *element;
832 struct iwl_rx_mem_buffer *rxb;
833 struct page *page;
834 unsigned long flags;
835 gfp_t gfp_mask = priority;
836
837 while (1) {
838 spin_lock_irqsave(&rxq->lock, flags);
839 if (list_empty(&rxq->rx_used)) {
840 spin_unlock_irqrestore(&rxq->lock, flags);
841 return;
842 }
843 spin_unlock_irqrestore(&rxq->lock, flags);
844
845 if (rxq->free_count > RX_LOW_WATERMARK)
846 gfp_mask |= __GFP_NOWARN;
847
848 if (priv->hw_params.rx_page_order > 0)
849 gfp_mask |= __GFP_COMP;
850
851 /* Alloc a new receive buffer */
852 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
853 if (!page) {
854 if (net_ratelimit())
855 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
856 "order: %d\n",
857 priv->hw_params.rx_page_order);
858
859 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
860 net_ratelimit())
861 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
862 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
863 rxq->free_count);
864 /* We don't reschedule replenish work here -- we will
865 * call the restock method and if it still needs
866 * more buffers it will schedule replenish */
867 return;
868 }
869
870 spin_lock_irqsave(&rxq->lock, flags);
871
872 if (list_empty(&rxq->rx_used)) {
873 spin_unlock_irqrestore(&rxq->lock, flags);
874 __free_pages(page, priv->hw_params.rx_page_order);
875 return;
876 }
877 element = rxq->rx_used.next;
878 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
879 list_del(element);
880
881 spin_unlock_irqrestore(&rxq->lock, flags);
882
883 BUG_ON(rxb->page);
884 rxb->page = page;
885 /* Get physical address of the RB */
886 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
887 PAGE_SIZE << priv->hw_params.rx_page_order,
888 PCI_DMA_FROMDEVICE);
889 /* dma address must be no more than 36 bits */
890 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
891 /* and also 256 byte aligned! */
892 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
893
894 spin_lock_irqsave(&rxq->lock, flags);
895
896 list_add_tail(&rxb->list, &rxq->rx_free);
897 rxq->free_count++;
898 priv->alloc_rxb_page++;
899
900 spin_unlock_irqrestore(&rxq->lock, flags);
901 }
902 }
903
904 void iwlagn_rx_replenish(struct iwl_priv *priv)
905 {
906 unsigned long flags;
907
908 iwlagn_rx_allocate(priv, GFP_KERNEL);
909
910 spin_lock_irqsave(&priv->lock, flags);
911 iwlagn_rx_queue_restock(priv);
912 spin_unlock_irqrestore(&priv->lock, flags);
913 }
914
915 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
916 {
917 iwlagn_rx_allocate(priv, GFP_ATOMIC);
918
919 iwlagn_rx_queue_restock(priv);
920 }
921
922 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
923 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
924 * This free routine walks the list of POOL entries and if SKB is set to
925 * non NULL it is unmapped and freed
926 */
927 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
928 {
929 int i;
930 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
931 if (rxq->pool[i].page != NULL) {
932 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
933 PAGE_SIZE << priv->hw_params.rx_page_order,
934 PCI_DMA_FROMDEVICE);
935 __iwl_free_pages(priv, rxq->pool[i].page);
936 rxq->pool[i].page = NULL;
937 }
938 }
939
940 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
941 rxq->bd_dma);
942 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
943 rxq->rb_stts, rxq->rb_stts_dma);
944 rxq->bd = NULL;
945 rxq->rb_stts = NULL;
946 }
947
948 int iwlagn_rxq_stop(struct iwl_priv *priv)
949 {
950
951 /* stop Rx DMA */
952 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
953 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
954 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
955
956 return 0;
957 }
958
959 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
960 {
961 int idx = 0;
962 int band_offset = 0;
963
964 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
965 if (rate_n_flags & RATE_MCS_HT_MSK) {
966 idx = (rate_n_flags & 0xff);
967 return idx;
968 /* Legacy rate format, search for match in table */
969 } else {
970 if (band == IEEE80211_BAND_5GHZ)
971 band_offset = IWL_FIRST_OFDM_RATE;
972 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
973 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
974 return idx - band_offset;
975 }
976
977 return -1;
978 }
979
980 /* Calc max signal level (dBm) among 3 possible receivers */
981 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
982 struct iwl_rx_phy_res *rx_resp)
983 {
984 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
985 }
986
987 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
988 {
989 u32 decrypt_out = 0;
990
991 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
992 RX_RES_STATUS_STATION_FOUND)
993 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
994 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
995
996 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
997
998 /* packet was not encrypted */
999 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1000 RX_RES_STATUS_SEC_TYPE_NONE)
1001 return decrypt_out;
1002
1003 /* packet was encrypted with unknown alg */
1004 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1005 RX_RES_STATUS_SEC_TYPE_ERR)
1006 return decrypt_out;
1007
1008 /* decryption was not done in HW */
1009 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1010 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1011 return decrypt_out;
1012
1013 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1014
1015 case RX_RES_STATUS_SEC_TYPE_CCMP:
1016 /* alg is CCM: check MIC only */
1017 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1018 /* Bad MIC */
1019 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1020 else
1021 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1022
1023 break;
1024
1025 case RX_RES_STATUS_SEC_TYPE_TKIP:
1026 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1027 /* Bad TTAK */
1028 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1029 break;
1030 }
1031 /* fall through if TTAK OK */
1032 default:
1033 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1034 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1035 else
1036 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1037 break;
1038 }
1039
1040 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1041 decrypt_in, decrypt_out);
1042
1043 return decrypt_out;
1044 }
1045
1046 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1047 struct ieee80211_hdr *hdr,
1048 u16 len,
1049 u32 ampdu_status,
1050 struct iwl_rx_mem_buffer *rxb,
1051 struct ieee80211_rx_status *stats)
1052 {
1053 struct sk_buff *skb;
1054 __le16 fc = hdr->frame_control;
1055
1056 /* We only process data packets if the interface is open */
1057 if (unlikely(!priv->is_open)) {
1058 IWL_DEBUG_DROP_LIMIT(priv,
1059 "Dropping packet while interface is not open.\n");
1060 return;
1061 }
1062
1063 /* In case of HW accelerated crypto and bad decryption, drop */
1064 if (!priv->cfg->mod_params->sw_crypto &&
1065 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1066 return;
1067
1068 skb = dev_alloc_skb(128);
1069 if (!skb) {
1070 IWL_ERR(priv, "dev_alloc_skb failed\n");
1071 return;
1072 }
1073
1074 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1075
1076 iwl_update_stats(priv, false, fc, len);
1077 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1078
1079 ieee80211_rx(priv->hw, skb);
1080 priv->alloc_rxb_page--;
1081 rxb->page = NULL;
1082 }
1083
1084 /* Called for REPLY_RX (legacy ABG frames), or
1085 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1086 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1087 struct iwl_rx_mem_buffer *rxb)
1088 {
1089 struct ieee80211_hdr *header;
1090 struct ieee80211_rx_status rx_status;
1091 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1092 struct iwl_rx_phy_res *phy_res;
1093 __le32 rx_pkt_status;
1094 struct iwl_rx_mpdu_res_start *amsdu;
1095 u32 len;
1096 u32 ampdu_status;
1097 u32 rate_n_flags;
1098
1099 /**
1100 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1101 * REPLY_RX: physical layer info is in this buffer
1102 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1103 * command and cached in priv->last_phy_res
1104 *
1105 * Here we set up local variables depending on which command is
1106 * received.
1107 */
1108 if (pkt->hdr.cmd == REPLY_RX) {
1109 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1110 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1111 + phy_res->cfg_phy_cnt);
1112
1113 len = le16_to_cpu(phy_res->byte_count);
1114 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1115 phy_res->cfg_phy_cnt + len);
1116 ampdu_status = le32_to_cpu(rx_pkt_status);
1117 } else {
1118 if (!priv->_agn.last_phy_res_valid) {
1119 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1120 return;
1121 }
1122 phy_res = &priv->_agn.last_phy_res;
1123 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1124 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1125 len = le16_to_cpu(amsdu->byte_count);
1126 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1127 ampdu_status = iwlagn_translate_rx_status(priv,
1128 le32_to_cpu(rx_pkt_status));
1129 }
1130
1131 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1132 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1133 phy_res->cfg_phy_cnt);
1134 return;
1135 }
1136
1137 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1138 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1139 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1140 le32_to_cpu(rx_pkt_status));
1141 return;
1142 }
1143
1144 /* This will be used in several places later */
1145 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1146
1147 /* rx_status carries information about the packet to mac80211 */
1148 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1149 rx_status.freq =
1150 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1151 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1152 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1153 rx_status.rate_idx =
1154 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1155 rx_status.flag = 0;
1156
1157 /* TSF isn't reliable. In order to allow smooth user experience,
1158 * this W/A doesn't propagate it to the mac80211 */
1159 /*rx_status.flag |= RX_FLAG_TSFT;*/
1160
1161 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1162
1163 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1164 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1165
1166 iwl_dbg_log_rx_data_frame(priv, len, header);
1167 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1168 rx_status.signal, (unsigned long long)rx_status.mactime);
1169
1170 /*
1171 * "antenna number"
1172 *
1173 * It seems that the antenna field in the phy flags value
1174 * is actually a bit field. This is undefined by radiotap,
1175 * it wants an actual antenna number but I always get "7"
1176 * for most legacy frames I receive indicating that the
1177 * same frame was received on all three RX chains.
1178 *
1179 * I think this field should be removed in favor of a
1180 * new 802.11n radiotap field "RX chains" that is defined
1181 * as a bitmask.
1182 */
1183 rx_status.antenna =
1184 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1185 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1186
1187 /* set the preamble flag if appropriate */
1188 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1189 rx_status.flag |= RX_FLAG_SHORTPRE;
1190
1191 /* Set up the HT phy flags */
1192 if (rate_n_flags & RATE_MCS_HT_MSK)
1193 rx_status.flag |= RX_FLAG_HT;
1194 if (rate_n_flags & RATE_MCS_HT40_MSK)
1195 rx_status.flag |= RX_FLAG_40MHZ;
1196 if (rate_n_flags & RATE_MCS_SGI_MSK)
1197 rx_status.flag |= RX_FLAG_SHORT_GI;
1198
1199 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1200 rxb, &rx_status);
1201 }
1202
1203 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1204 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1205 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1206 struct iwl_rx_mem_buffer *rxb)
1207 {
1208 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1209 priv->_agn.last_phy_res_valid = true;
1210 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1211 sizeof(struct iwl_rx_phy_res));
1212 }
1213
1214 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1215 struct ieee80211_vif *vif,
1216 enum ieee80211_band band,
1217 struct iwl_scan_channel *scan_ch)
1218 {
1219 const struct ieee80211_supported_band *sband;
1220 u16 passive_dwell = 0;
1221 u16 active_dwell = 0;
1222 int added = 0;
1223 u16 channel = 0;
1224
1225 sband = iwl_get_hw_mode(priv, band);
1226 if (!sband) {
1227 IWL_ERR(priv, "invalid band\n");
1228 return added;
1229 }
1230
1231 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1232 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1233
1234 if (passive_dwell <= active_dwell)
1235 passive_dwell = active_dwell + 1;
1236
1237 channel = iwl_get_single_channel_number(priv, band);
1238 if (channel) {
1239 scan_ch->channel = cpu_to_le16(channel);
1240 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1241 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1242 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1243 /* Set txpower levels to defaults */
1244 scan_ch->dsp_atten = 110;
1245 if (band == IEEE80211_BAND_5GHZ)
1246 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1247 else
1248 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1249 added++;
1250 } else
1251 IWL_ERR(priv, "no valid channel found\n");
1252 return added;
1253 }
1254
1255 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1256 struct ieee80211_vif *vif,
1257 enum ieee80211_band band,
1258 u8 is_active, u8 n_probes,
1259 struct iwl_scan_channel *scan_ch)
1260 {
1261 struct ieee80211_channel *chan;
1262 const struct ieee80211_supported_band *sband;
1263 const struct iwl_channel_info *ch_info;
1264 u16 passive_dwell = 0;
1265 u16 active_dwell = 0;
1266 int added, i;
1267 u16 channel;
1268
1269 sband = iwl_get_hw_mode(priv, band);
1270 if (!sband)
1271 return 0;
1272
1273 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1274 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1275
1276 if (passive_dwell <= active_dwell)
1277 passive_dwell = active_dwell + 1;
1278
1279 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1280 chan = priv->scan_request->channels[i];
1281
1282 if (chan->band != band)
1283 continue;
1284
1285 channel = chan->hw_value;
1286 scan_ch->channel = cpu_to_le16(channel);
1287
1288 ch_info = iwl_get_channel_info(priv, band, channel);
1289 if (!is_channel_valid(ch_info)) {
1290 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1291 channel);
1292 continue;
1293 }
1294
1295 if (!is_active || is_channel_passive(ch_info) ||
1296 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1297 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1298 else
1299 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1300
1301 if (n_probes)
1302 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1303
1304 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1305 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1306
1307 /* Set txpower levels to defaults */
1308 scan_ch->dsp_atten = 110;
1309
1310 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1311 * power level:
1312 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1313 */
1314 if (band == IEEE80211_BAND_5GHZ)
1315 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1316 else
1317 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1318
1319 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1320 channel, le32_to_cpu(scan_ch->type),
1321 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1322 "ACTIVE" : "PASSIVE",
1323 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1324 active_dwell : passive_dwell);
1325
1326 scan_ch++;
1327 added++;
1328 }
1329
1330 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1331 return added;
1332 }
1333
1334 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1335 {
1336 struct iwl_host_cmd cmd = {
1337 .id = REPLY_SCAN_CMD,
1338 .len = sizeof(struct iwl_scan_cmd),
1339 .flags = CMD_SIZE_HUGE,
1340 };
1341 struct iwl_scan_cmd *scan;
1342 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1343 u32 rate_flags = 0;
1344 u16 cmd_len;
1345 u16 rx_chain = 0;
1346 enum ieee80211_band band;
1347 u8 n_probes = 0;
1348 u8 rx_ant = priv->hw_params.valid_rx_ant;
1349 u8 rate;
1350 bool is_active = false;
1351 int chan_mod;
1352 u8 active_chains;
1353 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1354 int ret;
1355
1356 lockdep_assert_held(&priv->mutex);
1357
1358 if (vif)
1359 ctx = iwl_rxon_ctx_from_vif(vif);
1360
1361 if (!priv->scan_cmd) {
1362 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1363 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1364 if (!priv->scan_cmd) {
1365 IWL_DEBUG_SCAN(priv,
1366 "fail to allocate memory for scan\n");
1367 return -ENOMEM;
1368 }
1369 }
1370 scan = priv->scan_cmd;
1371 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1372
1373 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1374 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1375
1376 if (iwl_is_any_associated(priv)) {
1377 u16 interval = 0;
1378 u32 extra;
1379 u32 suspend_time = 100;
1380 u32 scan_suspend_time = 100;
1381 unsigned long flags;
1382
1383 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1384 spin_lock_irqsave(&priv->lock, flags);
1385 if (priv->is_internal_short_scan)
1386 interval = 0;
1387 else
1388 interval = vif->bss_conf.beacon_int;
1389 spin_unlock_irqrestore(&priv->lock, flags);
1390
1391 scan->suspend_time = 0;
1392 scan->max_out_time = cpu_to_le32(200 * 1024);
1393 if (!interval)
1394 interval = suspend_time;
1395
1396 extra = (suspend_time / interval) << 22;
1397 scan_suspend_time = (extra |
1398 ((suspend_time % interval) * 1024));
1399 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1400 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1401 scan_suspend_time, interval);
1402 }
1403
1404 if (priv->is_internal_short_scan) {
1405 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1406 } else if (priv->scan_request->n_ssids) {
1407 int i, p = 0;
1408 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1409 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1410 /* always does wildcard anyway */
1411 if (!priv->scan_request->ssids[i].ssid_len)
1412 continue;
1413 scan->direct_scan[p].id = WLAN_EID_SSID;
1414 scan->direct_scan[p].len =
1415 priv->scan_request->ssids[i].ssid_len;
1416 memcpy(scan->direct_scan[p].ssid,
1417 priv->scan_request->ssids[i].ssid,
1418 priv->scan_request->ssids[i].ssid_len);
1419 n_probes++;
1420 p++;
1421 }
1422 is_active = true;
1423 } else
1424 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1425
1426 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1427 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1428 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1429
1430 switch (priv->scan_band) {
1431 case IEEE80211_BAND_2GHZ:
1432 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1433 chan_mod = le32_to_cpu(
1434 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1435 RXON_FLG_CHANNEL_MODE_MSK)
1436 >> RXON_FLG_CHANNEL_MODE_POS;
1437 if (chan_mod == CHANNEL_MODE_PURE_40) {
1438 rate = IWL_RATE_6M_PLCP;
1439 } else {
1440 rate = IWL_RATE_1M_PLCP;
1441 rate_flags = RATE_MCS_CCK_MSK;
1442 }
1443 /*
1444 * Internal scans are passive, so we can indiscriminately set
1445 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1446 */
1447 if (priv->cfg->bt_params &&
1448 priv->cfg->bt_params->advanced_bt_coexist)
1449 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1450 break;
1451 case IEEE80211_BAND_5GHZ:
1452 rate = IWL_RATE_6M_PLCP;
1453 break;
1454 default:
1455 IWL_WARN(priv, "Invalid scan band\n");
1456 return -EIO;
1457 }
1458
1459 /*
1460 * If active scanning is requested but a certain channel is
1461 * marked passive, we can do active scanning if we detect
1462 * transmissions.
1463 *
1464 * There is an issue with some firmware versions that triggers
1465 * a sysassert on a "good CRC threshold" of zero (== disabled),
1466 * on a radar channel even though this means that we should NOT
1467 * send probes.
1468 *
1469 * The "good CRC threshold" is the number of frames that we
1470 * need to receive during our dwell time on a channel before
1471 * sending out probes -- setting this to a huge value will
1472 * mean we never reach it, but at the same time work around
1473 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1474 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1475 */
1476 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1477 IWL_GOOD_CRC_TH_NEVER;
1478
1479 band = priv->scan_band;
1480
1481 if (priv->cfg->scan_rx_antennas[band])
1482 rx_ant = priv->cfg->scan_rx_antennas[band];
1483
1484 if (priv->cfg->scan_tx_antennas[band])
1485 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1486
1487 if (priv->cfg->bt_params &&
1488 priv->cfg->bt_params->advanced_bt_coexist &&
1489 priv->bt_full_concurrent) {
1490 /* operated as 1x1 in full concurrency mode */
1491 scan_tx_antennas = first_antenna(
1492 priv->cfg->scan_tx_antennas[band]);
1493 }
1494
1495 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1496 scan_tx_antennas);
1497 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1498 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1499
1500 /* In power save mode use one chain, otherwise use all chains */
1501 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1502 /* rx_ant has been set to all valid chains previously */
1503 active_chains = rx_ant &
1504 ((u8)(priv->chain_noise_data.active_chains));
1505 if (!active_chains)
1506 active_chains = rx_ant;
1507
1508 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1509 priv->chain_noise_data.active_chains);
1510
1511 rx_ant = first_antenna(active_chains);
1512 }
1513 if (priv->cfg->bt_params &&
1514 priv->cfg->bt_params->advanced_bt_coexist &&
1515 priv->bt_full_concurrent) {
1516 /* operated as 1x1 in full concurrency mode */
1517 rx_ant = first_antenna(rx_ant);
1518 }
1519
1520 /* MIMO is not used here, but value is required */
1521 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1522 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1523 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1524 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1525 scan->rx_chain = cpu_to_le16(rx_chain);
1526 if (!priv->is_internal_short_scan) {
1527 cmd_len = iwl_fill_probe_req(priv,
1528 (struct ieee80211_mgmt *)scan->data,
1529 vif->addr,
1530 priv->scan_request->ie,
1531 priv->scan_request->ie_len,
1532 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1533 } else {
1534 /* use bcast addr, will not be transmitted but must be valid */
1535 cmd_len = iwl_fill_probe_req(priv,
1536 (struct ieee80211_mgmt *)scan->data,
1537 iwl_bcast_addr, NULL, 0,
1538 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1539
1540 }
1541 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1542
1543 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1544 RXON_FILTER_BCON_AWARE_MSK);
1545
1546 if (priv->is_internal_short_scan) {
1547 scan->channel_count =
1548 iwl_get_single_channel_for_scan(priv, vif, band,
1549 (void *)&scan->data[le16_to_cpu(
1550 scan->tx_cmd.len)]);
1551 } else {
1552 scan->channel_count =
1553 iwl_get_channels_for_scan(priv, vif, band,
1554 is_active, n_probes,
1555 (void *)&scan->data[le16_to_cpu(
1556 scan->tx_cmd.len)]);
1557 }
1558 if (scan->channel_count == 0) {
1559 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1560 return -EIO;
1561 }
1562
1563 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1564 scan->channel_count * sizeof(struct iwl_scan_channel);
1565 cmd.data = scan;
1566 scan->len = cpu_to_le16(cmd.len);
1567
1568 /* set scan bit here for PAN params */
1569 set_bit(STATUS_SCAN_HW, &priv->status);
1570
1571 if (priv->cfg->ops->hcmd->set_pan_params) {
1572 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1573 if (ret)
1574 return ret;
1575 }
1576
1577 ret = iwl_send_cmd_sync(priv, &cmd);
1578 if (ret) {
1579 clear_bit(STATUS_SCAN_HW, &priv->status);
1580 if (priv->cfg->ops->hcmd->set_pan_params)
1581 priv->cfg->ops->hcmd->set_pan_params(priv);
1582 }
1583
1584 return ret;
1585 }
1586
1587 void iwlagn_post_scan(struct iwl_priv *priv)
1588 {
1589 struct iwl_rxon_context *ctx;
1590
1591 /*
1592 * Since setting the RXON may have been deferred while
1593 * performing the scan, fire one off if needed
1594 */
1595 for_each_context(priv, ctx)
1596 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
1597 iwlagn_commit_rxon(priv, ctx);
1598
1599 if (priv->cfg->ops->hcmd->set_pan_params)
1600 priv->cfg->ops->hcmd->set_pan_params(priv);
1601 }
1602
1603 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1604 struct ieee80211_vif *vif, bool add)
1605 {
1606 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1607
1608 if (add)
1609 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1610 vif->bss_conf.bssid,
1611 &vif_priv->ibss_bssid_sta_id);
1612 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1613 vif->bss_conf.bssid);
1614 }
1615
1616 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1617 int sta_id, int tid, int freed)
1618 {
1619 lockdep_assert_held(&priv->sta_lock);
1620
1621 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1622 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1623 else {
1624 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1625 priv->stations[sta_id].tid[tid].tfds_in_queue,
1626 freed);
1627 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1628 }
1629 }
1630
1631 #define IWL_FLUSH_WAIT_MS 2000
1632
1633 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1634 {
1635 struct iwl_tx_queue *txq;
1636 struct iwl_queue *q;
1637 int cnt;
1638 unsigned long now = jiffies;
1639 int ret = 0;
1640
1641 /* waiting for all the tx frames complete might take a while */
1642 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1643 if (cnt == priv->cmd_queue)
1644 continue;
1645 txq = &priv->txq[cnt];
1646 q = &txq->q;
1647 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1648 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1649 msleep(1);
1650
1651 if (q->read_ptr != q->write_ptr) {
1652 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1653 ret = -ETIMEDOUT;
1654 break;
1655 }
1656 }
1657 return ret;
1658 }
1659
1660 #define IWL_TX_QUEUE_MSK 0xfffff
1661
1662 /**
1663 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1664 *
1665 * pre-requirements:
1666 * 1. acquire mutex before calling
1667 * 2. make sure rf is on and not in exit state
1668 */
1669 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1670 {
1671 struct iwl_txfifo_flush_cmd flush_cmd;
1672 struct iwl_host_cmd cmd = {
1673 .id = REPLY_TXFIFO_FLUSH,
1674 .len = sizeof(struct iwl_txfifo_flush_cmd),
1675 .flags = CMD_SYNC,
1676 .data = &flush_cmd,
1677 };
1678
1679 might_sleep();
1680
1681 memset(&flush_cmd, 0, sizeof(flush_cmd));
1682 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1683 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1684 if (priv->cfg->sku & IWL_SKU_N)
1685 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1686
1687 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1688 flush_cmd.fifo_control);
1689 flush_cmd.flush_control = cpu_to_le16(flush_control);
1690
1691 return iwl_send_cmd(priv, &cmd);
1692 }
1693
1694 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1695 {
1696 mutex_lock(&priv->mutex);
1697 ieee80211_stop_queues(priv->hw);
1698 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1699 IWL_ERR(priv, "flush request fail\n");
1700 goto done;
1701 }
1702 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1703 iwlagn_wait_tx_queue_empty(priv);
1704 done:
1705 ieee80211_wake_queues(priv->hw);
1706 mutex_unlock(&priv->mutex);
1707 }
1708
1709 /*
1710 * BT coex
1711 */
1712 /*
1713 * Macros to access the lookup table.
1714 *
1715 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1716 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1717 *
1718 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1719 *
1720 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1721 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1722 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1723 *
1724 * These macros encode that format.
1725 */
1726 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1727 wifi_txrx, wifi_sh_ant_req) \
1728 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1729 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1730
1731 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1732 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1733 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1734 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1735 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1736 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1737 wifi_sh_ant_req))))
1738 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1739 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1740 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1741 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1742 wifi_sh_ant_req))
1743 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1744 wifi_req, wifi_prio, wifi_txrx, \
1745 wifi_sh_ant_req) \
1746 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1747 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1748 wifi_sh_ant_req))
1749
1750 #define LUT_WLAN_KILL_OP(lut, op, val) \
1751 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1752 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1753 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1754 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1755 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1756 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1757 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1758 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1759 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1760 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1761 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1762 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1763 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1764
1765 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1766 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1767 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1768 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1769 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1770 wifi_req, wifi_prio, wifi_txrx, \
1771 wifi_sh_ant_req))))
1772 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1773 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1774 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1775 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1776 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1777 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1778 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1779 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1780
1781 static const __le32 iwlagn_def_3w_lookup[12] = {
1782 cpu_to_le32(0xaaaaaaaa),
1783 cpu_to_le32(0xaaaaaaaa),
1784 cpu_to_le32(0xaeaaaaaa),
1785 cpu_to_le32(0xaaaaaaaa),
1786 cpu_to_le32(0xcc00ff28),
1787 cpu_to_le32(0x0000aaaa),
1788 cpu_to_le32(0xcc00aaaa),
1789 cpu_to_le32(0x0000aaaa),
1790 cpu_to_le32(0xc0004000),
1791 cpu_to_le32(0x00004000),
1792 cpu_to_le32(0xf0005000),
1793 cpu_to_le32(0xf0004000),
1794 };
1795
1796 static const __le32 iwlagn_concurrent_lookup[12] = {
1797 cpu_to_le32(0xaaaaaaaa),
1798 cpu_to_le32(0xaaaaaaaa),
1799 cpu_to_le32(0xaaaaaaaa),
1800 cpu_to_le32(0xaaaaaaaa),
1801 cpu_to_le32(0xaaaaaaaa),
1802 cpu_to_le32(0xaaaaaaaa),
1803 cpu_to_le32(0xaaaaaaaa),
1804 cpu_to_le32(0xaaaaaaaa),
1805 cpu_to_le32(0x00000000),
1806 cpu_to_le32(0x00000000),
1807 cpu_to_le32(0x00000000),
1808 cpu_to_le32(0x00000000),
1809 };
1810
1811 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1812 {
1813 struct iwlagn_bt_cmd bt_cmd = {
1814 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1815 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1816 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1817 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1818 };
1819
1820 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1821 sizeof(bt_cmd.bt3_lookup_table));
1822
1823 if (priv->cfg->bt_params)
1824 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1825 else
1826 bt_cmd.prio_boost = 0;
1827 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1828 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1829 bt_cmd.valid = priv->bt_valid;
1830 bt_cmd.tx_prio_boost = 0;
1831 bt_cmd.rx_prio_boost = 0;
1832
1833 /*
1834 * Configure BT coex mode to "no coexistence" when the
1835 * user disabled BT coexistence, we have no interface
1836 * (might be in monitor mode), or the interface is in
1837 * IBSS mode (no proper uCode support for coex then).
1838 */
1839 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1840 bt_cmd.flags = 0;
1841 } else {
1842 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1843 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1844 if (priv->bt_ch_announce)
1845 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1846 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1847 }
1848 if (priv->bt_full_concurrent)
1849 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1850 sizeof(iwlagn_concurrent_lookup));
1851 else
1852 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1853 sizeof(iwlagn_def_3w_lookup));
1854
1855 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1856 bt_cmd.flags ? "active" : "disabled",
1857 priv->bt_full_concurrent ?
1858 "full concurrency" : "3-wire");
1859
1860 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1861 IWL_ERR(priv, "failed to send BT Coex Config\n");
1862
1863 /*
1864 * When we are doing a restart, need to also reconfigure BT
1865 * SCO to the device. If not doing a restart, bt_sco_active
1866 * will always be false, so there's no need to have an extra
1867 * variable to check for it.
1868 */
1869 if (priv->bt_sco_active) {
1870 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1871
1872 if (priv->bt_sco_active)
1873 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1874 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1875 sizeof(sco_cmd), &sco_cmd))
1876 IWL_ERR(priv, "failed to send BT SCO command\n");
1877 }
1878 }
1879
1880 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1881 {
1882 struct iwl_priv *priv =
1883 container_of(work, struct iwl_priv, bt_traffic_change_work);
1884 struct iwl_rxon_context *ctx;
1885 int smps_request = -1;
1886
1887 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1888 priv->bt_traffic_load);
1889
1890 switch (priv->bt_traffic_load) {
1891 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1892 smps_request = IEEE80211_SMPS_AUTOMATIC;
1893 break;
1894 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1895 smps_request = IEEE80211_SMPS_DYNAMIC;
1896 break;
1897 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1898 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1899 smps_request = IEEE80211_SMPS_STATIC;
1900 break;
1901 default:
1902 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1903 priv->bt_traffic_load);
1904 break;
1905 }
1906
1907 mutex_lock(&priv->mutex);
1908
1909 if (priv->cfg->ops->lib->update_chain_flags)
1910 priv->cfg->ops->lib->update_chain_flags(priv);
1911
1912 if (smps_request != -1) {
1913 for_each_context(priv, ctx) {
1914 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1915 ieee80211_request_smps(ctx->vif, smps_request);
1916 }
1917 }
1918
1919 mutex_unlock(&priv->mutex);
1920 }
1921
1922 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1923 struct iwl_bt_uart_msg *uart_msg)
1924 {
1925 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1926 "Update Req = 0x%X",
1927 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1928 BT_UART_MSG_FRAME1MSGTYPE_POS,
1929 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1930 BT_UART_MSG_FRAME1SSN_POS,
1931 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1932 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1933
1934 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1935 "Chl_SeqN = 0x%X, In band = 0x%X",
1936 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1937 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1938 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1939 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1940 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1941 BT_UART_MSG_FRAME2CHLSEQN_POS,
1942 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1943 BT_UART_MSG_FRAME2INBAND_POS);
1944
1945 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1946 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1947 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1948 BT_UART_MSG_FRAME3SCOESCO_POS,
1949 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1950 BT_UART_MSG_FRAME3SNIFF_POS,
1951 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1952 BT_UART_MSG_FRAME3A2DP_POS,
1953 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1954 BT_UART_MSG_FRAME3ACL_POS,
1955 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1956 BT_UART_MSG_FRAME3MASTER_POS,
1957 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1958 BT_UART_MSG_FRAME3OBEX_POS);
1959
1960 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1961 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1962 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1963
1964 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1965 "eSCO Retransmissions = 0x%X",
1966 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1967 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1968 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1969 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1970 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1971 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1972
1973 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1974 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1975 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1976 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1977 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1978
1979 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1980 "0x%X, Connectable = 0x%X",
1981 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1982 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1983 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1984 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1985 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1986 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1987 }
1988
1989 static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
1990 struct iwl_bt_uart_msg *uart_msg)
1991 {
1992 u8 kill_ack_msk;
1993 __le32 bt_kill_ack_msg[2] = {
1994 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
1995
1996 kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
1997 BT_UART_MSG_FRAME3SNIFF_MSK |
1998 BT_UART_MSG_FRAME3SCOESCO_MSK) &
1999 uart_msg->frame3) == 0) ? 1 : 0;
2000 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
2001 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2002 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
2003 /* schedule to send runtime bt_config */
2004 queue_work(priv->workqueue, &priv->bt_runtime_config);
2005 }
2006
2007 }
2008
2009 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2010 struct iwl_rx_mem_buffer *rxb)
2011 {
2012 unsigned long flags;
2013 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2014 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2015 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
2016 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2017 u8 last_traffic_load;
2018
2019 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2020 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
2021 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
2022 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
2023 coex->bt_ci_compliance);
2024 iwlagn_print_uartmsg(priv, uart_msg);
2025
2026 last_traffic_load = priv->notif_bt_traffic_load;
2027 priv->notif_bt_traffic_load = coex->bt_traffic_load;
2028 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2029 if (priv->bt_status != coex->bt_status ||
2030 last_traffic_load != coex->bt_traffic_load) {
2031 if (coex->bt_status) {
2032 /* BT on */
2033 if (!priv->bt_ch_announce)
2034 priv->bt_traffic_load =
2035 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2036 else
2037 priv->bt_traffic_load =
2038 coex->bt_traffic_load;
2039 } else {
2040 /* BT off */
2041 priv->bt_traffic_load =
2042 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2043 }
2044 priv->bt_status = coex->bt_status;
2045 queue_work(priv->workqueue,
2046 &priv->bt_traffic_change_work);
2047 }
2048 if (priv->bt_sco_active !=
2049 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2050 priv->bt_sco_active = uart_msg->frame3 &
2051 BT_UART_MSG_FRAME3SCOESCO_MSK;
2052 if (priv->bt_sco_active)
2053 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2054 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2055 sizeof(sco_cmd), &sco_cmd, NULL);
2056 }
2057 }
2058
2059 iwlagn_set_kill_ack_msk(priv, uart_msg);
2060
2061 /* FIXME: based on notification, adjust the prio_boost */
2062
2063 spin_lock_irqsave(&priv->lock, flags);
2064 priv->bt_ci_compliance = coex->bt_ci_compliance;
2065 spin_unlock_irqrestore(&priv->lock, flags);
2066 }
2067
2068 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2069 {
2070 iwlagn_rx_handler_setup(priv);
2071 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2072 iwlagn_bt_coex_profile_notif;
2073 }
2074
2075 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2076 {
2077 iwlagn_setup_deferred_work(priv);
2078
2079 INIT_WORK(&priv->bt_traffic_change_work,
2080 iwlagn_bt_traffic_change_work);
2081 }
2082
2083 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2084 {
2085 cancel_work_sync(&priv->bt_traffic_change_work);
2086 }
2087
2088 static bool is_single_rx_stream(struct iwl_priv *priv)
2089 {
2090 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2091 priv->current_ht_config.single_chain_sufficient;
2092 }
2093
2094 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
2095 #define IWL_NUM_RX_CHAINS_SINGLE 2
2096 #define IWL_NUM_IDLE_CHAINS_DUAL 2
2097 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
2098
2099 /*
2100 * Determine how many receiver/antenna chains to use.
2101 *
2102 * More provides better reception via diversity. Fewer saves power
2103 * at the expense of throughput, but only when not in powersave to
2104 * start with.
2105 *
2106 * MIMO (dual stream) requires at least 2, but works better with 3.
2107 * This does not determine *which* chains to use, just how many.
2108 */
2109 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2110 {
2111 if (priv->cfg->bt_params &&
2112 priv->cfg->bt_params->advanced_bt_coexist &&
2113 (priv->bt_full_concurrent ||
2114 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2115 /*
2116 * only use chain 'A' in bt high traffic load or
2117 * full concurrency mode
2118 */
2119 return IWL_NUM_RX_CHAINS_SINGLE;
2120 }
2121 /* # of Rx chains to use when expecting MIMO. */
2122 if (is_single_rx_stream(priv))
2123 return IWL_NUM_RX_CHAINS_SINGLE;
2124 else
2125 return IWL_NUM_RX_CHAINS_MULTIPLE;
2126 }
2127
2128 /*
2129 * When we are in power saving mode, unless device support spatial
2130 * multiplexing power save, use the active count for rx chain count.
2131 */
2132 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2133 {
2134 /* # Rx chains when idling, depending on SMPS mode */
2135 switch (priv->current_ht_config.smps) {
2136 case IEEE80211_SMPS_STATIC:
2137 case IEEE80211_SMPS_DYNAMIC:
2138 return IWL_NUM_IDLE_CHAINS_SINGLE;
2139 case IEEE80211_SMPS_OFF:
2140 return active_cnt;
2141 default:
2142 WARN(1, "invalid SMPS mode %d",
2143 priv->current_ht_config.smps);
2144 return active_cnt;
2145 }
2146 }
2147
2148 /* up to 4 chains */
2149 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2150 {
2151 u8 res;
2152 res = (chain_bitmap & BIT(0)) >> 0;
2153 res += (chain_bitmap & BIT(1)) >> 1;
2154 res += (chain_bitmap & BIT(2)) >> 2;
2155 res += (chain_bitmap & BIT(3)) >> 3;
2156 return res;
2157 }
2158
2159 /**
2160 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2161 *
2162 * Selects how many and which Rx receivers/antennas/chains to use.
2163 * This should not be used for scan command ... it puts data in wrong place.
2164 */
2165 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2166 {
2167 bool is_single = is_single_rx_stream(priv);
2168 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2169 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2170 u32 active_chains;
2171 u16 rx_chain;
2172
2173 /* Tell uCode which antennas are actually connected.
2174 * Before first association, we assume all antennas are connected.
2175 * Just after first association, iwl_chain_noise_calibration()
2176 * checks which antennas actually *are* connected. */
2177 if (priv->chain_noise_data.active_chains)
2178 active_chains = priv->chain_noise_data.active_chains;
2179 else
2180 active_chains = priv->hw_params.valid_rx_ant;
2181
2182 if (priv->cfg->bt_params &&
2183 priv->cfg->bt_params->advanced_bt_coexist &&
2184 (priv->bt_full_concurrent ||
2185 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2186 /*
2187 * only use chain 'A' in bt high traffic load or
2188 * full concurrency mode
2189 */
2190 active_chains = first_antenna(active_chains);
2191 }
2192
2193 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2194
2195 /* How many receivers should we use? */
2196 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2197 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2198
2199
2200 /* correct rx chain count according hw settings
2201 * and chain noise calibration
2202 */
2203 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2204 if (valid_rx_cnt < active_rx_cnt)
2205 active_rx_cnt = valid_rx_cnt;
2206
2207 if (valid_rx_cnt < idle_rx_cnt)
2208 idle_rx_cnt = valid_rx_cnt;
2209
2210 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2211 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2212
2213 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2214
2215 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2216 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2217 else
2218 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2219
2220 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2221 ctx->staging.rx_chain,
2222 active_rx_cnt, idle_rx_cnt);
2223
2224 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2225 active_rx_cnt < idle_rx_cnt);
2226 }
2227
2228 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2229 {
2230 int i;
2231 u8 ind = ant;
2232
2233 if (priv->band == IEEE80211_BAND_2GHZ &&
2234 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2235 return 0;
2236
2237 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2238 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2239 if (valid & BIT(ind))
2240 return ind;
2241 }
2242 return ant;
2243 }
2244
2245 static const char *get_csr_string(int cmd)
2246 {
2247 switch (cmd) {
2248 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2249 IWL_CMD(CSR_INT_COALESCING);
2250 IWL_CMD(CSR_INT);
2251 IWL_CMD(CSR_INT_MASK);
2252 IWL_CMD(CSR_FH_INT_STATUS);
2253 IWL_CMD(CSR_GPIO_IN);
2254 IWL_CMD(CSR_RESET);
2255 IWL_CMD(CSR_GP_CNTRL);
2256 IWL_CMD(CSR_HW_REV);
2257 IWL_CMD(CSR_EEPROM_REG);
2258 IWL_CMD(CSR_EEPROM_GP);
2259 IWL_CMD(CSR_OTP_GP_REG);
2260 IWL_CMD(CSR_GIO_REG);
2261 IWL_CMD(CSR_GP_UCODE_REG);
2262 IWL_CMD(CSR_GP_DRIVER_REG);
2263 IWL_CMD(CSR_UCODE_DRV_GP1);
2264 IWL_CMD(CSR_UCODE_DRV_GP2);
2265 IWL_CMD(CSR_LED_REG);
2266 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2267 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2268 IWL_CMD(CSR_ANA_PLL_CFG);
2269 IWL_CMD(CSR_HW_REV_WA_REG);
2270 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2271 default:
2272 return "UNKNOWN";
2273 }
2274 }
2275
2276 void iwl_dump_csr(struct iwl_priv *priv)
2277 {
2278 int i;
2279 u32 csr_tbl[] = {
2280 CSR_HW_IF_CONFIG_REG,
2281 CSR_INT_COALESCING,
2282 CSR_INT,
2283 CSR_INT_MASK,
2284 CSR_FH_INT_STATUS,
2285 CSR_GPIO_IN,
2286 CSR_RESET,
2287 CSR_GP_CNTRL,
2288 CSR_HW_REV,
2289 CSR_EEPROM_REG,
2290 CSR_EEPROM_GP,
2291 CSR_OTP_GP_REG,
2292 CSR_GIO_REG,
2293 CSR_GP_UCODE_REG,
2294 CSR_GP_DRIVER_REG,
2295 CSR_UCODE_DRV_GP1,
2296 CSR_UCODE_DRV_GP2,
2297 CSR_LED_REG,
2298 CSR_DRAM_INT_TBL_REG,
2299 CSR_GIO_CHICKEN_BITS,
2300 CSR_ANA_PLL_CFG,
2301 CSR_HW_REV_WA_REG,
2302 CSR_DBG_HPET_MEM_REG
2303 };
2304 IWL_ERR(priv, "CSR values:\n");
2305 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2306 "CSR_INT_PERIODIC_REG)\n");
2307 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2308 IWL_ERR(priv, " %25s: 0X%08x\n",
2309 get_csr_string(csr_tbl[i]),
2310 iwl_read32(priv, csr_tbl[i]));
2311 }
2312 }
2313
2314 static const char *get_fh_string(int cmd)
2315 {
2316 switch (cmd) {
2317 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2318 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2319 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2320 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2321 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2322 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2323 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2324 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2325 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2326 default:
2327 return "UNKNOWN";
2328 }
2329 }
2330
2331 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2332 {
2333 int i;
2334 #ifdef CONFIG_IWLWIFI_DEBUG
2335 int pos = 0;
2336 size_t bufsz = 0;
2337 #endif
2338 u32 fh_tbl[] = {
2339 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2340 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2341 FH_RSCSR_CHNL0_WPTR,
2342 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2343 FH_MEM_RSSR_SHARED_CTRL_REG,
2344 FH_MEM_RSSR_RX_STATUS_REG,
2345 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2346 FH_TSSR_TX_STATUS_REG,
2347 FH_TSSR_TX_ERROR_REG
2348 };
2349 #ifdef CONFIG_IWLWIFI_DEBUG
2350 if (display) {
2351 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2352 *buf = kmalloc(bufsz, GFP_KERNEL);
2353 if (!*buf)
2354 return -ENOMEM;
2355 pos += scnprintf(*buf + pos, bufsz - pos,
2356 "FH register values:\n");
2357 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2358 pos += scnprintf(*buf + pos, bufsz - pos,
2359 " %34s: 0X%08x\n",
2360 get_fh_string(fh_tbl[i]),
2361 iwl_read_direct32(priv, fh_tbl[i]));
2362 }
2363 return pos;
2364 }
2365 #endif
2366 IWL_ERR(priv, "FH register values:\n");
2367 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2368 IWL_ERR(priv, " %34s: 0X%08x\n",
2369 get_fh_string(fh_tbl[i]),
2370 iwl_read_direct32(priv, fh_tbl[i]));
2371 }
2372 return 0;
2373 }
kernel source for telekom puls (alcatel/mediatek)