projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
iwlagn: implement layout-agnostic EEPROM reading
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwlagn_tx_resp *tx_resp,
176 int txq_id, bool is_agg)
177 {
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195 }
196
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200 const char *iwl_get_agg_tx_fail_reason(u16 status)
201 {
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221 }
222 #endif /* CONFIG_IWLWIFI_DEBUG */
223
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
226 struct iwlagn_tx_resp *tx_resp,
227 int txq_id, u16 start_idx)
228 {
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
231 struct ieee80211_hdr *hdr = NULL;
232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
246 idx = start_idx;
247
248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
319 sh = idx - start;
320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
330 bitmap = bitmap << sh;
331 /* Now idx is the new start so sh = 0 */
332 sh = 0;
333 start = idx;
334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
346 sh = start - idx;
347 bitmap = bitmap << sh;
348 /* Now idx is the new start so sh = 0 */
349 start = idx;
350 sh = 0;
351 }
352 /* Sequence number start + sh was sent in this batch */
353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372 }
373
374 void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376 {
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
381 }
382 }
383
384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386 {
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
393 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
398 unsigned long flags;
399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
408 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
409 memset(&info->status, 0, sizeof(info->status));
410
411 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
412 IWLAGN_TX_RES_TID_POS;
413 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
414 IWLAGN_TX_RES_RA_POS;
415
416 spin_lock_irqsave(&priv->sta_lock, flags);
417 if (txq->sched_retry) {
418 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
419 struct iwl_ht_agg *agg;
420
421 agg = &priv->stations[sta_id].tid[tid].agg;
422 /*
423 * If the BT kill count is non-zero, we'll get this
424 * notification again.
425 */
426 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
427 priv->cfg->bt_params &&
428 priv->cfg->bt_params->advanced_bt_coexist) {
429 IWL_WARN(priv, "receive reply tx with bt_kill\n");
430 }
431 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
432
433 /* check if BAR is needed */
434 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
435 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
436
437 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
438 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
439 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
440 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
441 scd_ssn , index, txq_id, txq->swq_id);
442
443 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
444 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
445
446 if (priv->mac80211_registered &&
447 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
448 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
449 if (agg->state == IWL_AGG_OFF)
450 iwl_wake_queue(priv, txq_id);
451 else
452 iwl_wake_queue(priv, txq->swq_id);
453 }
454 }
455 } else {
456 BUG_ON(txq_id != txq->swq_id);
457 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
458 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
459 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
460
461 if (priv->mac80211_registered &&
462 (iwl_queue_space(&txq->q) > txq->q.low_mark))
463 iwl_wake_queue(priv, txq_id);
464 }
465
466 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
467
468 iwl_check_abort_status(priv, tx_resp->frame_count, status);
469 spin_unlock_irqrestore(&priv->sta_lock, flags);
470 }
471
472 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
473 {
474 /* init calibration handlers */
475 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
476 iwlagn_rx_calib_result;
477 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
478 iwlagn_rx_calib_complete;
479 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
480 }
481
482 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
483 {
484 /* in agn, the tx power calibration is done in uCode */
485 priv->disable_tx_power_cal = 1;
486 }
487
488 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
489 {
490 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
491 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
492 }
493
494 int iwlagn_send_tx_power(struct iwl_priv *priv)
495 {
496 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
497 u8 tx_ant_cfg_cmd;
498
499 /* half dBm need to multiply */
500 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
501
502 if (priv->tx_power_lmt_in_half_dbm &&
503 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
504 /*
505 * For the newer devices which using enhanced/extend tx power
506 * table in EEPROM, the format is in half dBm. driver need to
507 * convert to dBm format before report to mac80211.
508 * By doing so, there is a possibility of 1/2 dBm resolution
509 * lost. driver will perform "round-up" operation before
510 * reporting, but it will cause 1/2 dBm tx power over the
511 * regulatory limit. Perform the checking here, if the
512 * "tx_power_user_lmt" is higher than EEPROM value (in
513 * half-dBm format), lower the tx power based on EEPROM
514 */
515 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
516 }
517 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
518 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
519
520 if (IWL_UCODE_API(priv->ucode_ver) == 1)
521 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
522 else
523 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
524
525 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
526 sizeof(tx_power_cmd), &tx_power_cmd,
527 NULL);
528 }
529
530 void iwlagn_temperature(struct iwl_priv *priv)
531 {
532 /* store temperature from statistics (in Celsius) */
533 priv->temperature =
534 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
535 iwl_tt_handler(priv);
536 }
537
538 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
539 {
540 struct iwl_eeprom_calib_hdr {
541 u8 version;
542 u8 pa_type;
543 u16 voltage;
544 } *hdr;
545
546 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
547 EEPROM_CALIB_ALL);
548 return hdr->version;
549
550 }
551
552 /*
553 * EEPROM
554 */
555 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
556 {
557 u16 offset = 0;
558
559 if ((address & INDIRECT_ADDRESS) == 0)
560 return address;
561
562 switch (address & INDIRECT_TYPE_MSK) {
563 case INDIRECT_HOST:
564 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
565 break;
566 case INDIRECT_GENERAL:
567 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
568 break;
569 case INDIRECT_REGULATORY:
570 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
571 break;
572 case INDIRECT_TXP_LIMIT:
573 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
574 break;
575 case INDIRECT_TXP_LIMIT_SIZE:
576 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
577 break;
578 case INDIRECT_CALIBRATION:
579 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
580 break;
581 case INDIRECT_PROCESS_ADJST:
582 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
583 break;
584 case INDIRECT_OTHERS:
585 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
586 break;
587 default:
588 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
589 address & INDIRECT_TYPE_MSK);
590 break;
591 }
592
593 /* translate the offset from words to byte */
594 return (address & ADDRESS_MSK) + (offset << 1);
595 }
596
597 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
598 size_t offset)
599 {
600 u32 address = eeprom_indirect_address(priv, offset);
601 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
602 return &priv->eeprom[address];
603 }
604
605 struct iwl_mod_params iwlagn_mod_params = {
606 .amsdu_size_8K = 1,
607 .restart_fw = 1,
608 /* the rest are 0 by default */
609 };
610
611 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
612 {
613 unsigned long flags;
614 int i;
615 spin_lock_irqsave(&rxq->lock, flags);
616 INIT_LIST_HEAD(&rxq->rx_free);
617 INIT_LIST_HEAD(&rxq->rx_used);
618 /* Fill the rx_used queue with _all_ of the Rx buffers */
619 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
620 /* In the reset function, these buffers may have been allocated
621 * to an SKB, so we need to unmap and free potential storage */
622 if (rxq->pool[i].page != NULL) {
623 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
624 PAGE_SIZE << priv->hw_params.rx_page_order,
625 PCI_DMA_FROMDEVICE);
626 __iwl_free_pages(priv, rxq->pool[i].page);
627 rxq->pool[i].page = NULL;
628 }
629 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
630 }
631
632 for (i = 0; i < RX_QUEUE_SIZE; i++)
633 rxq->queue[i] = NULL;
634
635 /* Set us so that we have processed and used all buffers, but have
636 * not restocked the Rx queue with fresh buffers */
637 rxq->read = rxq->write = 0;
638 rxq->write_actual = 0;
639 rxq->free_count = 0;
640 spin_unlock_irqrestore(&rxq->lock, flags);
641 }
642
643 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
644 {
645 u32 rb_size;
646 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
647 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
648
649 if (!priv->cfg->base_params->use_isr_legacy)
650 rb_timeout = RX_RB_TIMEOUT;
651
652 if (priv->cfg->mod_params->amsdu_size_8K)
653 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
654 else
655 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
656
657 /* Stop Rx DMA */
658 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
659
660 /* Reset driver's Rx queue write index */
661 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
662
663 /* Tell device where to find RBD circular buffer in DRAM */
664 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
665 (u32)(rxq->bd_dma >> 8));
666
667 /* Tell device where in DRAM to update its Rx status */
668 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
669 rxq->rb_stts_dma >> 4);
670
671 /* Enable Rx DMA
672 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
673 * the credit mechanism in 5000 HW RX FIFO
674 * Direct rx interrupts to hosts
675 * Rx buffer size 4 or 8k
676 * RB timeout 0x10
677 * 256 RBDs
678 */
679 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
680 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
681 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
682 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
683 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
684 rb_size|
685 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
686 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
687
688 /* Set interrupt coalescing timer to default (2048 usecs) */
689 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
690
691 return 0;
692 }
693
694 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
695 {
696 /*
697 * (for documentation purposes)
698 * to set power to V_AUX, do:
699
700 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
701 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
702 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
703 ~APMG_PS_CTRL_MSK_PWR_SRC);
704 */
705
706 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
707 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
708 ~APMG_PS_CTRL_MSK_PWR_SRC);
709 }
710
711 int iwlagn_hw_nic_init(struct iwl_priv *priv)
712 {
713 unsigned long flags;
714 struct iwl_rx_queue *rxq = &priv->rxq;
715 int ret;
716
717 /* nic_init */
718 spin_lock_irqsave(&priv->lock, flags);
719 priv->cfg->ops->lib->apm_ops.init(priv);
720
721 /* Set interrupt coalescing calibration timer to default (512 usecs) */
722 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
723
724 spin_unlock_irqrestore(&priv->lock, flags);
725
726 iwlagn_set_pwr_vmain(priv);
727
728 priv->cfg->ops->lib->apm_ops.config(priv);
729
730 /* Allocate the RX queue, or reset if it is already allocated */
731 if (!rxq->bd) {
732 ret = iwl_rx_queue_alloc(priv);
733 if (ret) {
734 IWL_ERR(priv, "Unable to initialize Rx queue\n");
735 return -ENOMEM;
736 }
737 } else
738 iwlagn_rx_queue_reset(priv, rxq);
739
740 iwlagn_rx_replenish(priv);
741
742 iwlagn_rx_init(priv, rxq);
743
744 spin_lock_irqsave(&priv->lock, flags);
745
746 rxq->need_update = 1;
747 iwl_rx_queue_update_write_ptr(priv, rxq);
748
749 spin_unlock_irqrestore(&priv->lock, flags);
750
751 /* Allocate or reset and init all Tx and Command queues */
752 if (!priv->txq) {
753 ret = iwlagn_txq_ctx_alloc(priv);
754 if (ret)
755 return ret;
756 } else
757 iwlagn_txq_ctx_reset(priv);
758
759 set_bit(STATUS_INIT, &priv->status);
760
761 return 0;
762 }
763
764 /**
765 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
766 */
767 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
768 dma_addr_t dma_addr)
769 {
770 return cpu_to_le32((u32)(dma_addr >> 8));
771 }
772
773 /**
774 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
775 *
776 * If there are slots in the RX queue that need to be restocked,
777 * and we have free pre-allocated buffers, fill the ranks as much
778 * as we can, pulling from rx_free.
779 *
780 * This moves the 'write' index forward to catch up with 'processed', and
781 * also updates the memory address in the firmware to reference the new
782 * target buffer.
783 */
784 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
785 {
786 struct iwl_rx_queue *rxq = &priv->rxq;
787 struct list_head *element;
788 struct iwl_rx_mem_buffer *rxb;
789 unsigned long flags;
790
791 spin_lock_irqsave(&rxq->lock, flags);
792 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
793 /* The overwritten rxb must be a used one */
794 rxb = rxq->queue[rxq->write];
795 BUG_ON(rxb && rxb->page);
796
797 /* Get next free Rx buffer, remove from free list */
798 element = rxq->rx_free.next;
799 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
800 list_del(element);
801
802 /* Point to Rx buffer via next RBD in circular buffer */
803 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
804 rxb->page_dma);
805 rxq->queue[rxq->write] = rxb;
806 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
807 rxq->free_count--;
808 }
809 spin_unlock_irqrestore(&rxq->lock, flags);
810 /* If the pre-allocated buffer pool is dropping low, schedule to
811 * refill it */
812 if (rxq->free_count <= RX_LOW_WATERMARK)
813 queue_work(priv->workqueue, &priv->rx_replenish);
814
815
816 /* If we've added more space for the firmware to place data, tell it.
817 * Increment device's write pointer in multiples of 8. */
818 if (rxq->write_actual != (rxq->write & ~0x7)) {
819 spin_lock_irqsave(&rxq->lock, flags);
820 rxq->need_update = 1;
821 spin_unlock_irqrestore(&rxq->lock, flags);
822 iwl_rx_queue_update_write_ptr(priv, rxq);
823 }
824 }
825
826 /**
827 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
828 *
829 * When moving to rx_free an SKB is allocated for the slot.
830 *
831 * Also restock the Rx queue via iwl_rx_queue_restock.
832 * This is called as a scheduled work item (except for during initialization)
833 */
834 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
835 {
836 struct iwl_rx_queue *rxq = &priv->rxq;
837 struct list_head *element;
838 struct iwl_rx_mem_buffer *rxb;
839 struct page *page;
840 unsigned long flags;
841 gfp_t gfp_mask = priority;
842
843 while (1) {
844 spin_lock_irqsave(&rxq->lock, flags);
845 if (list_empty(&rxq->rx_used)) {
846 spin_unlock_irqrestore(&rxq->lock, flags);
847 return;
848 }
849 spin_unlock_irqrestore(&rxq->lock, flags);
850
851 if (rxq->free_count > RX_LOW_WATERMARK)
852 gfp_mask |= __GFP_NOWARN;
853
854 if (priv->hw_params.rx_page_order > 0)
855 gfp_mask |= __GFP_COMP;
856
857 /* Alloc a new receive buffer */
858 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
859 if (!page) {
860 if (net_ratelimit())
861 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
862 "order: %d\n",
863 priv->hw_params.rx_page_order);
864
865 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
866 net_ratelimit())
867 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
868 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
869 rxq->free_count);
870 /* We don't reschedule replenish work here -- we will
871 * call the restock method and if it still needs
872 * more buffers it will schedule replenish */
873 return;
874 }
875
876 spin_lock_irqsave(&rxq->lock, flags);
877
878 if (list_empty(&rxq->rx_used)) {
879 spin_unlock_irqrestore(&rxq->lock, flags);
880 __free_pages(page, priv->hw_params.rx_page_order);
881 return;
882 }
883 element = rxq->rx_used.next;
884 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
885 list_del(element);
886
887 spin_unlock_irqrestore(&rxq->lock, flags);
888
889 BUG_ON(rxb->page);
890 rxb->page = page;
891 /* Get physical address of the RB */
892 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
893 PAGE_SIZE << priv->hw_params.rx_page_order,
894 PCI_DMA_FROMDEVICE);
895 /* dma address must be no more than 36 bits */
896 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
897 /* and also 256 byte aligned! */
898 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
899
900 spin_lock_irqsave(&rxq->lock, flags);
901
902 list_add_tail(&rxb->list, &rxq->rx_free);
903 rxq->free_count++;
904 priv->alloc_rxb_page++;
905
906 spin_unlock_irqrestore(&rxq->lock, flags);
907 }
908 }
909
910 void iwlagn_rx_replenish(struct iwl_priv *priv)
911 {
912 unsigned long flags;
913
914 iwlagn_rx_allocate(priv, GFP_KERNEL);
915
916 spin_lock_irqsave(&priv->lock, flags);
917 iwlagn_rx_queue_restock(priv);
918 spin_unlock_irqrestore(&priv->lock, flags);
919 }
920
921 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
922 {
923 iwlagn_rx_allocate(priv, GFP_ATOMIC);
924
925 iwlagn_rx_queue_restock(priv);
926 }
927
928 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
929 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
930 * This free routine walks the list of POOL entries and if SKB is set to
931 * non NULL it is unmapped and freed
932 */
933 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
934 {
935 int i;
936 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
937 if (rxq->pool[i].page != NULL) {
938 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
939 PAGE_SIZE << priv->hw_params.rx_page_order,
940 PCI_DMA_FROMDEVICE);
941 __iwl_free_pages(priv, rxq->pool[i].page);
942 rxq->pool[i].page = NULL;
943 }
944 }
945
946 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
947 rxq->bd_dma);
948 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
949 rxq->rb_stts, rxq->rb_stts_dma);
950 rxq->bd = NULL;
951 rxq->rb_stts = NULL;
952 }
953
954 int iwlagn_rxq_stop(struct iwl_priv *priv)
955 {
956
957 /* stop Rx DMA */
958 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
959 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
960 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
961
962 return 0;
963 }
964
965 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
966 {
967 int idx = 0;
968 int band_offset = 0;
969
970 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
971 if (rate_n_flags & RATE_MCS_HT_MSK) {
972 idx = (rate_n_flags & 0xff);
973 return idx;
974 /* Legacy rate format, search for match in table */
975 } else {
976 if (band == IEEE80211_BAND_5GHZ)
977 band_offset = IWL_FIRST_OFDM_RATE;
978 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
979 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
980 return idx - band_offset;
981 }
982
983 return -1;
984 }
985
986 /* Calc max signal level (dBm) among 3 possible receivers */
987 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
988 struct iwl_rx_phy_res *rx_resp)
989 {
990 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
991 }
992
993 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
994 {
995 u32 decrypt_out = 0;
996
997 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
998 RX_RES_STATUS_STATION_FOUND)
999 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
1000 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
1001
1002 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
1003
1004 /* packet was not encrypted */
1005 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1006 RX_RES_STATUS_SEC_TYPE_NONE)
1007 return decrypt_out;
1008
1009 /* packet was encrypted with unknown alg */
1010 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1011 RX_RES_STATUS_SEC_TYPE_ERR)
1012 return decrypt_out;
1013
1014 /* decryption was not done in HW */
1015 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1016 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1017 return decrypt_out;
1018
1019 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1020
1021 case RX_RES_STATUS_SEC_TYPE_CCMP:
1022 /* alg is CCM: check MIC only */
1023 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1024 /* Bad MIC */
1025 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1026 else
1027 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1028
1029 break;
1030
1031 case RX_RES_STATUS_SEC_TYPE_TKIP:
1032 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1033 /* Bad TTAK */
1034 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1035 break;
1036 }
1037 /* fall through if TTAK OK */
1038 default:
1039 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1040 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1041 else
1042 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1043 break;
1044 }
1045
1046 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1047 decrypt_in, decrypt_out);
1048
1049 return decrypt_out;
1050 }
1051
1052 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1053 struct ieee80211_hdr *hdr,
1054 u16 len,
1055 u32 ampdu_status,
1056 struct iwl_rx_mem_buffer *rxb,
1057 struct ieee80211_rx_status *stats)
1058 {
1059 struct sk_buff *skb;
1060 __le16 fc = hdr->frame_control;
1061
1062 /* We only process data packets if the interface is open */
1063 if (unlikely(!priv->is_open)) {
1064 IWL_DEBUG_DROP_LIMIT(priv,
1065 "Dropping packet while interface is not open.\n");
1066 return;
1067 }
1068
1069 /* In case of HW accelerated crypto and bad decryption, drop */
1070 if (!priv->cfg->mod_params->sw_crypto &&
1071 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1072 return;
1073
1074 skb = dev_alloc_skb(128);
1075 if (!skb) {
1076 IWL_ERR(priv, "dev_alloc_skb failed\n");
1077 return;
1078 }
1079
1080 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1081
1082 iwl_update_stats(priv, false, fc, len);
1083 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1084
1085 ieee80211_rx(priv->hw, skb);
1086 priv->alloc_rxb_page--;
1087 rxb->page = NULL;
1088 }
1089
1090 /* Called for REPLY_RX (legacy ABG frames), or
1091 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1092 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1093 struct iwl_rx_mem_buffer *rxb)
1094 {
1095 struct ieee80211_hdr *header;
1096 struct ieee80211_rx_status rx_status;
1097 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1098 struct iwl_rx_phy_res *phy_res;
1099 __le32 rx_pkt_status;
1100 struct iwl_rx_mpdu_res_start *amsdu;
1101 u32 len;
1102 u32 ampdu_status;
1103 u32 rate_n_flags;
1104
1105 /**
1106 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1107 * REPLY_RX: physical layer info is in this buffer
1108 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1109 * command and cached in priv->last_phy_res
1110 *
1111 * Here we set up local variables depending on which command is
1112 * received.
1113 */
1114 if (pkt->hdr.cmd == REPLY_RX) {
1115 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1116 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1117 + phy_res->cfg_phy_cnt);
1118
1119 len = le16_to_cpu(phy_res->byte_count);
1120 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1121 phy_res->cfg_phy_cnt + len);
1122 ampdu_status = le32_to_cpu(rx_pkt_status);
1123 } else {
1124 if (!priv->_agn.last_phy_res_valid) {
1125 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1126 return;
1127 }
1128 phy_res = &priv->_agn.last_phy_res;
1129 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1130 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1131 len = le16_to_cpu(amsdu->byte_count);
1132 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1133 ampdu_status = iwlagn_translate_rx_status(priv,
1134 le32_to_cpu(rx_pkt_status));
1135 }
1136
1137 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1138 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1139 phy_res->cfg_phy_cnt);
1140 return;
1141 }
1142
1143 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1144 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1145 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1146 le32_to_cpu(rx_pkt_status));
1147 return;
1148 }
1149
1150 /* This will be used in several places later */
1151 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1152
1153 /* rx_status carries information about the packet to mac80211 */
1154 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1155 rx_status.freq =
1156 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1157 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1158 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1159 rx_status.rate_idx =
1160 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1161 rx_status.flag = 0;
1162
1163 /* TSF isn't reliable. In order to allow smooth user experience,
1164 * this W/A doesn't propagate it to the mac80211 */
1165 /*rx_status.flag |= RX_FLAG_TSFT;*/
1166
1167 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1168
1169 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1170 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1171
1172 iwl_dbg_log_rx_data_frame(priv, len, header);
1173 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1174 rx_status.signal, (unsigned long long)rx_status.mactime);
1175
1176 /*
1177 * "antenna number"
1178 *
1179 * It seems that the antenna field in the phy flags value
1180 * is actually a bit field. This is undefined by radiotap,
1181 * it wants an actual antenna number but I always get "7"
1182 * for most legacy frames I receive indicating that the
1183 * same frame was received on all three RX chains.
1184 *
1185 * I think this field should be removed in favor of a
1186 * new 802.11n radiotap field "RX chains" that is defined
1187 * as a bitmask.
1188 */
1189 rx_status.antenna =
1190 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1191 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1192
1193 /* set the preamble flag if appropriate */
1194 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1195 rx_status.flag |= RX_FLAG_SHORTPRE;
1196
1197 /* Set up the HT phy flags */
1198 if (rate_n_flags & RATE_MCS_HT_MSK)
1199 rx_status.flag |= RX_FLAG_HT;
1200 if (rate_n_flags & RATE_MCS_HT40_MSK)
1201 rx_status.flag |= RX_FLAG_40MHZ;
1202 if (rate_n_flags & RATE_MCS_SGI_MSK)
1203 rx_status.flag |= RX_FLAG_SHORT_GI;
1204
1205 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1206 rxb, &rx_status);
1207 }
1208
1209 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1210 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1211 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1212 struct iwl_rx_mem_buffer *rxb)
1213 {
1214 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1215 priv->_agn.last_phy_res_valid = true;
1216 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1217 sizeof(struct iwl_rx_phy_res));
1218 }
1219
1220 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1221 struct ieee80211_vif *vif,
1222 enum ieee80211_band band,
1223 struct iwl_scan_channel *scan_ch)
1224 {
1225 const struct ieee80211_supported_band *sband;
1226 u16 passive_dwell = 0;
1227 u16 active_dwell = 0;
1228 int added = 0;
1229 u16 channel = 0;
1230
1231 sband = iwl_get_hw_mode(priv, band);
1232 if (!sband) {
1233 IWL_ERR(priv, "invalid band\n");
1234 return added;
1235 }
1236
1237 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1238 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1239
1240 if (passive_dwell <= active_dwell)
1241 passive_dwell = active_dwell + 1;
1242
1243 channel = iwl_get_single_channel_number(priv, band);
1244 if (channel) {
1245 scan_ch->channel = cpu_to_le16(channel);
1246 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1247 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1248 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1249 /* Set txpower levels to defaults */
1250 scan_ch->dsp_atten = 110;
1251 if (band == IEEE80211_BAND_5GHZ)
1252 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1253 else
1254 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1255 added++;
1256 } else
1257 IWL_ERR(priv, "no valid channel found\n");
1258 return added;
1259 }
1260
1261 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1262 struct ieee80211_vif *vif,
1263 enum ieee80211_band band,
1264 u8 is_active, u8 n_probes,
1265 struct iwl_scan_channel *scan_ch)
1266 {
1267 struct ieee80211_channel *chan;
1268 const struct ieee80211_supported_band *sband;
1269 const struct iwl_channel_info *ch_info;
1270 u16 passive_dwell = 0;
1271 u16 active_dwell = 0;
1272 int added, i;
1273 u16 channel;
1274
1275 sband = iwl_get_hw_mode(priv, band);
1276 if (!sband)
1277 return 0;
1278
1279 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1280 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1281
1282 if (passive_dwell <= active_dwell)
1283 passive_dwell = active_dwell + 1;
1284
1285 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1286 chan = priv->scan_request->channels[i];
1287
1288 if (chan->band != band)
1289 continue;
1290
1291 channel = chan->hw_value;
1292 scan_ch->channel = cpu_to_le16(channel);
1293
1294 ch_info = iwl_get_channel_info(priv, band, channel);
1295 if (!is_channel_valid(ch_info)) {
1296 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1297 channel);
1298 continue;
1299 }
1300
1301 if (!is_active || is_channel_passive(ch_info) ||
1302 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1303 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1304 else
1305 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1306
1307 if (n_probes)
1308 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1309
1310 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1311 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1312
1313 /* Set txpower levels to defaults */
1314 scan_ch->dsp_atten = 110;
1315
1316 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1317 * power level:
1318 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1319 */
1320 if (band == IEEE80211_BAND_5GHZ)
1321 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1322 else
1323 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1324
1325 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1326 channel, le32_to_cpu(scan_ch->type),
1327 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1328 "ACTIVE" : "PASSIVE",
1329 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1330 active_dwell : passive_dwell);
1331
1332 scan_ch++;
1333 added++;
1334 }
1335
1336 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1337 return added;
1338 }
1339
1340 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1341 {
1342 struct iwl_host_cmd cmd = {
1343 .id = REPLY_SCAN_CMD,
1344 .len = sizeof(struct iwl_scan_cmd),
1345 .flags = CMD_SIZE_HUGE,
1346 };
1347 struct iwl_scan_cmd *scan;
1348 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1349 u32 rate_flags = 0;
1350 u16 cmd_len;
1351 u16 rx_chain = 0;
1352 enum ieee80211_band band;
1353 u8 n_probes = 0;
1354 u8 rx_ant = priv->hw_params.valid_rx_ant;
1355 u8 rate;
1356 bool is_active = false;
1357 int chan_mod;
1358 u8 active_chains;
1359 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1360 int ret;
1361
1362 lockdep_assert_held(&priv->mutex);
1363
1364 if (vif)
1365 ctx = iwl_rxon_ctx_from_vif(vif);
1366
1367 if (!priv->scan_cmd) {
1368 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1369 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1370 if (!priv->scan_cmd) {
1371 IWL_DEBUG_SCAN(priv,
1372 "fail to allocate memory for scan\n");
1373 return -ENOMEM;
1374 }
1375 }
1376 scan = priv->scan_cmd;
1377 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1378
1379 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1380 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1381
1382 if (iwl_is_any_associated(priv)) {
1383 u16 interval = 0;
1384 u32 extra;
1385 u32 suspend_time = 100;
1386 u32 scan_suspend_time = 100;
1387 unsigned long flags;
1388
1389 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1390 spin_lock_irqsave(&priv->lock, flags);
1391 if (priv->is_internal_short_scan)
1392 interval = 0;
1393 else
1394 interval = vif->bss_conf.beacon_int;
1395 spin_unlock_irqrestore(&priv->lock, flags);
1396
1397 scan->suspend_time = 0;
1398 scan->max_out_time = cpu_to_le32(200 * 1024);
1399 if (!interval)
1400 interval = suspend_time;
1401
1402 extra = (suspend_time / interval) << 22;
1403 scan_suspend_time = (extra |
1404 ((suspend_time % interval) * 1024));
1405 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1406 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1407 scan_suspend_time, interval);
1408 }
1409
1410 if (priv->is_internal_short_scan) {
1411 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1412 } else if (priv->scan_request->n_ssids) {
1413 int i, p = 0;
1414 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1415 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1416 /* always does wildcard anyway */
1417 if (!priv->scan_request->ssids[i].ssid_len)
1418 continue;
1419 scan->direct_scan[p].id = WLAN_EID_SSID;
1420 scan->direct_scan[p].len =
1421 priv->scan_request->ssids[i].ssid_len;
1422 memcpy(scan->direct_scan[p].ssid,
1423 priv->scan_request->ssids[i].ssid,
1424 priv->scan_request->ssids[i].ssid_len);
1425 n_probes++;
1426 p++;
1427 }
1428 is_active = true;
1429 } else
1430 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1431
1432 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1433 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1434 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1435
1436 switch (priv->scan_band) {
1437 case IEEE80211_BAND_2GHZ:
1438 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1439 chan_mod = le32_to_cpu(
1440 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1441 RXON_FLG_CHANNEL_MODE_MSK)
1442 >> RXON_FLG_CHANNEL_MODE_POS;
1443 if (chan_mod == CHANNEL_MODE_PURE_40) {
1444 rate = IWL_RATE_6M_PLCP;
1445 } else {
1446 rate = IWL_RATE_1M_PLCP;
1447 rate_flags = RATE_MCS_CCK_MSK;
1448 }
1449 /*
1450 * Internal scans are passive, so we can indiscriminately set
1451 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1452 */
1453 if (priv->cfg->bt_params &&
1454 priv->cfg->bt_params->advanced_bt_coexist)
1455 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1456 break;
1457 case IEEE80211_BAND_5GHZ:
1458 rate = IWL_RATE_6M_PLCP;
1459 break;
1460 default:
1461 IWL_WARN(priv, "Invalid scan band\n");
1462 return -EIO;
1463 }
1464
1465 /*
1466 * If active scanning is requested but a certain channel is
1467 * marked passive, we can do active scanning if we detect
1468 * transmissions.
1469 *
1470 * There is an issue with some firmware versions that triggers
1471 * a sysassert on a "good CRC threshold" of zero (== disabled),
1472 * on a radar channel even though this means that we should NOT
1473 * send probes.
1474 *
1475 * The "good CRC threshold" is the number of frames that we
1476 * need to receive during our dwell time on a channel before
1477 * sending out probes -- setting this to a huge value will
1478 * mean we never reach it, but at the same time work around
1479 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1480 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1481 */
1482 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1483 IWL_GOOD_CRC_TH_NEVER;
1484
1485 band = priv->scan_band;
1486
1487 if (priv->cfg->scan_rx_antennas[band])
1488 rx_ant = priv->cfg->scan_rx_antennas[band];
1489
1490 if (priv->cfg->scan_tx_antennas[band])
1491 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1492
1493 if (priv->cfg->bt_params &&
1494 priv->cfg->bt_params->advanced_bt_coexist &&
1495 priv->bt_full_concurrent) {
1496 /* operated as 1x1 in full concurrency mode */
1497 scan_tx_antennas = first_antenna(
1498 priv->cfg->scan_tx_antennas[band]);
1499 }
1500
1501 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1502 scan_tx_antennas);
1503 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1504 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1505
1506 /* In power save mode use one chain, otherwise use all chains */
1507 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1508 /* rx_ant has been set to all valid chains previously */
1509 active_chains = rx_ant &
1510 ((u8)(priv->chain_noise_data.active_chains));
1511 if (!active_chains)
1512 active_chains = rx_ant;
1513
1514 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1515 priv->chain_noise_data.active_chains);
1516
1517 rx_ant = first_antenna(active_chains);
1518 }
1519 if (priv->cfg->bt_params &&
1520 priv->cfg->bt_params->advanced_bt_coexist &&
1521 priv->bt_full_concurrent) {
1522 /* operated as 1x1 in full concurrency mode */
1523 rx_ant = first_antenna(rx_ant);
1524 }
1525
1526 /* MIMO is not used here, but value is required */
1527 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1528 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1529 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1530 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1531 scan->rx_chain = cpu_to_le16(rx_chain);
1532 if (!priv->is_internal_short_scan) {
1533 cmd_len = iwl_fill_probe_req(priv,
1534 (struct ieee80211_mgmt *)scan->data,
1535 vif->addr,
1536 priv->scan_request->ie,
1537 priv->scan_request->ie_len,
1538 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1539 } else {
1540 /* use bcast addr, will not be transmitted but must be valid */
1541 cmd_len = iwl_fill_probe_req(priv,
1542 (struct ieee80211_mgmt *)scan->data,
1543 iwl_bcast_addr, NULL, 0,
1544 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1545
1546 }
1547 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1548
1549 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1550 RXON_FILTER_BCON_AWARE_MSK);
1551
1552 if (priv->is_internal_short_scan) {
1553 scan->channel_count =
1554 iwl_get_single_channel_for_scan(priv, vif, band,
1555 (void *)&scan->data[le16_to_cpu(
1556 scan->tx_cmd.len)]);
1557 } else {
1558 scan->channel_count =
1559 iwl_get_channels_for_scan(priv, vif, band,
1560 is_active, n_probes,
1561 (void *)&scan->data[le16_to_cpu(
1562 scan->tx_cmd.len)]);
1563 }
1564 if (scan->channel_count == 0) {
1565 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1566 return -EIO;
1567 }
1568
1569 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1570 scan->channel_count * sizeof(struct iwl_scan_channel);
1571 cmd.data = scan;
1572 scan->len = cpu_to_le16(cmd.len);
1573
1574 /* set scan bit here for PAN params */
1575 set_bit(STATUS_SCAN_HW, &priv->status);
1576
1577 if (priv->cfg->ops->hcmd->set_pan_params) {
1578 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1579 if (ret)
1580 return ret;
1581 }
1582
1583 ret = iwl_send_cmd_sync(priv, &cmd);
1584 if (ret) {
1585 clear_bit(STATUS_SCAN_HW, &priv->status);
1586 if (priv->cfg->ops->hcmd->set_pan_params)
1587 priv->cfg->ops->hcmd->set_pan_params(priv);
1588 }
1589
1590 return ret;
1591 }
1592
1593 void iwlagn_post_scan(struct iwl_priv *priv)
1594 {
1595 struct iwl_rxon_context *ctx;
1596
1597 /*
1598 * Since setting the RXON may have been deferred while
1599 * performing the scan, fire one off if needed
1600 */
1601 for_each_context(priv, ctx)
1602 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
1603 iwlagn_commit_rxon(priv, ctx);
1604
1605 if (priv->cfg->ops->hcmd->set_pan_params)
1606 priv->cfg->ops->hcmd->set_pan_params(priv);
1607 }
1608
1609 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1610 struct ieee80211_vif *vif, bool add)
1611 {
1612 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1613
1614 if (add)
1615 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1616 vif->bss_conf.bssid,
1617 &vif_priv->ibss_bssid_sta_id);
1618 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1619 vif->bss_conf.bssid);
1620 }
1621
1622 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1623 int sta_id, int tid, int freed)
1624 {
1625 lockdep_assert_held(&priv->sta_lock);
1626
1627 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1628 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1629 else {
1630 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1631 priv->stations[sta_id].tid[tid].tfds_in_queue,
1632 freed);
1633 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1634 }
1635 }
1636
1637 #define IWL_FLUSH_WAIT_MS 2000
1638
1639 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1640 {
1641 struct iwl_tx_queue *txq;
1642 struct iwl_queue *q;
1643 int cnt;
1644 unsigned long now = jiffies;
1645 int ret = 0;
1646
1647 /* waiting for all the tx frames complete might take a while */
1648 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1649 if (cnt == priv->cmd_queue)
1650 continue;
1651 txq = &priv->txq[cnt];
1652 q = &txq->q;
1653 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1654 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1655 msleep(1);
1656
1657 if (q->read_ptr != q->write_ptr) {
1658 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1659 ret = -ETIMEDOUT;
1660 break;
1661 }
1662 }
1663 return ret;
1664 }
1665
1666 #define IWL_TX_QUEUE_MSK 0xfffff
1667
1668 /**
1669 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1670 *
1671 * pre-requirements:
1672 * 1. acquire mutex before calling
1673 * 2. make sure rf is on and not in exit state
1674 */
1675 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1676 {
1677 struct iwl_txfifo_flush_cmd flush_cmd;
1678 struct iwl_host_cmd cmd = {
1679 .id = REPLY_TXFIFO_FLUSH,
1680 .len = sizeof(struct iwl_txfifo_flush_cmd),
1681 .flags = CMD_SYNC,
1682 .data = &flush_cmd,
1683 };
1684
1685 might_sleep();
1686
1687 memset(&flush_cmd, 0, sizeof(flush_cmd));
1688 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1689 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1690 if (priv->cfg->sku & IWL_SKU_N)
1691 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1692
1693 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1694 flush_cmd.fifo_control);
1695 flush_cmd.flush_control = cpu_to_le16(flush_control);
1696
1697 return iwl_send_cmd(priv, &cmd);
1698 }
1699
1700 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1701 {
1702 mutex_lock(&priv->mutex);
1703 ieee80211_stop_queues(priv->hw);
1704 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1705 IWL_ERR(priv, "flush request fail\n");
1706 goto done;
1707 }
1708 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1709 iwlagn_wait_tx_queue_empty(priv);
1710 done:
1711 ieee80211_wake_queues(priv->hw);
1712 mutex_unlock(&priv->mutex);
1713 }
1714
1715 /*
1716 * BT coex
1717 */
1718 /*
1719 * Macros to access the lookup table.
1720 *
1721 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1722 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1723 *
1724 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1725 *
1726 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1727 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1728 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1729 *
1730 * These macros encode that format.
1731 */
1732 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1733 wifi_txrx, wifi_sh_ant_req) \
1734 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1735 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1736
1737 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1738 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1739 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1740 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1741 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1742 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1743 wifi_sh_ant_req))))
1744 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1745 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1746 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1747 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1748 wifi_sh_ant_req))
1749 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1750 wifi_req, wifi_prio, wifi_txrx, \
1751 wifi_sh_ant_req) \
1752 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1753 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1754 wifi_sh_ant_req))
1755
1756 #define LUT_WLAN_KILL_OP(lut, op, val) \
1757 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1758 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1759 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1760 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1761 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1762 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1763 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1764 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1765 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1766 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1767 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1768 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1769 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1770
1771 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1772 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1773 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1774 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1775 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1776 wifi_req, wifi_prio, wifi_txrx, \
1777 wifi_sh_ant_req))))
1778 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1779 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1780 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1781 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1782 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1783 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1784 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1785 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1786
1787 static const __le32 iwlagn_def_3w_lookup[12] = {
1788 cpu_to_le32(0xaaaaaaaa),
1789 cpu_to_le32(0xaaaaaaaa),
1790 cpu_to_le32(0xaeaaaaaa),
1791 cpu_to_le32(0xaaaaaaaa),
1792 cpu_to_le32(0xcc00ff28),
1793 cpu_to_le32(0x0000aaaa),
1794 cpu_to_le32(0xcc00aaaa),
1795 cpu_to_le32(0x0000aaaa),
1796 cpu_to_le32(0xc0004000),
1797 cpu_to_le32(0x00004000),
1798 cpu_to_le32(0xf0005000),
1799 cpu_to_le32(0xf0004000),
1800 };
1801
1802 static const __le32 iwlagn_concurrent_lookup[12] = {
1803 cpu_to_le32(0xaaaaaaaa),
1804 cpu_to_le32(0xaaaaaaaa),
1805 cpu_to_le32(0xaaaaaaaa),
1806 cpu_to_le32(0xaaaaaaaa),
1807 cpu_to_le32(0xaaaaaaaa),
1808 cpu_to_le32(0xaaaaaaaa),
1809 cpu_to_le32(0xaaaaaaaa),
1810 cpu_to_le32(0xaaaaaaaa),
1811 cpu_to_le32(0x00000000),
1812 cpu_to_le32(0x00000000),
1813 cpu_to_le32(0x00000000),
1814 cpu_to_le32(0x00000000),
1815 };
1816
1817 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1818 {
1819 struct iwlagn_bt_cmd bt_cmd = {
1820 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1821 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1822 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1823 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1824 };
1825
1826 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1827 sizeof(bt_cmd.bt3_lookup_table));
1828
1829 if (priv->cfg->bt_params)
1830 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1831 else
1832 bt_cmd.prio_boost = 0;
1833 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1834 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1835 bt_cmd.valid = priv->bt_valid;
1836 bt_cmd.tx_prio_boost = 0;
1837 bt_cmd.rx_prio_boost = 0;
1838
1839 /*
1840 * Configure BT coex mode to "no coexistence" when the
1841 * user disabled BT coexistence, we have no interface
1842 * (might be in monitor mode), or the interface is in
1843 * IBSS mode (no proper uCode support for coex then).
1844 */
1845 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1846 bt_cmd.flags = 0;
1847 } else {
1848 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1849 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1850 if (priv->bt_ch_announce)
1851 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1852 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1853 }
1854 if (priv->bt_full_concurrent)
1855 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1856 sizeof(iwlagn_concurrent_lookup));
1857 else
1858 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1859 sizeof(iwlagn_def_3w_lookup));
1860
1861 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1862 bt_cmd.flags ? "active" : "disabled",
1863 priv->bt_full_concurrent ?
1864 "full concurrency" : "3-wire");
1865
1866 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1867 IWL_ERR(priv, "failed to send BT Coex Config\n");
1868
1869 /*
1870 * When we are doing a restart, need to also reconfigure BT
1871 * SCO to the device. If not doing a restart, bt_sco_active
1872 * will always be false, so there's no need to have an extra
1873 * variable to check for it.
1874 */
1875 if (priv->bt_sco_active) {
1876 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1877
1878 if (priv->bt_sco_active)
1879 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1880 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1881 sizeof(sco_cmd), &sco_cmd))
1882 IWL_ERR(priv, "failed to send BT SCO command\n");
1883 }
1884 }
1885
1886 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1887 {
1888 struct iwl_priv *priv =
1889 container_of(work, struct iwl_priv, bt_traffic_change_work);
1890 struct iwl_rxon_context *ctx;
1891 int smps_request = -1;
1892
1893 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1894 priv->bt_traffic_load);
1895
1896 switch (priv->bt_traffic_load) {
1897 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1898 smps_request = IEEE80211_SMPS_AUTOMATIC;
1899 break;
1900 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1901 smps_request = IEEE80211_SMPS_DYNAMIC;
1902 break;
1903 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1904 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1905 smps_request = IEEE80211_SMPS_STATIC;
1906 break;
1907 default:
1908 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1909 priv->bt_traffic_load);
1910 break;
1911 }
1912
1913 mutex_lock(&priv->mutex);
1914
1915 if (priv->cfg->ops->lib->update_chain_flags)
1916 priv->cfg->ops->lib->update_chain_flags(priv);
1917
1918 if (smps_request != -1) {
1919 for_each_context(priv, ctx) {
1920 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1921 ieee80211_request_smps(ctx->vif, smps_request);
1922 }
1923 }
1924
1925 mutex_unlock(&priv->mutex);
1926 }
1927
1928 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1929 struct iwl_bt_uart_msg *uart_msg)
1930 {
1931 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1932 "Update Req = 0x%X",
1933 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1934 BT_UART_MSG_FRAME1MSGTYPE_POS,
1935 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1936 BT_UART_MSG_FRAME1SSN_POS,
1937 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1938 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1939
1940 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1941 "Chl_SeqN = 0x%X, In band = 0x%X",
1942 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1943 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1944 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1945 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1946 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1947 BT_UART_MSG_FRAME2CHLSEQN_POS,
1948 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1949 BT_UART_MSG_FRAME2INBAND_POS);
1950
1951 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1952 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1953 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1954 BT_UART_MSG_FRAME3SCOESCO_POS,
1955 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1956 BT_UART_MSG_FRAME3SNIFF_POS,
1957 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1958 BT_UART_MSG_FRAME3A2DP_POS,
1959 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1960 BT_UART_MSG_FRAME3ACL_POS,
1961 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1962 BT_UART_MSG_FRAME3MASTER_POS,
1963 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1964 BT_UART_MSG_FRAME3OBEX_POS);
1965
1966 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1967 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1968 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1969
1970 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1971 "eSCO Retransmissions = 0x%X",
1972 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1973 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1974 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1975 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1976 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1977 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1978
1979 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1980 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1981 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1982 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1983 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1984
1985 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1986 "0x%X, Connectable = 0x%X",
1987 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1988 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1989 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1990 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1991 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1992 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1993 }
1994
1995 static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
1996 struct iwl_bt_uart_msg *uart_msg)
1997 {
1998 u8 kill_ack_msk;
1999 __le32 bt_kill_ack_msg[2] = {
2000 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
2001
2002 kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
2003 BT_UART_MSG_FRAME3SNIFF_MSK |
2004 BT_UART_MSG_FRAME3SCOESCO_MSK) &
2005 uart_msg->frame3) == 0) ? 1 : 0;
2006 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
2007 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2008 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
2009 /* schedule to send runtime bt_config */
2010 queue_work(priv->workqueue, &priv->bt_runtime_config);
2011 }
2012
2013 }
2014
2015 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2016 struct iwl_rx_mem_buffer *rxb)
2017 {
2018 unsigned long flags;
2019 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2020 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2021 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
2022 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2023 u8 last_traffic_load;
2024
2025 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2026 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
2027 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
2028 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
2029 coex->bt_ci_compliance);
2030 iwlagn_print_uartmsg(priv, uart_msg);
2031
2032 last_traffic_load = priv->notif_bt_traffic_load;
2033 priv->notif_bt_traffic_load = coex->bt_traffic_load;
2034 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2035 if (priv->bt_status != coex->bt_status ||
2036 last_traffic_load != coex->bt_traffic_load) {
2037 if (coex->bt_status) {
2038 /* BT on */
2039 if (!priv->bt_ch_announce)
2040 priv->bt_traffic_load =
2041 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2042 else
2043 priv->bt_traffic_load =
2044 coex->bt_traffic_load;
2045 } else {
2046 /* BT off */
2047 priv->bt_traffic_load =
2048 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2049 }
2050 priv->bt_status = coex->bt_status;
2051 queue_work(priv->workqueue,
2052 &priv->bt_traffic_change_work);
2053 }
2054 if (priv->bt_sco_active !=
2055 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2056 priv->bt_sco_active = uart_msg->frame3 &
2057 BT_UART_MSG_FRAME3SCOESCO_MSK;
2058 if (priv->bt_sco_active)
2059 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2060 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2061 sizeof(sco_cmd), &sco_cmd, NULL);
2062 }
2063 }
2064
2065 iwlagn_set_kill_ack_msk(priv, uart_msg);
2066
2067 /* FIXME: based on notification, adjust the prio_boost */
2068
2069 spin_lock_irqsave(&priv->lock, flags);
2070 priv->bt_ci_compliance = coex->bt_ci_compliance;
2071 spin_unlock_irqrestore(&priv->lock, flags);
2072 }
2073
2074 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2075 {
2076 iwlagn_rx_handler_setup(priv);
2077 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2078 iwlagn_bt_coex_profile_notif;
2079 }
2080
2081 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2082 {
2083 iwlagn_setup_deferred_work(priv);
2084
2085 INIT_WORK(&priv->bt_traffic_change_work,
2086 iwlagn_bt_traffic_change_work);
2087 }
2088
2089 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2090 {
2091 cancel_work_sync(&priv->bt_traffic_change_work);
2092 }
2093
2094 static bool is_single_rx_stream(struct iwl_priv *priv)
2095 {
2096 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2097 priv->current_ht_config.single_chain_sufficient;
2098 }
2099
2100 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
2101 #define IWL_NUM_RX_CHAINS_SINGLE 2
2102 #define IWL_NUM_IDLE_CHAINS_DUAL 2
2103 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
2104
2105 /*
2106 * Determine how many receiver/antenna chains to use.
2107 *
2108 * More provides better reception via diversity. Fewer saves power
2109 * at the expense of throughput, but only when not in powersave to
2110 * start with.
2111 *
2112 * MIMO (dual stream) requires at least 2, but works better with 3.
2113 * This does not determine *which* chains to use, just how many.
2114 */
2115 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2116 {
2117 if (priv->cfg->bt_params &&
2118 priv->cfg->bt_params->advanced_bt_coexist &&
2119 (priv->bt_full_concurrent ||
2120 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2121 /*
2122 * only use chain 'A' in bt high traffic load or
2123 * full concurrency mode
2124 */
2125 return IWL_NUM_RX_CHAINS_SINGLE;
2126 }
2127 /* # of Rx chains to use when expecting MIMO. */
2128 if (is_single_rx_stream(priv))
2129 return IWL_NUM_RX_CHAINS_SINGLE;
2130 else
2131 return IWL_NUM_RX_CHAINS_MULTIPLE;
2132 }
2133
2134 /*
2135 * When we are in power saving mode, unless device support spatial
2136 * multiplexing power save, use the active count for rx chain count.
2137 */
2138 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2139 {
2140 /* # Rx chains when idling, depending on SMPS mode */
2141 switch (priv->current_ht_config.smps) {
2142 case IEEE80211_SMPS_STATIC:
2143 case IEEE80211_SMPS_DYNAMIC:
2144 return IWL_NUM_IDLE_CHAINS_SINGLE;
2145 case IEEE80211_SMPS_OFF:
2146 return active_cnt;
2147 default:
2148 WARN(1, "invalid SMPS mode %d",
2149 priv->current_ht_config.smps);
2150 return active_cnt;
2151 }
2152 }
2153
2154 /* up to 4 chains */
2155 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2156 {
2157 u8 res;
2158 res = (chain_bitmap & BIT(0)) >> 0;
2159 res += (chain_bitmap & BIT(1)) >> 1;
2160 res += (chain_bitmap & BIT(2)) >> 2;
2161 res += (chain_bitmap & BIT(3)) >> 3;
2162 return res;
2163 }
2164
2165 /**
2166 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2167 *
2168 * Selects how many and which Rx receivers/antennas/chains to use.
2169 * This should not be used for scan command ... it puts data in wrong place.
2170 */
2171 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2172 {
2173 bool is_single = is_single_rx_stream(priv);
2174 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2175 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2176 u32 active_chains;
2177 u16 rx_chain;
2178
2179 /* Tell uCode which antennas are actually connected.
2180 * Before first association, we assume all antennas are connected.
2181 * Just after first association, iwl_chain_noise_calibration()
2182 * checks which antennas actually *are* connected. */
2183 if (priv->chain_noise_data.active_chains)
2184 active_chains = priv->chain_noise_data.active_chains;
2185 else
2186 active_chains = priv->hw_params.valid_rx_ant;
2187
2188 if (priv->cfg->bt_params &&
2189 priv->cfg->bt_params->advanced_bt_coexist &&
2190 (priv->bt_full_concurrent ||
2191 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2192 /*
2193 * only use chain 'A' in bt high traffic load or
2194 * full concurrency mode
2195 */
2196 active_chains = first_antenna(active_chains);
2197 }
2198
2199 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2200
2201 /* How many receivers should we use? */
2202 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2203 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2204
2205
2206 /* correct rx chain count according hw settings
2207 * and chain noise calibration
2208 */
2209 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2210 if (valid_rx_cnt < active_rx_cnt)
2211 active_rx_cnt = valid_rx_cnt;
2212
2213 if (valid_rx_cnt < idle_rx_cnt)
2214 idle_rx_cnt = valid_rx_cnt;
2215
2216 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2217 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2218
2219 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2220
2221 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2222 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2223 else
2224 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2225
2226 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2227 ctx->staging.rx_chain,
2228 active_rx_cnt, idle_rx_cnt);
2229
2230 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2231 active_rx_cnt < idle_rx_cnt);
2232 }
2233
2234 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2235 {
2236 int i;
2237 u8 ind = ant;
2238
2239 if (priv->band == IEEE80211_BAND_2GHZ &&
2240 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2241 return 0;
2242
2243 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2244 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2245 if (valid & BIT(ind))
2246 return ind;
2247 }
2248 return ant;
2249 }
2250
2251 static const char *get_csr_string(int cmd)
2252 {
2253 switch (cmd) {
2254 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2255 IWL_CMD(CSR_INT_COALESCING);
2256 IWL_CMD(CSR_INT);
2257 IWL_CMD(CSR_INT_MASK);
2258 IWL_CMD(CSR_FH_INT_STATUS);
2259 IWL_CMD(CSR_GPIO_IN);
2260 IWL_CMD(CSR_RESET);
2261 IWL_CMD(CSR_GP_CNTRL);
2262 IWL_CMD(CSR_HW_REV);
2263 IWL_CMD(CSR_EEPROM_REG);
2264 IWL_CMD(CSR_EEPROM_GP);
2265 IWL_CMD(CSR_OTP_GP_REG);
2266 IWL_CMD(CSR_GIO_REG);
2267 IWL_CMD(CSR_GP_UCODE_REG);
2268 IWL_CMD(CSR_GP_DRIVER_REG);
2269 IWL_CMD(CSR_UCODE_DRV_GP1);
2270 IWL_CMD(CSR_UCODE_DRV_GP2);
2271 IWL_CMD(CSR_LED_REG);
2272 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2273 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2274 IWL_CMD(CSR_ANA_PLL_CFG);
2275 IWL_CMD(CSR_HW_REV_WA_REG);
2276 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2277 default:
2278 return "UNKNOWN";
2279 }
2280 }
2281
2282 void iwl_dump_csr(struct iwl_priv *priv)
2283 {
2284 int i;
2285 u32 csr_tbl[] = {
2286 CSR_HW_IF_CONFIG_REG,
2287 CSR_INT_COALESCING,
2288 CSR_INT,
2289 CSR_INT_MASK,
2290 CSR_FH_INT_STATUS,
2291 CSR_GPIO_IN,
2292 CSR_RESET,
2293 CSR_GP_CNTRL,
2294 CSR_HW_REV,
2295 CSR_EEPROM_REG,
2296 CSR_EEPROM_GP,
2297 CSR_OTP_GP_REG,
2298 CSR_GIO_REG,
2299 CSR_GP_UCODE_REG,
2300 CSR_GP_DRIVER_REG,
2301 CSR_UCODE_DRV_GP1,
2302 CSR_UCODE_DRV_GP2,
2303 CSR_LED_REG,
2304 CSR_DRAM_INT_TBL_REG,
2305 CSR_GIO_CHICKEN_BITS,
2306 CSR_ANA_PLL_CFG,
2307 CSR_HW_REV_WA_REG,
2308 CSR_DBG_HPET_MEM_REG
2309 };
2310 IWL_ERR(priv, "CSR values:\n");
2311 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2312 "CSR_INT_PERIODIC_REG)\n");
2313 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2314 IWL_ERR(priv, " %25s: 0X%08x\n",
2315 get_csr_string(csr_tbl[i]),
2316 iwl_read32(priv, csr_tbl[i]));
2317 }
2318 }
2319
2320 static const char *get_fh_string(int cmd)
2321 {
2322 switch (cmd) {
2323 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2324 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2325 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2326 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2327 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2328 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2329 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2330 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2331 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2332 default:
2333 return "UNKNOWN";
2334 }
2335 }
2336
2337 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2338 {
2339 int i;
2340 #ifdef CONFIG_IWLWIFI_DEBUG
2341 int pos = 0;
2342 size_t bufsz = 0;
2343 #endif
2344 u32 fh_tbl[] = {
2345 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2346 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2347 FH_RSCSR_CHNL0_WPTR,
2348 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2349 FH_MEM_RSSR_SHARED_CTRL_REG,
2350 FH_MEM_RSSR_RX_STATUS_REG,
2351 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2352 FH_TSSR_TX_STATUS_REG,
2353 FH_TSSR_TX_ERROR_REG
2354 };
2355 #ifdef CONFIG_IWLWIFI_DEBUG
2356 if (display) {
2357 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2358 *buf = kmalloc(bufsz, GFP_KERNEL);
2359 if (!*buf)
2360 return -ENOMEM;
2361 pos += scnprintf(*buf + pos, bufsz - pos,
2362 "FH register values:\n");
2363 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2364 pos += scnprintf(*buf + pos, bufsz - pos,
2365 " %34s: 0X%08x\n",
2366 get_fh_string(fh_tbl[i]),
2367 iwl_read_direct32(priv, fh_tbl[i]));
2368 }
2369 return pos;
2370 }
2371 #endif
2372 IWL_ERR(priv, "FH register values:\n");
2373 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2374 IWL_ERR(priv, " %34s: 0X%08x\n",
2375 get_fh_string(fh_tbl[i]),
2376 iwl_read_direct32(priv, fh_tbl[i]));
2377 }
2378 return 0;
2379 }
kernel source for telekom puls (alcatel/mediatek)