drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/leds.h>
  23 #include <linux/completion.h>
  24
  25 #include "debug.h"
  26 #include "common.h"
  27
  28 /*
  29  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  30  * should rely on this file or its contents.
  31  */
  32
  33 struct ath_node;
  34
  35 /* Macro to expand scalars to 64-bit objects */
  36
  37 #define ito64(x) (sizeof(x) == 1) ?                     \
  38         (((unsigned long long int)(x)) & (0xff)) :      \
  39         (sizeof(x) == 2) ?                              \
  40         (((unsigned long long int)(x)) & 0xffff) :      \
  41         ((sizeof(x) == 4) ?                             \
  42          (((unsigned long long int)(x)) & 0xffffffff) : \
  43          (unsigned long long int)(x))
  44
  45 /* increment with wrap-around */
  46 #define INCR(_l, _sz)   do {                    \
  47                 (_l)++;                         \
  48                 (_l) &= ((_sz) - 1);            \
  49         } while (0)
  50
  51 /* decrement with wrap-around */
  52 #define DECR(_l,  _sz)  do {                    \
  53                 (_l)--;                         \
  54                 (_l) &= ((_sz) - 1);            \
  55         } while (0)
  56
  57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  58
  59 #define TSF_TO_TU(_h,_l) \
  60         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  61
  62 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  63
  64 struct ath_config {
  65         u32 ath_aggr_prot;
  66         u16 txpowlimit;
  67         u8 cabqReadytime;
  68 };
  69
  70 /*************************/
  71 /* Descriptor Management */
  72 /*************************/
  73
  74 #define ATH_TXBUF_RESET(_bf) do {                               \
  75                 (_bf)->bf_stale = false;                        \
  76                 (_bf)->bf_lastbf = NULL;                        \
  77                 (_bf)->bf_next = NULL;                          \
  78                 memset(&((_bf)->bf_state), 0,                   \
  79                        sizeof(struct ath_buf_state));           \
  80         } while (0)
  81
  82 #define ATH_RXBUF_RESET(_bf) do {               \
  83                 (_bf)->bf_stale = false;        \
  84         } while (0)
  85
  86 /**
  87  * enum buffer_type - Buffer type flags
  88  *
  89  * @BUF_HT: Send this buffer using HT capabilities
  90  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  91  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  92  *      (used in aggregation scheduling)
  93  * @BUF_RETRY: Indicates whether the buffer is retried
  94  * @BUF_XRETRY: To denote excessive retries of the buffer
  95  */
  96 enum buffer_type {
  97         BUF_HT                  = BIT(1),
  98         BUF_AMPDU               = BIT(2),
  99         BUF_AGGR                = BIT(3),
 100         BUF_RETRY               = BIT(4),
 101         BUF_XRETRY              = BIT(5),
 102 };
 103
 104 #define bf_nframes              bf_state.bfs_nframes
 105 #define bf_al                   bf_state.bfs_al
 106 #define bf_frmlen               bf_state.bfs_frmlen
 107 #define bf_retries              bf_state.bfs_retries
 108 #define bf_seqno                bf_state.bfs_seqno
 109 #define bf_tidno                bf_state.bfs_tidno
 110 #define bf_keyix                bf_state.bfs_keyix
 111 #define bf_keytype              bf_state.bfs_keytype
 112 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 113 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 114 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 115 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 116 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 117
 118 #define ATH_TXSTATUS_RING_SIZE 64
 119
 120 struct ath_descdma {
 121         void *dd_desc;
 122         dma_addr_t dd_desc_paddr;
 123         u32 dd_desc_len;
 124         struct ath_buf *dd_bufptr;
 125 };
 126
 127 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 128                       struct list_head *head, const char *name,
 129                       int nbuf, int ndesc, bool is_tx);
 130 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 131                          struct list_head *head);
 132
 133 /***********/
 134 /* RX / TX */
 135 /***********/
 136
 137 #define ATH_MAX_ANTENNA         3
 138 #define ATH_RXBUF               512
 139 #define ATH_TXBUF               512
 140 #define ATH_TXBUF_RESERVE       5
 141 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 142 #define ATH_TXMAXTRY            13
 143 #define ATH_MGT_TXMAXTRY        4
 144
 145 #define TID_TO_WME_AC(_tid)                             \
 146         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 147          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 148          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 149          WME_AC_VO)
 150
 151 #define ADDBA_EXCHANGE_ATTEMPTS    10
 152 #define ATH_AGGR_DELIM_SZ          4
 153 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 154 /* number of delimiters for encryption padding */
 155 #define ATH_AGGR_ENCRYPTDELIM      10
 156 /* minimum h/w qdepth to be sustained to maximize aggregation */
 157 #define ATH_AGGR_MIN_QDEPTH        2
 158 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 159
 160 #define IEEE80211_SEQ_SEQ_SHIFT    4
 161 #define IEEE80211_SEQ_MAX          4096
 162 #define IEEE80211_WEP_IVLEN        3
 163 #define IEEE80211_WEP_KIDLEN       1
 164 #define IEEE80211_WEP_CRCLEN       4
 165 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 166                                     (IEEE80211_WEP_IVLEN +      \
 167                                      IEEE80211_WEP_KIDLEN +     \
 168                                      IEEE80211_WEP_CRCLEN))
 169
 170 /* return whether a bit at index _n in bitmap _bm is set
 171  * _sz is the size of the bitmap  */
 172 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 173                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 174
 175 /* return block-ack bitmap index given sequence and starting sequence */
 176 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 177
 178 /* returns delimiter padding required given the packet length */
 179 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 180         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 181           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 182
 183 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 184         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 185
 186 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 187
 188 #define ATH_TX_COMPLETE_POLL_INT        1000
 189
 190 enum ATH_AGGR_STATUS {
 191         ATH_AGGR_DONE,
 192         ATH_AGGR_BAW_CLOSED,
 193         ATH_AGGR_LIMITED,
 194 };
 195
 196 #define ATH_TXFIFO_DEPTH 8
 197 struct ath_txq {
 198         int axq_class;
 199         u32 axq_qnum;
 200         u32 *axq_link;
 201         struct list_head axq_q;
 202         spinlock_t axq_lock;
 203         u32 axq_depth;
 204         bool stopped;
 205         bool axq_tx_inprogress;
 206         struct list_head axq_acq;
 207         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 208         struct list_head txq_fifo_pending;
 209         u8 txq_headidx;
 210         u8 txq_tailidx;
 211 };
 212
 213 struct ath_atx_ac {
 214         int sched;
 215         int qnum;
 216         struct list_head list;
 217         struct list_head tid_q;
 218 };
 219
 220 struct ath_buf_state {
 221         int bfs_nframes;
 222         u16 bfs_al;
 223         u16 bfs_frmlen;
 224         int bfs_seqno;
 225         int bfs_tidno;
 226         int bfs_retries;
 227         u8 bf_type;
 228         u8 bfs_paprd;
 229         unsigned long bfs_paprd_timestamp;
 230         u32 bfs_keyix;
 231         enum ath9k_key_type bfs_keytype;
 232 };
 233
 234 struct ath_buf {
 235         struct list_head list;
 236         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 237                                            an aggregate) */
 238         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 239         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 240         void *bf_desc;                  /* virtual addr of desc */
 241         dma_addr_t bf_daddr;            /* physical addr of desc */
 242         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 243         bool bf_stale;
 244         bool bf_tx_aborted;
 245         u16 bf_flags;
 246         struct ath_buf_state bf_state;
 247         struct ath_wiphy *aphy;
 248 };
 249
 250 struct ath_atx_tid {
 251         struct list_head list;
 252         struct list_head buf_q;
 253         struct ath_node *an;
 254         struct ath_atx_ac *ac;
 255         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 256         u16 seq_start;
 257         u16 seq_next;
 258         u16 baw_size;
 259         int tidno;
 260         int baw_head;   /* first un-acked tx buffer */
 261         int baw_tail;   /* next unused tx buffer slot */
 262         int sched;
 263         int paused;
 264         u8 state;
 265 };
 266
 267 struct ath_node {
 268         struct ath_common *common;
 269         struct ath_atx_tid tid[WME_NUM_TID];
 270         struct ath_atx_ac ac[WME_NUM_AC];
 271         u16 maxampdu;
 272         u8 mpdudensity;
 273         int last_rssi;
 274 };
 275
 276 #define AGGR_CLEANUP         BIT(1)
 277 #define AGGR_ADDBA_COMPLETE  BIT(2)
 278 #define AGGR_ADDBA_PROGRESS  BIT(3)
 279
 280 struct ath_tx_control {
 281         struct ath_txq *txq;
 282         int if_id;
 283         enum ath9k_internal_frame_type frame_type;
 284         u8 paprd;
 285 };
 286
 287 #define ATH_TX_ERROR        0x01
 288 #define ATH_TX_XRETRY       0x02
 289 #define ATH_TX_BAR          0x04
 290
 291 struct ath_tx {
 292         u16 seq_no;
 293         u32 txqsetup;
 294         int hwq_map[WME_NUM_AC];
 295         spinlock_t txbuflock;
 296         struct list_head txbuf;
 297         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 298         struct ath_descdma txdma;
 299         int pending_frames[WME_NUM_AC];
 300 };
 301
 302 struct ath_rx_edma {
 303         struct sk_buff_head rx_fifo;
 304         struct sk_buff_head rx_buffers;
 305         u32 rx_fifo_hwsize;
 306 };
 307
 308 struct ath_rx {
 309         u8 defant;
 310         u8 rxotherant;
 311         u32 *rxlink;
 312         unsigned int rxfilter;
 313         spinlock_t pcu_lock;
 314         spinlock_t rxbuflock;
 315         struct list_head rxbuf;
 316         struct ath_descdma rxdma;
 317         struct ath_buf *rx_bufptr;
 318         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 319 };
 320
 321 int ath_startrecv(struct ath_softc *sc);
 322 bool ath_stoprecv(struct ath_softc *sc);
 323 void ath_flushrecv(struct ath_softc *sc);
 324 u32 ath_calcrxfilter(struct ath_softc *sc);
 325 int ath_rx_init(struct ath_softc *sc, int nbufs);
 326 void ath_rx_cleanup(struct ath_softc *sc);
 327 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 328 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 329 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 330 int ath_tx_setup(struct ath_softc *sc, int haltype);
 331 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 332 void ath_draintxq(struct ath_softc *sc,
 333                      struct ath_txq *txq, bool retry_tx);
 334 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 335 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 336 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 337 int ath_tx_init(struct ath_softc *sc, int nbufs);
 338 void ath_tx_cleanup(struct ath_softc *sc);
 339 int ath_txq_update(struct ath_softc *sc, int qnum,
 340                    struct ath9k_tx_queue_info *q);
 341 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 342                  struct ath_tx_control *txctl);
 343 void ath_tx_tasklet(struct ath_softc *sc);
 344 void ath_tx_edma_tasklet(struct ath_softc *sc);
 345 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
 346 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 347                       u16 tid, u16 *ssn);
 348 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 349 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 350
 351 /********/
 352 /* VIFs */
 353 /********/
 354
 355 struct ath_vif {
 356         int av_bslot;
 357         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 358         enum nl80211_iftype av_opmode;
 359         struct ath_buf *av_bcbuf;
 360         struct ath_tx_control av_btxctl;
 361         u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 362 };
 363
 364 /*******************/
 365 /* Beacon Handling */
 366 /*******************/
 367
 368 /*
 369  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 370  * number of BSSIDs) if a given beacon does not go out even after waiting this
 371  * number of beacon intervals, the game's up.
 372  */
 373 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 374 #define ATH_BCBUF                       4
 375 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 376 #define ATH_DEFAULT_BMISS_LIMIT         10
 377 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 378
 379 struct ath_beacon_config {
 380         u16 beacon_interval;
 381         u16 listen_interval;
 382         u16 dtim_period;
 383         u16 bmiss_timeout;
 384         u8 dtim_count;
 385 };
 386
 387 struct ath_beacon {
 388         enum {
 389                 OK,             /* no change needed */
 390                 UPDATE,         /* update pending */
 391                 COMMIT          /* beacon sent, commit change */
 392         } updateslot;           /* slot time update fsm */
 393
 394         u32 beaconq;
 395         u32 bmisscnt;
 396         u32 ast_be_xmit;
 397         u64 bc_tstamp;
 398         struct ieee80211_vif *bslot[ATH_BCBUF];
 399         struct ath_wiphy *bslot_aphy[ATH_BCBUF];
 400         int slottime;
 401         int slotupdate;
 402         struct ath9k_tx_queue_info beacon_qi;
 403         struct ath_descdma bdma;
 404         struct ath_txq *cabq;
 405         struct list_head bbuf;
 406 };
 407
 408 void ath_beacon_tasklet(unsigned long data);
 409 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 410 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
 411 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 412 int ath_beaconq_config(struct ath_softc *sc);
 413
 414 /*******/
 415 /* ANI */
 416 /*******/
 417
 418 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 419 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 420 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 421 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 422 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 423 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 424 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 425
 426 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 427
 428 void ath_hw_check(struct work_struct *work);
 429 void ath_paprd_calibrate(struct work_struct *work);
 430 void ath_ani_calibrate(unsigned long data);
 431
 432 /**********/
 433 /* BTCOEX */
 434 /**********/
 435
 436 struct ath_btcoex {
 437         bool hw_timer_enabled;
 438         spinlock_t btcoex_lock;
 439         struct timer_list period_timer; /* Timer for BT period */
 440         u32 bt_priority_cnt;
 441         unsigned long bt_priority_time;
 442         int bt_stomp_type; /* Types of BT stomping */
 443         u32 btcoex_no_stomp; /* in usec */
 444         u32 btcoex_period; /* in usec */
 445         u32 btscan_no_stomp; /* in usec */
 446         struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 447 };
 448
 449 int ath_init_btcoex_timer(struct ath_softc *sc);
 450 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 451 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 452
 453 /********************/
 454 /*   LED Control    */
 455 /********************/
 456
 457 #define ATH_LED_PIN_DEF                 1
 458 #define ATH_LED_PIN_9287                8
 459 #define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
 460 #define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
 461
 462 enum ath_led_type {
 463         ATH_LED_RADIO,
 464         ATH_LED_ASSOC,
 465         ATH_LED_TX,
 466         ATH_LED_RX
 467 };
 468
 469 struct ath_led {
 470         struct ath_softc *sc;
 471         struct led_classdev led_cdev;
 472         enum ath_led_type led_type;
 473         char name[32];
 474         bool registered;
 475 };
 476
 477 void ath_init_leds(struct ath_softc *sc);
 478 void ath_deinit_leds(struct ath_softc *sc);
 479
 480 /* Antenna diversity/combining */
 481 #define ATH_ANT_RX_CURRENT_SHIFT 4
 482 #define ATH_ANT_RX_MAIN_SHIFT 2
 483 #define ATH_ANT_RX_MASK 0x3
 484
 485 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 486 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 487 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 488 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 489 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 490 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 491 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 492
 493 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
 494 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
 495 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 496 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 497 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 498
 499 enum ath9k_ant_div_comb_lna_conf {
 500         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
 501         ATH_ANT_DIV_COMB_LNA2,
 502         ATH_ANT_DIV_COMB_LNA1,
 503         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 504 };
 505
 506 struct ath_ant_comb {
 507         u16 count;
 508         u16 total_pkt_count;
 509         bool scan;
 510         bool scan_not_start;
 511         int main_total_rssi;
 512         int alt_total_rssi;
 513         int alt_recv_cnt;
 514         int main_recv_cnt;
 515         int rssi_lna1;
 516         int rssi_lna2;
 517         int rssi_add;
 518         int rssi_sub;
 519         int rssi_first;
 520         int rssi_second;
 521         int rssi_third;
 522         bool alt_good;
 523         int quick_scan_cnt;
 524         int main_conf;
 525         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 526         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 527         int first_bias;
 528         int second_bias;
 529         bool first_ratio;
 530         bool second_ratio;
 531         unsigned long scan_start_time;
 532 };
 533
 534 /********************/
 535 /* Main driver core */
 536 /********************/
 537
 538 /*
 539  * Default cache line size, in bytes.
 540  * Used when PCI device not fully initialized by bootrom/BIOS
 541 */
 542 #define DEFAULT_CACHELINE       32
 543 #define ATH_REGCLASSIDS_MAX     10
 544 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 545 #define ATH_MAX_SW_RETRIES      10
 546 #define ATH_CHAN_MAX            255
 547 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 548
 549 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 550 #define ATH_RATE_DUMMY_MARKER   0
 551
 552 #define SC_OP_INVALID                BIT(0)
 553 #define SC_OP_BEACONS                BIT(1)
 554 #define SC_OP_RXAGGR                 BIT(2)
 555 #define SC_OP_TXAGGR                 BIT(3)
 556 #define SC_OP_OFFCHANNEL             BIT(4)
 557 #define SC_OP_PREAMBLE_SHORT         BIT(5)
 558 #define SC_OP_PROTECT_ENABLE         BIT(6)
 559 #define SC_OP_RXFLUSH                BIT(7)
 560 #define SC_OP_LED_ASSOCIATED         BIT(8)
 561 #define SC_OP_LED_ON                 BIT(9)
 562 #define SC_OP_TSF_RESET              BIT(11)
 563 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 564 #define SC_OP_BT_SCAN                BIT(13)
 565 #define SC_OP_ANI_RUN                BIT(14)
 566
 567 /* Powersave flags */
 568 #define PS_WAIT_FOR_BEACON        BIT(0)
 569 #define PS_WAIT_FOR_CAB           BIT(1)
 570 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 571 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 572 #define PS_BEACON_SYNC            BIT(4)
 573
 574 struct ath_wiphy;
 575 struct ath_rate_table;
 576
 577 struct ath_softc {
 578         struct ieee80211_hw *hw;
 579         struct device *dev;
 580
 581         spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
 582         struct ath_wiphy *pri_wiphy;
 583         struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
 584                                        * have NULL entries */
 585         int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
 586         int chan_idx;
 587         int chan_is_ht;
 588         struct ath_wiphy *next_wiphy;
 589         struct work_struct chan_work;
 590         int wiphy_select_failures;
 591         unsigned long wiphy_select_first_fail;
 592         struct delayed_work wiphy_work;
 593         unsigned long wiphy_scheduler_int;
 594         int wiphy_scheduler_index;
 595         struct survey_info *cur_survey;
 596         struct survey_info survey[ATH9K_NUM_CHANNELS];
 597
 598         struct tasklet_struct intr_tq;
 599         struct tasklet_struct bcon_tasklet;
 600         struct ath_hw *sc_ah;
 601         void __iomem *mem;
 602         int irq;
 603         spinlock_t sc_resetlock;
 604         spinlock_t sc_serial_rw;
 605         spinlock_t sc_pm_lock;
 606         struct mutex mutex;
 607         struct work_struct paprd_work;
 608         struct work_struct hw_check_work;
 609         struct completion paprd_complete;
 610
 611         u32 intrstatus;
 612         u32 sc_flags; /* SC_OP_* */
 613         u16 ps_flags; /* PS_* */
 614         u16 curtxpow;
 615         u8 nbcnvifs;
 616         u16 nvifs;
 617         bool ps_enabled;
 618         bool ps_idle;
 619         unsigned long ps_usecount;
 620
 621         struct ath_config config;
 622         struct ath_rx rx;
 623         struct ath_tx tx;
 624         struct ath_beacon beacon;
 625         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 626
 627         struct ath_led radio_led;
 628         struct ath_led assoc_led;
 629         struct ath_led tx_led;
 630         struct ath_led rx_led;
 631         struct delayed_work ath_led_blink_work;
 632         int led_on_duration;
 633         int led_off_duration;
 634         int led_on_cnt;
 635         int led_off_cnt;
 636
 637         int beacon_interval;
 638
 639 #ifdef CONFIG_ATH9K_DEBUGFS
 640         struct ath9k_debug debug;
 641 #endif
 642         struct ath_beacon_config cur_beacon_conf;
 643         struct delayed_work tx_complete_work;
 644         struct ath_btcoex btcoex;
 645
 646         struct ath_descdma txsdma;
 647
 648         struct ath_ant_comb ant_comb;
 649 };
 650
 651 struct ath_wiphy {
 652         struct ath_softc *sc; /* shared for all virtual wiphys */
 653         struct ieee80211_hw *hw;
 654         struct ath9k_hw_cal_data caldata;
 655         enum ath_wiphy_state {
 656                 ATH_WIPHY_INACTIVE,
 657                 ATH_WIPHY_ACTIVE,
 658                 ATH_WIPHY_PAUSING,
 659                 ATH_WIPHY_PAUSED,
 660                 ATH_WIPHY_SCAN,
 661         } state;
 662         bool idle;
 663         int chan_idx;
 664         int chan_is_ht;
 665 };
 666
 667 void ath9k_tasklet(unsigned long data);
 668 int ath_reset(struct ath_softc *sc, bool retry_tx);
 669 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 670 int ath_cabq_update(struct ath_softc *);
 671
 672 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 673 {
 674         common->bus_ops->read_cachesize(common, csz);
 675 }
 676
 677 extern struct ieee80211_ops ath9k_ops;
 678 extern struct pm_qos_request_list ath9k_pm_qos_req;
 679 extern int modparam_nohwcrypt;
 680 extern int led_blink;
 681
 682 irqreturn_t ath_isr(int irq, void *dev);
 683 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
 684                     const struct ath_bus_ops *bus_ops);
 685 void ath9k_deinit_device(struct ath_softc *sc);
 686 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 687 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
 688                            struct ath9k_channel *ichan);
 689 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 690 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 691                     struct ath9k_channel *hchan);
 692
 693 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
 694 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
 695 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
 696
 697 #ifdef CONFIG_PCI
 698 int ath_pci_init(void);
 699 void ath_pci_exit(void);
 700 #else
 701 static inline int ath_pci_init(void) { return 0; };
 702 static inline void ath_pci_exit(void) {};
 703 #endif
 704
 705 #ifdef CONFIG_ATHEROS_AR71XX
 706 int ath_ahb_init(void);
 707 void ath_ahb_exit(void);
 708 #else
 709 static inline int ath_ahb_init(void) { return 0; };
 710 static inline void ath_ahb_exit(void) {};
 711 #endif
 712
 713 void ath9k_ps_wakeup(struct ath_softc *sc);
 714 void ath9k_ps_restore(struct ath_softc *sc);
 715
 716 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
 717 int ath9k_wiphy_add(struct ath_softc *sc);
 718 int ath9k_wiphy_del(struct ath_wiphy *aphy);
 719 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
 720 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
 721 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
 722 int ath9k_wiphy_select(struct ath_wiphy *aphy);
 723 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
 724 void ath9k_wiphy_chan_work(struct work_struct *work);
 725 bool ath9k_wiphy_started(struct ath_softc *sc);
 726 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
 727                                   struct ath_wiphy *selected);
 728 bool ath9k_wiphy_scanning(struct ath_softc *sc);
 729 void ath9k_wiphy_work(struct work_struct *work);
 730 bool ath9k_all_wiphys_idle(struct ath_softc *sc);
 731 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
 732
 733 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
 734 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
 735
 736 void ath_start_rfkill_poll(struct ath_softc *sc);
 737 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 738
 739 #endif /* ATH9K_H */