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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath5k / eeprom.c
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 /*************************************\
21 * EEPROM access functions and helpers *
22 \*************************************/
23
24 #include <linux/slab.h>
25
26 #include "ath5k.h"
27 #include "reg.h"
28 #include "debug.h"
29 #include "base.h"
30
31 /*
32 * Read from eeprom
33 */
34 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
35 {
36 u32 status, timeout;
37
38 ATH5K_TRACE(ah->ah_sc);
39 /*
40 * Initialize EEPROM access
41 */
42 if (ah->ah_version == AR5K_AR5210) {
43 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
44 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
45 } else {
46 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
47 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
48 AR5K_EEPROM_CMD_READ);
49 }
50
51 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
52 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
53 if (status & AR5K_EEPROM_STAT_RDDONE) {
54 if (status & AR5K_EEPROM_STAT_RDERR)
55 return -EIO;
56 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
57 0xffff);
58 return 0;
59 }
60 udelay(15);
61 }
62
63 return -ETIMEDOUT;
64 }
65
66 /*
67 * Translate binary channel representation in EEPROM to frequency
68 */
69 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
70 unsigned int mode)
71 {
72 u16 val;
73
74 if (bin == AR5K_EEPROM_CHANNEL_DIS)
75 return bin;
76
77 if (mode == AR5K_EEPROM_MODE_11A) {
78 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
79 val = (5 * bin) + 4800;
80 else
81 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
82 (bin * 10) + 5100;
83 } else {
84 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
85 val = bin + 2300;
86 else
87 val = bin + 2400;
88 }
89
90 return val;
91 }
92
93 /*
94 * Initialize eeprom & capabilities structs
95 */
96 static int
97 ath5k_eeprom_init_header(struct ath5k_hw *ah)
98 {
99 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
100 int ret;
101 u16 val;
102 u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
103
104 /*
105 * Read values from EEPROM and store them in the capability structure
106 */
107 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
108 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
109 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
110 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
111 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
112
113 /* Return if we have an old EEPROM */
114 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
115 return 0;
116
117 /*
118 * Validate the checksum of the EEPROM date. There are some
119 * devices with invalid EEPROMs.
120 */
121 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
122 if (val) {
123 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
124 AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
125 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
126 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
127
128 /*
129 * Fail safe check to prevent stupid loops due
130 * to busted EEPROMs. XXX: This value is likely too
131 * big still, waiting on a better value.
132 */
133 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
134 ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
135 "%d (0x%04x) max expected: %d (0x%04x)\n",
136 eep_max, eep_max,
137 3 * AR5K_EEPROM_INFO_MAX,
138 3 * AR5K_EEPROM_INFO_MAX);
139 return -EIO;
140 }
141 }
142
143 for (cksum = 0, offset = 0; offset < eep_max; offset++) {
144 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
145 cksum ^= val;
146 }
147 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
148 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
149 "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
150 cksum, eep_max,
151 eep_max == AR5K_EEPROM_INFO_MAX ?
152 "default size" : "custom size");
153 return -EIO;
154 }
155
156 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
157 ee_ant_gain);
158
159 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
160 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
161 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
162
163 /* XXX: Don't know which versions include these two */
164 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
165
166 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
167 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
168
169 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
170 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
171 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
172 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
173 }
174 }
175
176 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
177 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
178 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
179 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
180
181 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
182 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
183 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
184 }
185
186 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
187
188 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
189 ee->ee_is_hb63 = true;
190 else
191 ee->ee_is_hb63 = false;
192
193 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
194 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
195 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
196
197 /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
198 * and enable serdes programming if needed.
199 *
200 * XXX: Serdes values seem to be fixed so
201 * no need to read them here, we write them
202 * during ath5k_hw_attach */
203 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
204 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
205 true : false;
206
207 return 0;
208 }
209
210
211 /*
212 * Read antenna infos from eeprom
213 */
214 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
215 unsigned int mode)
216 {
217 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
218 u32 o = *offset;
219 u16 val;
220 int ret, i = 0;
221
222 AR5K_EEPROM_READ(o++, val);
223 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
224 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
225 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
226
227 AR5K_EEPROM_READ(o++, val);
228 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
229 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
230 ee->ee_ant_control[mode][i++] = val & 0x3f;
231
232 AR5K_EEPROM_READ(o++, val);
233 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
234 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
235 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
236
237 AR5K_EEPROM_READ(o++, val);
238 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
239 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
240 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
241 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
242
243 AR5K_EEPROM_READ(o++, val);
244 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
245 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
246 ee->ee_ant_control[mode][i++] = val & 0x3f;
247
248 /* Get antenna switch tables */
249 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
250 (ee->ee_ant_control[mode][0] << 4);
251 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
252 ee->ee_ant_control[mode][1] |
253 (ee->ee_ant_control[mode][2] << 6) |
254 (ee->ee_ant_control[mode][3] << 12) |
255 (ee->ee_ant_control[mode][4] << 18) |
256 (ee->ee_ant_control[mode][5] << 24);
257 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
258 ee->ee_ant_control[mode][6] |
259 (ee->ee_ant_control[mode][7] << 6) |
260 (ee->ee_ant_control[mode][8] << 12) |
261 (ee->ee_ant_control[mode][9] << 18) |
262 (ee->ee_ant_control[mode][10] << 24);
263
264 /* return new offset */
265 *offset = o;
266
267 return 0;
268 }
269
270 /*
271 * Read supported modes and some mode-specific calibration data
272 * from eeprom
273 */
274 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
275 unsigned int mode)
276 {
277 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
278 u32 o = *offset;
279 u16 val;
280 int ret;
281
282 ee->ee_n_piers[mode] = 0;
283 AR5K_EEPROM_READ(o++, val);
284 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
285 switch(mode) {
286 case AR5K_EEPROM_MODE_11A:
287 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
288 ee->ee_db[mode][3] = (val >> 2) & 0x7;
289 ee->ee_ob[mode][2] = (val << 1) & 0x7;
290
291 AR5K_EEPROM_READ(o++, val);
292 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
293 ee->ee_db[mode][2] = (val >> 12) & 0x7;
294 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
295 ee->ee_db[mode][1] = (val >> 6) & 0x7;
296 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
297 ee->ee_db[mode][0] = val & 0x7;
298 break;
299 case AR5K_EEPROM_MODE_11G:
300 case AR5K_EEPROM_MODE_11B:
301 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
302 ee->ee_db[mode][1] = val & 0x7;
303 break;
304 }
305
306 AR5K_EEPROM_READ(o++, val);
307 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
308 ee->ee_thr_62[mode] = val & 0xff;
309
310 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
311 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
312
313 AR5K_EEPROM_READ(o++, val);
314 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
315 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
316
317 AR5K_EEPROM_READ(o++, val);
318 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
319
320 if ((val & 0xff) & 0x80)
321 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
322 else
323 ee->ee_noise_floor_thr[mode] = val & 0xff;
324
325 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
326 ee->ee_noise_floor_thr[mode] =
327 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
328
329 AR5K_EEPROM_READ(o++, val);
330 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
331 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
332 ee->ee_xpd[mode] = val & 0x1;
333
334 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
335 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
336
337 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
338 AR5K_EEPROM_READ(o++, val);
339 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
340
341 if (mode == AR5K_EEPROM_MODE_11A)
342 ee->ee_xr_power[mode] = val & 0x3f;
343 else {
344 ee->ee_ob[mode][0] = val & 0x7;
345 ee->ee_db[mode][0] = (val >> 3) & 0x7;
346 }
347 }
348
349 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
350 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
351 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
352 } else {
353 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
354
355 AR5K_EEPROM_READ(o++, val);
356 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
357
358 if (mode == AR5K_EEPROM_MODE_11G) {
359 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
360 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
361 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
362 }
363 }
364
365 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
366 mode == AR5K_EEPROM_MODE_11A) {
367 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
368 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
369 }
370
371 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
372 goto done;
373
374 /* Note: >= v5 have bg freq piers on another location
375 * so these freq piers are ignored for >= v5 (should be 0xff
376 * anyway) */
377 switch(mode) {
378 case AR5K_EEPROM_MODE_11A:
379 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
380 break;
381
382 AR5K_EEPROM_READ(o++, val);
383 ee->ee_margin_tx_rx[mode] = val & 0x3f;
384 break;
385 case AR5K_EEPROM_MODE_11B:
386 AR5K_EEPROM_READ(o++, val);
387
388 ee->ee_pwr_cal_b[0].freq =
389 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
390 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
391 ee->ee_n_piers[mode]++;
392
393 ee->ee_pwr_cal_b[1].freq =
394 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
395 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
396 ee->ee_n_piers[mode]++;
397
398 AR5K_EEPROM_READ(o++, val);
399 ee->ee_pwr_cal_b[2].freq =
400 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
401 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
402 ee->ee_n_piers[mode]++;
403
404 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
405 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
406 break;
407 case AR5K_EEPROM_MODE_11G:
408 AR5K_EEPROM_READ(o++, val);
409
410 ee->ee_pwr_cal_g[0].freq =
411 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
412 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
413 ee->ee_n_piers[mode]++;
414
415 ee->ee_pwr_cal_g[1].freq =
416 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
417 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
418 ee->ee_n_piers[mode]++;
419
420 AR5K_EEPROM_READ(o++, val);
421 ee->ee_turbo_max_power[mode] = val & 0x7f;
422 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
423
424 AR5K_EEPROM_READ(o++, val);
425 ee->ee_pwr_cal_g[2].freq =
426 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
427 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
428 ee->ee_n_piers[mode]++;
429
430 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
431 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
432
433 AR5K_EEPROM_READ(o++, val);
434 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
435 ee->ee_q_cal[mode] = val & 0x1f;
436
437 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
438 AR5K_EEPROM_READ(o++, val);
439 ee->ee_cck_ofdm_gain_delta = val & 0xff;
440 }
441 break;
442 }
443
444 /*
445 * Read turbo mode information on newer EEPROM versions
446 */
447 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
448 goto done;
449
450 switch (mode){
451 case AR5K_EEPROM_MODE_11A:
452 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
453
454 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
455 AR5K_EEPROM_READ(o++, val);
456 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
457 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
458
459 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
460 AR5K_EEPROM_READ(o++, val);
461 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
462 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
463
464 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
465 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
466 break;
467 case AR5K_EEPROM_MODE_11G:
468 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
469
470 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
471 AR5K_EEPROM_READ(o++, val);
472 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
473 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
474
475 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
476 AR5K_EEPROM_READ(o++, val);
477 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
478 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
479 break;
480 }
481
482 done:
483 /* return new offset */
484 *offset = o;
485
486 return 0;
487 }
488
489 /* Read mode-specific data (except power calibration data) */
490 static int
491 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
492 {
493 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
494 u32 mode_offset[3];
495 unsigned int mode;
496 u32 offset;
497 int ret;
498
499 /*
500 * Get values for all modes
501 */
502 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
503 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
504 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
505
506 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
507 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
508
509 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
510 offset = mode_offset[mode];
511
512 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
513 if (ret)
514 return ret;
515
516 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
517 if (ret)
518 return ret;
519 }
520
521 /* override for older eeprom versions for better performance */
522 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
523 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
524 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
525 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
526 }
527
528 return 0;
529 }
530
531 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
532 * frequency mask) */
533 static inline int
534 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
535 struct ath5k_chan_pcal_info *pc, unsigned int mode)
536 {
537 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
538 int o = *offset;
539 int i = 0;
540 u8 freq1, freq2;
541 int ret;
542 u16 val;
543
544 ee->ee_n_piers[mode] = 0;
545 while(i < max) {
546 AR5K_EEPROM_READ(o++, val);
547
548 freq1 = val & 0xff;
549 if (!freq1)
550 break;
551
552 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
553 freq1, mode);
554 ee->ee_n_piers[mode]++;
555
556 freq2 = (val >> 8) & 0xff;
557 if (!freq2)
558 break;
559
560 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
561 freq2, mode);
562 ee->ee_n_piers[mode]++;
563 }
564
565 /* return new offset */
566 *offset = o;
567
568 return 0;
569 }
570
571 /* Read frequency piers for 802.11a */
572 static int
573 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
574 {
575 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
576 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
577 int i, ret;
578 u16 val;
579 u8 mask;
580
581 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
582 ath5k_eeprom_read_freq_list(ah, &offset,
583 AR5K_EEPROM_N_5GHZ_CHAN, pcal,
584 AR5K_EEPROM_MODE_11A);
585 } else {
586 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
587
588 AR5K_EEPROM_READ(offset++, val);
589 pcal[0].freq = (val >> 9) & mask;
590 pcal[1].freq = (val >> 2) & mask;
591 pcal[2].freq = (val << 5) & mask;
592
593 AR5K_EEPROM_READ(offset++, val);
594 pcal[2].freq |= (val >> 11) & 0x1f;
595 pcal[3].freq = (val >> 4) & mask;
596 pcal[4].freq = (val << 3) & mask;
597
598 AR5K_EEPROM_READ(offset++, val);
599 pcal[4].freq |= (val >> 13) & 0x7;
600 pcal[5].freq = (val >> 6) & mask;
601 pcal[6].freq = (val << 1) & mask;
602
603 AR5K_EEPROM_READ(offset++, val);
604 pcal[6].freq |= (val >> 15) & 0x1;
605 pcal[7].freq = (val >> 8) & mask;
606 pcal[8].freq = (val >> 1) & mask;
607 pcal[9].freq = (val << 6) & mask;
608
609 AR5K_EEPROM_READ(offset++, val);
610 pcal[9].freq |= (val >> 10) & 0x3f;
611
612 /* Fixed number of piers */
613 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
614
615 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
616 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
617 pcal[i].freq, AR5K_EEPROM_MODE_11A);
618 }
619 }
620
621 return 0;
622 }
623
624 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
625 static inline int
626 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
627 {
628 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
629 struct ath5k_chan_pcal_info *pcal;
630
631 switch(mode) {
632 case AR5K_EEPROM_MODE_11B:
633 pcal = ee->ee_pwr_cal_b;
634 break;
635 case AR5K_EEPROM_MODE_11G:
636 pcal = ee->ee_pwr_cal_g;
637 break;
638 default:
639 return -EINVAL;
640 }
641
642 ath5k_eeprom_read_freq_list(ah, &offset,
643 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
644 mode);
645
646 return 0;
647 }
648
649 /*
650 * Read power calibration for RF5111 chips
651 *
652 * For RF5111 we have an XPD -eXternal Power Detector- curve
653 * for each calibrated channel. Each curve has 0,5dB Power steps
654 * on x axis and PCDAC steps (offsets) on y axis and looks like an
655 * exponential function. To recreate the curve we read 11 points
656 * here and interpolate later.
657 */
658
659 /* Used to match PCDAC steps with power values on RF5111 chips
660 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
661 * steps that match with the power values we read from eeprom. On
662 * older eeprom versions (< 3.2) these steps are equaly spaced at
663 * 10% of the pcdac curve -until the curve reaches it's maximum-
664 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
665 * these 11 steps are spaced in a different way. This function returns
666 * the pcdac steps based on eeprom version and curve min/max so that we
667 * can have pcdac/pwr points.
668 */
669 static inline void
670 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
671 {
672 static const u16 intercepts3[] =
673 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
674 static const u16 intercepts3_2[] =
675 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
676 const u16 *ip;
677 int i;
678
679 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
680 ip = intercepts3_2;
681 else
682 ip = intercepts3;
683
684 for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
685 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
686 }
687
688 /* Convert RF5111 specific data to generic raw data
689 * used by interpolation code */
690 static int
691 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
692 struct ath5k_chan_pcal_info *chinfo)
693 {
694 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
695 struct ath5k_chan_pcal_info_rf5111 *pcinfo;
696 struct ath5k_pdgain_info *pd;
697 u8 pier, point, idx;
698 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
699
700 /* Fill raw data for each calibration pier */
701 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
702
703 pcinfo = &chinfo[pier].rf5111_info;
704
705 /* Allocate pd_curves for this cal pier */
706 chinfo[pier].pd_curves =
707 kcalloc(AR5K_EEPROM_N_PD_CURVES,
708 sizeof(struct ath5k_pdgain_info),
709 GFP_KERNEL);
710
711 if (!chinfo[pier].pd_curves)
712 return -ENOMEM;
713
714 /* Only one curve for RF5111
715 * find out which one and place
716 * in in pd_curves.
717 * Note: ee_x_gain is reversed here */
718 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
719
720 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
721 pdgain_idx[0] = idx;
722 break;
723 }
724 }
725
726 ee->ee_pd_gains[mode] = 1;
727
728 pd = &chinfo[pier].pd_curves[idx];
729
730 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
731
732 /* Allocate pd points for this curve */
733 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
734 sizeof(u8), GFP_KERNEL);
735 if (!pd->pd_step)
736 return -ENOMEM;
737
738 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
739 sizeof(s16), GFP_KERNEL);
740 if (!pd->pd_pwr)
741 return -ENOMEM;
742
743 /* Fill raw dataset
744 * (convert power to 0.25dB units
745 * for RF5112 combatibility) */
746 for (point = 0; point < pd->pd_points; point++) {
747
748 /* Absolute values */
749 pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
750
751 /* Already sorted */
752 pd->pd_step[point] = pcinfo->pcdac[point];
753 }
754
755 /* Set min/max pwr */
756 chinfo[pier].min_pwr = pd->pd_pwr[0];
757 chinfo[pier].max_pwr = pd->pd_pwr[10];
758
759 }
760
761 return 0;
762 }
763
764 /* Parse EEPROM data */
765 static int
766 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
767 {
768 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
769 struct ath5k_chan_pcal_info *pcal;
770 int offset, ret;
771 int i;
772 u16 val;
773
774 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
775 switch(mode) {
776 case AR5K_EEPROM_MODE_11A:
777 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
778 return 0;
779
780 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
781 offset + AR5K_EEPROM_GROUP1_OFFSET);
782 if (ret < 0)
783 return ret;
784
785 offset += AR5K_EEPROM_GROUP2_OFFSET;
786 pcal = ee->ee_pwr_cal_a;
787 break;
788 case AR5K_EEPROM_MODE_11B:
789 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
790 !AR5K_EEPROM_HDR_11G(ee->ee_header))
791 return 0;
792
793 pcal = ee->ee_pwr_cal_b;
794 offset += AR5K_EEPROM_GROUP3_OFFSET;
795
796 /* fixed piers */
797 pcal[0].freq = 2412;
798 pcal[1].freq = 2447;
799 pcal[2].freq = 2484;
800 ee->ee_n_piers[mode] = 3;
801 break;
802 case AR5K_EEPROM_MODE_11G:
803 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
804 return 0;
805
806 pcal = ee->ee_pwr_cal_g;
807 offset += AR5K_EEPROM_GROUP4_OFFSET;
808
809 /* fixed piers */
810 pcal[0].freq = 2312;
811 pcal[1].freq = 2412;
812 pcal[2].freq = 2484;
813 ee->ee_n_piers[mode] = 3;
814 break;
815 default:
816 return -EINVAL;
817 }
818
819 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
820 struct ath5k_chan_pcal_info_rf5111 *cdata =
821 &pcal[i].rf5111_info;
822
823 AR5K_EEPROM_READ(offset++, val);
824 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
825 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
826 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
827
828 AR5K_EEPROM_READ(offset++, val);
829 cdata->pwr[0] |= ((val >> 14) & 0x3);
830 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
831 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
832 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
833
834 AR5K_EEPROM_READ(offset++, val);
835 cdata->pwr[3] |= ((val >> 12) & 0xf);
836 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
837 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
838
839 AR5K_EEPROM_READ(offset++, val);
840 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
841 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
842 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
843
844 AR5K_EEPROM_READ(offset++, val);
845 cdata->pwr[8] |= ((val >> 14) & 0x3);
846 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
847 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
848
849 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
850 cdata->pcdac_max, cdata->pcdac);
851 }
852
853 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
854 }
855
856
857 /*
858 * Read power calibration for RF5112 chips
859 *
860 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
861 * for each calibrated channel on 0, -6, -12 and -18dbm but we only
862 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
863 * power steps on x axis and PCDAC steps on y axis and looks like a
864 * linear function. To recreate the curve and pass the power values
865 * on hw, we read 4 points for xpd 0 (lower gain -> max power)
866 * and 3 points for xpd 3 (higher gain -> lower power) here and
867 * interpolate later.
868 *
869 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
870 */
871
872 /* Convert RF5112 specific data to generic raw data
873 * used by interpolation code */
874 static int
875 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
876 struct ath5k_chan_pcal_info *chinfo)
877 {
878 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
879 struct ath5k_chan_pcal_info_rf5112 *pcinfo;
880 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
881 unsigned int pier, pdg, point;
882
883 /* Fill raw data for each calibration pier */
884 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
885
886 pcinfo = &chinfo[pier].rf5112_info;
887
888 /* Allocate pd_curves for this cal pier */
889 chinfo[pier].pd_curves =
890 kcalloc(AR5K_EEPROM_N_PD_CURVES,
891 sizeof(struct ath5k_pdgain_info),
892 GFP_KERNEL);
893
894 if (!chinfo[pier].pd_curves)
895 return -ENOMEM;
896
897 /* Fill pd_curves */
898 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
899
900 u8 idx = pdgain_idx[pdg];
901 struct ath5k_pdgain_info *pd =
902 &chinfo[pier].pd_curves[idx];
903
904 /* Lowest gain curve (max power) */
905 if (pdg == 0) {
906 /* One more point for better accuracy */
907 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
908
909 /* Allocate pd points for this curve */
910 pd->pd_step = kcalloc(pd->pd_points,
911 sizeof(u8), GFP_KERNEL);
912
913 if (!pd->pd_step)
914 return -ENOMEM;
915
916 pd->pd_pwr = kcalloc(pd->pd_points,
917 sizeof(s16), GFP_KERNEL);
918
919 if (!pd->pd_pwr)
920 return -ENOMEM;
921
922
923 /* Fill raw dataset
924 * (all power levels are in 0.25dB units) */
925 pd->pd_step[0] = pcinfo->pcdac_x0[0];
926 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
927
928 for (point = 1; point < pd->pd_points;
929 point++) {
930 /* Absolute values */
931 pd->pd_pwr[point] =
932 pcinfo->pwr_x0[point];
933
934 /* Deltas */
935 pd->pd_step[point] =
936 pd->pd_step[point - 1] +
937 pcinfo->pcdac_x0[point];
938 }
939
940 /* Set min power for this frequency */
941 chinfo[pier].min_pwr = pd->pd_pwr[0];
942
943 /* Highest gain curve (min power) */
944 } else if (pdg == 1) {
945
946 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
947
948 /* Allocate pd points for this curve */
949 pd->pd_step = kcalloc(pd->pd_points,
950 sizeof(u8), GFP_KERNEL);
951
952 if (!pd->pd_step)
953 return -ENOMEM;
954
955 pd->pd_pwr = kcalloc(pd->pd_points,
956 sizeof(s16), GFP_KERNEL);
957
958 if (!pd->pd_pwr)
959 return -ENOMEM;
960
961 /* Fill raw dataset
962 * (all power levels are in 0.25dB units) */
963 for (point = 0; point < pd->pd_points;
964 point++) {
965 /* Absolute values */
966 pd->pd_pwr[point] =
967 pcinfo->pwr_x3[point];
968
969 /* Fixed points */
970 pd->pd_step[point] =
971 pcinfo->pcdac_x3[point];
972 }
973
974 /* Since we have a higher gain curve
975 * override min power */
976 chinfo[pier].min_pwr = pd->pd_pwr[0];
977 }
978 }
979 }
980
981 return 0;
982 }
983
984 /* Parse EEPROM data */
985 static int
986 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
987 {
988 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
989 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
990 struct ath5k_chan_pcal_info *gen_chan_info;
991 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
992 u32 offset;
993 u8 i, c;
994 u16 val;
995 int ret;
996 u8 pd_gains = 0;
997
998 /* Count how many curves we have and
999 * identify them (which one of the 4
1000 * available curves we have on each count).
1001 * Curves are stored from lower (x0) to
1002 * higher (x3) gain */
1003 for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
1004 /* ee_x_gain[mode] is x gain mask */
1005 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1006 pdgain_idx[pd_gains++] = i;
1007 }
1008 ee->ee_pd_gains[mode] = pd_gains;
1009
1010 if (pd_gains == 0 || pd_gains > 2)
1011 return -EINVAL;
1012
1013 switch (mode) {
1014 case AR5K_EEPROM_MODE_11A:
1015 /*
1016 * Read 5GHz EEPROM channels
1017 */
1018 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1019 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1020
1021 offset += AR5K_EEPROM_GROUP2_OFFSET;
1022 gen_chan_info = ee->ee_pwr_cal_a;
1023 break;
1024 case AR5K_EEPROM_MODE_11B:
1025 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1026 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1027 offset += AR5K_EEPROM_GROUP3_OFFSET;
1028
1029 /* NB: frequency piers parsed during mode init */
1030 gen_chan_info = ee->ee_pwr_cal_b;
1031 break;
1032 case AR5K_EEPROM_MODE_11G:
1033 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1034 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1035 offset += AR5K_EEPROM_GROUP4_OFFSET;
1036 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1037 offset += AR5K_EEPROM_GROUP2_OFFSET;
1038
1039 /* NB: frequency piers parsed during mode init */
1040 gen_chan_info = ee->ee_pwr_cal_g;
1041 break;
1042 default:
1043 return -EINVAL;
1044 }
1045
1046 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1047 chan_pcal_info = &gen_chan_info[i].rf5112_info;
1048
1049 /* Power values in quarter dB
1050 * for the lower xpd gain curve
1051 * (0 dBm -> higher output power) */
1052 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1053 AR5K_EEPROM_READ(offset++, val);
1054 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1055 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1056 }
1057
1058 /* PCDAC steps
1059 * corresponding to the above power
1060 * measurements */
1061 AR5K_EEPROM_READ(offset++, val);
1062 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1063 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1064 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
1065
1066 /* Power values in quarter dB
1067 * for the higher xpd gain curve
1068 * (18 dBm -> lower output power) */
1069 AR5K_EEPROM_READ(offset++, val);
1070 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1071 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
1072
1073 AR5K_EEPROM_READ(offset++, val);
1074 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1075
1076 /* PCDAC steps
1077 * corresponding to the above power
1078 * measurements (fixed) */
1079 chan_pcal_info->pcdac_x3[0] = 20;
1080 chan_pcal_info->pcdac_x3[1] = 35;
1081 chan_pcal_info->pcdac_x3[2] = 63;
1082
1083 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1084 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1085
1086 /* Last xpd0 power level is also channel maximum */
1087 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1088 } else {
1089 chan_pcal_info->pcdac_x0[0] = 1;
1090 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1091 }
1092
1093 }
1094
1095 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1096 }
1097
1098
1099 /*
1100 * Read power calibration for RF2413 chips
1101 *
1102 * For RF2413 we have a Power to PDDAC table (Power Detector)
1103 * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1104 * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1105 * axis and looks like an exponential function like the RF5111 curve.
1106 *
1107 * To recreate the curves we read here the points and interpolate
1108 * later. Note that in most cases only 2 (higher and lower) curves are
1109 * used (like RF5112) but vendors have the oportunity to include all
1110 * 4 curves on eeprom. The final curve (higher power) has an extra
1111 * point for better accuracy like RF5112.
1112 */
1113
1114 /* For RF2413 power calibration data doesn't start on a fixed location and
1115 * if a mode is not supported, it's section is missing -not zeroed-.
1116 * So we need to calculate the starting offset for each section by using
1117 * these two functions */
1118
1119 /* Return the size of each section based on the mode and the number of pd
1120 * gains available (maximum 4). */
1121 static inline unsigned int
1122 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1123 {
1124 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1125 unsigned int sz;
1126
1127 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1128 sz *= ee->ee_n_piers[mode];
1129
1130 return sz;
1131 }
1132
1133 /* Return the starting offset for a section based on the modes supported
1134 * and each section's size. */
1135 static unsigned int
1136 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1137 {
1138 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1139
1140 switch(mode) {
1141 case AR5K_EEPROM_MODE_11G:
1142 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1143 offset += ath5k_pdgains_size_2413(ee,
1144 AR5K_EEPROM_MODE_11B) +
1145 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1146 /* fall through */
1147 case AR5K_EEPROM_MODE_11B:
1148 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1149 offset += ath5k_pdgains_size_2413(ee,
1150 AR5K_EEPROM_MODE_11A) +
1151 AR5K_EEPROM_N_5GHZ_CHAN / 2;
1152 /* fall through */
1153 case AR5K_EEPROM_MODE_11A:
1154 break;
1155 default:
1156 break;
1157 }
1158
1159 return offset;
1160 }
1161
1162 /* Convert RF2413 specific data to generic raw data
1163 * used by interpolation code */
1164 static int
1165 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1166 struct ath5k_chan_pcal_info *chinfo)
1167 {
1168 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1169 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1170 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1171 unsigned int pier, pdg, point;
1172
1173 /* Fill raw data for each calibration pier */
1174 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1175
1176 pcinfo = &chinfo[pier].rf2413_info;
1177
1178 /* Allocate pd_curves for this cal pier */
1179 chinfo[pier].pd_curves =
1180 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1181 sizeof(struct ath5k_pdgain_info),
1182 GFP_KERNEL);
1183
1184 if (!chinfo[pier].pd_curves)
1185 return -ENOMEM;
1186
1187 /* Fill pd_curves */
1188 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1189
1190 u8 idx = pdgain_idx[pdg];
1191 struct ath5k_pdgain_info *pd =
1192 &chinfo[pier].pd_curves[idx];
1193
1194 /* One more point for the highest power
1195 * curve (lowest gain) */
1196 if (pdg == ee->ee_pd_gains[mode] - 1)
1197 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1198 else
1199 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1200
1201 /* Allocate pd points for this curve */
1202 pd->pd_step = kcalloc(pd->pd_points,
1203 sizeof(u8), GFP_KERNEL);
1204
1205 if (!pd->pd_step)
1206 return -ENOMEM;
1207
1208 pd->pd_pwr = kcalloc(pd->pd_points,
1209 sizeof(s16), GFP_KERNEL);
1210
1211 if (!pd->pd_pwr)
1212 return -ENOMEM;
1213
1214 /* Fill raw dataset
1215 * convert all pwr levels to
1216 * quarter dB for RF5112 combatibility */
1217 pd->pd_step[0] = pcinfo->pddac_i[pdg];
1218 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1219
1220 for (point = 1; point < pd->pd_points; point++) {
1221
1222 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1223 2 * pcinfo->pwr[pdg][point - 1];
1224
1225 pd->pd_step[point] = pd->pd_step[point - 1] +
1226 pcinfo->pddac[pdg][point - 1];
1227
1228 }
1229
1230 /* Highest gain curve -> min power */
1231 if (pdg == 0)
1232 chinfo[pier].min_pwr = pd->pd_pwr[0];
1233
1234 /* Lowest gain curve -> max power */
1235 if (pdg == ee->ee_pd_gains[mode] - 1)
1236 chinfo[pier].max_pwr =
1237 pd->pd_pwr[pd->pd_points - 1];
1238 }
1239 }
1240
1241 return 0;
1242 }
1243
1244 /* Parse EEPROM data */
1245 static int
1246 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1247 {
1248 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1249 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1250 struct ath5k_chan_pcal_info *chinfo;
1251 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1252 u32 offset;
1253 int idx, i, ret;
1254 u16 val;
1255 u8 pd_gains = 0;
1256
1257 /* Count how many curves we have and
1258 * identify them (which one of the 4
1259 * available curves we have on each count).
1260 * Curves are stored from higher to
1261 * lower gain so we go backwards */
1262 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1263 /* ee_x_gain[mode] is x gain mask */
1264 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1265 pdgain_idx[pd_gains++] = idx;
1266
1267 }
1268 ee->ee_pd_gains[mode] = pd_gains;
1269
1270 if (pd_gains == 0)
1271 return -EINVAL;
1272
1273 offset = ath5k_cal_data_offset_2413(ee, mode);
1274 switch (mode) {
1275 case AR5K_EEPROM_MODE_11A:
1276 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1277 return 0;
1278
1279 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1280 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
1281 chinfo = ee->ee_pwr_cal_a;
1282 break;
1283 case AR5K_EEPROM_MODE_11B:
1284 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1285 return 0;
1286
1287 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1288 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1289 chinfo = ee->ee_pwr_cal_b;
1290 break;
1291 case AR5K_EEPROM_MODE_11G:
1292 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1293 return 0;
1294
1295 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1296 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1297 chinfo = ee->ee_pwr_cal_g;
1298 break;
1299 default:
1300 return -EINVAL;
1301 }
1302
1303 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1304 pcinfo = &chinfo[i].rf2413_info;
1305
1306 /*
1307 * Read pwr_i, pddac_i and the first
1308 * 2 pd points (pwr, pddac)
1309 */
1310 AR5K_EEPROM_READ(offset++, val);
1311 pcinfo->pwr_i[0] = val & 0x1f;
1312 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1313 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
1314
1315 AR5K_EEPROM_READ(offset++, val);
1316 pcinfo->pddac[0][0] = val & 0x3f;
1317 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1318 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1319
1320 AR5K_EEPROM_READ(offset++, val);
1321 pcinfo->pwr[0][2] = val & 0xf;
1322 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1323
1324 pcinfo->pwr[0][3] = 0;
1325 pcinfo->pddac[0][3] = 0;
1326
1327 if (pd_gains > 1) {
1328 /*
1329 * Pd gain 0 is not the last pd gain
1330 * so it only has 2 pd points.
1331 * Continue wih pd gain 1.
1332 */
1333 pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1334
1335 pcinfo->pddac_i[1] = (val >> 15) & 0x1;
1336 AR5K_EEPROM_READ(offset++, val);
1337 pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1338
1339 pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1340 pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1341
1342 AR5K_EEPROM_READ(offset++, val);
1343 pcinfo->pwr[1][1] = val & 0xf;
1344 pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1345 pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1346
1347 pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1348 AR5K_EEPROM_READ(offset++, val);
1349 pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1350
1351 pcinfo->pwr[1][3] = 0;
1352 pcinfo->pddac[1][3] = 0;
1353 } else if (pd_gains == 1) {
1354 /*
1355 * Pd gain 0 is the last one so
1356 * read the extra point.
1357 */
1358 pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1359
1360 pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1361 AR5K_EEPROM_READ(offset++, val);
1362 pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1363 }
1364
1365 /*
1366 * Proceed with the other pd_gains
1367 * as above.
1368 */
1369 if (pd_gains > 2) {
1370 pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1371 pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1372
1373 AR5K_EEPROM_READ(offset++, val);
1374 pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1375 pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1376 pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1377
1378 pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1379 AR5K_EEPROM_READ(offset++, val);
1380 pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1381
1382 pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1383 pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1384
1385 pcinfo->pwr[2][3] = 0;
1386 pcinfo->pddac[2][3] = 0;
1387 } else if (pd_gains == 2) {
1388 pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1389 pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1390 }
1391
1392 if (pd_gains > 3) {
1393 pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1394 AR5K_EEPROM_READ(offset++, val);
1395 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1396
1397 pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1398 pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1399 pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1400
1401 AR5K_EEPROM_READ(offset++, val);
1402 pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1403 pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1404 pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1405
1406 pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1407 AR5K_EEPROM_READ(offset++, val);
1408 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1409
1410 pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1411 pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1412
1413 pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1414 AR5K_EEPROM_READ(offset++, val);
1415 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1416 } else if (pd_gains == 3) {
1417 pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1418 AR5K_EEPROM_READ(offset++, val);
1419 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1420
1421 pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
1422 }
1423 }
1424
1425 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1426 }
1427
1428
1429 /*
1430 * Read per rate target power (this is the maximum tx power
1431 * supported by the card). This info is used when setting
1432 * tx power, no matter the channel.
1433 *
1434 * This also works for v5 EEPROMs.
1435 */
1436 static int
1437 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1438 {
1439 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1440 struct ath5k_rate_pcal_info *rate_pcal_info;
1441 u8 *rate_target_pwr_num;
1442 u32 offset;
1443 u16 val;
1444 int ret, i;
1445
1446 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1447 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1448 switch (mode) {
1449 case AR5K_EEPROM_MODE_11A:
1450 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1451 rate_pcal_info = ee->ee_rate_tpwr_a;
1452 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1453 break;
1454 case AR5K_EEPROM_MODE_11B:
1455 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1456 rate_pcal_info = ee->ee_rate_tpwr_b;
1457 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1458 break;
1459 case AR5K_EEPROM_MODE_11G:
1460 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1461 rate_pcal_info = ee->ee_rate_tpwr_g;
1462 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1463 break;
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 /* Different freq mask for older eeproms (<= v3.2) */
1469 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1470 for (i = 0; i < (*rate_target_pwr_num); i++) {
1471 AR5K_EEPROM_READ(offset++, val);
1472 rate_pcal_info[i].freq =
1473 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1474
1475 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1476 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1477
1478 AR5K_EEPROM_READ(offset++, val);
1479
1480 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1481 val == 0) {
1482 (*rate_target_pwr_num) = i;
1483 break;
1484 }
1485
1486 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1487 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1488 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1489 }
1490 } else {
1491 for (i = 0; i < (*rate_target_pwr_num); i++) {
1492 AR5K_EEPROM_READ(offset++, val);
1493 rate_pcal_info[i].freq =
1494 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1495
1496 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1497 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1498
1499 AR5K_EEPROM_READ(offset++, val);
1500
1501 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1502 val == 0) {
1503 (*rate_target_pwr_num) = i;
1504 break;
1505 }
1506
1507 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1508 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1509 rate_pcal_info[i].target_power_54 = (val & 0x3f);
1510 }
1511 }
1512
1513 return 0;
1514 }
1515
1516 /*
1517 * Read per channel calibration info from EEPROM
1518 *
1519 * This info is used to calibrate the baseband power table. Imagine
1520 * that for each channel there is a power curve that's hw specific
1521 * (depends on amplifier etc) and we try to "correct" this curve using
1522 * offsets we pass on to phy chip (baseband -> before amplifier) so that
1523 * it can use accurate power values when setting tx power (takes amplifier's
1524 * performance on each channel into account).
1525 *
1526 * EEPROM provides us with the offsets for some pre-calibrated channels
1527 * and we have to interpolate to create the full table for these channels and
1528 * also the table for any channel.
1529 */
1530 static int
1531 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1532 {
1533 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1534 int (*read_pcal)(struct ath5k_hw *hw, int mode);
1535 int mode;
1536 int err;
1537
1538 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1539 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1540 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1541 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1542 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1543 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1544 else
1545 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1546
1547
1548 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1549 mode++) {
1550 err = read_pcal(ah, mode);
1551 if (err)
1552 return err;
1553
1554 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1555 if (err < 0)
1556 return err;
1557 }
1558
1559 return 0;
1560 }
1561
1562 static int
1563 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
1564 {
1565 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1566 struct ath5k_chan_pcal_info *chinfo;
1567 u8 pier, pdg;
1568
1569 switch (mode) {
1570 case AR5K_EEPROM_MODE_11A:
1571 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1572 return 0;
1573 chinfo = ee->ee_pwr_cal_a;
1574 break;
1575 case AR5K_EEPROM_MODE_11B:
1576 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1577 return 0;
1578 chinfo = ee->ee_pwr_cal_b;
1579 break;
1580 case AR5K_EEPROM_MODE_11G:
1581 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1582 return 0;
1583 chinfo = ee->ee_pwr_cal_g;
1584 break;
1585 default:
1586 return -EINVAL;
1587 }
1588
1589 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1590 if (!chinfo[pier].pd_curves)
1591 continue;
1592
1593 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1594 struct ath5k_pdgain_info *pd =
1595 &chinfo[pier].pd_curves[pdg];
1596
1597 if (pd != NULL) {
1598 kfree(pd->pd_step);
1599 kfree(pd->pd_pwr);
1600 }
1601 }
1602
1603 kfree(chinfo[pier].pd_curves);
1604 }
1605
1606 return 0;
1607 }
1608
1609 void
1610 ath5k_eeprom_detach(struct ath5k_hw *ah)
1611 {
1612 u8 mode;
1613
1614 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1615 ath5k_eeprom_free_pcal_info(ah, mode);
1616 }
1617
1618 /* Read conformance test limits used for regulatory control */
1619 static int
1620 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1621 {
1622 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1623 struct ath5k_edge_power *rep;
1624 unsigned int fmask, pmask;
1625 unsigned int ctl_mode;
1626 int ret, i, j;
1627 u32 offset;
1628 u16 val;
1629
1630 pmask = AR5K_EEPROM_POWER_M;
1631 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1632 offset = AR5K_EEPROM_CTL(ee->ee_version);
1633 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1634 for (i = 0; i < ee->ee_ctls; i += 2) {
1635 AR5K_EEPROM_READ(offset++, val);
1636 ee->ee_ctl[i] = (val >> 8) & 0xff;
1637 ee->ee_ctl[i + 1] = val & 0xff;
1638 }
1639
1640 offset = AR5K_EEPROM_GROUP8_OFFSET;
1641 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1642 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1643 AR5K_EEPROM_GROUP5_OFFSET;
1644 else
1645 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1646
1647 rep = ee->ee_ctl_pwr;
1648 for(i = 0; i < ee->ee_ctls; i++) {
1649 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1650 case AR5K_CTL_11A:
1651 case AR5K_CTL_TURBO:
1652 ctl_mode = AR5K_EEPROM_MODE_11A;
1653 break;
1654 default:
1655 ctl_mode = AR5K_EEPROM_MODE_11G;
1656 break;
1657 }
1658 if (ee->ee_ctl[i] == 0) {
1659 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1660 offset += 8;
1661 else
1662 offset += 7;
1663 rep += AR5K_EEPROM_N_EDGES;
1664 continue;
1665 }
1666 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1667 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1668 AR5K_EEPROM_READ(offset++, val);
1669 rep[j].freq = (val >> 8) & fmask;
1670 rep[j + 1].freq = val & fmask;
1671 }
1672 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1673 AR5K_EEPROM_READ(offset++, val);
1674 rep[j].edge = (val >> 8) & pmask;
1675 rep[j].flag = (val >> 14) & 1;
1676 rep[j + 1].edge = val & pmask;
1677 rep[j + 1].flag = (val >> 6) & 1;
1678 }
1679 } else {
1680 AR5K_EEPROM_READ(offset++, val);
1681 rep[0].freq = (val >> 9) & fmask;
1682 rep[1].freq = (val >> 2) & fmask;
1683 rep[2].freq = (val << 5) & fmask;
1684
1685 AR5K_EEPROM_READ(offset++, val);
1686 rep[2].freq |= (val >> 11) & 0x1f;
1687 rep[3].freq = (val >> 4) & fmask;
1688 rep[4].freq = (val << 3) & fmask;
1689
1690 AR5K_EEPROM_READ(offset++, val);
1691 rep[4].freq |= (val >> 13) & 0x7;
1692 rep[5].freq = (val >> 6) & fmask;
1693 rep[6].freq = (val << 1) & fmask;
1694
1695 AR5K_EEPROM_READ(offset++, val);
1696 rep[6].freq |= (val >> 15) & 0x1;
1697 rep[7].freq = (val >> 8) & fmask;
1698
1699 rep[0].edge = (val >> 2) & pmask;
1700 rep[1].edge = (val << 4) & pmask;
1701
1702 AR5K_EEPROM_READ(offset++, val);
1703 rep[1].edge |= (val >> 12) & 0xf;
1704 rep[2].edge = (val >> 6) & pmask;
1705 rep[3].edge = val & pmask;
1706
1707 AR5K_EEPROM_READ(offset++, val);
1708 rep[4].edge = (val >> 10) & pmask;
1709 rep[5].edge = (val >> 4) & pmask;
1710 rep[6].edge = (val << 2) & pmask;
1711
1712 AR5K_EEPROM_READ(offset++, val);
1713 rep[6].edge |= (val >> 14) & 0x3;
1714 rep[7].edge = (val >> 8) & pmask;
1715 }
1716 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1717 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1718 rep[j].freq, ctl_mode);
1719 }
1720 rep += AR5K_EEPROM_N_EDGES;
1721 }
1722
1723 return 0;
1724 }
1725
1726 static int
1727 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1728 {
1729 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1730 u32 offset;
1731 u16 val;
1732 int ret = 0, i;
1733
1734 offset = AR5K_EEPROM_CTL(ee->ee_version) +
1735 AR5K_EEPROM_N_CTLS(ee->ee_version);
1736
1737 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1738 /* No spur info for 5GHz */
1739 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1740 /* 2 channels for 2GHz (2464/2420) */
1741 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1742 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1743 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1744 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1745 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1746 AR5K_EEPROM_READ(offset, val);
1747 ee->ee_spur_chans[i][0] = val;
1748 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1749 val);
1750 ee->ee_spur_chans[i][1] = val;
1751 offset++;
1752 }
1753 }
1754
1755 return ret;
1756 }
1757
1758 /*
1759 * Initialize eeprom data structure
1760 */
1761 int
1762 ath5k_eeprom_init(struct ath5k_hw *ah)
1763 {
1764 int err;
1765
1766 err = ath5k_eeprom_init_header(ah);
1767 if (err < 0)
1768 return err;
1769
1770 err = ath5k_eeprom_init_modes(ah);
1771 if (err < 0)
1772 return err;
1773
1774 err = ath5k_eeprom_read_pcal_info(ah);
1775 if (err < 0)
1776 return err;
1777
1778 err = ath5k_eeprom_read_ctl_info(ah);
1779 if (err < 0)
1780 return err;
1781
1782 err = ath5k_eeprom_read_spur_chans(ah);
1783 if (err < 0)
1784 return err;
1785
1786 return 0;
1787 }
1788
1789 /*
1790 * Read the MAC address from eeprom
1791 */
1792 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1793 {
1794 u8 mac_d[ETH_ALEN] = {};
1795 u32 total, offset;
1796 u16 data;
1797 int octet, ret;
1798
1799 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1800 if (ret)
1801 return ret;
1802
1803 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1804 ret = ath5k_hw_eeprom_read(ah, offset, &data);
1805 if (ret)
1806 return ret;
1807
1808 total += data;
1809 mac_d[octet + 1] = data & 0xff;
1810 mac_d[octet] = data >> 8;
1811 octet += 2;
1812 }
1813
1814 if (!total || total == 3 * 0xffff)
1815 return -EINVAL;
1816
1817 memcpy(mac, mac_d, ETH_ALEN);
1818
1819 return 0;
1820 }
kernel source for telekom puls (alcatel/mediatek)