drivers/net/wan/wanxlfw.S

   1 .psize 0
   2 /*
   3   wanXL serial card driver for Linux
   4   card firmware part
   5
   6   Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
   7
   8   This program is free software; you can redistribute it and/or modify it
   9   under the terms of version 2 of the GNU General Public License
  10   as published by the Free Software Foundation.
  11
  12
  13
  14
  15         DPRAM BDs:
  16         0x000 - 0x050 TX#0      0x050 - 0x140 RX#0
  17         0x140 - 0x190 TX#1      0x190 - 0x280 RX#1
  18         0x280 - 0x2D0 TX#2      0x2D0 - 0x3C0 RX#2
  19         0x3C0 - 0x410 TX#3      0x410 - 0x500 RX#3
  20
  21
  22         000 5FF 1536 Bytes Dual-Port RAM User Data / BDs
  23         600 6FF 256 Bytes Dual-Port RAM User Data / BDs
  24         700 7FF 256 Bytes Dual-Port RAM User Data / BDs
  25         C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 1
  26         D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 2
  27         E00 EBF 192 Bytes Dual-Port RAM Parameter RAM Page 3
  28         F00 FBF 192 Bytes Dual-Port RAM Parameter RAM Page 4
  29
  30         local interrupts                    level
  31         NMI                                     7
  32         PIT timer, CPM (RX/TX complete)         4
  33         PCI9060 DMA and PCI doorbells           3
  34         Cable - not used                        1
  35 */
  36
  37 #include <linux/hdlc.h>
  38 #include "wanxl.h"
  39
  40 /* memory addresses and offsets */
  41
  42 MAX_RAM_SIZE    = 16 * 1024 * 1024      // max RAM supported by hardware
  43
  44 PCI9060_VECTOR  = 0x0000006C
  45 CPM_IRQ_BASE    = 0x40
  46 ERROR_VECTOR    = CPM_IRQ_BASE * 4
  47 SCC1_VECTOR     = (CPM_IRQ_BASE + 0x1E) * 4
  48 SCC2_VECTOR     = (CPM_IRQ_BASE + 0x1D) * 4
  49 SCC3_VECTOR     = (CPM_IRQ_BASE + 0x1C) * 4
  50 SCC4_VECTOR     = (CPM_IRQ_BASE + 0x1B) * 4
  51 CPM_IRQ_LEVEL   = 4
  52 TIMER_IRQ       = 128
  53 TIMER_IRQ_LEVEL = 4
  54 PITR_CONST      = 0x100 + 16            // 1 Hz timer
  55
  56 MBAR            = 0x0003FF00
  57
  58 VALUE_WINDOW    = 0x40000000
  59 ORDER_WINDOW    = 0xC0000000
  60
  61 PLX             = 0xFFF90000
  62
  63 CSRA            = 0xFFFB0000
  64 CSRB            = 0xFFFB0002
  65 CSRC            = 0xFFFB0004
  66 CSRD            = 0xFFFB0006
  67 STATUS_CABLE_LL         = 0x2000
  68 STATUS_CABLE_DTR        = 0x1000
  69
  70 DPRBASE         = 0xFFFC0000
  71
  72 SCC1_BASE       = DPRBASE + 0xC00
  73 MISC_BASE       = DPRBASE + 0xCB0
  74 SCC2_BASE       = DPRBASE + 0xD00
  75 SCC3_BASE       = DPRBASE + 0xE00
  76 SCC4_BASE       = DPRBASE + 0xF00
  77
  78 // offset from SCCx_BASE
  79 // SCC_xBASE contain offsets from DPRBASE and must be divisible by 8
  80 SCC_RBASE       = 0             // 16-bit RxBD base address
  81 SCC_TBASE       = 2             // 16-bit TxBD base address
  82 SCC_RFCR        = 4             // 8-bit Rx function code
  83 SCC_TFCR        = 5             // 8-bit Tx function code
  84 SCC_MRBLR       = 6             // 16-bit maximum Rx buffer length
  85 SCC_C_MASK      = 0x34          // 32-bit CRC constant
  86 SCC_C_PRES      = 0x38          // 32-bit CRC preset
  87 SCC_MFLR        = 0x46          // 16-bit max Rx frame length (without flags)
  88
  89 REGBASE         = DPRBASE + 0x1000
  90 PICR            = REGBASE + 0x026       // 16-bit periodic irq control
  91 PITR            = REGBASE + 0x02A       // 16-bit periodic irq timing
  92 OR1             = REGBASE + 0x064       // 32-bit RAM bank #1 options
  93 CICR            = REGBASE + 0x540       // 32(24)-bit CP interrupt config
  94 CIMR            = REGBASE + 0x548       // 32-bit CP interrupt mask
  95 CISR            = REGBASE + 0x54C       // 32-bit CP interrupts in-service
  96 PADIR           = REGBASE + 0x550       // 16-bit PortA data direction bitmap
  97 PAPAR           = REGBASE + 0x552       // 16-bit PortA pin assignment bitmap
  98 PAODR           = REGBASE + 0x554       // 16-bit PortA open drain bitmap
  99 PADAT           = REGBASE + 0x556       // 16-bit PortA data register
 100
 101 PCDIR           = REGBASE + 0x560       // 16-bit PortC data direction bitmap
 102 PCPAR           = REGBASE + 0x562       // 16-bit PortC pin assignment bitmap
 103 PCSO            = REGBASE + 0x564       // 16-bit PortC special options
 104 PCDAT           = REGBASE + 0x566       // 16-bit PortC data register
 105 PCINT           = REGBASE + 0x568       // 16-bit PortC interrupt control
 106 CR              = REGBASE + 0x5C0       // 16-bit Command register
 107
 108 SCC1_REGS       = REGBASE + 0x600
 109 SCC2_REGS       = REGBASE + 0x620
 110 SCC3_REGS       = REGBASE + 0x640
 111 SCC4_REGS       = REGBASE + 0x660
 112 SICR            = REGBASE + 0x6EC       // 32-bit SI clock route
 113
 114 // offset from SCCx_REGS
 115 SCC_GSMR_L      = 0x00  // 32 bits
 116 SCC_GSMR_H      = 0x04  // 32 bits
 117 SCC_PSMR        = 0x08  // 16 bits
 118 SCC_TODR        = 0x0C  // 16 bits
 119 SCC_DSR         = 0x0E  // 16 bits
 120 SCC_SCCE        = 0x10  // 16 bits
 121 SCC_SCCM        = 0x14  // 16 bits
 122 SCC_SCCS        = 0x17  // 8 bits
 123
 124 #if QUICC_MEMCPY_USES_PLX
 125         .macro memcpy_from_pci src, dest, len // len must be < 8 MB
 126         addl #3, \len
 127         andl #0xFFFFFFFC, \len          // always copy n * 4 bytes
 128         movel \src, PLX_DMA_0_PCI
 129         movel \dest, PLX_DMA_0_LOCAL
 130         movel \len, PLX_DMA_0_LENGTH
 131         movel #0x0103, PLX_DMA_CMD_STS  // start channel 0 transfer
 132         bsr memcpy_from_pci_run
 133         .endm
 134
 135         .macro memcpy_to_pci src, dest, len
 136         addl #3, \len
 137         andl #0xFFFFFFFC, \len          // always copy n * 4 bytes
 138         movel \src, PLX_DMA_1_LOCAL
 139         movel \dest, PLX_DMA_1_PCI
 140         movel \len, PLX_DMA_1_LENGTH
 141         movel #0x0301, PLX_DMA_CMD_STS  // start channel 1 transfer
 142         bsr memcpy_to_pci_run
 143         .endm
 144
 145 #else
 146
 147         .macro memcpy src, dest, len    // len must be < 65536 bytes
 148         movel %d7, -(%sp)               // src and dest must be < 256 MB
 149         movel \len, %d7                 // bits 0 and 1
 150         lsrl #2, \len
 151         andl \len, \len
 152         beq 99f                         // only 0 - 3 bytes
 153         subl #1, \len                   // for dbf
 154 98:     movel (\src)+, (\dest)+
 155         dbfw \len, 98b
 156 99:     movel %d7, \len
 157         btstl #1, \len
 158         beq 99f
 159         movew (\src)+, (\dest)+
 160 99:     btstl #0, \len
 161         beq 99f
 162         moveb (\src)+, (\dest)+
 163 99:
 164         movel (%sp)+, %d7
 165         .endm
 166
 167         .macro memcpy_from_pci src, dest, len
 168         addl #VALUE_WINDOW, \src
 169         memcpy \src, \dest, \len
 170         .endm
 171
 172         .macro memcpy_to_pci src, dest, len
 173         addl #VALUE_WINDOW, \dest
 174         memcpy \src, \dest, \len
 175         .endm
 176 #endif
 177
 178
 179         .macro wait_for_command
 180 99:     btstl #0, CR
 181         bne 99b
 182         .endm
 183
 184
 185
 186
 187 /****************************** card initialization *******************/
 188         .text
 189         .global _start
 190 _start: bra init
 191
 192         .org _start + 4
 193 ch_status_addr: .long 0, 0, 0, 0
 194 rx_descs_addr:  .long 0
 195
 196 init:
 197 #if DETECT_RAM
 198         movel OR1, %d0
 199         andl #0xF00007FF, %d0           // mask AMxx bits
 200         orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
 201         movel %d0, OR1
 202 #endif
 203
 204         addl #VALUE_WINDOW, rx_descs_addr // PCI addresses of shared data
 205         clrl %d0                        // D0 = 4 * port
 206 init_1: tstl ch_status_addr(%d0)
 207         beq init_2
 208         addl #VALUE_WINDOW, ch_status_addr(%d0)
 209 init_2: addl #4, %d0
 210         cmpl #4 * 4, %d0
 211         bne init_1
 212
 213         movel #pci9060_interrupt, PCI9060_VECTOR
 214         movel #error_interrupt, ERROR_VECTOR
 215         movel #port_interrupt_1, SCC1_VECTOR
 216         movel #port_interrupt_2, SCC2_VECTOR
 217         movel #port_interrupt_3, SCC3_VECTOR
 218         movel #port_interrupt_4, SCC4_VECTOR
 219         movel #timer_interrupt, TIMER_IRQ * 4
 220
 221         movel #0x78000000, CIMR         // only SCCx IRQs from CPM
 222         movew #(TIMER_IRQ_LEVEL << 8) + TIMER_IRQ, PICR // interrupt from PIT
 223         movew #PITR_CONST, PITR
 224
 225         // SCC1=SCCa SCC2=SCCb SCC3=SCCc SCC4=SCCd prio=4 HP=-1 IRQ=64-79
 226         movel #0xD41F40 + (CPM_IRQ_LEVEL << 13), CICR
 227         movel #0x543, PLX_DMA_0_MODE    // 32-bit, Ready, Burst, IRQ
 228         movel #0x543, PLX_DMA_1_MODE
 229         movel #0x0, PLX_DMA_0_DESC      // from PCI to local
 230         movel #0x8, PLX_DMA_1_DESC      // from local to PCI
 231         movel #0x101, PLX_DMA_CMD_STS   // enable both DMA channels
 232         // enable local IRQ, DMA, doorbells and PCI IRQ
 233         orl #0x000F0300, PLX_INTERRUPT_CS
 234
 235 #if DETECT_RAM
 236         bsr ram_test
 237 #else
 238         movel #1, PLX_MAILBOX_5         // non-zero value = init complete
 239 #endif
 240         bsr check_csr
 241
 242         movew #0xFFFF, PAPAR            // all pins are clocks/data
 243         clrw PADIR                      // first function
 244         clrw PCSO                       // CD and CTS always active
 245
 246
 247 /****************************** main loop *****************************/
 248
 249 main:   movel channel_stats, %d7        // D7 = doorbell + irq status
 250         clrl channel_stats
 251
 252         tstl %d7
 253         bne main_1
 254         // nothing to do - wait for next event
 255         stop #0x2200                    // supervisor + IRQ level 2
 256         movew #0x2700, %sr              // disable IRQs again
 257         bra main
 258
 259 main_1: clrl %d0                        // D0 = 4 * port
 260         clrl %d6                        // D6 = doorbell to host value
 261
 262 main_l: btstl #DOORBELL_TO_CARD_CLOSE_0, %d7
 263         beq main_op
 264         bclrl #DOORBELL_TO_CARD_OPEN_0, %d7 // in case both bits are set
 265         bsr close_port
 266 main_op:
 267         btstl #DOORBELL_TO_CARD_OPEN_0, %d7
 268         beq main_cl
 269         bsr open_port
 270 main_cl:
 271         btstl #DOORBELL_TO_CARD_TX_0, %d7
 272         beq main_txend
 273         bsr tx
 274 main_txend:
 275         btstl #TASK_SCC_0, %d7
 276         beq main_next
 277         bsr tx_end
 278         bsr rx
 279
 280 main_next:
 281         lsrl #1, %d7                    // port status for next port
 282         addl #4, %d0                    // D0 = 4 * next port
 283         cmpl #4 * 4, %d0
 284         bne main_l
 285         movel %d6, PLX_DOORBELL_FROM_CARD // signal the host
 286         bra main
 287
 288
 289 /****************************** open port *****************************/
 290
 291 open_port:                              // D0 = 4 * port, D6 = doorbell to host
 292         movel ch_status_addr(%d0), %a0  // A0 = port status address
 293         tstl STATUS_OPEN(%a0)
 294         bne open_port_ret               // port already open
 295         movel #1, STATUS_OPEN(%a0)      // confirm the port is open
 296 // setup BDs
 297         clrl tx_in(%d0)
 298         clrl tx_out(%d0)
 299         clrl tx_count(%d0)
 300         clrl rx_in(%d0)
 301
 302         movel SICR, %d1                 // D1 = clock settings in SICR
 303         andl clocking_mask(%d0), %d1
 304         cmpl #CLOCK_TXFROMRX, STATUS_CLOCKING(%a0)
 305         bne open_port_clock_ext
 306         orl clocking_txfromrx(%d0), %d1
 307         bra open_port_set_clock
 308
 309 open_port_clock_ext:
 310         orl clocking_ext(%d0), %d1
 311 open_port_set_clock:
 312         movel %d1, SICR                 // update clock settings in SICR
 313
 314         orw #STATUS_CABLE_DTR, csr_output(%d0)  // DTR on
 315         bsr check_csr                   // call with disabled timer interrupt
 316
 317 // Setup TX descriptors
 318         movel first_buffer(%d0), %d1    // D1 = starting buffer address
 319         movel tx_first_bd(%d0), %a1     // A1 = starting TX BD address
 320         movel #TX_BUFFERS - 2, %d2      // D2 = TX_BUFFERS - 1 counter
 321         movel #0x18000000, %d3          // D3 = initial TX BD flags: Int + Last
 322         cmpl #PARITY_NONE, STATUS_PARITY(%a0)
 323         beq open_port_tx_loop
 324         bsetl #26, %d3                  // TX BD flag: Transmit CRC
 325 open_port_tx_loop:
 326         movel %d3, (%a1)+               // TX flags + length
 327         movel %d1, (%a1)+               // buffer address
 328         addl #BUFFER_LENGTH, %d1
 329         dbfw %d2, open_port_tx_loop
 330
 331         bsetl #29, %d3                  // TX BD flag: Wrap (last BD)
 332         movel %d3, (%a1)+               // Final TX flags + length
 333         movel %d1, (%a1)+               // buffer address
 334
 335 // Setup RX descriptors                 // A1 = starting RX BD address
 336         movel #RX_BUFFERS - 2, %d2      // D2 = RX_BUFFERS - 1 counter
 337 open_port_rx_loop:
 338         movel #0x90000000, (%a1)+       // RX flags + length
 339         movel %d1, (%a1)+               // buffer address
 340         addl #BUFFER_LENGTH, %d1
 341         dbfw %d2, open_port_rx_loop
 342
 343         movel #0xB0000000, (%a1)+       // Final RX flags + length
 344         movel %d1, (%a1)+               // buffer address
 345
 346 // Setup port parameters
 347         movel scc_base_addr(%d0), %a1   // A1 = SCC_BASE address
 348         movel scc_reg_addr(%d0), %a2    // A2 = SCC_REGS address
 349
 350         movel #0xFFFF, SCC_SCCE(%a2)    // clear status bits
 351         movel #0x0000, SCC_SCCM(%a2)    // interrupt mask
 352
 353         movel tx_first_bd(%d0), %d1
 354         movew %d1, SCC_TBASE(%a1)       // D1 = offset of first TxBD
 355         addl #TX_BUFFERS * 8, %d1
 356         movew %d1, SCC_RBASE(%a1)       // D1 = offset of first RxBD
 357         moveb #0x8, SCC_RFCR(%a1)       // Intel mode, 1000
 358         moveb #0x8, SCC_TFCR(%a1)
 359
 360 // Parity settings
 361         cmpl #PARITY_CRC16_PR1_CCITT, STATUS_PARITY(%a0)
 362         bne open_port_parity_1
 363         clrw SCC_PSMR(%a2)              // CRC16-CCITT
 364         movel #0xF0B8, SCC_C_MASK(%a1)
 365         movel #0xFFFF, SCC_C_PRES(%a1)
 366         movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
 367         movew #2, parity_bytes(%d0)
 368         bra open_port_2
 369
 370 open_port_parity_1:
 371         cmpl #PARITY_CRC32_PR1_CCITT, STATUS_PARITY(%a0)
 372         bne open_port_parity_2
 373         movew #0x0800, SCC_PSMR(%a2)    // CRC32-CCITT
 374         movel #0xDEBB20E3, SCC_C_MASK(%a1)
 375         movel #0xFFFFFFFF, SCC_C_PRES(%a1)
 376         movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
 377         movew #4, parity_bytes(%d0)
 378         bra open_port_2
 379
 380 open_port_parity_2:
 381         cmpl #PARITY_CRC16_PR0_CCITT, STATUS_PARITY(%a0)
 382         bne open_port_parity_3
 383         clrw SCC_PSMR(%a2)              // CRC16-CCITT preset 0
 384         movel #0xF0B8, SCC_C_MASK(%a1)
 385         clrl SCC_C_PRES(%a1)
 386         movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
 387         movew #2, parity_bytes(%d0)
 388         bra open_port_2
 389
 390 open_port_parity_3:
 391         cmpl #PARITY_CRC32_PR0_CCITT, STATUS_PARITY(%a0)
 392         bne open_port_parity_4
 393         movew #0x0800, SCC_PSMR(%a2)    // CRC32-CCITT preset 0
 394         movel #0xDEBB20E3, SCC_C_MASK(%a1)
 395         clrl SCC_C_PRES(%a1)
 396         movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
 397         movew #4, parity_bytes(%d0)
 398         bra open_port_2
 399
 400 open_port_parity_4:
 401         clrw SCC_PSMR(%a2)              // no parity
 402         movel #0xF0B8, SCC_C_MASK(%a1)
 403         movel #0xFFFF, SCC_C_PRES(%a1)
 404         movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
 405         clrw parity_bytes(%d0)
 406
 407 open_port_2:
 408         movel #0x00000003, SCC_GSMR_H(%a2) // RTSM
 409         cmpl #ENCODING_NRZI, STATUS_ENCODING(%a0)
 410         bne open_port_nrz
 411         movel #0x10040900, SCC_GSMR_L(%a2) // NRZI: TCI Tend RECN+TENC=1
 412         bra open_port_3
 413
 414 open_port_nrz:
 415         movel #0x10040000, SCC_GSMR_L(%a2) // NRZ: TCI Tend RECN+TENC=0
 416 open_port_3:
 417         movew #BUFFER_LENGTH, SCC_MRBLR(%a1)
 418         movel %d0, %d1
 419         lsll #4, %d1                    // D1 bits 7 and 6 = port
 420         orl #1, %d1
 421         movew %d1, CR                   // Init SCC RX and TX params
 422         wait_for_command
 423
 424         // TCI Tend ENR ENT
 425         movew #0x001F, SCC_SCCM(%a2)    // TXE RXF BSY TXB RXB interrupts
 426         orl #0x00000030, SCC_GSMR_L(%a2) // enable SCC
 427 open_port_ret:
 428         rts
 429
 430
 431 /****************************** close port ****************************/
 432
 433 close_port:                             // D0 = 4 * port, D6 = doorbell to host
 434         movel scc_reg_addr(%d0), %a0    // A0 = SCC_REGS address
 435         clrw SCC_SCCM(%a0)              // no SCC interrupts
 436         andl #0xFFFFFFCF, SCC_GSMR_L(%a0) // Disable ENT and ENR
 437
 438         andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off
 439         bsr check_csr                   // call with disabled timer interrupt
 440
 441         movel ch_status_addr(%d0), %d1
 442         clrl STATUS_OPEN(%d1)           // confirm the port is closed
 443         rts
 444
 445
 446 /****************************** transmit packet ***********************/
 447 // queue packets for transmission
 448 tx:                                     // D0 = 4 * port, D6 = doorbell to host
 449         cmpl #TX_BUFFERS, tx_count(%d0)
 450         beq tx_ret                      // all DB's = descs in use
 451
 452         movel tx_out(%d0), %d1
 453         movel %d1, %d2                  // D1 = D2 = tx_out BD# = desc#
 454         mulul #DESC_LENGTH, %d2         // D2 = TX desc offset
 455         addl ch_status_addr(%d0), %d2
 456         addl #STATUS_TX_DESCS, %d2      // D2 = TX desc address
 457         cmpl #PACKET_FULL, (%d2)        // desc status
 458         bne tx_ret
 459
 460 // queue it
 461         movel 4(%d2), %a0               // PCI address
 462         lsll #3, %d1                    // BD is 8-bytes long
 463         addl tx_first_bd(%d0), %d1      // D1 = current tx_out BD addr
 464
 465         movel 4(%d1), %a1               // A1 = dest address
 466         movel 8(%d2), %d2               // D2 = length
 467         movew %d2, 2(%d1)               // length into BD
 468         memcpy_from_pci %a0, %a1, %d2
 469         bsetl #31, (%d1)                // CP go ahead
 470
 471 // update tx_out and tx_count
 472         movel tx_out(%d0), %d1
 473         addl #1, %d1
 474         cmpl #TX_BUFFERS, %d1
 475         bne tx_1
 476         clrl %d1
 477 tx_1:   movel %d1, tx_out(%d0)
 478
 479         addl #1, tx_count(%d0)
 480         bra tx
 481
 482 tx_ret: rts
 483
 484
 485 /****************************** packet received ***********************/
 486
 487 // Service receive buffers              // D0 = 4 * port, D6 = doorbell to host
 488 rx:     movel rx_in(%d0), %d1           // D1 = rx_in BD#
 489         lsll #3, %d1                    // BD is 8-bytes long
 490         addl rx_first_bd(%d0), %d1      // D1 = current rx_in BD address
 491         movew (%d1), %d2                // D2 = RX BD flags
 492         btstl #15, %d2
 493         bne rx_ret                      // BD still empty
 494
 495         btstl #1, %d2
 496         bne rx_overrun
 497
 498         tstw parity_bytes(%d0)
 499         bne rx_parity
 500         bclrl #2, %d2                   // do not test for CRC errors
 501 rx_parity:
 502         andw #0x0CBC, %d2               // mask status bits
 503         cmpw #0x0C00, %d2               // correct frame
 504         bne rx_bad_frame
 505         clrl %d3
 506         movew 2(%d1), %d3
 507         subw parity_bytes(%d0), %d3     // D3 = packet length
 508         cmpw #HDLC_MAX_MRU, %d3
 509         bgt rx_bad_frame
 510
 511 rx_good_frame:
 512         movel rx_out, %d2
 513         mulul #DESC_LENGTH, %d2
 514         addl rx_descs_addr, %d2         // D2 = RX desc address
 515         cmpl #PACKET_EMPTY, (%d2)       // desc stat
 516         bne rx_overrun
 517
 518         movel %d3, 8(%d2)
 519         movel 4(%d1), %a0               // A0 = source address
 520         movel 4(%d2), %a1
 521         tstl %a1
 522         beq rx_ignore_data
 523         memcpy_to_pci %a0, %a1, %d3
 524 rx_ignore_data:
 525         movel packet_full(%d0), (%d2)   // update desc stat
 526
 527 // update D6 and rx_out
 528         bsetl #DOORBELL_FROM_CARD_RX, %d6 // signal host that RX completed
 529         movel rx_out, %d2
 530         addl #1, %d2
 531         cmpl #RX_QUEUE_LENGTH, %d2
 532         bne rx_1
 533         clrl %d2
 534 rx_1:   movel %d2, rx_out
 535
 536 rx_free_bd:
 537         andw #0xF000, (%d1)             // clear CM and error bits
 538         bsetl #31, (%d1)                // free BD
 539 // update rx_in
 540         movel rx_in(%d0), %d1
 541         addl #1, %d1
 542         cmpl #RX_BUFFERS, %d1
 543         bne rx_2
 544         clrl %d1
 545 rx_2:   movel %d1, rx_in(%d0)
 546         bra rx
 547
 548 rx_overrun:
 549         movel ch_status_addr(%d0), %d2
 550         addl #1, STATUS_RX_OVERRUNS(%d2)
 551         bra rx_free_bd
 552
 553 rx_bad_frame:
 554         movel ch_status_addr(%d0), %d2
 555         addl #1, STATUS_RX_FRAME_ERRORS(%d2)
 556         bra rx_free_bd
 557
 558 rx_ret: rts
 559
 560
 561 /****************************** packet transmitted ********************/
 562
 563 // Service transmit buffers             // D0 = 4 * port, D6 = doorbell to host
 564 tx_end: tstl tx_count(%d0)
 565         beq tx_end_ret                  // TX buffers already empty
 566
 567         movel tx_in(%d0), %d1
 568         movel %d1, %d2                  // D1 = D2 = tx_in BD# = desc#
 569         lsll #3, %d1                    // BD is 8-bytes long
 570         addl tx_first_bd(%d0), %d1      // D1 = current tx_in BD address
 571         movew (%d1), %d3                // D3 = TX BD flags
 572         btstl #15, %d3
 573         bne tx_end_ret                  // BD still being transmitted
 574
 575 // update D6, tx_in and tx_count
 576         orl bell_tx(%d0), %d6           // signal host that TX desc freed
 577         subl #1, tx_count(%d0)
 578         movel tx_in(%d0), %d1
 579         addl #1, %d1
 580         cmpl #TX_BUFFERS, %d1
 581         bne tx_end_1
 582         clrl %d1
 583 tx_end_1:
 584         movel %d1, tx_in(%d0)
 585
 586 // free host's descriptor
 587         mulul #DESC_LENGTH, %d2         // D2 = TX desc offset
 588         addl ch_status_addr(%d0), %d2
 589         addl #STATUS_TX_DESCS, %d2      // D2 = TX desc address
 590         btstl #1, %d3
 591         bne tx_end_underrun
 592         movel #PACKET_SENT, (%d2)
 593         bra tx_end
 594
 595 tx_end_underrun:
 596         movel #PACKET_UNDERRUN, (%d2)
 597         bra tx_end
 598
 599 tx_end_ret: rts
 600
 601
 602 /****************************** PLX PCI9060 DMA memcpy ****************/
 603
 604 #if QUICC_MEMCPY_USES_PLX
 605 // called with interrupts disabled
 606 memcpy_from_pci_run:
 607         movel %d0, -(%sp)
 608         movew %sr, -(%sp)
 609 memcpy_1:
 610         movel PLX_DMA_CMD_STS, %d0      // do not btst PLX register directly
 611         btstl #4, %d0                   // transfer done?
 612         bne memcpy_end
 613         stop #0x2200                    // enable PCI9060 interrupts
 614         movew #0x2700, %sr              // disable interrupts again
 615         bra memcpy_1
 616
 617 memcpy_to_pci_run:
 618         movel %d0, -(%sp)
 619         movew %sr, -(%sp)
 620 memcpy_2:
 621         movel PLX_DMA_CMD_STS, %d0      // do not btst PLX register directly
 622         btstl #12, %d0                  // transfer done?
 623         bne memcpy_end
 624         stop #0x2200                    // enable PCI9060 interrupts
 625         movew #0x2700, %sr              // disable interrupts again
 626         bra memcpy_2
 627
 628 memcpy_end:
 629         movew (%sp)+, %sr
 630         movel (%sp)+, %d0
 631         rts
 632 #endif
 633
 634
 635
 636
 637
 638
 639 /****************************** PLX PCI9060 interrupt *****************/
 640
 641 pci9060_interrupt:
 642         movel %d0, -(%sp)
 643
 644         movel PLX_DOORBELL_TO_CARD, %d0
 645         movel %d0, PLX_DOORBELL_TO_CARD // confirm all requests
 646         orl %d0, channel_stats
 647
 648         movel #0x0909, PLX_DMA_CMD_STS  // clear DMA ch #0 and #1 interrupts
 649
 650         movel (%sp)+, %d0
 651         rte
 652
 653 /****************************** SCC interrupts ************************/
 654
 655 port_interrupt_1:
 656         orl #0, SCC1_REGS + SCC_SCCE; // confirm SCC events
 657         orl #1 << TASK_SCC_0, channel_stats
 658         movel #0x40000000, CISR
 659         rte
 660
 661 port_interrupt_2:
 662         orl #0, SCC2_REGS + SCC_SCCE; // confirm SCC events
 663         orl #1 << TASK_SCC_1, channel_stats
 664         movel #0x20000000, CISR
 665         rte
 666
 667 port_interrupt_3:
 668         orl #0, SCC3_REGS + SCC_SCCE; // confirm SCC events
 669         orl #1 << TASK_SCC_2, channel_stats
 670         movel #0x10000000, CISR
 671         rte
 672
 673 port_interrupt_4:
 674         orl #0, SCC4_REGS + SCC_SCCE; // confirm SCC events
 675         orl #1 << TASK_SCC_3, channel_stats
 676         movel #0x08000000, CISR
 677         rte
 678
 679 error_interrupt:
 680         rte
 681
 682
 683 /****************************** cable and PM routine ******************/
 684 // modified registers: none
 685 check_csr:
 686         movel %d0, -(%sp)
 687         movel %d1, -(%sp)
 688         movel %d2, -(%sp)
 689         movel %a0, -(%sp)
 690         movel %a1, -(%sp)
 691
 692         clrl %d0                        // D0 = 4 * port
 693         movel #CSRA, %a0                // A0 = CSR address
 694
 695 check_csr_loop:
 696         movew (%a0), %d1                // D1 = CSR input bits
 697         andl #0xE7, %d1                 // PM and cable sense bits (no DCE bit)
 698         cmpw #STATUS_CABLE_V35 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
 699         bne check_csr_1
 700         movew #0x0E08, %d1
 701         bra check_csr_valid
 702
 703 check_csr_1:
 704         cmpw #STATUS_CABLE_X21 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
 705         bne check_csr_2
 706         movew #0x0408, %d1
 707         bra check_csr_valid
 708
 709 check_csr_2:
 710         cmpw #STATUS_CABLE_V24 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
 711         bne check_csr_3
 712         movew #0x0208, %d1
 713         bra check_csr_valid
 714
 715 check_csr_3:
 716         cmpw #STATUS_CABLE_EIA530 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
 717         bne check_csr_disable
 718         movew #0x0D08, %d1
 719         bra check_csr_valid
 720
 721 check_csr_disable:
 722         movew #0x0008, %d1              // D1 = disable everything
 723         movew #0x80E7, %d2              // D2 = input mask: ignore DSR
 724         bra check_csr_write
 725
 726 check_csr_valid:                        // D1 = mode and IRQ bits
 727         movew csr_output(%d0), %d2
 728         andw #0x3000, %d2               // D2 = requested LL and DTR bits
 729         orw %d2, %d1                    // D1 = all requested output bits
 730         movew #0x80FF, %d2              // D2 = input mask: include DSR
 731
 732 check_csr_write:
 733         cmpw old_csr_output(%d0), %d1
 734         beq check_csr_input
 735         movew %d1, old_csr_output(%d0)
 736         movew %d1, (%a0)                // Write CSR output bits
 737
 738 check_csr_input:
 739         movew (PCDAT), %d1
 740         andw dcd_mask(%d0), %d1
 741         beq check_csr_dcd_on            // DCD and CTS signals are negated
 742         movew (%a0), %d1                // D1 = CSR input bits
 743         andw #~STATUS_CABLE_DCD, %d1    // DCD off
 744         bra check_csr_previous
 745
 746 check_csr_dcd_on:
 747         movew (%a0), %d1                // D1 = CSR input bits
 748         orw #STATUS_CABLE_DCD, %d1      // DCD on
 749 check_csr_previous:
 750         andw %d2, %d1                   // input mask
 751         movel ch_status_addr(%d0), %a1
 752         cmpl STATUS_CABLE(%a1), %d1     // check for change
 753         beq check_csr_next
 754         movel %d1, STATUS_CABLE(%a1)    // update status
 755         movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD   // signal the host
 756
 757 check_csr_next:
 758         addl #2, %a0                    // next CSR register
 759         addl #4, %d0                    // D0 = 4 * next port
 760         cmpl #4 * 4, %d0
 761         bne check_csr_loop
 762
 763         movel (%sp)+, %a1
 764         movel (%sp)+, %a0
 765         movel (%sp)+, %d2
 766         movel (%sp)+, %d1
 767         movel (%sp)+, %d0
 768         rts
 769
 770
 771 /****************************** timer interrupt ***********************/
 772
 773 timer_interrupt:
 774         bsr check_csr
 775         rte
 776
 777
 778 /****************************** RAM sizing and test *******************/
 779 #if DETECT_RAM
 780 ram_test:
 781         movel #0x12345678, %d1          // D1 = test value
 782         movel %d1, (128 * 1024 - 4)
 783         movel #128 * 1024, %d0          // D0 = RAM size tested
 784 ram_test_size:
 785         cmpl #MAX_RAM_SIZE, %d0
 786         beq ram_test_size_found
 787         movel %d0, %a0
 788         addl #128 * 1024 - 4, %a0
 789         cmpl (%a0), %d1
 790         beq ram_test_size_check
 791 ram_test_next_size:
 792         lsll #1, %d0
 793         bra ram_test_size
 794
 795 ram_test_size_check:
 796         eorl #0xFFFFFFFF, %d1
 797         movel %d1, (128 * 1024 - 4)
 798         cmpl (%a0), %d1
 799         bne ram_test_next_size
 800
 801 ram_test_size_found:                    // D0 = RAM size
 802         movel %d0, %a0                  // A0 = fill ptr
 803         subl #firmware_end + 4, %d0
 804         lsrl #2, %d0
 805         movel %d0, %d1                  // D1 = DBf counter
 806 ram_test_fill:
 807         movel %a0, -(%a0)
 808         dbfw %d1, ram_test_fill
 809         subl #0x10000, %d1
 810         cmpl #0xFFFFFFFF, %d1
 811         bne ram_test_fill
 812
 813 ram_test_loop:                          // D0 = DBf counter
 814         cmpl (%a0)+, %a0
 815         dbnew %d0, ram_test_loop
 816         bne ram_test_found_bad
 817         subl #0x10000, %d0
 818         cmpl #0xFFFFFFFF, %d0
 819         bne ram_test_loop
 820         bra ram_test_all_ok
 821
 822 ram_test_found_bad:
 823         subl #4, %a0
 824 ram_test_all_ok:
 825         movel %a0, PLX_MAILBOX_5
 826         rts
 827 #endif
 828
 829
 830 /****************************** constants *****************************/
 831
 832 scc_reg_addr:
 833         .long SCC1_REGS, SCC2_REGS, SCC3_REGS, SCC4_REGS
 834 scc_base_addr:
 835         .long SCC1_BASE, SCC2_BASE, SCC3_BASE, SCC4_BASE
 836
 837 tx_first_bd:
 838         .long DPRBASE
 839         .long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8
 840         .long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8 * 2
 841         .long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8 * 3
 842
 843 rx_first_bd:
 844         .long DPRBASE + TX_BUFFERS * 8
 845         .long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8
 846         .long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8 * 2
 847         .long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8 * 3
 848
 849 first_buffer:
 850         .long BUFFERS_ADDR
 851         .long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH
 852         .long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * 2
 853         .long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * 3
 854
 855 bell_tx:
 856         .long 1 << DOORBELL_FROM_CARD_TX_0, 1 << DOORBELL_FROM_CARD_TX_1
 857         .long 1 << DOORBELL_FROM_CARD_TX_2, 1 << DOORBELL_FROM_CARD_TX_3
 858
 859 bell_cable:
 860         .long 1 << DOORBELL_FROM_CARD_CABLE_0, 1 << DOORBELL_FROM_CARD_CABLE_1
 861         .long 1 << DOORBELL_FROM_CARD_CABLE_2, 1 << DOORBELL_FROM_CARD_CABLE_3
 862
 863 packet_full:
 864         .long PACKET_FULL, PACKET_FULL + 1, PACKET_FULL + 2, PACKET_FULL + 3
 865
 866 clocking_ext:
 867         .long 0x0000002C, 0x00003E00, 0x002C0000, 0x3E000000
 868 clocking_txfromrx:
 869         .long 0x0000002D, 0x00003F00, 0x002D0000, 0x3F000000
 870 clocking_mask:
 871         .long 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000
 872 dcd_mask:
 873         .word 0x020, 0, 0x080, 0, 0x200, 0, 0x800
 874
 875         .ascii "wanXL firmware\n"
 876         .asciz "Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>\n"
 877
 878
 879 /****************************** variables *****************************/
 880
 881                 .align 4
 882 channel_stats:  .long 0
 883
 884 tx_in:          .long 0, 0, 0, 0        // transmitted
 885 tx_out:         .long 0, 0, 0, 0        // received from host for transmission
 886 tx_count:       .long 0, 0, 0, 0        // currently in transmit queue
 887
 888 rx_in:          .long 0, 0, 0, 0        // received from port
 889 rx_out:         .long 0                 // transmitted to host
 890 parity_bytes:   .word 0, 0, 0, 0, 0, 0, 0 // only 4 words are used
 891
 892 csr_output:     .word 0
 893 old_csr_output: .word 0, 0, 0, 0, 0, 0, 0
 894                 .align 4
 895 firmware_end:                           // must be dword-aligned