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usbnet: smsc95xx: fix memory leak in smsc95xx_suspend
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / usb / smsc95xx.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21 #include <linux/module.h>
22 #include <linux/kmod.h>
23 #include <linux/init.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/mii.h>
28 #include <linux/usb.h>
29 #include <linux/bitrev.h>
30 #include <linux/crc16.h>
31 #include <linux/crc32.h>
32 #include <linux/usb/usbnet.h>
33 #include <linux/slab.h>
34 #include "smsc95xx.h"
35
36 #define SMSC_CHIPNAME "smsc95xx"
37 #define SMSC_DRIVER_VERSION "1.0.4"
38 #define HS_USB_PKT_SIZE (512)
39 #define FS_USB_PKT_SIZE (64)
40 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
41 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
42 #define DEFAULT_BULK_IN_DELAY (0x00002000)
43 #define MAX_SINGLE_PACKET_SIZE (2048)
44 #define LAN95XX_EEPROM_MAGIC (0x9500)
45 #define EEPROM_MAC_OFFSET (0x01)
46 #define DEFAULT_TX_CSUM_ENABLE (true)
47 #define DEFAULT_RX_CSUM_ENABLE (true)
48 #define SMSC95XX_INTERNAL_PHY_ID (1)
49 #define SMSC95XX_TX_OVERHEAD (8)
50 #define SMSC95XX_TX_OVERHEAD_CSUM (12)
51 #define SUPPORTED_WAKE (WAKE_UCAST | WAKE_BCAST | \
52 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
53
54 #define check_warn(ret, fmt, args...) \
55 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
56
57 #define check_warn_return(ret, fmt, args...) \
58 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
59
60 #define check_warn_goto_done(ret, fmt, args...) \
61 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
62
63 struct smsc95xx_priv {
64 u32 mac_cr;
65 u32 hash_hi;
66 u32 hash_lo;
67 u32 wolopts;
68 spinlock_t mac_cr_lock;
69 int wuff_filter_count;
70 };
71
72 static bool turbo_mode = true;
73 module_param(turbo_mode, bool, 0644);
74 MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
75
76 static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
77 u32 *data)
78 {
79 u32 buf;
80 int ret;
81
82 BUG_ON(!dev);
83
84 ret = usbnet_read_cmd(dev, USB_VENDOR_REQUEST_READ_REGISTER,
85 USB_DIR_IN | USB_TYPE_VENDOR |
86 USB_RECIP_DEVICE,
87 0, index, &buf, 4);
88 if (unlikely(ret < 0))
89 netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index);
90
91 le32_to_cpus(&buf);
92 *data = buf;
93
94 return ret;
95 }
96
97 static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
98 u32 data)
99 {
100 u32 buf;
101 int ret;
102
103 BUG_ON(!dev);
104
105 buf = data;
106 cpu_to_le32s(&buf);
107
108
109 ret = usbnet_write_cmd(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
110 USB_DIR_OUT | USB_TYPE_VENDOR |
111 USB_RECIP_DEVICE,
112 0, index, &buf, 4);
113 if (unlikely(ret < 0))
114 netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
115
116 return ret;
117 }
118
119 static int smsc95xx_set_feature(struct usbnet *dev, u32 feature)
120 {
121 if (WARN_ON_ONCE(!dev))
122 return -EINVAL;
123
124 return usbnet_write_cmd(dev, USB_REQ_SET_FEATURE,
125 USB_RECIP_DEVICE, feature, 0, NULL, 0);
126 }
127
128 static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature)
129 {
130 if (WARN_ON_ONCE(!dev))
131 return -EINVAL;
132
133 return usbnet_write_cmd(dev, USB_REQ_CLEAR_FEATURE,
134 USB_RECIP_DEVICE, feature, 0, NULL, 0);
135 }
136
137 /* Loop until the read is completed with timeout
138 * called with phy_mutex held */
139 static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev)
140 {
141 unsigned long start_time = jiffies;
142 u32 val;
143 int ret;
144
145 do {
146 ret = smsc95xx_read_reg(dev, MII_ADDR, &val);
147 check_warn_return(ret, "Error reading MII_ACCESS");
148 if (!(val & MII_BUSY_))
149 return 0;
150 } while (!time_after(jiffies, start_time + HZ));
151
152 return -EIO;
153 }
154
155 static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
156 {
157 struct usbnet *dev = netdev_priv(netdev);
158 u32 val, addr;
159 int ret;
160
161 mutex_lock(&dev->phy_mutex);
162
163 /* confirm MII not busy */
164 ret = smsc95xx_phy_wait_not_busy(dev);
165 check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read");
166
167 /* set the address, index & direction (read from PHY) */
168 phy_id &= dev->mii.phy_id_mask;
169 idx &= dev->mii.reg_num_mask;
170 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
171 ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
172 check_warn_goto_done(ret, "Error writing MII_ADDR");
173
174 ret = smsc95xx_phy_wait_not_busy(dev);
175 check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx);
176
177 ret = smsc95xx_read_reg(dev, MII_DATA, &val);
178 check_warn_goto_done(ret, "Error reading MII_DATA");
179
180 ret = (u16)(val & 0xFFFF);
181
182 done:
183 mutex_unlock(&dev->phy_mutex);
184 return ret;
185 }
186
187 static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
188 int regval)
189 {
190 struct usbnet *dev = netdev_priv(netdev);
191 u32 val, addr;
192 int ret;
193
194 mutex_lock(&dev->phy_mutex);
195
196 /* confirm MII not busy */
197 ret = smsc95xx_phy_wait_not_busy(dev);
198 check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write");
199
200 val = regval;
201 ret = smsc95xx_write_reg(dev, MII_DATA, val);
202 check_warn_goto_done(ret, "Error writing MII_DATA");
203
204 /* set the address, index & direction (write to PHY) */
205 phy_id &= dev->mii.phy_id_mask;
206 idx &= dev->mii.reg_num_mask;
207 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
208 ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
209 check_warn_goto_done(ret, "Error writing MII_ADDR");
210
211 ret = smsc95xx_phy_wait_not_busy(dev);
212 check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx);
213
214 done:
215 mutex_unlock(&dev->phy_mutex);
216 }
217
218 static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
219 {
220 unsigned long start_time = jiffies;
221 u32 val;
222 int ret;
223
224 do {
225 ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
226 check_warn_return(ret, "Error reading E2P_CMD");
227 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
228 break;
229 udelay(40);
230 } while (!time_after(jiffies, start_time + HZ));
231
232 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
233 netdev_warn(dev->net, "EEPROM read operation timeout\n");
234 return -EIO;
235 }
236
237 return 0;
238 }
239
240 static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
241 {
242 unsigned long start_time = jiffies;
243 u32 val;
244 int ret;
245
246 do {
247 ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
248 check_warn_return(ret, "Error reading E2P_CMD");
249
250 if (!(val & E2P_CMD_BUSY_))
251 return 0;
252
253 udelay(40);
254 } while (!time_after(jiffies, start_time + HZ));
255
256 netdev_warn(dev->net, "EEPROM is busy\n");
257 return -EIO;
258 }
259
260 static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
261 u8 *data)
262 {
263 u32 val;
264 int i, ret;
265
266 BUG_ON(!dev);
267 BUG_ON(!data);
268
269 ret = smsc95xx_eeprom_confirm_not_busy(dev);
270 if (ret)
271 return ret;
272
273 for (i = 0; i < length; i++) {
274 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
275 ret = smsc95xx_write_reg(dev, E2P_CMD, val);
276 check_warn_return(ret, "Error writing E2P_CMD");
277
278 ret = smsc95xx_wait_eeprom(dev);
279 if (ret < 0)
280 return ret;
281
282 ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
283 check_warn_return(ret, "Error reading E2P_DATA");
284
285 data[i] = val & 0xFF;
286 offset++;
287 }
288
289 return 0;
290 }
291
292 static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
293 u8 *data)
294 {
295 u32 val;
296 int i, ret;
297
298 BUG_ON(!dev);
299 BUG_ON(!data);
300
301 ret = smsc95xx_eeprom_confirm_not_busy(dev);
302 if (ret)
303 return ret;
304
305 /* Issue write/erase enable command */
306 val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
307 ret = smsc95xx_write_reg(dev, E2P_CMD, val);
308 check_warn_return(ret, "Error writing E2P_DATA");
309
310 ret = smsc95xx_wait_eeprom(dev);
311 if (ret < 0)
312 return ret;
313
314 for (i = 0; i < length; i++) {
315
316 /* Fill data register */
317 val = data[i];
318 ret = smsc95xx_write_reg(dev, E2P_DATA, val);
319 check_warn_return(ret, "Error writing E2P_DATA");
320
321 /* Send "write" command */
322 val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
323 ret = smsc95xx_write_reg(dev, E2P_CMD, val);
324 check_warn_return(ret, "Error writing E2P_CMD");
325
326 ret = smsc95xx_wait_eeprom(dev);
327 if (ret < 0)
328 return ret;
329
330 offset++;
331 }
332
333 return 0;
334 }
335
336 static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
337 u32 *data)
338 {
339 const u16 size = 4;
340 int ret;
341
342 ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
343 USB_DIR_OUT | USB_TYPE_VENDOR |
344 USB_RECIP_DEVICE,
345 0, index, data, size);
346 if (ret < 0)
347 netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
348 ret);
349 return ret;
350 }
351
352 /* returns hash bit number for given MAC address
353 * example:
354 * 01 00 5E 00 00 01 -> returns bit number 31 */
355 static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
356 {
357 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
358 }
359
360 static void smsc95xx_set_multicast(struct net_device *netdev)
361 {
362 struct usbnet *dev = netdev_priv(netdev);
363 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
364 unsigned long flags;
365 int ret;
366
367 pdata->hash_hi = 0;
368 pdata->hash_lo = 0;
369
370 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
371
372 if (dev->net->flags & IFF_PROMISC) {
373 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
374 pdata->mac_cr |= MAC_CR_PRMS_;
375 pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
376 } else if (dev->net->flags & IFF_ALLMULTI) {
377 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
378 pdata->mac_cr |= MAC_CR_MCPAS_;
379 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
380 } else if (!netdev_mc_empty(dev->net)) {
381 struct netdev_hw_addr *ha;
382
383 pdata->mac_cr |= MAC_CR_HPFILT_;
384 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
385
386 netdev_for_each_mc_addr(ha, netdev) {
387 u32 bitnum = smsc95xx_hash(ha->addr);
388 u32 mask = 0x01 << (bitnum & 0x1F);
389 if (bitnum & 0x20)
390 pdata->hash_hi |= mask;
391 else
392 pdata->hash_lo |= mask;
393 }
394
395 netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
396 pdata->hash_hi, pdata->hash_lo);
397 } else {
398 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
399 pdata->mac_cr &=
400 ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
401 }
402
403 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
404
405 /* Initiate async writes, as we can't wait for completion here */
406 ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi);
407 check_warn(ret, "failed to initiate async write to HASHH");
408
409 ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo);
410 check_warn(ret, "failed to initiate async write to HASHL");
411
412 ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
413 check_warn(ret, "failed to initiate async write to MAC_CR");
414 }
415
416 static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
417 u16 lcladv, u16 rmtadv)
418 {
419 u32 flow, afc_cfg = 0;
420
421 int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
422 check_warn_return(ret, "Error reading AFC_CFG");
423
424 if (duplex == DUPLEX_FULL) {
425 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
426
427 if (cap & FLOW_CTRL_RX)
428 flow = 0xFFFF0002;
429 else
430 flow = 0;
431
432 if (cap & FLOW_CTRL_TX)
433 afc_cfg |= 0xF;
434 else
435 afc_cfg &= ~0xF;
436
437 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
438 cap & FLOW_CTRL_RX ? "enabled" : "disabled",
439 cap & FLOW_CTRL_TX ? "enabled" : "disabled");
440 } else {
441 netif_dbg(dev, link, dev->net, "half duplex\n");
442 flow = 0;
443 afc_cfg |= 0xF;
444 }
445
446 ret = smsc95xx_write_reg(dev, FLOW, flow);
447 check_warn_return(ret, "Error writing FLOW");
448
449 ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
450 check_warn_return(ret, "Error writing AFC_CFG");
451
452 return 0;
453 }
454
455 static int smsc95xx_link_reset(struct usbnet *dev)
456 {
457 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
458 struct mii_if_info *mii = &dev->mii;
459 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
460 unsigned long flags;
461 u16 lcladv, rmtadv;
462 int ret;
463
464 /* clear interrupt status */
465 ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
466 check_warn_return(ret, "Error reading PHY_INT_SRC");
467
468 ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
469 check_warn_return(ret, "Error writing INT_STS");
470
471 mii_check_media(mii, 1, 1);
472 mii_ethtool_gset(&dev->mii, &ecmd);
473 lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
474 rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
475
476 netif_dbg(dev, link, dev->net,
477 "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
478 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
479
480 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
481 if (ecmd.duplex != DUPLEX_FULL) {
482 pdata->mac_cr &= ~MAC_CR_FDPX_;
483 pdata->mac_cr |= MAC_CR_RCVOWN_;
484 } else {
485 pdata->mac_cr &= ~MAC_CR_RCVOWN_;
486 pdata->mac_cr |= MAC_CR_FDPX_;
487 }
488 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
489
490 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
491 check_warn_return(ret, "Error writing MAC_CR");
492
493 ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
494 check_warn_return(ret, "Error updating PHY flow control");
495
496 return 0;
497 }
498
499 static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
500 {
501 u32 intdata;
502
503 if (urb->actual_length != 4) {
504 netdev_warn(dev->net, "unexpected urb length %d\n",
505 urb->actual_length);
506 return;
507 }
508
509 memcpy(&intdata, urb->transfer_buffer, 4);
510 le32_to_cpus(&intdata);
511
512 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
513
514 if (intdata & INT_ENP_PHY_INT_)
515 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
516 else
517 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
518 intdata);
519 }
520
521 /* Enable or disable Tx & Rx checksum offload engines */
522 static int smsc95xx_set_features(struct net_device *netdev,
523 netdev_features_t features)
524 {
525 struct usbnet *dev = netdev_priv(netdev);
526 u32 read_buf;
527 int ret;
528
529 ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
530 check_warn_return(ret, "Failed to read COE_CR: %d\n", ret);
531
532 if (features & NETIF_F_HW_CSUM)
533 read_buf |= Tx_COE_EN_;
534 else
535 read_buf &= ~Tx_COE_EN_;
536
537 if (features & NETIF_F_RXCSUM)
538 read_buf |= Rx_COE_EN_;
539 else
540 read_buf &= ~Rx_COE_EN_;
541
542 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
543 check_warn_return(ret, "Failed to write COE_CR: %d\n", ret);
544
545 netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
546 return 0;
547 }
548
549 static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
550 {
551 return MAX_EEPROM_SIZE;
552 }
553
554 static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
555 struct ethtool_eeprom *ee, u8 *data)
556 {
557 struct usbnet *dev = netdev_priv(netdev);
558
559 ee->magic = LAN95XX_EEPROM_MAGIC;
560
561 return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
562 }
563
564 static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
565 struct ethtool_eeprom *ee, u8 *data)
566 {
567 struct usbnet *dev = netdev_priv(netdev);
568
569 if (ee->magic != LAN95XX_EEPROM_MAGIC) {
570 netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
571 ee->magic);
572 return -EINVAL;
573 }
574
575 return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
576 }
577
578 static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
579 {
580 /* all smsc95xx registers */
581 return COE_CR - ID_REV + 1;
582 }
583
584 static void
585 smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
586 void *buf)
587 {
588 struct usbnet *dev = netdev_priv(netdev);
589 unsigned int i, j;
590 int retval;
591 u32 *data = buf;
592
593 retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
594 if (retval < 0) {
595 netdev_warn(netdev, "REGS: cannot read ID_REV\n");
596 return;
597 }
598
599 for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
600 retval = smsc95xx_read_reg(dev, i, &data[j]);
601 if (retval < 0) {
602 netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
603 return;
604 }
605 }
606 }
607
608 static void smsc95xx_ethtool_get_wol(struct net_device *net,
609 struct ethtool_wolinfo *wolinfo)
610 {
611 struct usbnet *dev = netdev_priv(net);
612 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
613
614 wolinfo->supported = SUPPORTED_WAKE;
615 wolinfo->wolopts = pdata->wolopts;
616 }
617
618 static int smsc95xx_ethtool_set_wol(struct net_device *net,
619 struct ethtool_wolinfo *wolinfo)
620 {
621 struct usbnet *dev = netdev_priv(net);
622 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
623
624 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
625 return 0;
626 }
627
628 static const struct ethtool_ops smsc95xx_ethtool_ops = {
629 .get_link = usbnet_get_link,
630 .nway_reset = usbnet_nway_reset,
631 .get_drvinfo = usbnet_get_drvinfo,
632 .get_msglevel = usbnet_get_msglevel,
633 .set_msglevel = usbnet_set_msglevel,
634 .get_settings = usbnet_get_settings,
635 .set_settings = usbnet_set_settings,
636 .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
637 .get_eeprom = smsc95xx_ethtool_get_eeprom,
638 .set_eeprom = smsc95xx_ethtool_set_eeprom,
639 .get_regs_len = smsc95xx_ethtool_getregslen,
640 .get_regs = smsc95xx_ethtool_getregs,
641 .get_wol = smsc95xx_ethtool_get_wol,
642 .set_wol = smsc95xx_ethtool_set_wol,
643 };
644
645 static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
646 {
647 struct usbnet *dev = netdev_priv(netdev);
648
649 if (!netif_running(netdev))
650 return -EINVAL;
651
652 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
653 }
654
655 static void smsc95xx_init_mac_address(struct usbnet *dev)
656 {
657 /* try reading mac address from EEPROM */
658 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
659 dev->net->dev_addr) == 0) {
660 if (is_valid_ether_addr(dev->net->dev_addr)) {
661 /* eeprom values are valid so use them */
662 netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
663 return;
664 }
665 }
666
667 /* no eeprom, or eeprom values are invalid. generate random MAC */
668 eth_hw_addr_random(dev->net);
669 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
670 }
671
672 static int smsc95xx_set_mac_address(struct usbnet *dev)
673 {
674 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
675 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
676 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
677 int ret;
678
679 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
680 check_warn_return(ret, "Failed to write ADDRL: %d\n", ret);
681
682 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
683 check_warn_return(ret, "Failed to write ADDRH: %d\n", ret);
684
685 return 0;
686 }
687
688 /* starts the TX path */
689 static int smsc95xx_start_tx_path(struct usbnet *dev)
690 {
691 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
692 unsigned long flags;
693 int ret;
694
695 /* Enable Tx at MAC */
696 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
697 pdata->mac_cr |= MAC_CR_TXEN_;
698 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
699
700 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
701 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
702
703 /* Enable Tx at SCSRs */
704 ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
705 check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret);
706
707 return 0;
708 }
709
710 /* Starts the Receive path */
711 static int smsc95xx_start_rx_path(struct usbnet *dev)
712 {
713 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
714 unsigned long flags;
715 int ret;
716
717 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
718 pdata->mac_cr |= MAC_CR_RXEN_;
719 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
720
721 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
722 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
723
724 return 0;
725 }
726
727 static int smsc95xx_phy_initialize(struct usbnet *dev)
728 {
729 int bmcr, ret, timeout = 0;
730
731 /* Initialize MII structure */
732 dev->mii.dev = dev->net;
733 dev->mii.mdio_read = smsc95xx_mdio_read;
734 dev->mii.mdio_write = smsc95xx_mdio_write;
735 dev->mii.phy_id_mask = 0x1f;
736 dev->mii.reg_num_mask = 0x1f;
737 dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
738
739 /* reset phy and wait for reset to complete */
740 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
741
742 do {
743 msleep(10);
744 bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
745 timeout++;
746 } while ((bmcr & BMCR_RESET) && (timeout < 100));
747
748 if (timeout >= 100) {
749 netdev_warn(dev->net, "timeout on PHY Reset");
750 return -EIO;
751 }
752
753 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
754 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
755 ADVERTISE_PAUSE_ASYM);
756
757 /* read to clear */
758 ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
759 check_warn_return(ret, "Failed to read PHY_INT_SRC during init");
760
761 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
762 PHY_INT_MASK_DEFAULT_);
763 mii_nway_restart(&dev->mii);
764
765 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
766 return 0;
767 }
768
769 static int smsc95xx_reset(struct usbnet *dev)
770 {
771 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
772 u32 read_buf, write_buf, burst_cap;
773 int ret = 0, timeout;
774
775 netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
776
777 ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
778 check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n");
779
780 timeout = 0;
781 do {
782 msleep(10);
783 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
784 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
785 timeout++;
786 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
787
788 if (timeout >= 100) {
789 netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
790 return ret;
791 }
792
793 ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
794 check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret);
795
796 timeout = 0;
797 do {
798 msleep(10);
799 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
800 check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret);
801 timeout++;
802 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
803
804 if (timeout >= 100) {
805 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
806 return ret;
807 }
808
809 ret = smsc95xx_set_mac_address(dev);
810 if (ret < 0)
811 return ret;
812
813 netif_dbg(dev, ifup, dev->net,
814 "MAC Address: %pM\n", dev->net->dev_addr);
815
816 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
817 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
818
819 netif_dbg(dev, ifup, dev->net,
820 "Read Value from HW_CFG : 0x%08x\n", read_buf);
821
822 read_buf |= HW_CFG_BIR_;
823
824 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
825 check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n");
826
827 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
828 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
829 netif_dbg(dev, ifup, dev->net,
830 "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
831 read_buf);
832
833 if (!turbo_mode) {
834 burst_cap = 0;
835 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
836 } else if (dev->udev->speed == USB_SPEED_HIGH) {
837 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
838 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
839 } else {
840 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
841 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
842 }
843
844 netif_dbg(dev, ifup, dev->net,
845 "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
846
847 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
848 check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret);
849
850 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
851 check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret);
852
853 netif_dbg(dev, ifup, dev->net,
854 "Read Value from BURST_CAP after writing: 0x%08x\n",
855 read_buf);
856
857 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
858 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret);
859
860 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
861 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret);
862
863 netif_dbg(dev, ifup, dev->net,
864 "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
865 read_buf);
866
867 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
868 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
869
870 netif_dbg(dev, ifup, dev->net,
871 "Read Value from HW_CFG: 0x%08x\n", read_buf);
872
873 if (turbo_mode)
874 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
875
876 read_buf &= ~HW_CFG_RXDOFF_;
877
878 /* set Rx data offset=2, Make IP header aligns on word boundary. */
879 read_buf |= NET_IP_ALIGN << 9;
880
881 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
882 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
883
884 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
885 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
886
887 netif_dbg(dev, ifup, dev->net,
888 "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
889
890 ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
891 check_warn_return(ret, "Failed to write INT_STS: %d\n", ret);
892
893 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
894 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
895 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
896
897 /* Configure GPIO pins as LED outputs */
898 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
899 LED_GPIO_CFG_FDX_LED;
900 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
901 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret);
902
903 /* Init Tx */
904 ret = smsc95xx_write_reg(dev, FLOW, 0);
905 check_warn_return(ret, "Failed to write FLOW: %d\n", ret);
906
907 ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
908 check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret);
909
910 /* Don't need mac_cr_lock during initialisation */
911 ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
912 check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret);
913
914 /* Init Rx */
915 /* Set Vlan */
916 ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
917 check_warn_return(ret, "Failed to write VLAN1: %d\n", ret);
918
919 /* Enable or disable checksum offload engines */
920 ret = smsc95xx_set_features(dev->net, dev->net->features);
921 check_warn_return(ret, "Failed to set checksum offload features");
922
923 smsc95xx_set_multicast(dev->net);
924
925 ret = smsc95xx_phy_initialize(dev);
926 check_warn_return(ret, "Failed to init PHY");
927
928 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
929 check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret);
930
931 /* enable PHY interrupts */
932 read_buf |= INT_EP_CTL_PHY_INT_;
933
934 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
935 check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret);
936
937 ret = smsc95xx_start_tx_path(dev);
938 check_warn_return(ret, "Failed to start TX path");
939
940 ret = smsc95xx_start_rx_path(dev);
941 check_warn_return(ret, "Failed to start RX path");
942
943 netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
944 return 0;
945 }
946
947 static const struct net_device_ops smsc95xx_netdev_ops = {
948 .ndo_open = usbnet_open,
949 .ndo_stop = usbnet_stop,
950 .ndo_start_xmit = usbnet_start_xmit,
951 .ndo_tx_timeout = usbnet_tx_timeout,
952 .ndo_change_mtu = usbnet_change_mtu,
953 .ndo_set_mac_address = eth_mac_addr,
954 .ndo_validate_addr = eth_validate_addr,
955 .ndo_do_ioctl = smsc95xx_ioctl,
956 .ndo_set_rx_mode = smsc95xx_set_multicast,
957 .ndo_set_features = smsc95xx_set_features,
958 };
959
960 static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
961 {
962 struct smsc95xx_priv *pdata = NULL;
963 u32 val;
964 int ret;
965
966 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
967
968 ret = usbnet_get_endpoints(dev, intf);
969 check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret);
970
971 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
972 GFP_KERNEL);
973
974 pdata = (struct smsc95xx_priv *)(dev->data[0]);
975 if (!pdata) {
976 netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
977 return -ENOMEM;
978 }
979
980 spin_lock_init(&pdata->mac_cr_lock);
981
982 if (DEFAULT_TX_CSUM_ENABLE)
983 dev->net->features |= NETIF_F_HW_CSUM;
984 if (DEFAULT_RX_CSUM_ENABLE)
985 dev->net->features |= NETIF_F_RXCSUM;
986
987 dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
988
989 smsc95xx_init_mac_address(dev);
990
991 /* Init all registers */
992 ret = smsc95xx_reset(dev);
993
994 /* detect device revision as different features may be available */
995 ret = smsc95xx_read_reg(dev, ID_REV, &val);
996 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
997 val >>= 16;
998 if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9512_))
999 pdata->wuff_filter_count = LAN9500A_WUFF_NUM;
1000 else
1001 pdata->wuff_filter_count = LAN9500_WUFF_NUM;
1002
1003 dev->net->netdev_ops = &smsc95xx_netdev_ops;
1004 dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
1005 dev->net->flags |= IFF_MULTICAST;
1006 dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
1007 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
1008 return 0;
1009 }
1010
1011 static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1012 {
1013 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1014 if (pdata) {
1015 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
1016 kfree(pdata);
1017 pdata = NULL;
1018 dev->data[0] = 0;
1019 }
1020 }
1021
1022 static u16 smsc_crc(const u8 *buffer, size_t len, int filter)
1023 {
1024 return bitrev16(crc16(0xFFFF, buffer, len)) << ((filter % 2) * 16);
1025 }
1026
1027 static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
1028 {
1029 struct usbnet *dev = usb_get_intfdata(intf);
1030 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1031 int ret;
1032 u32 val;
1033
1034 ret = usbnet_suspend(intf, message);
1035 check_warn_return(ret, "usbnet_suspend error");
1036
1037 /* if no wol options set, enter lowest power SUSPEND2 mode */
1038 if (!(pdata->wolopts & SUPPORTED_WAKE)) {
1039 netdev_info(dev->net, "entering SUSPEND2 mode");
1040
1041 /* disable energy detect (link up) & wake up events */
1042 ret = smsc95xx_read_reg(dev, WUCSR, &val);
1043 check_warn_return(ret, "Error reading WUCSR");
1044
1045 val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
1046
1047 ret = smsc95xx_write_reg(dev, WUCSR, val);
1048 check_warn_return(ret, "Error writing WUCSR");
1049
1050 ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
1051 check_warn_return(ret, "Error reading PM_CTRL");
1052
1053 val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
1054
1055 ret = smsc95xx_write_reg(dev, PM_CTRL, val);
1056 check_warn_return(ret, "Error writing PM_CTRL");
1057
1058 /* enter suspend2 mode */
1059 ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
1060 check_warn_return(ret, "Error reading PM_CTRL");
1061
1062 val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
1063 val |= PM_CTL_SUS_MODE_2;
1064
1065 ret = smsc95xx_write_reg(dev, PM_CTRL, val);
1066 check_warn_return(ret, "Error writing PM_CTRL");
1067
1068 return 0;
1069 }
1070
1071 if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
1072 u32 *filter_mask = kzalloc(32, GFP_KERNEL);
1073 u32 command[2];
1074 u32 offset[2];
1075 u32 crc[4];
1076 int i, filter = 0;
1077
1078 memset(command, 0, sizeof(command));
1079 memset(offset, 0, sizeof(offset));
1080 memset(crc, 0, sizeof(crc));
1081
1082 if (pdata->wolopts & WAKE_BCAST) {
1083 const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
1084 netdev_info(dev->net, "enabling broadcast detection");
1085 filter_mask[filter * 4] = 0x003F;
1086 filter_mask[filter * 4 + 1] = 0x00;
1087 filter_mask[filter * 4 + 2] = 0x00;
1088 filter_mask[filter * 4 + 3] = 0x00;
1089 command[filter/4] |= 0x05UL << ((filter % 4) * 8);
1090 offset[filter/4] |= 0x00 << ((filter % 4) * 8);
1091 crc[filter/2] |= smsc_crc(bcast, 6, filter);
1092 filter++;
1093 }
1094
1095 if (pdata->wolopts & WAKE_MCAST) {
1096 const u8 mcast[] = {0x01, 0x00, 0x5E};
1097 netdev_info(dev->net, "enabling multicast detection");
1098 filter_mask[filter * 4] = 0x0007;
1099 filter_mask[filter * 4 + 1] = 0x00;
1100 filter_mask[filter * 4 + 2] = 0x00;
1101 filter_mask[filter * 4 + 3] = 0x00;
1102 command[filter/4] |= 0x09UL << ((filter % 4) * 8);
1103 offset[filter/4] |= 0x00 << ((filter % 4) * 8);
1104 crc[filter/2] |= smsc_crc(mcast, 3, filter);
1105 filter++;
1106 }
1107
1108 if (pdata->wolopts & WAKE_ARP) {
1109 const u8 arp[] = {0x08, 0x06};
1110 netdev_info(dev->net, "enabling ARP detection");
1111 filter_mask[filter * 4] = 0x0003;
1112 filter_mask[filter * 4 + 1] = 0x00;
1113 filter_mask[filter * 4 + 2] = 0x00;
1114 filter_mask[filter * 4 + 3] = 0x00;
1115 command[filter/4] |= 0x05UL << ((filter % 4) * 8);
1116 offset[filter/4] |= 0x0C << ((filter % 4) * 8);
1117 crc[filter/2] |= smsc_crc(arp, 2, filter);
1118 filter++;
1119 }
1120
1121 if (pdata->wolopts & WAKE_UCAST) {
1122 netdev_info(dev->net, "enabling unicast detection");
1123 filter_mask[filter * 4] = 0x003F;
1124 filter_mask[filter * 4 + 1] = 0x00;
1125 filter_mask[filter * 4 + 2] = 0x00;
1126 filter_mask[filter * 4 + 3] = 0x00;
1127 command[filter/4] |= 0x01UL << ((filter % 4) * 8);
1128 offset[filter/4] |= 0x00 << ((filter % 4) * 8);
1129 crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
1130 filter++;
1131 }
1132
1133 for (i = 0; i < (pdata->wuff_filter_count * 4); i++) {
1134 ret = smsc95xx_write_reg(dev, WUFF, filter_mask[i]);
1135 if (ret < 0)
1136 kfree(filter_mask);
1137 check_warn_return(ret, "Error writing WUFF");
1138 }
1139 kfree(filter_mask);
1140
1141 for (i = 0; i < (pdata->wuff_filter_count / 4); i++) {
1142 ret = smsc95xx_write_reg(dev, WUFF, command[i]);
1143 check_warn_return(ret, "Error writing WUFF");
1144 }
1145
1146 for (i = 0; i < (pdata->wuff_filter_count / 4); i++) {
1147 ret = smsc95xx_write_reg(dev, WUFF, offset[i]);
1148 check_warn_return(ret, "Error writing WUFF");
1149 }
1150
1151 for (i = 0; i < (pdata->wuff_filter_count / 2); i++) {
1152 ret = smsc95xx_write_reg(dev, WUFF, crc[i]);
1153 check_warn_return(ret, "Error writing WUFF");
1154 }
1155
1156 /* clear any pending pattern match packet status */
1157 ret = smsc95xx_read_reg(dev, WUCSR, &val);
1158 check_warn_return(ret, "Error reading WUCSR");
1159
1160 val |= WUCSR_WUFR_;
1161
1162 ret = smsc95xx_write_reg(dev, WUCSR, val);
1163 check_warn_return(ret, "Error writing WUCSR");
1164 }
1165
1166 if (pdata->wolopts & WAKE_MAGIC) {
1167 /* clear any pending magic packet status */
1168 ret = smsc95xx_read_reg(dev, WUCSR, &val);
1169 check_warn_return(ret, "Error reading WUCSR");
1170
1171 val |= WUCSR_MPR_;
1172
1173 ret = smsc95xx_write_reg(dev, WUCSR, val);
1174 check_warn_return(ret, "Error writing WUCSR");
1175 }
1176
1177 /* enable/disable wakeup sources */
1178 ret = smsc95xx_read_reg(dev, WUCSR, &val);
1179 check_warn_return(ret, "Error reading WUCSR");
1180
1181 if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
1182 netdev_info(dev->net, "enabling pattern match wakeup");
1183 val |= WUCSR_WAKE_EN_;
1184 } else {
1185 netdev_info(dev->net, "disabling pattern match wakeup");
1186 val &= ~WUCSR_WAKE_EN_;
1187 }
1188
1189 if (pdata->wolopts & WAKE_MAGIC) {
1190 netdev_info(dev->net, "enabling magic packet wakeup");
1191 val |= WUCSR_MPEN_;
1192 } else {
1193 netdev_info(dev->net, "disabling magic packet wakeup");
1194 val &= ~WUCSR_MPEN_;
1195 }
1196
1197 ret = smsc95xx_write_reg(dev, WUCSR, val);
1198 check_warn_return(ret, "Error writing WUCSR");
1199
1200 /* enable wol wakeup source */
1201 ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
1202 check_warn_return(ret, "Error reading PM_CTRL");
1203
1204 val |= PM_CTL_WOL_EN_;
1205
1206 ret = smsc95xx_write_reg(dev, PM_CTRL, val);
1207 check_warn_return(ret, "Error writing PM_CTRL");
1208
1209 /* enable receiver to enable frame reception */
1210 smsc95xx_start_rx_path(dev);
1211
1212 /* some wol options are enabled, so enter SUSPEND0 */
1213 netdev_info(dev->net, "entering SUSPEND0 mode");
1214
1215 ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
1216 check_warn_return(ret, "Error reading PM_CTRL");
1217
1218 val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
1219 val |= PM_CTL_SUS_MODE_0;
1220
1221 ret = smsc95xx_write_reg(dev, PM_CTRL, val);
1222 check_warn_return(ret, "Error writing PM_CTRL");
1223
1224 /* clear wol status */
1225 val &= ~PM_CTL_WUPS_;
1226 val |= PM_CTL_WUPS_WOL_;
1227 ret = smsc95xx_write_reg(dev, PM_CTRL, val);
1228 check_warn_return(ret, "Error writing PM_CTRL");
1229
1230 /* read back PM_CTRL */
1231 ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
1232 check_warn_return(ret, "Error reading PM_CTRL");
1233
1234 smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1235
1236 return 0;
1237 }
1238
1239 static int smsc95xx_resume(struct usb_interface *intf)
1240 {
1241 struct usbnet *dev = usb_get_intfdata(intf);
1242 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1243 int ret;
1244 u32 val;
1245
1246 BUG_ON(!dev);
1247
1248 if (pdata->wolopts) {
1249 smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1250
1251 /* clear wake-up sources */
1252 ret = smsc95xx_read_reg(dev, WUCSR, &val);
1253 check_warn_return(ret, "Error reading WUCSR");
1254
1255 val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
1256
1257 ret = smsc95xx_write_reg(dev, WUCSR, val);
1258 check_warn_return(ret, "Error writing WUCSR");
1259
1260 /* clear wake-up status */
1261 ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
1262 check_warn_return(ret, "Error reading PM_CTRL");
1263
1264 val &= ~PM_CTL_WOL_EN_;
1265 val |= PM_CTL_WUPS_;
1266
1267 ret = smsc95xx_write_reg(dev, PM_CTRL, val);
1268 check_warn_return(ret, "Error writing PM_CTRL");
1269 }
1270
1271 return usbnet_resume(intf);
1272 check_warn_return(ret, "usbnet_resume error");
1273
1274 return 0;
1275 }
1276
1277 static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
1278 {
1279 skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
1280 skb->ip_summed = CHECKSUM_COMPLETE;
1281 skb_trim(skb, skb->len - 2);
1282 }
1283
1284 static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
1285 {
1286 while (skb->len > 0) {
1287 u32 header, align_count;
1288 struct sk_buff *ax_skb;
1289 unsigned char *packet;
1290 u16 size;
1291
1292 memcpy(&header, skb->data, sizeof(header));
1293 le32_to_cpus(&header);
1294 skb_pull(skb, 4 + NET_IP_ALIGN);
1295 packet = skb->data;
1296
1297 /* get the packet length */
1298 size = (u16)((header & RX_STS_FL_) >> 16);
1299 align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
1300
1301 if (unlikely(header & RX_STS_ES_)) {
1302 netif_dbg(dev, rx_err, dev->net,
1303 "Error header=0x%08x\n", header);
1304 dev->net->stats.rx_errors++;
1305 dev->net->stats.rx_dropped++;
1306
1307 if (header & RX_STS_CRC_) {
1308 dev->net->stats.rx_crc_errors++;
1309 } else {
1310 if (header & (RX_STS_TL_ | RX_STS_RF_))
1311 dev->net->stats.rx_frame_errors++;
1312
1313 if ((header & RX_STS_LE_) &&
1314 (!(header & RX_STS_FT_)))
1315 dev->net->stats.rx_length_errors++;
1316 }
1317 } else {
1318 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
1319 if (unlikely(size > (ETH_FRAME_LEN + 12))) {
1320 netif_dbg(dev, rx_err, dev->net,
1321 "size err header=0x%08x\n", header);
1322 return 0;
1323 }
1324
1325 /* last frame in this batch */
1326 if (skb->len == size) {
1327 if (dev->net->features & NETIF_F_RXCSUM)
1328 smsc95xx_rx_csum_offload(skb);
1329 skb_trim(skb, skb->len - 4); /* remove fcs */
1330 skb->truesize = size + sizeof(struct sk_buff);
1331
1332 return 1;
1333 }
1334
1335 ax_skb = skb_clone(skb, GFP_ATOMIC);
1336 if (unlikely(!ax_skb)) {
1337 netdev_warn(dev->net, "Error allocating skb\n");
1338 return 0;
1339 }
1340
1341 ax_skb->len = size;
1342 ax_skb->data = packet;
1343 skb_set_tail_pointer(ax_skb, size);
1344
1345 if (dev->net->features & NETIF_F_RXCSUM)
1346 smsc95xx_rx_csum_offload(ax_skb);
1347 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
1348 ax_skb->truesize = size + sizeof(struct sk_buff);
1349
1350 usbnet_skb_return(dev, ax_skb);
1351 }
1352
1353 skb_pull(skb, size);
1354
1355 /* padding bytes before the next frame starts */
1356 if (skb->len)
1357 skb_pull(skb, align_count);
1358 }
1359
1360 if (unlikely(skb->len < 0)) {
1361 netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
1362 return 0;
1363 }
1364
1365 return 1;
1366 }
1367
1368 static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
1369 {
1370 u16 low_16 = (u16)skb_checksum_start_offset(skb);
1371 u16 high_16 = low_16 + skb->csum_offset;
1372 return (high_16 << 16) | low_16;
1373 }
1374
1375 static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
1376 struct sk_buff *skb, gfp_t flags)
1377 {
1378 bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
1379 int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
1380 u32 tx_cmd_a, tx_cmd_b;
1381
1382 /* We do not advertise SG, so skbs should be already linearized */
1383 BUG_ON(skb_shinfo(skb)->nr_frags);
1384
1385 if (skb_headroom(skb) < overhead) {
1386 struct sk_buff *skb2 = skb_copy_expand(skb,
1387 overhead, 0, flags);
1388 dev_kfree_skb_any(skb);
1389 skb = skb2;
1390 if (!skb)
1391 return NULL;
1392 }
1393
1394 if (csum) {
1395 if (skb->len <= 45) {
1396 /* workaround - hardware tx checksum does not work
1397 * properly with extremely small packets */
1398 long csstart = skb_checksum_start_offset(skb);
1399 __wsum calc = csum_partial(skb->data + csstart,
1400 skb->len - csstart, 0);
1401 *((__sum16 *)(skb->data + csstart
1402 + skb->csum_offset)) = csum_fold(calc);
1403
1404 csum = false;
1405 } else {
1406 u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
1407 skb_push(skb, 4);
1408 memcpy(skb->data, &csum_preamble, 4);
1409 }
1410 }
1411
1412 skb_push(skb, 4);
1413 tx_cmd_b = (u32)(skb->len - 4);
1414 if (csum)
1415 tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
1416 cpu_to_le32s(&tx_cmd_b);
1417 memcpy(skb->data, &tx_cmd_b, 4);
1418
1419 skb_push(skb, 4);
1420 tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
1421 TX_CMD_A_LAST_SEG_;
1422 cpu_to_le32s(&tx_cmd_a);
1423 memcpy(skb->data, &tx_cmd_a, 4);
1424
1425 return skb;
1426 }
1427
1428 static const struct driver_info smsc95xx_info = {
1429 .description = "smsc95xx USB 2.0 Ethernet",
1430 .bind = smsc95xx_bind,
1431 .unbind = smsc95xx_unbind,
1432 .link_reset = smsc95xx_link_reset,
1433 .reset = smsc95xx_reset,
1434 .rx_fixup = smsc95xx_rx_fixup,
1435 .tx_fixup = smsc95xx_tx_fixup,
1436 .status = smsc95xx_status,
1437 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
1438 };
1439
1440 static const struct usb_device_id products[] = {
1441 {
1442 /* SMSC9500 USB Ethernet Device */
1443 USB_DEVICE(0x0424, 0x9500),
1444 .driver_info = (unsigned long) &smsc95xx_info,
1445 },
1446 {
1447 /* SMSC9505 USB Ethernet Device */
1448 USB_DEVICE(0x0424, 0x9505),
1449 .driver_info = (unsigned long) &smsc95xx_info,
1450 },
1451 {
1452 /* SMSC9500A USB Ethernet Device */
1453 USB_DEVICE(0x0424, 0x9E00),
1454 .driver_info = (unsigned long) &smsc95xx_info,
1455 },
1456 {
1457 /* SMSC9505A USB Ethernet Device */
1458 USB_DEVICE(0x0424, 0x9E01),
1459 .driver_info = (unsigned long) &smsc95xx_info,
1460 },
1461 {
1462 /* SMSC9512/9514 USB Hub & Ethernet Device */
1463 USB_DEVICE(0x0424, 0xec00),
1464 .driver_info = (unsigned long) &smsc95xx_info,
1465 },
1466 {
1467 /* SMSC9500 USB Ethernet Device (SAL10) */
1468 USB_DEVICE(0x0424, 0x9900),
1469 .driver_info = (unsigned long) &smsc95xx_info,
1470 },
1471 {
1472 /* SMSC9505 USB Ethernet Device (SAL10) */
1473 USB_DEVICE(0x0424, 0x9901),
1474 .driver_info = (unsigned long) &smsc95xx_info,
1475 },
1476 {
1477 /* SMSC9500A USB Ethernet Device (SAL10) */
1478 USB_DEVICE(0x0424, 0x9902),
1479 .driver_info = (unsigned long) &smsc95xx_info,
1480 },
1481 {
1482 /* SMSC9505A USB Ethernet Device (SAL10) */
1483 USB_DEVICE(0x0424, 0x9903),
1484 .driver_info = (unsigned long) &smsc95xx_info,
1485 },
1486 {
1487 /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
1488 USB_DEVICE(0x0424, 0x9904),
1489 .driver_info = (unsigned long) &smsc95xx_info,
1490 },
1491 {
1492 /* SMSC9500A USB Ethernet Device (HAL) */
1493 USB_DEVICE(0x0424, 0x9905),
1494 .driver_info = (unsigned long) &smsc95xx_info,
1495 },
1496 {
1497 /* SMSC9505A USB Ethernet Device (HAL) */
1498 USB_DEVICE(0x0424, 0x9906),
1499 .driver_info = (unsigned long) &smsc95xx_info,
1500 },
1501 {
1502 /* SMSC9500 USB Ethernet Device (Alternate ID) */
1503 USB_DEVICE(0x0424, 0x9907),
1504 .driver_info = (unsigned long) &smsc95xx_info,
1505 },
1506 {
1507 /* SMSC9500A USB Ethernet Device (Alternate ID) */
1508 USB_DEVICE(0x0424, 0x9908),
1509 .driver_info = (unsigned long) &smsc95xx_info,
1510 },
1511 {
1512 /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
1513 USB_DEVICE(0x0424, 0x9909),
1514 .driver_info = (unsigned long) &smsc95xx_info,
1515 },
1516 {
1517 /* SMSC LAN9530 USB Ethernet Device */
1518 USB_DEVICE(0x0424, 0x9530),
1519 .driver_info = (unsigned long) &smsc95xx_info,
1520 },
1521 {
1522 /* SMSC LAN9730 USB Ethernet Device */
1523 USB_DEVICE(0x0424, 0x9730),
1524 .driver_info = (unsigned long) &smsc95xx_info,
1525 },
1526 {
1527 /* SMSC LAN89530 USB Ethernet Device */
1528 USB_DEVICE(0x0424, 0x9E08),
1529 .driver_info = (unsigned long) &smsc95xx_info,
1530 },
1531 { }, /* END */
1532 };
1533 MODULE_DEVICE_TABLE(usb, products);
1534
1535 static struct usb_driver smsc95xx_driver = {
1536 .name = "smsc95xx",
1537 .id_table = products,
1538 .probe = usbnet_probe,
1539 .suspend = smsc95xx_suspend,
1540 .resume = smsc95xx_resume,
1541 .reset_resume = smsc95xx_resume,
1542 .disconnect = usbnet_disconnect,
1543 .disable_hub_initiated_lpm = 1,
1544 };
1545
1546 module_usb_driver(smsc95xx_driver);
1547
1548 MODULE_AUTHOR("Nancy Lin");
1549 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
1550 MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
1551 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)