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net: use netdev_mc_count and netdev_mc_empty when appropriate
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { 0 }
145 };
146
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
153
154 static void sky2_set_multicast(struct net_device *dev);
155
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
158 {
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
171 return 0;
172
173 udelay(10);
174 }
175
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
177 return -ETIMEDOUT;
178
179 io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
182 }
183
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
185 {
186 int i;
187
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
201 udelay(10);
202 }
203
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 return -ETIMEDOUT;
206 io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
209 }
210
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 {
213 u16 v;
214 __gm_phy_read(hw, port, reg, &v);
215 return v;
216 }
217
218
219 static void sky2_power_on(struct sky2_hw *hw)
220 {
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
224
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
227
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 u32 reg;
239
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
251
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
253
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
258
259 sky2_read32(hw, B2_GP_IO);
260 }
261
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 }
265
266 static void sky2_power_aux(struct sky2_hw *hw)
267 {
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
283
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
286 }
287
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 {
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303 }
304
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 };
312
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 };
320
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327 };
328
329
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 {
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334
335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 PHY_M_EC_MAC_S_MSK);
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 }
390
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 }
413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
415 }
416
417 ctrl = PHY_CT_RESET;
418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
420 reg = 0;
421
422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
436
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
442 }
443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
461 break;
462 }
463
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
469 }
470
471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
474 else
475 adv |= fiber_fc_adv[sky2->flow_mode];
476 } else {
477 reg |= GM_GPCR_AU_FCT_DIS;
478 reg |= gm_fc_disable[sky2->flow_mode];
479
480 /* Forward pause packets to GMAC? */
481 if (sky2->flow_mode & FC_RX)
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
483 else
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
485 }
486
487 gma_write16(hw, port, GM_GP_CTRL, reg);
488
489 if (hw->flags & SKY2_HW_GIGABIT)
490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
491
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
494
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 ledover = 0;
498
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
503
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
505
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 break;
512
513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
517
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
521
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
526
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 break;
529
530 case CHIP_ID_YUKON_XL:
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
532
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
535
536 /* set LED Function Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
542
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
551
552 /* restore page register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
554 break;
555
556 case CHIP_ID_YUKON_EC_U:
557 case CHIP_ID_YUKON_EX:
558 case CHIP_ID_YUKON_SUPR:
559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
560
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
563
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
570
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 break;
577
578 default:
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
581
582 /* turn off the Rx LED (LED_RX) */
583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
584 }
585
586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
589
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
593
594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
598 }
599
600 /* set page register to 0 */
601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
610
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
614
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
621
622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
626 }
627
628 if (ledover)
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
630
631 }
632
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
636 else
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638 }
639
640 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
642
643 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
644 {
645 u32 reg1;
646
647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
648 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
649 reg1 &= ~phy_power[port];
650
651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
652 reg1 |= coma_mode[port];
653
654 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
656 sky2_pci_read32(hw, PCI_DEV_REG1);
657
658 if (hw->chip_id == CHIP_ID_YUKON_FE)
659 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
660 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 }
663
664 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
665 {
666 u32 reg1;
667 u16 ctrl;
668
669 /* release GPHY Control reset */
670 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
671
672 /* release GMAC reset */
673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
674
675 if (hw->flags & SKY2_HW_NEWER_PHY) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
678
679 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
680 /* allow GMII Power Down */
681 ctrl &= ~PHY_M_MAC_GMIF_PUP;
682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
683
684 /* set page register back to 0 */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 }
687
688 /* setup General Purpose Control Register */
689 gma_write16(hw, port, GM_GP_CTRL,
690 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
691 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 GM_GPCR_AU_SPD_DIS);
693
694 if (hw->chip_id != CHIP_ID_YUKON_EC) {
695 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
698
699 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
700 /* enable Power Down */
701 ctrl |= PHY_M_PC_POW_D_ENA;
702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
703
704 /* set page register back to 0 */
705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
706 }
707
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 }
711
712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
713 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
714 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
717 }
718
719 /* Force a renegotiation */
720 static void sky2_phy_reinit(struct sky2_port *sky2)
721 {
722 spin_lock_bh(&sky2->phy_lock);
723 sky2_phy_init(sky2->hw, sky2->port);
724 spin_unlock_bh(&sky2->phy_lock);
725 }
726
727 /* Put device in state to listen for Wake On Lan */
728 static void sky2_wol_init(struct sky2_port *sky2)
729 {
730 struct sky2_hw *hw = sky2->hw;
731 unsigned port = sky2->port;
732 enum flow_control save_mode;
733 u16 ctrl;
734 u32 reg1;
735
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
739
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
742
743 /* Force to 10/100
744 * sky2_reset will re-enable on resume
745 */
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
748
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
751
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
756
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
759
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
764
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
768
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
771 ctrl = 0;
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
774 else
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
776
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
779 else
780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
781
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
784
785 /* Turn on legacy PCI-Express PME mode */
786 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
787 reg1 |= PCI_Y2_PME_LEGACY;
788 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
789
790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
792
793 }
794
795 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
796 {
797 struct net_device *dev = hw->dev[port];
798
799 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
800 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
801 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
804
805 if (dev->mtu <= ETH_DATA_LEN)
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_DIS | TX_STFW_ENA);
808
809 else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_ENA| TX_STFW_ENA);
812 } else {
813 if (dev->mtu <= ETH_DATA_LEN)
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
815 else {
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
818 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
819
820 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
821
822 /* Can't do offload because of lack of store/forward */
823 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
824 }
825 }
826 }
827
828 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
829 {
830 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
831 u16 reg;
832 u32 rx_reg;
833 int i;
834 const u8 *addr = hw->dev[port]->dev_addr;
835
836 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
837 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
838
839 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
840
841 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
845 do {
846 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
847 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
848 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
849 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
850 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
851 }
852
853 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
854
855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
857
858 spin_lock_bh(&sky2->phy_lock);
859 sky2_phy_power_up(hw, port);
860 sky2_phy_init(hw, port);
861 spin_unlock_bh(&sky2->phy_lock);
862
863 /* MIB clear */
864 reg = gma_read16(hw, port, GM_PHY_ADDR);
865 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
866
867 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
868 gma_read16(hw, port, i);
869 gma_write16(hw, port, GM_PHY_ADDR, reg);
870
871 /* transmit control */
872 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
873
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw, port, GM_RX_CTRL,
876 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
877
878 /* transmit flow control */
879 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
880
881 /* transmit parameter */
882 gma_write16(hw, port, GM_TX_PARAM,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
887
888 /* serial mode register */
889 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
890 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
891
892 if (hw->dev[port]->mtu > ETH_DATA_LEN)
893 reg |= GM_SMOD_JUMBO_ENA;
894
895 gma_write16(hw, port, GM_SERIAL_MODE, reg);
896
897 /* virtual address for data */
898 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
899
900 /* physical address: used for pause frames */
901 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
902
903 /* ignore counter overflows */
904 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
906 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
907
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
910 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
911 if (hw->chip_id == CHIP_ID_YUKON_EX ||
912 hw->chip_id == CHIP_ID_YUKON_FE_P)
913 rx_reg |= GMF_RX_OVER_ON;
914
915 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
916
917 if (hw->chip_id == CHIP_ID_YUKON_XL) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
920 } else {
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
923 }
924
925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
926 reg = RX_GMF_FL_THR_DEF + 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
929 hw->chip_rev == CHIP_REV_YU_FE2_A0)
930 reg = 0x178;
931 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
932
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
935 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
936
937 /* On chips without ram buffer, pause is controled by MAC level */
938 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
939 /* Pause threshold is scaled by 8 in bytes */
940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0)
942 reg = 1568 / 8;
943 else
944 reg = 1024 / 8;
945 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
946 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
947
948 sky2_set_tx_stfwd(hw, port);
949 }
950
951 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
952 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
953 /* disable dynamic watermark */
954 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
955 reg &= ~TX_DYN_WM_ENA;
956 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
957 }
958 }
959
960 /* Assign Ram Buffer allocation to queue */
961 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
962 {
963 u32 end;
964
965 /* convert from K bytes to qwords used for hw register */
966 start *= 1024/8;
967 space *= 1024/8;
968 end = start + space - 1;
969
970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
971 sky2_write32(hw, RB_ADDR(q, RB_START), start);
972 sky2_write32(hw, RB_ADDR(q, RB_END), end);
973 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
974 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
975
976 if (q == Q_R1 || q == Q_R2) {
977 u32 tp = space - space/4;
978
979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
982 */
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
985
986 tp = space - 2048/8;
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
989 } else {
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
992 */
993 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
994 }
995
996 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
997 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
998 }
999
1000 /* Setup Bus Memory Interface */
1001 static void sky2_qset(struct sky2_hw *hw, u16 q)
1002 {
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1006 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1007 }
1008
1009 /* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1011 */
1012 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1013 dma_addr_t addr, u32 last)
1014 {
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1019 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1021
1022 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1023 }
1024
1025 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1026 {
1027 struct sky2_tx_le *le = sky2->tx_le + *slot;
1028
1029 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1030 le->ctrl = 0;
1031 return le;
1032 }
1033
1034 static void tx_init(struct sky2_port *sky2)
1035 {
1036 struct sky2_tx_le *le;
1037
1038 sky2->tx_prod = sky2->tx_cons = 0;
1039 sky2->tx_tcpsum = 0;
1040 sky2->tx_last_mss = 0;
1041
1042 le = get_tx_le(sky2, &sky2->tx_prod);
1043 le->addr = 0;
1044 le->opcode = OP_ADDR64 | HW_OWNER;
1045 sky2->tx_last_upper = 0;
1046 }
1047
1048 /* Update chip's next pointer */
1049 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1050 {
1051 /* Make sure write' to descriptors are complete before we tell hardware */
1052 wmb();
1053 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1054
1055 /* Synchronize I/O on since next processor may write to tail */
1056 mmiowb();
1057 }
1058
1059
1060 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1061 {
1062 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1063 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1064 le->ctrl = 0;
1065 return le;
1066 }
1067
1068 /* Build description to hardware for one receive segment */
1069 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1070 dma_addr_t map, unsigned len)
1071 {
1072 struct sky2_rx_le *le;
1073
1074 if (sizeof(dma_addr_t) > sizeof(u32)) {
1075 le = sky2_next_rx(sky2);
1076 le->addr = cpu_to_le32(upper_32_bits(map));
1077 le->opcode = OP_ADDR64 | HW_OWNER;
1078 }
1079
1080 le = sky2_next_rx(sky2);
1081 le->addr = cpu_to_le32(lower_32_bits(map));
1082 le->length = cpu_to_le16(len);
1083 le->opcode = op | HW_OWNER;
1084 }
1085
1086 /* Build description to hardware for one possibly fragmented skb */
1087 static void sky2_rx_submit(struct sky2_port *sky2,
1088 const struct rx_ring_info *re)
1089 {
1090 int i;
1091
1092 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1093
1094 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1095 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1096 }
1097
1098
1099 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1100 unsigned size)
1101 {
1102 struct sk_buff *skb = re->skb;
1103 int i;
1104
1105 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1106 if (pci_dma_mapping_error(pdev, re->data_addr))
1107 goto mapping_error;
1108
1109 pci_unmap_len_set(re, data_size, size);
1110
1111 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1112 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1113
1114 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1115 frag->page_offset,
1116 frag->size,
1117 PCI_DMA_FROMDEVICE);
1118
1119 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1120 goto map_page_error;
1121 }
1122 return 0;
1123
1124 map_page_error:
1125 while (--i >= 0) {
1126 pci_unmap_page(pdev, re->frag_addr[i],
1127 skb_shinfo(skb)->frags[i].size,
1128 PCI_DMA_FROMDEVICE);
1129 }
1130
1131 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1132 PCI_DMA_FROMDEVICE);
1133
1134 mapping_error:
1135 if (net_ratelimit())
1136 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1137 skb->dev->name);
1138 return -EIO;
1139 }
1140
1141 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1142 {
1143 struct sk_buff *skb = re->skb;
1144 int i;
1145
1146 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1147 PCI_DMA_FROMDEVICE);
1148
1149 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1150 pci_unmap_page(pdev, re->frag_addr[i],
1151 skb_shinfo(skb)->frags[i].size,
1152 PCI_DMA_FROMDEVICE);
1153 }
1154
1155 /* Tell chip where to start receive checksum.
1156 * Actually has two checksums, but set both same to avoid possible byte
1157 * order problems.
1158 */
1159 static void rx_set_checksum(struct sky2_port *sky2)
1160 {
1161 struct sky2_rx_le *le = sky2_next_rx(sky2);
1162
1163 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1164 le->ctrl = 0;
1165 le->opcode = OP_TCPSTART | HW_OWNER;
1166
1167 sky2_write32(sky2->hw,
1168 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1169 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1170 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1171 }
1172
1173 /*
1174 * The RX Stop command will not work for Yukon-2 if the BMU does not
1175 * reach the end of packet and since we can't make sure that we have
1176 * incoming data, we must reset the BMU while it is not doing a DMA
1177 * transfer. Since it is possible that the RX path is still active,
1178 * the RX RAM buffer will be stopped first, so any possible incoming
1179 * data will not trigger a DMA. After the RAM buffer is stopped, the
1180 * BMU is polled until any DMA in progress is ended and only then it
1181 * will be reset.
1182 */
1183 static void sky2_rx_stop(struct sky2_port *sky2)
1184 {
1185 struct sky2_hw *hw = sky2->hw;
1186 unsigned rxq = rxqaddr[sky2->port];
1187 int i;
1188
1189 /* disable the RAM Buffer receive queue */
1190 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1191
1192 for (i = 0; i < 0xffff; i++)
1193 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1194 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1195 goto stopped;
1196
1197 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1198 sky2->netdev->name);
1199 stopped:
1200 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1201
1202 /* reset the Rx prefetch unit */
1203 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1204 mmiowb();
1205 }
1206
1207 /* Clean out receive buffer area, assumes receiver hardware stopped */
1208 static void sky2_rx_clean(struct sky2_port *sky2)
1209 {
1210 unsigned i;
1211
1212 memset(sky2->rx_le, 0, RX_LE_BYTES);
1213 for (i = 0; i < sky2->rx_pending; i++) {
1214 struct rx_ring_info *re = sky2->rx_ring + i;
1215
1216 if (re->skb) {
1217 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1218 kfree_skb(re->skb);
1219 re->skb = NULL;
1220 }
1221 }
1222 }
1223
1224 /* Basic MII support */
1225 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1226 {
1227 struct mii_ioctl_data *data = if_mii(ifr);
1228 struct sky2_port *sky2 = netdev_priv(dev);
1229 struct sky2_hw *hw = sky2->hw;
1230 int err = -EOPNOTSUPP;
1231
1232 if (!netif_running(dev))
1233 return -ENODEV; /* Phy still in reset */
1234
1235 switch (cmd) {
1236 case SIOCGMIIPHY:
1237 data->phy_id = PHY_ADDR_MARV;
1238
1239 /* fallthru */
1240 case SIOCGMIIREG: {
1241 u16 val = 0;
1242
1243 spin_lock_bh(&sky2->phy_lock);
1244 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1245 spin_unlock_bh(&sky2->phy_lock);
1246
1247 data->val_out = val;
1248 break;
1249 }
1250
1251 case SIOCSMIIREG:
1252 spin_lock_bh(&sky2->phy_lock);
1253 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1254 data->val_in);
1255 spin_unlock_bh(&sky2->phy_lock);
1256 break;
1257 }
1258 return err;
1259 }
1260
1261 #ifdef SKY2_VLAN_TAG_USED
1262 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1263 {
1264 if (onoff) {
1265 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1266 RX_VLAN_STRIP_ON);
1267 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1268 TX_VLAN_TAG_ON);
1269 } else {
1270 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1271 RX_VLAN_STRIP_OFF);
1272 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1273 TX_VLAN_TAG_OFF);
1274 }
1275 }
1276
1277 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1278 {
1279 struct sky2_port *sky2 = netdev_priv(dev);
1280 struct sky2_hw *hw = sky2->hw;
1281 u16 port = sky2->port;
1282
1283 netif_tx_lock_bh(dev);
1284 napi_disable(&hw->napi);
1285
1286 sky2->vlgrp = grp;
1287 sky2_set_vlan_mode(hw, port, grp != NULL);
1288
1289 sky2_read32(hw, B0_Y2_SP_LISR);
1290 napi_enable(&hw->napi);
1291 netif_tx_unlock_bh(dev);
1292 }
1293 #endif
1294
1295 /* Amount of required worst case padding in rx buffer */
1296 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1297 {
1298 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1299 }
1300
1301 /*
1302 * Allocate an skb for receiving. If the MTU is large enough
1303 * make the skb non-linear with a fragment list of pages.
1304 */
1305 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1306 {
1307 struct sk_buff *skb;
1308 int i;
1309
1310 skb = netdev_alloc_skb(sky2->netdev,
1311 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1312 if (!skb)
1313 goto nomem;
1314
1315 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1316 unsigned char *start;
1317 /*
1318 * Workaround for a bug in FIFO that cause hang
1319 * if the FIFO if the receive buffer is not 64 byte aligned.
1320 * The buffer returned from netdev_alloc_skb is
1321 * aligned except if slab debugging is enabled.
1322 */
1323 start = PTR_ALIGN(skb->data, 8);
1324 skb_reserve(skb, start - skb->data);
1325 } else
1326 skb_reserve(skb, NET_IP_ALIGN);
1327
1328 for (i = 0; i < sky2->rx_nfrags; i++) {
1329 struct page *page = alloc_page(GFP_ATOMIC);
1330
1331 if (!page)
1332 goto free_partial;
1333 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1334 }
1335
1336 return skb;
1337 free_partial:
1338 kfree_skb(skb);
1339 nomem:
1340 return NULL;
1341 }
1342
1343 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1344 {
1345 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1346 }
1347
1348 /*
1349 * Allocate and setup receiver buffer pool.
1350 * Normal case this ends up creating one list element for skb
1351 * in the receive ring. Worst case if using large MTU and each
1352 * allocation falls on a different 64 bit region, that results
1353 * in 6 list elements per ring entry.
1354 * One element is used for checksum enable/disable, and one
1355 * extra to avoid wrap.
1356 */
1357 static int sky2_rx_start(struct sky2_port *sky2)
1358 {
1359 struct sky2_hw *hw = sky2->hw;
1360 struct rx_ring_info *re;
1361 unsigned rxq = rxqaddr[sky2->port];
1362 unsigned i, size, thresh;
1363
1364 sky2->rx_put = sky2->rx_next = 0;
1365 sky2_qset(hw, rxq);
1366
1367 /* On PCI express lowering the watermark gives better performance */
1368 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1369 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1370
1371 /* These chips have no ram buffer?
1372 * MAC Rx RAM Read is controlled by hardware */
1373 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1374 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1375 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1376 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1377
1378 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1379
1380 if (!(hw->flags & SKY2_HW_NEW_LE))
1381 rx_set_checksum(sky2);
1382
1383 /* Space needed for frame data + headers rounded up */
1384 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1385
1386 /* Stopping point for hardware truncation */
1387 thresh = (size - 8) / sizeof(u32);
1388
1389 sky2->rx_nfrags = size >> PAGE_SHIFT;
1390 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1391
1392 /* Compute residue after pages */
1393 size -= sky2->rx_nfrags << PAGE_SHIFT;
1394
1395 /* Optimize to handle small packets and headers */
1396 if (size < copybreak)
1397 size = copybreak;
1398 if (size < ETH_HLEN)
1399 size = ETH_HLEN;
1400
1401 sky2->rx_data_size = size;
1402
1403 /* Fill Rx ring */
1404 for (i = 0; i < sky2->rx_pending; i++) {
1405 re = sky2->rx_ring + i;
1406
1407 re->skb = sky2_rx_alloc(sky2);
1408 if (!re->skb)
1409 goto nomem;
1410
1411 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1412 dev_kfree_skb(re->skb);
1413 re->skb = NULL;
1414 goto nomem;
1415 }
1416
1417 sky2_rx_submit(sky2, re);
1418 }
1419
1420 /*
1421 * The receiver hangs if it receives frames larger than the
1422 * packet buffer. As a workaround, truncate oversize frames, but
1423 * the register is limited to 9 bits, so if you do frames > 2052
1424 * you better get the MTU right!
1425 */
1426 if (thresh > 0x1ff)
1427 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1428 else {
1429 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1430 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1431 }
1432
1433 /* Tell chip about available buffers */
1434 sky2_rx_update(sky2, rxq);
1435
1436 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1437 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1438 /*
1439 * Disable flushing of non ASF packets;
1440 * must be done after initializing the BMUs;
1441 * drivers without ASF support should do this too, otherwise
1442 * it may happen that they cannot run on ASF devices;
1443 * remember that the MAC FIFO isn't reset during initialization.
1444 */
1445 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1446 }
1447
1448 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1449 /* Enable RX Home Address & Routing Header checksum fix */
1450 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1451 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1452
1453 /* Enable TX Home Address & Routing Header checksum fix */
1454 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1455 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1456 }
1457
1458
1459
1460 return 0;
1461 nomem:
1462 sky2_rx_clean(sky2);
1463 return -ENOMEM;
1464 }
1465
1466 static int sky2_alloc_buffers(struct sky2_port *sky2)
1467 {
1468 struct sky2_hw *hw = sky2->hw;
1469
1470 /* must be power of 2 */
1471 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1472 sky2->tx_ring_size *
1473 sizeof(struct sky2_tx_le),
1474 &sky2->tx_le_map);
1475 if (!sky2->tx_le)
1476 goto nomem;
1477
1478 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1479 GFP_KERNEL);
1480 if (!sky2->tx_ring)
1481 goto nomem;
1482
1483 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1484 &sky2->rx_le_map);
1485 if (!sky2->rx_le)
1486 goto nomem;
1487 memset(sky2->rx_le, 0, RX_LE_BYTES);
1488
1489 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1490 GFP_KERNEL);
1491 if (!sky2->rx_ring)
1492 goto nomem;
1493
1494 return 0;
1495 nomem:
1496 return -ENOMEM;
1497 }
1498
1499 static void sky2_free_buffers(struct sky2_port *sky2)
1500 {
1501 struct sky2_hw *hw = sky2->hw;
1502
1503 if (sky2->rx_le) {
1504 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1505 sky2->rx_le, sky2->rx_le_map);
1506 sky2->rx_le = NULL;
1507 }
1508 if (sky2->tx_le) {
1509 pci_free_consistent(hw->pdev,
1510 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1511 sky2->tx_le, sky2->tx_le_map);
1512 sky2->tx_le = NULL;
1513 }
1514 kfree(sky2->tx_ring);
1515 kfree(sky2->rx_ring);
1516
1517 sky2->tx_ring = NULL;
1518 sky2->rx_ring = NULL;
1519 }
1520
1521 /* Bring up network interface. */
1522 static int sky2_up(struct net_device *dev)
1523 {
1524 struct sky2_port *sky2 = netdev_priv(dev);
1525 struct sky2_hw *hw = sky2->hw;
1526 unsigned port = sky2->port;
1527 u32 imask, ramsize;
1528 int cap, err;
1529 struct net_device *otherdev = hw->dev[sky2->port^1];
1530
1531 /*
1532 * On dual port PCI-X card, there is an problem where status
1533 * can be received out of order due to split transactions
1534 */
1535 if (otherdev && netif_running(otherdev) &&
1536 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1537 u16 cmd;
1538
1539 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1540 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1541 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1542
1543 }
1544
1545 netif_carrier_off(dev);
1546
1547 err = sky2_alloc_buffers(sky2);
1548 if (err)
1549 goto err_out;
1550
1551 tx_init(sky2);
1552
1553 sky2_mac_init(hw, port);
1554
1555 /* Register is number of 4K blocks on internal RAM buffer. */
1556 ramsize = sky2_read8(hw, B2_E_0) * 4;
1557 if (ramsize > 0) {
1558 u32 rxspace;
1559
1560 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1561 if (ramsize < 16)
1562 rxspace = ramsize / 2;
1563 else
1564 rxspace = 8 + (2*(ramsize - 16))/3;
1565
1566 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1567 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1568
1569 /* Make sure SyncQ is disabled */
1570 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1571 RB_RST_SET);
1572 }
1573
1574 sky2_qset(hw, txqaddr[port]);
1575
1576 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1577 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1578 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1579
1580 /* Set almost empty threshold */
1581 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1582 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1583 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1584
1585 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1586 sky2->tx_ring_size - 1);
1587
1588 #ifdef SKY2_VLAN_TAG_USED
1589 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1590 #endif
1591
1592 err = sky2_rx_start(sky2);
1593 if (err)
1594 goto err_out;
1595
1596 /* Enable interrupts from phy/mac for port */
1597 imask = sky2_read32(hw, B0_IMSK);
1598 imask |= portirq_msk[port];
1599 sky2_write32(hw, B0_IMSK, imask);
1600 sky2_read32(hw, B0_IMSK);
1601
1602 if (netif_msg_ifup(sky2))
1603 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1604
1605 return 0;
1606
1607 err_out:
1608 sky2_free_buffers(sky2);
1609 return err;
1610 }
1611
1612 /* Modular subtraction in ring */
1613 static inline int tx_inuse(const struct sky2_port *sky2)
1614 {
1615 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1616 }
1617
1618 /* Number of list elements available for next tx */
1619 static inline int tx_avail(const struct sky2_port *sky2)
1620 {
1621 return sky2->tx_pending - tx_inuse(sky2);
1622 }
1623
1624 /* Estimate of number of transmit list elements required */
1625 static unsigned tx_le_req(const struct sk_buff *skb)
1626 {
1627 unsigned count;
1628
1629 count = (skb_shinfo(skb)->nr_frags + 1)
1630 * (sizeof(dma_addr_t) / sizeof(u32));
1631
1632 if (skb_is_gso(skb))
1633 ++count;
1634 else if (sizeof(dma_addr_t) == sizeof(u32))
1635 ++count; /* possible vlan */
1636
1637 if (skb->ip_summed == CHECKSUM_PARTIAL)
1638 ++count;
1639
1640 return count;
1641 }
1642
1643 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1644 {
1645 if (re->flags & TX_MAP_SINGLE)
1646 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1647 pci_unmap_len(re, maplen),
1648 PCI_DMA_TODEVICE);
1649 else if (re->flags & TX_MAP_PAGE)
1650 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1651 pci_unmap_len(re, maplen),
1652 PCI_DMA_TODEVICE);
1653 re->flags = 0;
1654 }
1655
1656 /*
1657 * Put one packet in ring for transmit.
1658 * A single packet can generate multiple list elements, and
1659 * the number of ring elements will probably be less than the number
1660 * of list elements used.
1661 */
1662 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1663 struct net_device *dev)
1664 {
1665 struct sky2_port *sky2 = netdev_priv(dev);
1666 struct sky2_hw *hw = sky2->hw;
1667 struct sky2_tx_le *le = NULL;
1668 struct tx_ring_info *re;
1669 unsigned i, len;
1670 dma_addr_t mapping;
1671 u32 upper;
1672 u16 slot;
1673 u16 mss;
1674 u8 ctrl;
1675
1676 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1677 return NETDEV_TX_BUSY;
1678
1679 len = skb_headlen(skb);
1680 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1681
1682 if (pci_dma_mapping_error(hw->pdev, mapping))
1683 goto mapping_error;
1684
1685 slot = sky2->tx_prod;
1686 if (unlikely(netif_msg_tx_queued(sky2)))
1687 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1688 dev->name, slot, skb->len);
1689
1690 /* Send high bits if needed */
1691 upper = upper_32_bits(mapping);
1692 if (upper != sky2->tx_last_upper) {
1693 le = get_tx_le(sky2, &slot);
1694 le->addr = cpu_to_le32(upper);
1695 sky2->tx_last_upper = upper;
1696 le->opcode = OP_ADDR64 | HW_OWNER;
1697 }
1698
1699 /* Check for TCP Segmentation Offload */
1700 mss = skb_shinfo(skb)->gso_size;
1701 if (mss != 0) {
1702
1703 if (!(hw->flags & SKY2_HW_NEW_LE))
1704 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1705
1706 if (mss != sky2->tx_last_mss) {
1707 le = get_tx_le(sky2, &slot);
1708 le->addr = cpu_to_le32(mss);
1709
1710 if (hw->flags & SKY2_HW_NEW_LE)
1711 le->opcode = OP_MSS | HW_OWNER;
1712 else
1713 le->opcode = OP_LRGLEN | HW_OWNER;
1714 sky2->tx_last_mss = mss;
1715 }
1716 }
1717
1718 ctrl = 0;
1719 #ifdef SKY2_VLAN_TAG_USED
1720 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1721 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1722 if (!le) {
1723 le = get_tx_le(sky2, &slot);
1724 le->addr = 0;
1725 le->opcode = OP_VLAN|HW_OWNER;
1726 } else
1727 le->opcode |= OP_VLAN;
1728 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1729 ctrl |= INS_VLAN;
1730 }
1731 #endif
1732
1733 /* Handle TCP checksum offload */
1734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1735 /* On Yukon EX (some versions) encoding change. */
1736 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1737 ctrl |= CALSUM; /* auto checksum */
1738 else {
1739 const unsigned offset = skb_transport_offset(skb);
1740 u32 tcpsum;
1741
1742 tcpsum = offset << 16; /* sum start */
1743 tcpsum |= offset + skb->csum_offset; /* sum write */
1744
1745 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1746 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1747 ctrl |= UDPTCP;
1748
1749 if (tcpsum != sky2->tx_tcpsum) {
1750 sky2->tx_tcpsum = tcpsum;
1751
1752 le = get_tx_le(sky2, &slot);
1753 le->addr = cpu_to_le32(tcpsum);
1754 le->length = 0; /* initial checksum value */
1755 le->ctrl = 1; /* one packet */
1756 le->opcode = OP_TCPLISW | HW_OWNER;
1757 }
1758 }
1759 }
1760
1761 re = sky2->tx_ring + slot;
1762 re->flags = TX_MAP_SINGLE;
1763 pci_unmap_addr_set(re, mapaddr, mapping);
1764 pci_unmap_len_set(re, maplen, len);
1765
1766 le = get_tx_le(sky2, &slot);
1767 le->addr = cpu_to_le32(lower_32_bits(mapping));
1768 le->length = cpu_to_le16(len);
1769 le->ctrl = ctrl;
1770 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1771
1772
1773 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1774 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1775
1776 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1777 frag->size, PCI_DMA_TODEVICE);
1778
1779 if (pci_dma_mapping_error(hw->pdev, mapping))
1780 goto mapping_unwind;
1781
1782 upper = upper_32_bits(mapping);
1783 if (upper != sky2->tx_last_upper) {
1784 le = get_tx_le(sky2, &slot);
1785 le->addr = cpu_to_le32(upper);
1786 sky2->tx_last_upper = upper;
1787 le->opcode = OP_ADDR64 | HW_OWNER;
1788 }
1789
1790 re = sky2->tx_ring + slot;
1791 re->flags = TX_MAP_PAGE;
1792 pci_unmap_addr_set(re, mapaddr, mapping);
1793 pci_unmap_len_set(re, maplen, frag->size);
1794
1795 le = get_tx_le(sky2, &slot);
1796 le->addr = cpu_to_le32(lower_32_bits(mapping));
1797 le->length = cpu_to_le16(frag->size);
1798 le->ctrl = ctrl;
1799 le->opcode = OP_BUFFER | HW_OWNER;
1800 }
1801
1802 re->skb = skb;
1803 le->ctrl |= EOP;
1804
1805 sky2->tx_prod = slot;
1806
1807 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1808 netif_stop_queue(dev);
1809
1810 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1811
1812 return NETDEV_TX_OK;
1813
1814 mapping_unwind:
1815 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1816 re = sky2->tx_ring + i;
1817
1818 sky2_tx_unmap(hw->pdev, re);
1819 }
1820
1821 mapping_error:
1822 if (net_ratelimit())
1823 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1824 dev_kfree_skb(skb);
1825 return NETDEV_TX_OK;
1826 }
1827
1828 /*
1829 * Free ring elements from starting at tx_cons until "done"
1830 *
1831 * NB:
1832 * 1. The hardware will tell us about partial completion of multi-part
1833 * buffers so make sure not to free skb to early.
1834 * 2. This may run in parallel start_xmit because the it only
1835 * looks at the tail of the queue of FIFO (tx_cons), not
1836 * the head (tx_prod)
1837 */
1838 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1839 {
1840 struct net_device *dev = sky2->netdev;
1841 unsigned idx;
1842
1843 BUG_ON(done >= sky2->tx_ring_size);
1844
1845 for (idx = sky2->tx_cons; idx != done;
1846 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1847 struct tx_ring_info *re = sky2->tx_ring + idx;
1848 struct sk_buff *skb = re->skb;
1849
1850 sky2_tx_unmap(sky2->hw->pdev, re);
1851
1852 if (skb) {
1853 if (unlikely(netif_msg_tx_done(sky2)))
1854 printk(KERN_DEBUG "%s: tx done %u\n",
1855 dev->name, idx);
1856
1857 dev->stats.tx_packets++;
1858 dev->stats.tx_bytes += skb->len;
1859
1860 re->skb = NULL;
1861 dev_kfree_skb_any(skb);
1862
1863 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1864 }
1865 }
1866
1867 sky2->tx_cons = idx;
1868 smp_mb();
1869
1870 /* Wake unless it's detached, and called e.g. from sky2_down() */
1871 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
1872 netif_wake_queue(dev);
1873 }
1874
1875 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1876 {
1877 /* Disable Force Sync bit and Enable Alloc bit */
1878 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1879 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1880
1881 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1882 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1883 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1884
1885 /* Reset the PCI FIFO of the async Tx queue */
1886 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1887 BMU_RST_SET | BMU_FIFO_RST);
1888
1889 /* Reset the Tx prefetch units */
1890 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1891 PREF_UNIT_RST_SET);
1892
1893 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1894 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1895 }
1896
1897 /* Network shutdown */
1898 static int sky2_down(struct net_device *dev)
1899 {
1900 struct sky2_port *sky2 = netdev_priv(dev);
1901 struct sky2_hw *hw = sky2->hw;
1902 unsigned port = sky2->port;
1903 u16 ctrl;
1904 u32 imask;
1905
1906 /* Never really got started! */
1907 if (!sky2->tx_le)
1908 return 0;
1909
1910 if (netif_msg_ifdown(sky2))
1911 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1912
1913 /* Force flow control off */
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1915
1916 /* Stop transmitter */
1917 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1918 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1919
1920 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1921 RB_RST_SET | RB_DIS_OP_MD);
1922
1923 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1924 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1925 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1926
1927 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1928
1929 /* Workaround shared GMAC reset */
1930 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1931 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1933
1934 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1935
1936 /* Force any delayed status interrrupt and NAPI */
1937 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1938 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1939 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1940 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1941
1942 sky2_rx_stop(sky2);
1943
1944 /* Disable port IRQ */
1945 imask = sky2_read32(hw, B0_IMSK);
1946 imask &= ~portirq_msk[port];
1947 sky2_write32(hw, B0_IMSK, imask);
1948 sky2_read32(hw, B0_IMSK);
1949
1950 synchronize_irq(hw->pdev->irq);
1951 napi_synchronize(&hw->napi);
1952
1953 spin_lock_bh(&sky2->phy_lock);
1954 sky2_phy_power_down(hw, port);
1955 spin_unlock_bh(&sky2->phy_lock);
1956
1957 sky2_tx_reset(hw, port);
1958
1959 /* Free any pending frames stuck in HW queue */
1960 sky2_tx_complete(sky2, sky2->tx_prod);
1961
1962 sky2_rx_clean(sky2);
1963
1964 sky2_free_buffers(sky2);
1965
1966 return 0;
1967 }
1968
1969 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1970 {
1971 if (hw->flags & SKY2_HW_FIBRE_PHY)
1972 return SPEED_1000;
1973
1974 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1975 if (aux & PHY_M_PS_SPEED_100)
1976 return SPEED_100;
1977 else
1978 return SPEED_10;
1979 }
1980
1981 switch (aux & PHY_M_PS_SPEED_MSK) {
1982 case PHY_M_PS_SPEED_1000:
1983 return SPEED_1000;
1984 case PHY_M_PS_SPEED_100:
1985 return SPEED_100;
1986 default:
1987 return SPEED_10;
1988 }
1989 }
1990
1991 static void sky2_link_up(struct sky2_port *sky2)
1992 {
1993 struct sky2_hw *hw = sky2->hw;
1994 unsigned port = sky2->port;
1995 u16 reg;
1996 static const char *fc_name[] = {
1997 [FC_NONE] = "none",
1998 [FC_TX] = "tx",
1999 [FC_RX] = "rx",
2000 [FC_BOTH] = "both",
2001 };
2002
2003 /* enable Rx/Tx */
2004 reg = gma_read16(hw, port, GM_GP_CTRL);
2005 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2006 gma_write16(hw, port, GM_GP_CTRL, reg);
2007
2008 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2009
2010 netif_carrier_on(sky2->netdev);
2011
2012 mod_timer(&hw->watchdog_timer, jiffies + 1);
2013
2014 /* Turn on link LED */
2015 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2016 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2017
2018 if (netif_msg_link(sky2))
2019 printk(KERN_INFO PFX
2020 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2021 sky2->netdev->name, sky2->speed,
2022 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2023 fc_name[sky2->flow_status]);
2024 }
2025
2026 static void sky2_link_down(struct sky2_port *sky2)
2027 {
2028 struct sky2_hw *hw = sky2->hw;
2029 unsigned port = sky2->port;
2030 u16 reg;
2031
2032 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2033
2034 reg = gma_read16(hw, port, GM_GP_CTRL);
2035 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2036 gma_write16(hw, port, GM_GP_CTRL, reg);
2037
2038 netif_carrier_off(sky2->netdev);
2039
2040 /* Turn off link LED */
2041 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2042
2043 if (netif_msg_link(sky2))
2044 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2045
2046 sky2_phy_init(hw, port);
2047 }
2048
2049 static enum flow_control sky2_flow(int rx, int tx)
2050 {
2051 if (rx)
2052 return tx ? FC_BOTH : FC_RX;
2053 else
2054 return tx ? FC_TX : FC_NONE;
2055 }
2056
2057 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2058 {
2059 struct sky2_hw *hw = sky2->hw;
2060 unsigned port = sky2->port;
2061 u16 advert, lpa;
2062
2063 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2064 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2065 if (lpa & PHY_M_AN_RF) {
2066 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2067 return -1;
2068 }
2069
2070 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2071 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2072 sky2->netdev->name);
2073 return -1;
2074 }
2075
2076 sky2->speed = sky2_phy_speed(hw, aux);
2077 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2078
2079 /* Since the pause result bits seem to in different positions on
2080 * different chips. look at registers.
2081 */
2082 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2083 /* Shift for bits in fiber PHY */
2084 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2085 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2086
2087 if (advert & ADVERTISE_1000XPAUSE)
2088 advert |= ADVERTISE_PAUSE_CAP;
2089 if (advert & ADVERTISE_1000XPSE_ASYM)
2090 advert |= ADVERTISE_PAUSE_ASYM;
2091 if (lpa & LPA_1000XPAUSE)
2092 lpa |= LPA_PAUSE_CAP;
2093 if (lpa & LPA_1000XPAUSE_ASYM)
2094 lpa |= LPA_PAUSE_ASYM;
2095 }
2096
2097 sky2->flow_status = FC_NONE;
2098 if (advert & ADVERTISE_PAUSE_CAP) {
2099 if (lpa & LPA_PAUSE_CAP)
2100 sky2->flow_status = FC_BOTH;
2101 else if (advert & ADVERTISE_PAUSE_ASYM)
2102 sky2->flow_status = FC_RX;
2103 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2104 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2105 sky2->flow_status = FC_TX;
2106 }
2107
2108 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2109 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2110 sky2->flow_status = FC_NONE;
2111
2112 if (sky2->flow_status & FC_TX)
2113 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2114 else
2115 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2116
2117 return 0;
2118 }
2119
2120 /* Interrupt from PHY */
2121 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2122 {
2123 struct net_device *dev = hw->dev[port];
2124 struct sky2_port *sky2 = netdev_priv(dev);
2125 u16 istatus, phystat;
2126
2127 if (!netif_running(dev))
2128 return;
2129
2130 spin_lock(&sky2->phy_lock);
2131 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2132 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2133
2134 if (netif_msg_intr(sky2))
2135 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2136 sky2->netdev->name, istatus, phystat);
2137
2138 if (istatus & PHY_M_IS_AN_COMPL) {
2139 if (sky2_autoneg_done(sky2, phystat) == 0)
2140 sky2_link_up(sky2);
2141 goto out;
2142 }
2143
2144 if (istatus & PHY_M_IS_LSP_CHANGE)
2145 sky2->speed = sky2_phy_speed(hw, phystat);
2146
2147 if (istatus & PHY_M_IS_DUP_CHANGE)
2148 sky2->duplex =
2149 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2150
2151 if (istatus & PHY_M_IS_LST_CHANGE) {
2152 if (phystat & PHY_M_PS_LINK_UP)
2153 sky2_link_up(sky2);
2154 else
2155 sky2_link_down(sky2);
2156 }
2157 out:
2158 spin_unlock(&sky2->phy_lock);
2159 }
2160
2161 /* Special quick link interrupt (Yukon-2 Optima only) */
2162 static void sky2_qlink_intr(struct sky2_hw *hw)
2163 {
2164 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2165 u32 imask;
2166 u16 phy;
2167
2168 /* disable irq */
2169 imask = sky2_read32(hw, B0_IMSK);
2170 imask &= ~Y2_IS_PHY_QLNK;
2171 sky2_write32(hw, B0_IMSK, imask);
2172
2173 /* reset PHY Link Detect */
2174 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2175 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2176 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2177 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2178
2179 sky2_link_up(sky2);
2180 }
2181
2182 /* Transmit timeout is only called if we are running, carrier is up
2183 * and tx queue is full (stopped).
2184 */
2185 static void sky2_tx_timeout(struct net_device *dev)
2186 {
2187 struct sky2_port *sky2 = netdev_priv(dev);
2188 struct sky2_hw *hw = sky2->hw;
2189
2190 if (netif_msg_timer(sky2))
2191 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2192
2193 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2194 dev->name, sky2->tx_cons, sky2->tx_prod,
2195 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2196 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2197
2198 /* can't restart safely under softirq */
2199 schedule_work(&hw->restart_work);
2200 }
2201
2202 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2203 {
2204 struct sky2_port *sky2 = netdev_priv(dev);
2205 struct sky2_hw *hw = sky2->hw;
2206 unsigned port = sky2->port;
2207 int err;
2208 u16 ctl, mode;
2209 u32 imask;
2210
2211 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2212 return -EINVAL;
2213
2214 if (new_mtu > ETH_DATA_LEN &&
2215 (hw->chip_id == CHIP_ID_YUKON_FE ||
2216 hw->chip_id == CHIP_ID_YUKON_FE_P))
2217 return -EINVAL;
2218
2219 if (!netif_running(dev)) {
2220 dev->mtu = new_mtu;
2221 return 0;
2222 }
2223
2224 imask = sky2_read32(hw, B0_IMSK);
2225 sky2_write32(hw, B0_IMSK, 0);
2226
2227 dev->trans_start = jiffies; /* prevent tx timeout */
2228 netif_stop_queue(dev);
2229 napi_disable(&hw->napi);
2230
2231 synchronize_irq(hw->pdev->irq);
2232
2233 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2234 sky2_set_tx_stfwd(hw, port);
2235
2236 ctl = gma_read16(hw, port, GM_GP_CTRL);
2237 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2238 sky2_rx_stop(sky2);
2239 sky2_rx_clean(sky2);
2240
2241 dev->mtu = new_mtu;
2242
2243 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2244 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2245
2246 if (dev->mtu > ETH_DATA_LEN)
2247 mode |= GM_SMOD_JUMBO_ENA;
2248
2249 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2250
2251 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2252
2253 err = sky2_rx_start(sky2);
2254 sky2_write32(hw, B0_IMSK, imask);
2255
2256 sky2_read32(hw, B0_Y2_SP_LISR);
2257 napi_enable(&hw->napi);
2258
2259 if (err)
2260 dev_close(dev);
2261 else {
2262 gma_write16(hw, port, GM_GP_CTRL, ctl);
2263
2264 netif_wake_queue(dev);
2265 }
2266
2267 return err;
2268 }
2269
2270 /* For small just reuse existing skb for next receive */
2271 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2272 const struct rx_ring_info *re,
2273 unsigned length)
2274 {
2275 struct sk_buff *skb;
2276
2277 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2278 if (likely(skb)) {
2279 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2280 length, PCI_DMA_FROMDEVICE);
2281 skb_copy_from_linear_data(re->skb, skb->data, length);
2282 skb->ip_summed = re->skb->ip_summed;
2283 skb->csum = re->skb->csum;
2284 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2285 length, PCI_DMA_FROMDEVICE);
2286 re->skb->ip_summed = CHECKSUM_NONE;
2287 skb_put(skb, length);
2288 }
2289 return skb;
2290 }
2291
2292 /* Adjust length of skb with fragments to match received data */
2293 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2294 unsigned int length)
2295 {
2296 int i, num_frags;
2297 unsigned int size;
2298
2299 /* put header into skb */
2300 size = min(length, hdr_space);
2301 skb->tail += size;
2302 skb->len += size;
2303 length -= size;
2304
2305 num_frags = skb_shinfo(skb)->nr_frags;
2306 for (i = 0; i < num_frags; i++) {
2307 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2308
2309 if (length == 0) {
2310 /* don't need this page */
2311 __free_page(frag->page);
2312 --skb_shinfo(skb)->nr_frags;
2313 } else {
2314 size = min(length, (unsigned) PAGE_SIZE);
2315
2316 frag->size = size;
2317 skb->data_len += size;
2318 skb->truesize += size;
2319 skb->len += size;
2320 length -= size;
2321 }
2322 }
2323 }
2324
2325 /* Normal packet - take skb from ring element and put in a new one */
2326 static struct sk_buff *receive_new(struct sky2_port *sky2,
2327 struct rx_ring_info *re,
2328 unsigned int length)
2329 {
2330 struct sk_buff *skb;
2331 struct rx_ring_info nre;
2332 unsigned hdr_space = sky2->rx_data_size;
2333
2334 nre.skb = sky2_rx_alloc(sky2);
2335 if (unlikely(!nre.skb))
2336 goto nobuf;
2337
2338 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2339 goto nomap;
2340
2341 skb = re->skb;
2342 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2343 prefetch(skb->data);
2344 *re = nre;
2345
2346 if (skb_shinfo(skb)->nr_frags)
2347 skb_put_frags(skb, hdr_space, length);
2348 else
2349 skb_put(skb, length);
2350 return skb;
2351
2352 nomap:
2353 dev_kfree_skb(nre.skb);
2354 nobuf:
2355 return NULL;
2356 }
2357
2358 /*
2359 * Receive one packet.
2360 * For larger packets, get new buffer.
2361 */
2362 static struct sk_buff *sky2_receive(struct net_device *dev,
2363 u16 length, u32 status)
2364 {
2365 struct sky2_port *sky2 = netdev_priv(dev);
2366 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2367 struct sk_buff *skb = NULL;
2368 u16 count = (status & GMR_FS_LEN) >> 16;
2369
2370 #ifdef SKY2_VLAN_TAG_USED
2371 /* Account for vlan tag */
2372 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2373 count -= VLAN_HLEN;
2374 #endif
2375
2376 if (unlikely(netif_msg_rx_status(sky2)))
2377 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2378 dev->name, sky2->rx_next, status, length);
2379
2380 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2381 prefetch(sky2->rx_ring + sky2->rx_next);
2382
2383 /* This chip has hardware problems that generates bogus status.
2384 * So do only marginal checking and expect higher level protocols
2385 * to handle crap frames.
2386 */
2387 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2388 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2389 length != count)
2390 goto okay;
2391
2392 if (status & GMR_FS_ANY_ERR)
2393 goto error;
2394
2395 if (!(status & GMR_FS_RX_OK))
2396 goto resubmit;
2397
2398 /* if length reported by DMA does not match PHY, packet was truncated */
2399 if (length != count)
2400 goto len_error;
2401
2402 okay:
2403 if (length < copybreak)
2404 skb = receive_copy(sky2, re, length);
2405 else
2406 skb = receive_new(sky2, re, length);
2407
2408 dev->stats.rx_dropped += (skb == NULL);
2409
2410 resubmit:
2411 sky2_rx_submit(sky2, re);
2412
2413 return skb;
2414
2415 len_error:
2416 /* Truncation of overlength packets
2417 causes PHY length to not match MAC length */
2418 ++dev->stats.rx_length_errors;
2419 if (netif_msg_rx_err(sky2) && net_ratelimit())
2420 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2421 dev->name, status, length);
2422 goto resubmit;
2423
2424 error:
2425 ++dev->stats.rx_errors;
2426 if (status & GMR_FS_RX_FF_OV) {
2427 dev->stats.rx_over_errors++;
2428 goto resubmit;
2429 }
2430
2431 if (netif_msg_rx_err(sky2) && net_ratelimit())
2432 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2433 dev->name, status, length);
2434
2435 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2436 dev->stats.rx_length_errors++;
2437 if (status & GMR_FS_FRAGMENT)
2438 dev->stats.rx_frame_errors++;
2439 if (status & GMR_FS_CRC_ERR)
2440 dev->stats.rx_crc_errors++;
2441
2442 goto resubmit;
2443 }
2444
2445 /* Transmit complete */
2446 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2447 {
2448 struct sky2_port *sky2 = netdev_priv(dev);
2449
2450 if (netif_running(dev))
2451 sky2_tx_complete(sky2, last);
2452 }
2453
2454 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2455 u32 status, struct sk_buff *skb)
2456 {
2457 #ifdef SKY2_VLAN_TAG_USED
2458 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2459 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2460 if (skb->ip_summed == CHECKSUM_NONE)
2461 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2462 else
2463 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2464 vlan_tag, skb);
2465 return;
2466 }
2467 #endif
2468 if (skb->ip_summed == CHECKSUM_NONE)
2469 netif_receive_skb(skb);
2470 else
2471 napi_gro_receive(&sky2->hw->napi, skb);
2472 }
2473
2474 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2475 unsigned packets, unsigned bytes)
2476 {
2477 if (packets) {
2478 struct net_device *dev = hw->dev[port];
2479
2480 dev->stats.rx_packets += packets;
2481 dev->stats.rx_bytes += bytes;
2482 dev->last_rx = jiffies;
2483 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2484 }
2485 }
2486
2487 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2488 {
2489 /* If this happens then driver assuming wrong format for chip type */
2490 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2491
2492 /* Both checksum counters are programmed to start at
2493 * the same offset, so unless there is a problem they
2494 * should match. This failure is an early indication that
2495 * hardware receive checksumming won't work.
2496 */
2497 if (likely((u16)(status >> 16) == (u16)status)) {
2498 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2499 skb->ip_summed = CHECKSUM_COMPLETE;
2500 skb->csum = le16_to_cpu(status);
2501 } else {
2502 dev_notice(&sky2->hw->pdev->dev,
2503 "%s: receive checksum problem (status = %#x)\n",
2504 sky2->netdev->name, status);
2505
2506 /* Disable checksum offload */
2507 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2508 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2509 BMU_DIS_RX_CHKSUM);
2510 }
2511 }
2512
2513 /* Process status response ring */
2514 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2515 {
2516 int work_done = 0;
2517 unsigned int total_bytes[2] = { 0 };
2518 unsigned int total_packets[2] = { 0 };
2519
2520 rmb();
2521 do {
2522 struct sky2_port *sky2;
2523 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2524 unsigned port;
2525 struct net_device *dev;
2526 struct sk_buff *skb;
2527 u32 status;
2528 u16 length;
2529 u8 opcode = le->opcode;
2530
2531 if (!(opcode & HW_OWNER))
2532 break;
2533
2534 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2535
2536 port = le->css & CSS_LINK_BIT;
2537 dev = hw->dev[port];
2538 sky2 = netdev_priv(dev);
2539 length = le16_to_cpu(le->length);
2540 status = le32_to_cpu(le->status);
2541
2542 le->opcode = 0;
2543 switch (opcode & ~HW_OWNER) {
2544 case OP_RXSTAT:
2545 total_packets[port]++;
2546 total_bytes[port] += length;
2547
2548 skb = sky2_receive(dev, length, status);
2549 if (!skb)
2550 break;
2551
2552 /* This chip reports checksum status differently */
2553 if (hw->flags & SKY2_HW_NEW_LE) {
2554 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2555 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2556 (le->css & CSS_TCPUDPCSOK))
2557 skb->ip_summed = CHECKSUM_UNNECESSARY;
2558 else
2559 skb->ip_summed = CHECKSUM_NONE;
2560 }
2561
2562 skb->protocol = eth_type_trans(skb, dev);
2563
2564 sky2_skb_rx(sky2, status, skb);
2565
2566 /* Stop after net poll weight */
2567 if (++work_done >= to_do)
2568 goto exit_loop;
2569 break;
2570
2571 #ifdef SKY2_VLAN_TAG_USED
2572 case OP_RXVLAN:
2573 sky2->rx_tag = length;
2574 break;
2575
2576 case OP_RXCHKSVLAN:
2577 sky2->rx_tag = length;
2578 /* fall through */
2579 #endif
2580 case OP_RXCHKS:
2581 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2582 sky2_rx_checksum(sky2, status);
2583 break;
2584
2585 case OP_TXINDEXLE:
2586 /* TX index reports status for both ports */
2587 sky2_tx_done(hw->dev[0], status & 0xfff);
2588 if (hw->dev[1])
2589 sky2_tx_done(hw->dev[1],
2590 ((status >> 24) & 0xff)
2591 | (u16)(length & 0xf) << 8);
2592 break;
2593
2594 default:
2595 if (net_ratelimit())
2596 printk(KERN_WARNING PFX
2597 "unknown status opcode 0x%x\n", opcode);
2598 }
2599 } while (hw->st_idx != idx);
2600
2601 /* Fully processed status ring so clear irq */
2602 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2603
2604 exit_loop:
2605 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2606 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2607
2608 return work_done;
2609 }
2610
2611 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2612 {
2613 struct net_device *dev = hw->dev[port];
2614
2615 if (net_ratelimit())
2616 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2617 dev->name, status);
2618
2619 if (status & Y2_IS_PAR_RD1) {
2620 if (net_ratelimit())
2621 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2622 dev->name);
2623 /* Clear IRQ */
2624 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2625 }
2626
2627 if (status & Y2_IS_PAR_WR1) {
2628 if (net_ratelimit())
2629 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2630 dev->name);
2631
2632 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2633 }
2634
2635 if (status & Y2_IS_PAR_MAC1) {
2636 if (net_ratelimit())
2637 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2638 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2639 }
2640
2641 if (status & Y2_IS_PAR_RX1) {
2642 if (net_ratelimit())
2643 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2644 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2645 }
2646
2647 if (status & Y2_IS_TCP_TXA1) {
2648 if (net_ratelimit())
2649 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2650 dev->name);
2651 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2652 }
2653 }
2654
2655 static void sky2_hw_intr(struct sky2_hw *hw)
2656 {
2657 struct pci_dev *pdev = hw->pdev;
2658 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2659 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2660
2661 status &= hwmsk;
2662
2663 if (status & Y2_IS_TIST_OV)
2664 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2665
2666 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2667 u16 pci_err;
2668
2669 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2670 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2671 if (net_ratelimit())
2672 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2673 pci_err);
2674
2675 sky2_pci_write16(hw, PCI_STATUS,
2676 pci_err | PCI_STATUS_ERROR_BITS);
2677 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2678 }
2679
2680 if (status & Y2_IS_PCI_EXP) {
2681 /* PCI-Express uncorrectable Error occurred */
2682 u32 err;
2683
2684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2685 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2686 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2687 0xfffffffful);
2688 if (net_ratelimit())
2689 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2690
2691 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2692 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2693 }
2694
2695 if (status & Y2_HWE_L1_MASK)
2696 sky2_hw_error(hw, 0, status);
2697 status >>= 8;
2698 if (status & Y2_HWE_L1_MASK)
2699 sky2_hw_error(hw, 1, status);
2700 }
2701
2702 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2703 {
2704 struct net_device *dev = hw->dev[port];
2705 struct sky2_port *sky2 = netdev_priv(dev);
2706 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2707
2708 if (netif_msg_intr(sky2))
2709 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2710 dev->name, status);
2711
2712 if (status & GM_IS_RX_CO_OV)
2713 gma_read16(hw, port, GM_RX_IRQ_SRC);
2714
2715 if (status & GM_IS_TX_CO_OV)
2716 gma_read16(hw, port, GM_TX_IRQ_SRC);
2717
2718 if (status & GM_IS_RX_FF_OR) {
2719 ++dev->stats.rx_fifo_errors;
2720 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2721 }
2722
2723 if (status & GM_IS_TX_FF_UR) {
2724 ++dev->stats.tx_fifo_errors;
2725 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2726 }
2727 }
2728
2729 /* This should never happen it is a bug. */
2730 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2731 {
2732 struct net_device *dev = hw->dev[port];
2733 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2734
2735 dev_err(&hw->pdev->dev, PFX
2736 "%s: descriptor error q=%#x get=%u put=%u\n",
2737 dev->name, (unsigned) q, (unsigned) idx,
2738 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2739
2740 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2741 }
2742
2743 static int sky2_rx_hung(struct net_device *dev)
2744 {
2745 struct sky2_port *sky2 = netdev_priv(dev);
2746 struct sky2_hw *hw = sky2->hw;
2747 unsigned port = sky2->port;
2748 unsigned rxq = rxqaddr[port];
2749 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2750 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2751 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2752 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2753
2754 /* If idle and MAC or PCI is stuck */
2755 if (sky2->check.last == dev->last_rx &&
2756 ((mac_rp == sky2->check.mac_rp &&
2757 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2758 /* Check if the PCI RX hang */
2759 (fifo_rp == sky2->check.fifo_rp &&
2760 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2761 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2762 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2763 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2764 return 1;
2765 } else {
2766 sky2->check.last = dev->last_rx;
2767 sky2->check.mac_rp = mac_rp;
2768 sky2->check.mac_lev = mac_lev;
2769 sky2->check.fifo_rp = fifo_rp;
2770 sky2->check.fifo_lev = fifo_lev;
2771 return 0;
2772 }
2773 }
2774
2775 static void sky2_watchdog(unsigned long arg)
2776 {
2777 struct sky2_hw *hw = (struct sky2_hw *) arg;
2778
2779 /* Check for lost IRQ once a second */
2780 if (sky2_read32(hw, B0_ISRC)) {
2781 napi_schedule(&hw->napi);
2782 } else {
2783 int i, active = 0;
2784
2785 for (i = 0; i < hw->ports; i++) {
2786 struct net_device *dev = hw->dev[i];
2787 if (!netif_running(dev))
2788 continue;
2789 ++active;
2790
2791 /* For chips with Rx FIFO, check if stuck */
2792 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2793 sky2_rx_hung(dev)) {
2794 pr_info(PFX "%s: receiver hang detected\n",
2795 dev->name);
2796 schedule_work(&hw->restart_work);
2797 return;
2798 }
2799 }
2800
2801 if (active == 0)
2802 return;
2803 }
2804
2805 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2806 }
2807
2808 /* Hardware/software error handling */
2809 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2810 {
2811 if (net_ratelimit())
2812 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2813
2814 if (status & Y2_IS_HW_ERR)
2815 sky2_hw_intr(hw);
2816
2817 if (status & Y2_IS_IRQ_MAC1)
2818 sky2_mac_intr(hw, 0);
2819
2820 if (status & Y2_IS_IRQ_MAC2)
2821 sky2_mac_intr(hw, 1);
2822
2823 if (status & Y2_IS_CHK_RX1)
2824 sky2_le_error(hw, 0, Q_R1);
2825
2826 if (status & Y2_IS_CHK_RX2)
2827 sky2_le_error(hw, 1, Q_R2);
2828
2829 if (status & Y2_IS_CHK_TXA1)
2830 sky2_le_error(hw, 0, Q_XA1);
2831
2832 if (status & Y2_IS_CHK_TXA2)
2833 sky2_le_error(hw, 1, Q_XA2);
2834 }
2835
2836 static int sky2_poll(struct napi_struct *napi, int work_limit)
2837 {
2838 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2839 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2840 int work_done = 0;
2841 u16 idx;
2842
2843 if (unlikely(status & Y2_IS_ERROR))
2844 sky2_err_intr(hw, status);
2845
2846 if (status & Y2_IS_IRQ_PHY1)
2847 sky2_phy_intr(hw, 0);
2848
2849 if (status & Y2_IS_IRQ_PHY2)
2850 sky2_phy_intr(hw, 1);
2851
2852 if (status & Y2_IS_PHY_QLNK)
2853 sky2_qlink_intr(hw);
2854
2855 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2856 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2857
2858 if (work_done >= work_limit)
2859 goto done;
2860 }
2861
2862 napi_complete(napi);
2863 sky2_read32(hw, B0_Y2_SP_LISR);
2864 done:
2865
2866 return work_done;
2867 }
2868
2869 static irqreturn_t sky2_intr(int irq, void *dev_id)
2870 {
2871 struct sky2_hw *hw = dev_id;
2872 u32 status;
2873
2874 /* Reading this mask interrupts as side effect */
2875 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2876 if (status == 0 || status == ~0)
2877 return IRQ_NONE;
2878
2879 prefetch(&hw->st_le[hw->st_idx]);
2880
2881 napi_schedule(&hw->napi);
2882
2883 return IRQ_HANDLED;
2884 }
2885
2886 #ifdef CONFIG_NET_POLL_CONTROLLER
2887 static void sky2_netpoll(struct net_device *dev)
2888 {
2889 struct sky2_port *sky2 = netdev_priv(dev);
2890
2891 napi_schedule(&sky2->hw->napi);
2892 }
2893 #endif
2894
2895 /* Chip internal frequency for clock calculations */
2896 static u32 sky2_mhz(const struct sky2_hw *hw)
2897 {
2898 switch (hw->chip_id) {
2899 case CHIP_ID_YUKON_EC:
2900 case CHIP_ID_YUKON_EC_U:
2901 case CHIP_ID_YUKON_EX:
2902 case CHIP_ID_YUKON_SUPR:
2903 case CHIP_ID_YUKON_UL_2:
2904 case CHIP_ID_YUKON_OPT:
2905 return 125;
2906
2907 case CHIP_ID_YUKON_FE:
2908 return 100;
2909
2910 case CHIP_ID_YUKON_FE_P:
2911 return 50;
2912
2913 case CHIP_ID_YUKON_XL:
2914 return 156;
2915
2916 default:
2917 BUG();
2918 }
2919 }
2920
2921 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2922 {
2923 return sky2_mhz(hw) * us;
2924 }
2925
2926 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2927 {
2928 return clk / sky2_mhz(hw);
2929 }
2930
2931
2932 static int __devinit sky2_init(struct sky2_hw *hw)
2933 {
2934 u8 t8;
2935
2936 /* Enable all clocks and check for bad PCI access */
2937 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2938
2939 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2940
2941 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2942 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2943
2944 switch(hw->chip_id) {
2945 case CHIP_ID_YUKON_XL:
2946 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2947 break;
2948
2949 case CHIP_ID_YUKON_EC_U:
2950 hw->flags = SKY2_HW_GIGABIT
2951 | SKY2_HW_NEWER_PHY
2952 | SKY2_HW_ADV_POWER_CTL;
2953 break;
2954
2955 case CHIP_ID_YUKON_EX:
2956 hw->flags = SKY2_HW_GIGABIT
2957 | SKY2_HW_NEWER_PHY
2958 | SKY2_HW_NEW_LE
2959 | SKY2_HW_ADV_POWER_CTL;
2960
2961 /* New transmit checksum */
2962 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2963 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2964 break;
2965
2966 case CHIP_ID_YUKON_EC:
2967 /* This rev is really old, and requires untested workarounds */
2968 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2969 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2970 return -EOPNOTSUPP;
2971 }
2972 hw->flags = SKY2_HW_GIGABIT;
2973 break;
2974
2975 case CHIP_ID_YUKON_FE:
2976 break;
2977
2978 case CHIP_ID_YUKON_FE_P:
2979 hw->flags = SKY2_HW_NEWER_PHY
2980 | SKY2_HW_NEW_LE
2981 | SKY2_HW_AUTO_TX_SUM
2982 | SKY2_HW_ADV_POWER_CTL;
2983 break;
2984
2985 case CHIP_ID_YUKON_SUPR:
2986 hw->flags = SKY2_HW_GIGABIT
2987 | SKY2_HW_NEWER_PHY
2988 | SKY2_HW_NEW_LE
2989 | SKY2_HW_AUTO_TX_SUM
2990 | SKY2_HW_ADV_POWER_CTL;
2991 break;
2992
2993 case CHIP_ID_YUKON_UL_2:
2994 hw->flags = SKY2_HW_GIGABIT
2995 | SKY2_HW_ADV_POWER_CTL;
2996 break;
2997
2998 case CHIP_ID_YUKON_OPT:
2999 hw->flags = SKY2_HW_GIGABIT
3000 | SKY2_HW_NEW_LE
3001 | SKY2_HW_ADV_POWER_CTL;
3002 break;
3003
3004 default:
3005 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3006 hw->chip_id);
3007 return -EOPNOTSUPP;
3008 }
3009
3010 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3011 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3012 hw->flags |= SKY2_HW_FIBRE_PHY;
3013
3014 hw->ports = 1;
3015 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3016 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3017 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3018 ++hw->ports;
3019 }
3020
3021 if (sky2_read8(hw, B2_E_0))
3022 hw->flags |= SKY2_HW_RAM_BUFFER;
3023
3024 return 0;
3025 }
3026
3027 static void sky2_reset(struct sky2_hw *hw)
3028 {
3029 struct pci_dev *pdev = hw->pdev;
3030 u16 status;
3031 int i, cap;
3032 u32 hwe_mask = Y2_HWE_ALL_MASK;
3033
3034 /* disable ASF */
3035 if (hw->chip_id == CHIP_ID_YUKON_EX
3036 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3037 sky2_write32(hw, CPU_WDOG, 0);
3038 status = sky2_read16(hw, HCU_CCSR);
3039 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3040 HCU_CCSR_UC_STATE_MSK);
3041 /*
3042 * CPU clock divider shouldn't be used because
3043 * - ASF firmware may malfunction
3044 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3045 */
3046 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3047 sky2_write16(hw, HCU_CCSR, status);
3048 sky2_write32(hw, CPU_WDOG, 0);
3049 } else
3050 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3051 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3052
3053 /* do a SW reset */
3054 sky2_write8(hw, B0_CTST, CS_RST_SET);
3055 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3056
3057 /* allow writes to PCI config */
3058 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3059
3060 /* clear PCI errors, if any */
3061 status = sky2_pci_read16(hw, PCI_STATUS);
3062 status |= PCI_STATUS_ERROR_BITS;
3063 sky2_pci_write16(hw, PCI_STATUS, status);
3064
3065 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3066
3067 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3068 if (cap) {
3069 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3070 0xfffffffful);
3071
3072 /* If error bit is stuck on ignore it */
3073 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3074 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3075 else
3076 hwe_mask |= Y2_IS_PCI_EXP;
3077 }
3078
3079 sky2_power_on(hw);
3080 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3081
3082 for (i = 0; i < hw->ports; i++) {
3083 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3084 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3085
3086 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3087 hw->chip_id == CHIP_ID_YUKON_SUPR)
3088 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3089 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3090 | GMC_BYP_RETR_ON);
3091
3092 }
3093
3094 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3095 /* enable MACSec clock gating */
3096 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3097 }
3098
3099 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3100 u16 reg;
3101 u32 msk;
3102
3103 if (hw->chip_rev == 0) {
3104 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3105 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3106
3107 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3108 reg = 10;
3109 } else {
3110 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3111 reg = 3;
3112 }
3113
3114 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3115
3116 /* reset PHY Link Detect */
3117 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3118 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3119 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3120 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3121
3122
3123 /* enable PHY Quick Link */
3124 msk = sky2_read32(hw, B0_IMSK);
3125 msk |= Y2_IS_PHY_QLNK;
3126 sky2_write32(hw, B0_IMSK, msk);
3127
3128 /* check if PSMv2 was running before */
3129 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3130 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3131 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3132 /* restore the PCIe Link Control register */
3133 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3134 }
3135 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3136
3137 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3138 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3139 }
3140
3141 /* Clear I2C IRQ noise */
3142 sky2_write32(hw, B2_I2C_IRQ, 1);
3143
3144 /* turn off hardware timer (unused) */
3145 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3146 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3147
3148 /* Turn off descriptor polling */
3149 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3150
3151 /* Turn off receive timestamp */
3152 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3153 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3154
3155 /* enable the Tx Arbiters */
3156 for (i = 0; i < hw->ports; i++)
3157 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3158
3159 /* Initialize ram interface */
3160 for (i = 0; i < hw->ports; i++) {
3161 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3162
3163 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3164 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3165 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3166 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3167 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3168 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3169 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3170 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3171 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3172 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3173 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3174 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3175 }
3176
3177 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3178
3179 for (i = 0; i < hw->ports; i++)
3180 sky2_gmac_reset(hw, i);
3181
3182 memset(hw->st_le, 0, STATUS_LE_BYTES);
3183 hw->st_idx = 0;
3184
3185 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3186 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3187
3188 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3189 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3190
3191 /* Set the list last index */
3192 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3193
3194 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3195 sky2_write8(hw, STAT_FIFO_WM, 16);
3196
3197 /* set Status-FIFO ISR watermark */
3198 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3199 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3200 else
3201 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3202
3203 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3204 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3205 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3206
3207 /* enable status unit */
3208 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3209
3210 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3211 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3212 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3213 }
3214
3215 /* Take device down (offline).
3216 * Equivalent to doing dev_stop() but this does not
3217 * inform upper layers of the transistion.
3218 */
3219 static void sky2_detach(struct net_device *dev)
3220 {
3221 if (netif_running(dev)) {
3222 netif_tx_lock(dev);
3223 netif_device_detach(dev); /* stop txq */
3224 netif_tx_unlock(dev);
3225 sky2_down(dev);
3226 }
3227 }
3228
3229 /* Bring device back after doing sky2_detach */
3230 static int sky2_reattach(struct net_device *dev)
3231 {
3232 int err = 0;
3233
3234 if (netif_running(dev)) {
3235 err = sky2_up(dev);
3236 if (err) {
3237 printk(KERN_INFO PFX "%s: could not restart %d\n",
3238 dev->name, err);
3239 dev_close(dev);
3240 } else {
3241 netif_device_attach(dev);
3242 sky2_set_multicast(dev);
3243 }
3244 }
3245
3246 return err;
3247 }
3248
3249 static void sky2_restart(struct work_struct *work)
3250 {
3251 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3252 int i;
3253
3254 rtnl_lock();
3255 for (i = 0; i < hw->ports; i++)
3256 sky2_detach(hw->dev[i]);
3257
3258 napi_disable(&hw->napi);
3259 sky2_write32(hw, B0_IMSK, 0);
3260 sky2_reset(hw);
3261 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3262 napi_enable(&hw->napi);
3263
3264 for (i = 0; i < hw->ports; i++)
3265 sky2_reattach(hw->dev[i]);
3266
3267 rtnl_unlock();
3268 }
3269
3270 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3271 {
3272 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3273 }
3274
3275 static void sky2_hw_set_wol(struct sky2_hw *hw)
3276 {
3277 int wol = 0;
3278 int i;
3279
3280 for (i = 0; i < hw->ports; i++) {
3281 struct net_device *dev = hw->dev[i];
3282 struct sky2_port *sky2 = netdev_priv(dev);
3283
3284 if (sky2->wol)
3285 wol = 1;
3286 }
3287
3288 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3289 hw->chip_id == CHIP_ID_YUKON_EX ||
3290 hw->chip_id == CHIP_ID_YUKON_FE_P)
3291 sky2_write32(hw, B0_CTST, wol ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3292
3293 device_set_wakeup_enable(&hw->pdev->dev, wol);
3294 }
3295
3296 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3297 {
3298 const struct sky2_port *sky2 = netdev_priv(dev);
3299
3300 wol->supported = sky2_wol_supported(sky2->hw);
3301 wol->wolopts = sky2->wol;
3302 }
3303
3304 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3305 {
3306 struct sky2_port *sky2 = netdev_priv(dev);
3307 struct sky2_hw *hw = sky2->hw;
3308
3309 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3310 !device_can_wakeup(&hw->pdev->dev))
3311 return -EOPNOTSUPP;
3312
3313 sky2->wol = wol->wolopts;
3314
3315 sky2_hw_set_wol(hw);
3316
3317 if (!netif_running(dev))
3318 sky2_wol_init(sky2);
3319 return 0;
3320 }
3321
3322 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3323 {
3324 if (sky2_is_copper(hw)) {
3325 u32 modes = SUPPORTED_10baseT_Half
3326 | SUPPORTED_10baseT_Full
3327 | SUPPORTED_100baseT_Half
3328 | SUPPORTED_100baseT_Full
3329 | SUPPORTED_Autoneg | SUPPORTED_TP;
3330
3331 if (hw->flags & SKY2_HW_GIGABIT)
3332 modes |= SUPPORTED_1000baseT_Half
3333 | SUPPORTED_1000baseT_Full;
3334 return modes;
3335 } else
3336 return SUPPORTED_1000baseT_Half
3337 | SUPPORTED_1000baseT_Full
3338 | SUPPORTED_Autoneg
3339 | SUPPORTED_FIBRE;
3340 }
3341
3342 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3343 {
3344 struct sky2_port *sky2 = netdev_priv(dev);
3345 struct sky2_hw *hw = sky2->hw;
3346
3347 ecmd->transceiver = XCVR_INTERNAL;
3348 ecmd->supported = sky2_supported_modes(hw);
3349 ecmd->phy_address = PHY_ADDR_MARV;
3350 if (sky2_is_copper(hw)) {
3351 ecmd->port = PORT_TP;
3352 ecmd->speed = sky2->speed;
3353 } else {
3354 ecmd->speed = SPEED_1000;
3355 ecmd->port = PORT_FIBRE;
3356 }
3357
3358 ecmd->advertising = sky2->advertising;
3359 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3360 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3361 ecmd->duplex = sky2->duplex;
3362 return 0;
3363 }
3364
3365 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3366 {
3367 struct sky2_port *sky2 = netdev_priv(dev);
3368 const struct sky2_hw *hw = sky2->hw;
3369 u32 supported = sky2_supported_modes(hw);
3370
3371 if (ecmd->autoneg == AUTONEG_ENABLE) {
3372 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3373 ecmd->advertising = supported;
3374 sky2->duplex = -1;
3375 sky2->speed = -1;
3376 } else {
3377 u32 setting;
3378
3379 switch (ecmd->speed) {
3380 case SPEED_1000:
3381 if (ecmd->duplex == DUPLEX_FULL)
3382 setting = SUPPORTED_1000baseT_Full;
3383 else if (ecmd->duplex == DUPLEX_HALF)
3384 setting = SUPPORTED_1000baseT_Half;
3385 else
3386 return -EINVAL;
3387 break;
3388 case SPEED_100:
3389 if (ecmd->duplex == DUPLEX_FULL)
3390 setting = SUPPORTED_100baseT_Full;
3391 else if (ecmd->duplex == DUPLEX_HALF)
3392 setting = SUPPORTED_100baseT_Half;
3393 else
3394 return -EINVAL;
3395 break;
3396
3397 case SPEED_10:
3398 if (ecmd->duplex == DUPLEX_FULL)
3399 setting = SUPPORTED_10baseT_Full;
3400 else if (ecmd->duplex == DUPLEX_HALF)
3401 setting = SUPPORTED_10baseT_Half;
3402 else
3403 return -EINVAL;
3404 break;
3405 default:
3406 return -EINVAL;
3407 }
3408
3409 if ((setting & supported) == 0)
3410 return -EINVAL;
3411
3412 sky2->speed = ecmd->speed;
3413 sky2->duplex = ecmd->duplex;
3414 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3415 }
3416
3417 sky2->advertising = ecmd->advertising;
3418
3419 if (netif_running(dev)) {
3420 sky2_phy_reinit(sky2);
3421 sky2_set_multicast(dev);
3422 }
3423
3424 return 0;
3425 }
3426
3427 static void sky2_get_drvinfo(struct net_device *dev,
3428 struct ethtool_drvinfo *info)
3429 {
3430 struct sky2_port *sky2 = netdev_priv(dev);
3431
3432 strcpy(info->driver, DRV_NAME);
3433 strcpy(info->version, DRV_VERSION);
3434 strcpy(info->fw_version, "N/A");
3435 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3436 }
3437
3438 static const struct sky2_stat {
3439 char name[ETH_GSTRING_LEN];
3440 u16 offset;
3441 } sky2_stats[] = {
3442 { "tx_bytes", GM_TXO_OK_HI },
3443 { "rx_bytes", GM_RXO_OK_HI },
3444 { "tx_broadcast", GM_TXF_BC_OK },
3445 { "rx_broadcast", GM_RXF_BC_OK },
3446 { "tx_multicast", GM_TXF_MC_OK },
3447 { "rx_multicast", GM_RXF_MC_OK },
3448 { "tx_unicast", GM_TXF_UC_OK },
3449 { "rx_unicast", GM_RXF_UC_OK },
3450 { "tx_mac_pause", GM_TXF_MPAUSE },
3451 { "rx_mac_pause", GM_RXF_MPAUSE },
3452 { "collisions", GM_TXF_COL },
3453 { "late_collision",GM_TXF_LAT_COL },
3454 { "aborted", GM_TXF_ABO_COL },
3455 { "single_collisions", GM_TXF_SNG_COL },
3456 { "multi_collisions", GM_TXF_MUL_COL },
3457
3458 { "rx_short", GM_RXF_SHT },
3459 { "rx_runt", GM_RXE_FRAG },
3460 { "rx_64_byte_packets", GM_RXF_64B },
3461 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3462 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3463 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3464 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3465 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3466 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3467 { "rx_too_long", GM_RXF_LNG_ERR },
3468 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3469 { "rx_jabber", GM_RXF_JAB_PKT },
3470 { "rx_fcs_error", GM_RXF_FCS_ERR },
3471
3472 { "tx_64_byte_packets", GM_TXF_64B },
3473 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3474 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3475 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3476 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3477 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3478 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3479 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3480 };
3481
3482 static u32 sky2_get_rx_csum(struct net_device *dev)
3483 {
3484 struct sky2_port *sky2 = netdev_priv(dev);
3485
3486 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3487 }
3488
3489 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3490 {
3491 struct sky2_port *sky2 = netdev_priv(dev);
3492
3493 if (data)
3494 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3495 else
3496 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3497
3498 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3499 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3500
3501 return 0;
3502 }
3503
3504 static u32 sky2_get_msglevel(struct net_device *netdev)
3505 {
3506 struct sky2_port *sky2 = netdev_priv(netdev);
3507 return sky2->msg_enable;
3508 }
3509
3510 static int sky2_nway_reset(struct net_device *dev)
3511 {
3512 struct sky2_port *sky2 = netdev_priv(dev);
3513
3514 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3515 return -EINVAL;
3516
3517 sky2_phy_reinit(sky2);
3518 sky2_set_multicast(dev);
3519
3520 return 0;
3521 }
3522
3523 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3524 {
3525 struct sky2_hw *hw = sky2->hw;
3526 unsigned port = sky2->port;
3527 int i;
3528
3529 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3530 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3531 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3532 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3533
3534 for (i = 2; i < count; i++)
3535 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3536 }
3537
3538 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3539 {
3540 struct sky2_port *sky2 = netdev_priv(netdev);
3541 sky2->msg_enable = value;
3542 }
3543
3544 static int sky2_get_sset_count(struct net_device *dev, int sset)
3545 {
3546 switch (sset) {
3547 case ETH_SS_STATS:
3548 return ARRAY_SIZE(sky2_stats);
3549 default:
3550 return -EOPNOTSUPP;
3551 }
3552 }
3553
3554 static void sky2_get_ethtool_stats(struct net_device *dev,
3555 struct ethtool_stats *stats, u64 * data)
3556 {
3557 struct sky2_port *sky2 = netdev_priv(dev);
3558
3559 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3560 }
3561
3562 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3563 {
3564 int i;
3565
3566 switch (stringset) {
3567 case ETH_SS_STATS:
3568 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3569 memcpy(data + i * ETH_GSTRING_LEN,
3570 sky2_stats[i].name, ETH_GSTRING_LEN);
3571 break;
3572 }
3573 }
3574
3575 static int sky2_set_mac_address(struct net_device *dev, void *p)
3576 {
3577 struct sky2_port *sky2 = netdev_priv(dev);
3578 struct sky2_hw *hw = sky2->hw;
3579 unsigned port = sky2->port;
3580 const struct sockaddr *addr = p;
3581
3582 if (!is_valid_ether_addr(addr->sa_data))
3583 return -EADDRNOTAVAIL;
3584
3585 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3586 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3587 dev->dev_addr, ETH_ALEN);
3588 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3589 dev->dev_addr, ETH_ALEN);
3590
3591 /* virtual address for data */
3592 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3593
3594 /* physical address: used for pause frames */
3595 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3596
3597 return 0;
3598 }
3599
3600 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3601 {
3602 u32 bit;
3603
3604 bit = ether_crc(ETH_ALEN, addr) & 63;
3605 filter[bit >> 3] |= 1 << (bit & 7);
3606 }
3607
3608 static void sky2_set_multicast(struct net_device *dev)
3609 {
3610 struct sky2_port *sky2 = netdev_priv(dev);
3611 struct sky2_hw *hw = sky2->hw;
3612 unsigned port = sky2->port;
3613 struct dev_mc_list *list = dev->mc_list;
3614 u16 reg;
3615 u8 filter[8];
3616 int rx_pause;
3617 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3618
3619 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3620 memset(filter, 0, sizeof(filter));
3621
3622 reg = gma_read16(hw, port, GM_RX_CTRL);
3623 reg |= GM_RXCR_UCF_ENA;
3624
3625 if (dev->flags & IFF_PROMISC) /* promiscuous */
3626 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3627 else if (dev->flags & IFF_ALLMULTI)
3628 memset(filter, 0xff, sizeof(filter));
3629 else if (netdev_mc_empty(dev) && !rx_pause)
3630 reg &= ~GM_RXCR_MCF_ENA;
3631 else {
3632 int i;
3633 reg |= GM_RXCR_MCF_ENA;
3634
3635 if (rx_pause)
3636 sky2_add_filter(filter, pause_mc_addr);
3637
3638 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
3639 sky2_add_filter(filter, list->dmi_addr);
3640 }
3641
3642 gma_write16(hw, port, GM_MC_ADDR_H1,
3643 (u16) filter[0] | ((u16) filter[1] << 8));
3644 gma_write16(hw, port, GM_MC_ADDR_H2,
3645 (u16) filter[2] | ((u16) filter[3] << 8));
3646 gma_write16(hw, port, GM_MC_ADDR_H3,
3647 (u16) filter[4] | ((u16) filter[5] << 8));
3648 gma_write16(hw, port, GM_MC_ADDR_H4,
3649 (u16) filter[6] | ((u16) filter[7] << 8));
3650
3651 gma_write16(hw, port, GM_RX_CTRL, reg);
3652 }
3653
3654 /* Can have one global because blinking is controlled by
3655 * ethtool and that is always under RTNL mutex
3656 */
3657 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3658 {
3659 struct sky2_hw *hw = sky2->hw;
3660 unsigned port = sky2->port;
3661
3662 spin_lock_bh(&sky2->phy_lock);
3663 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3664 hw->chip_id == CHIP_ID_YUKON_EX ||
3665 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3666 u16 pg;
3667 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3668 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3669
3670 switch (mode) {
3671 case MO_LED_OFF:
3672 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3673 PHY_M_LEDC_LOS_CTRL(8) |
3674 PHY_M_LEDC_INIT_CTRL(8) |
3675 PHY_M_LEDC_STA1_CTRL(8) |
3676 PHY_M_LEDC_STA0_CTRL(8));
3677 break;
3678 case MO_LED_ON:
3679 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3680 PHY_M_LEDC_LOS_CTRL(9) |
3681 PHY_M_LEDC_INIT_CTRL(9) |
3682 PHY_M_LEDC_STA1_CTRL(9) |
3683 PHY_M_LEDC_STA0_CTRL(9));
3684 break;
3685 case MO_LED_BLINK:
3686 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3687 PHY_M_LEDC_LOS_CTRL(0xa) |
3688 PHY_M_LEDC_INIT_CTRL(0xa) |
3689 PHY_M_LEDC_STA1_CTRL(0xa) |
3690 PHY_M_LEDC_STA0_CTRL(0xa));
3691 break;
3692 case MO_LED_NORM:
3693 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3694 PHY_M_LEDC_LOS_CTRL(1) |
3695 PHY_M_LEDC_INIT_CTRL(8) |
3696 PHY_M_LEDC_STA1_CTRL(7) |
3697 PHY_M_LEDC_STA0_CTRL(7));
3698 }
3699
3700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3701 } else
3702 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3703 PHY_M_LED_MO_DUP(mode) |
3704 PHY_M_LED_MO_10(mode) |
3705 PHY_M_LED_MO_100(mode) |
3706 PHY_M_LED_MO_1000(mode) |
3707 PHY_M_LED_MO_RX(mode) |
3708 PHY_M_LED_MO_TX(mode));
3709
3710 spin_unlock_bh(&sky2->phy_lock);
3711 }
3712
3713 /* blink LED's for finding board */
3714 static int sky2_phys_id(struct net_device *dev, u32 data)
3715 {
3716 struct sky2_port *sky2 = netdev_priv(dev);
3717 unsigned int i;
3718
3719 if (data == 0)
3720 data = UINT_MAX;
3721
3722 for (i = 0; i < data; i++) {
3723 sky2_led(sky2, MO_LED_ON);
3724 if (msleep_interruptible(500))
3725 break;
3726 sky2_led(sky2, MO_LED_OFF);
3727 if (msleep_interruptible(500))
3728 break;
3729 }
3730 sky2_led(sky2, MO_LED_NORM);
3731
3732 return 0;
3733 }
3734
3735 static void sky2_get_pauseparam(struct net_device *dev,
3736 struct ethtool_pauseparam *ecmd)
3737 {
3738 struct sky2_port *sky2 = netdev_priv(dev);
3739
3740 switch (sky2->flow_mode) {
3741 case FC_NONE:
3742 ecmd->tx_pause = ecmd->rx_pause = 0;
3743 break;
3744 case FC_TX:
3745 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3746 break;
3747 case FC_RX:
3748 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3749 break;
3750 case FC_BOTH:
3751 ecmd->tx_pause = ecmd->rx_pause = 1;
3752 }
3753
3754 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3755 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3756 }
3757
3758 static int sky2_set_pauseparam(struct net_device *dev,
3759 struct ethtool_pauseparam *ecmd)
3760 {
3761 struct sky2_port *sky2 = netdev_priv(dev);
3762
3763 if (ecmd->autoneg == AUTONEG_ENABLE)
3764 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3765 else
3766 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3767
3768 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3769
3770 if (netif_running(dev))
3771 sky2_phy_reinit(sky2);
3772
3773 return 0;
3774 }
3775
3776 static int sky2_get_coalesce(struct net_device *dev,
3777 struct ethtool_coalesce *ecmd)
3778 {
3779 struct sky2_port *sky2 = netdev_priv(dev);
3780 struct sky2_hw *hw = sky2->hw;
3781
3782 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3783 ecmd->tx_coalesce_usecs = 0;
3784 else {
3785 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3786 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3787 }
3788 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3789
3790 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3791 ecmd->rx_coalesce_usecs = 0;
3792 else {
3793 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3794 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3795 }
3796 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3797
3798 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3799 ecmd->rx_coalesce_usecs_irq = 0;
3800 else {
3801 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3802 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3803 }
3804
3805 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3806
3807 return 0;
3808 }
3809
3810 /* Note: this affect both ports */
3811 static int sky2_set_coalesce(struct net_device *dev,
3812 struct ethtool_coalesce *ecmd)
3813 {
3814 struct sky2_port *sky2 = netdev_priv(dev);
3815 struct sky2_hw *hw = sky2->hw;
3816 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3817
3818 if (ecmd->tx_coalesce_usecs > tmax ||
3819 ecmd->rx_coalesce_usecs > tmax ||
3820 ecmd->rx_coalesce_usecs_irq > tmax)
3821 return -EINVAL;
3822
3823 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3824 return -EINVAL;
3825 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3826 return -EINVAL;
3827 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3828 return -EINVAL;
3829
3830 if (ecmd->tx_coalesce_usecs == 0)
3831 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3832 else {
3833 sky2_write32(hw, STAT_TX_TIMER_INI,
3834 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3835 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3836 }
3837 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3838
3839 if (ecmd->rx_coalesce_usecs == 0)
3840 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3841 else {
3842 sky2_write32(hw, STAT_LEV_TIMER_INI,
3843 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3844 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3845 }
3846 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3847
3848 if (ecmd->rx_coalesce_usecs_irq == 0)
3849 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3850 else {
3851 sky2_write32(hw, STAT_ISR_TIMER_INI,
3852 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3853 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3854 }
3855 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3856 return 0;
3857 }
3858
3859 static void sky2_get_ringparam(struct net_device *dev,
3860 struct ethtool_ringparam *ering)
3861 {
3862 struct sky2_port *sky2 = netdev_priv(dev);
3863
3864 ering->rx_max_pending = RX_MAX_PENDING;
3865 ering->rx_mini_max_pending = 0;
3866 ering->rx_jumbo_max_pending = 0;
3867 ering->tx_max_pending = TX_MAX_PENDING;
3868
3869 ering->rx_pending = sky2->rx_pending;
3870 ering->rx_mini_pending = 0;
3871 ering->rx_jumbo_pending = 0;
3872 ering->tx_pending = sky2->tx_pending;
3873 }
3874
3875 static int sky2_set_ringparam(struct net_device *dev,
3876 struct ethtool_ringparam *ering)
3877 {
3878 struct sky2_port *sky2 = netdev_priv(dev);
3879
3880 if (ering->rx_pending > RX_MAX_PENDING ||
3881 ering->rx_pending < 8 ||
3882 ering->tx_pending < TX_MIN_PENDING ||
3883 ering->tx_pending > TX_MAX_PENDING)
3884 return -EINVAL;
3885
3886 sky2_detach(dev);
3887
3888 sky2->rx_pending = ering->rx_pending;
3889 sky2->tx_pending = ering->tx_pending;
3890 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3891
3892 return sky2_reattach(dev);
3893 }
3894
3895 static int sky2_get_regs_len(struct net_device *dev)
3896 {
3897 return 0x4000;
3898 }
3899
3900 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3901 {
3902 /* This complicated switch statement is to make sure and
3903 * only access regions that are unreserved.
3904 * Some blocks are only valid on dual port cards.
3905 */
3906 switch (b) {
3907 /* second port */
3908 case 5: /* Tx Arbiter 2 */
3909 case 9: /* RX2 */
3910 case 14 ... 15: /* TX2 */
3911 case 17: case 19: /* Ram Buffer 2 */
3912 case 22 ... 23: /* Tx Ram Buffer 2 */
3913 case 25: /* Rx MAC Fifo 1 */
3914 case 27: /* Tx MAC Fifo 2 */
3915 case 31: /* GPHY 2 */
3916 case 40 ... 47: /* Pattern Ram 2 */
3917 case 52: case 54: /* TCP Segmentation 2 */
3918 case 112 ... 116: /* GMAC 2 */
3919 return hw->ports > 1;
3920
3921 case 0: /* Control */
3922 case 2: /* Mac address */
3923 case 4: /* Tx Arbiter 1 */
3924 case 7: /* PCI express reg */
3925 case 8: /* RX1 */
3926 case 12 ... 13: /* TX1 */
3927 case 16: case 18:/* Rx Ram Buffer 1 */
3928 case 20 ... 21: /* Tx Ram Buffer 1 */
3929 case 24: /* Rx MAC Fifo 1 */
3930 case 26: /* Tx MAC Fifo 1 */
3931 case 28 ... 29: /* Descriptor and status unit */
3932 case 30: /* GPHY 1*/
3933 case 32 ... 39: /* Pattern Ram 1 */
3934 case 48: case 50: /* TCP Segmentation 1 */
3935 case 56 ... 60: /* PCI space */
3936 case 80 ... 84: /* GMAC 1 */
3937 return 1;
3938
3939 default:
3940 return 0;
3941 }
3942 }
3943
3944 /*
3945 * Returns copy of control register region
3946 * Note: ethtool_get_regs always provides full size (16k) buffer
3947 */
3948 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3949 void *p)
3950 {
3951 const struct sky2_port *sky2 = netdev_priv(dev);
3952 const void __iomem *io = sky2->hw->regs;
3953 unsigned int b;
3954
3955 regs->version = 1;
3956
3957 for (b = 0; b < 128; b++) {
3958 /* skip poisonous diagnostic ram region in block 3 */
3959 if (b == 3)
3960 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3961 else if (sky2_reg_access_ok(sky2->hw, b))
3962 memcpy_fromio(p, io, 128);
3963 else
3964 memset(p, 0, 128);
3965
3966 p += 128;
3967 io += 128;
3968 }
3969 }
3970
3971 /* In order to do Jumbo packets on these chips, need to turn off the
3972 * transmit store/forward. Therefore checksum offload won't work.
3973 */
3974 static int no_tx_offload(struct net_device *dev)
3975 {
3976 const struct sky2_port *sky2 = netdev_priv(dev);
3977 const struct sky2_hw *hw = sky2->hw;
3978
3979 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3980 }
3981
3982 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3983 {
3984 if (data && no_tx_offload(dev))
3985 return -EINVAL;
3986
3987 return ethtool_op_set_tx_csum(dev, data);
3988 }
3989
3990
3991 static int sky2_set_tso(struct net_device *dev, u32 data)
3992 {
3993 if (data && no_tx_offload(dev))
3994 return -EINVAL;
3995
3996 return ethtool_op_set_tso(dev, data);
3997 }
3998
3999 static int sky2_get_eeprom_len(struct net_device *dev)
4000 {
4001 struct sky2_port *sky2 = netdev_priv(dev);
4002 struct sky2_hw *hw = sky2->hw;
4003 u16 reg2;
4004
4005 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4006 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4007 }
4008
4009 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4010 {
4011 unsigned long start = jiffies;
4012
4013 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4014 /* Can take up to 10.6 ms for write */
4015 if (time_after(jiffies, start + HZ/4)) {
4016 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
4017 return -ETIMEDOUT;
4018 }
4019 mdelay(1);
4020 }
4021
4022 return 0;
4023 }
4024
4025 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4026 u16 offset, size_t length)
4027 {
4028 int rc = 0;
4029
4030 while (length > 0) {
4031 u32 val;
4032
4033 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4034 rc = sky2_vpd_wait(hw, cap, 0);
4035 if (rc)
4036 break;
4037
4038 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4039
4040 memcpy(data, &val, min(sizeof(val), length));
4041 offset += sizeof(u32);
4042 data += sizeof(u32);
4043 length -= sizeof(u32);
4044 }
4045
4046 return rc;
4047 }
4048
4049 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4050 u16 offset, unsigned int length)
4051 {
4052 unsigned int i;
4053 int rc = 0;
4054
4055 for (i = 0; i < length; i += sizeof(u32)) {
4056 u32 val = *(u32 *)(data + i);
4057
4058 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4059 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4060
4061 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4062 if (rc)
4063 break;
4064 }
4065 return rc;
4066 }
4067
4068 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4069 u8 *data)
4070 {
4071 struct sky2_port *sky2 = netdev_priv(dev);
4072 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4073
4074 if (!cap)
4075 return -EINVAL;
4076
4077 eeprom->magic = SKY2_EEPROM_MAGIC;
4078
4079 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4080 }
4081
4082 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4083 u8 *data)
4084 {
4085 struct sky2_port *sky2 = netdev_priv(dev);
4086 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4087
4088 if (!cap)
4089 return -EINVAL;
4090
4091 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4092 return -EINVAL;
4093
4094 /* Partial writes not supported */
4095 if ((eeprom->offset & 3) || (eeprom->len & 3))
4096 return -EINVAL;
4097
4098 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4099 }
4100
4101
4102 static const struct ethtool_ops sky2_ethtool_ops = {
4103 .get_settings = sky2_get_settings,
4104 .set_settings = sky2_set_settings,
4105 .get_drvinfo = sky2_get_drvinfo,
4106 .get_wol = sky2_get_wol,
4107 .set_wol = sky2_set_wol,
4108 .get_msglevel = sky2_get_msglevel,
4109 .set_msglevel = sky2_set_msglevel,
4110 .nway_reset = sky2_nway_reset,
4111 .get_regs_len = sky2_get_regs_len,
4112 .get_regs = sky2_get_regs,
4113 .get_link = ethtool_op_get_link,
4114 .get_eeprom_len = sky2_get_eeprom_len,
4115 .get_eeprom = sky2_get_eeprom,
4116 .set_eeprom = sky2_set_eeprom,
4117 .set_sg = ethtool_op_set_sg,
4118 .set_tx_csum = sky2_set_tx_csum,
4119 .set_tso = sky2_set_tso,
4120 .get_rx_csum = sky2_get_rx_csum,
4121 .set_rx_csum = sky2_set_rx_csum,
4122 .get_strings = sky2_get_strings,
4123 .get_coalesce = sky2_get_coalesce,
4124 .set_coalesce = sky2_set_coalesce,
4125 .get_ringparam = sky2_get_ringparam,
4126 .set_ringparam = sky2_set_ringparam,
4127 .get_pauseparam = sky2_get_pauseparam,
4128 .set_pauseparam = sky2_set_pauseparam,
4129 .phys_id = sky2_phys_id,
4130 .get_sset_count = sky2_get_sset_count,
4131 .get_ethtool_stats = sky2_get_ethtool_stats,
4132 };
4133
4134 #ifdef CONFIG_SKY2_DEBUG
4135
4136 static struct dentry *sky2_debug;
4137
4138
4139 /*
4140 * Read and parse the first part of Vital Product Data
4141 */
4142 #define VPD_SIZE 128
4143 #define VPD_MAGIC 0x82
4144
4145 static const struct vpd_tag {
4146 char tag[2];
4147 char *label;
4148 } vpd_tags[] = {
4149 { "PN", "Part Number" },
4150 { "EC", "Engineering Level" },
4151 { "MN", "Manufacturer" },
4152 { "SN", "Serial Number" },
4153 { "YA", "Asset Tag" },
4154 { "VL", "First Error Log Message" },
4155 { "VF", "Second Error Log Message" },
4156 { "VB", "Boot Agent ROM Configuration" },
4157 { "VE", "EFI UNDI Configuration" },
4158 };
4159
4160 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4161 {
4162 size_t vpd_size;
4163 loff_t offs;
4164 u8 len;
4165 unsigned char *buf;
4166 u16 reg2;
4167
4168 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4169 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4170
4171 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4172 buf = kmalloc(vpd_size, GFP_KERNEL);
4173 if (!buf) {
4174 seq_puts(seq, "no memory!\n");
4175 return;
4176 }
4177
4178 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4179 seq_puts(seq, "VPD read failed\n");
4180 goto out;
4181 }
4182
4183 if (buf[0] != VPD_MAGIC) {
4184 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4185 goto out;
4186 }
4187 len = buf[1];
4188 if (len == 0 || len > vpd_size - 4) {
4189 seq_printf(seq, "Invalid id length: %d\n", len);
4190 goto out;
4191 }
4192
4193 seq_printf(seq, "%.*s\n", len, buf + 3);
4194 offs = len + 3;
4195
4196 while (offs < vpd_size - 4) {
4197 int i;
4198
4199 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4200 break;
4201 len = buf[offs + 2];
4202 if (offs + len + 3 >= vpd_size)
4203 break;
4204
4205 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4206 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4207 seq_printf(seq, " %s: %.*s\n",
4208 vpd_tags[i].label, len, buf + offs + 3);
4209 break;
4210 }
4211 }
4212 offs += len + 3;
4213 }
4214 out:
4215 kfree(buf);
4216 }
4217
4218 static int sky2_debug_show(struct seq_file *seq, void *v)
4219 {
4220 struct net_device *dev = seq->private;
4221 const struct sky2_port *sky2 = netdev_priv(dev);
4222 struct sky2_hw *hw = sky2->hw;
4223 unsigned port = sky2->port;
4224 unsigned idx, last;
4225 int sop;
4226
4227 sky2_show_vpd(seq, hw);
4228
4229 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4230 sky2_read32(hw, B0_ISRC),
4231 sky2_read32(hw, B0_IMSK),
4232 sky2_read32(hw, B0_Y2_SP_ICR));
4233
4234 if (!netif_running(dev)) {
4235 seq_printf(seq, "network not running\n");
4236 return 0;
4237 }
4238
4239 napi_disable(&hw->napi);
4240 last = sky2_read16(hw, STAT_PUT_IDX);
4241
4242 if (hw->st_idx == last)
4243 seq_puts(seq, "Status ring (empty)\n");
4244 else {
4245 seq_puts(seq, "Status ring\n");
4246 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4247 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4248 const struct sky2_status_le *le = hw->st_le + idx;
4249 seq_printf(seq, "[%d] %#x %d %#x\n",
4250 idx, le->opcode, le->length, le->status);
4251 }
4252 seq_puts(seq, "\n");
4253 }
4254
4255 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4256 sky2->tx_cons, sky2->tx_prod,
4257 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4258 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4259
4260 /* Dump contents of tx ring */
4261 sop = 1;
4262 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4263 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4264 const struct sky2_tx_le *le = sky2->tx_le + idx;
4265 u32 a = le32_to_cpu(le->addr);
4266
4267 if (sop)
4268 seq_printf(seq, "%u:", idx);
4269 sop = 0;
4270
4271 switch(le->opcode & ~HW_OWNER) {
4272 case OP_ADDR64:
4273 seq_printf(seq, " %#x:", a);
4274 break;
4275 case OP_LRGLEN:
4276 seq_printf(seq, " mtu=%d", a);
4277 break;
4278 case OP_VLAN:
4279 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4280 break;
4281 case OP_TCPLISW:
4282 seq_printf(seq, " csum=%#x", a);
4283 break;
4284 case OP_LARGESEND:
4285 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4286 break;
4287 case OP_PACKET:
4288 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4289 break;
4290 case OP_BUFFER:
4291 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4292 break;
4293 default:
4294 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4295 a, le16_to_cpu(le->length));
4296 }
4297
4298 if (le->ctrl & EOP) {
4299 seq_putc(seq, '\n');
4300 sop = 1;
4301 }
4302 }
4303
4304 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4305 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4306 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4307 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4308
4309 sky2_read32(hw, B0_Y2_SP_LISR);
4310 napi_enable(&hw->napi);
4311 return 0;
4312 }
4313
4314 static int sky2_debug_open(struct inode *inode, struct file *file)
4315 {
4316 return single_open(file, sky2_debug_show, inode->i_private);
4317 }
4318
4319 static const struct file_operations sky2_debug_fops = {
4320 .owner = THIS_MODULE,
4321 .open = sky2_debug_open,
4322 .read = seq_read,
4323 .llseek = seq_lseek,
4324 .release = single_release,
4325 };
4326
4327 /*
4328 * Use network device events to create/remove/rename
4329 * debugfs file entries
4330 */
4331 static int sky2_device_event(struct notifier_block *unused,
4332 unsigned long event, void *ptr)
4333 {
4334 struct net_device *dev = ptr;
4335 struct sky2_port *sky2 = netdev_priv(dev);
4336
4337 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4338 return NOTIFY_DONE;
4339
4340 switch(event) {
4341 case NETDEV_CHANGENAME:
4342 if (sky2->debugfs) {
4343 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4344 sky2_debug, dev->name);
4345 }
4346 break;
4347
4348 case NETDEV_GOING_DOWN:
4349 if (sky2->debugfs) {
4350 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4351 dev->name);
4352 debugfs_remove(sky2->debugfs);
4353 sky2->debugfs = NULL;
4354 }
4355 break;
4356
4357 case NETDEV_UP:
4358 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4359 sky2_debug, dev,
4360 &sky2_debug_fops);
4361 if (IS_ERR(sky2->debugfs))
4362 sky2->debugfs = NULL;
4363 }
4364
4365 return NOTIFY_DONE;
4366 }
4367
4368 static struct notifier_block sky2_notifier = {
4369 .notifier_call = sky2_device_event,
4370 };
4371
4372
4373 static __init void sky2_debug_init(void)
4374 {
4375 struct dentry *ent;
4376
4377 ent = debugfs_create_dir("sky2", NULL);
4378 if (!ent || IS_ERR(ent))
4379 return;
4380
4381 sky2_debug = ent;
4382 register_netdevice_notifier(&sky2_notifier);
4383 }
4384
4385 static __exit void sky2_debug_cleanup(void)
4386 {
4387 if (sky2_debug) {
4388 unregister_netdevice_notifier(&sky2_notifier);
4389 debugfs_remove(sky2_debug);
4390 sky2_debug = NULL;
4391 }
4392 }
4393
4394 #else
4395 #define sky2_debug_init()
4396 #define sky2_debug_cleanup()
4397 #endif
4398
4399 /* Two copies of network device operations to handle special case of
4400 not allowing netpoll on second port */
4401 static const struct net_device_ops sky2_netdev_ops[2] = {
4402 {
4403 .ndo_open = sky2_up,
4404 .ndo_stop = sky2_down,
4405 .ndo_start_xmit = sky2_xmit_frame,
4406 .ndo_do_ioctl = sky2_ioctl,
4407 .ndo_validate_addr = eth_validate_addr,
4408 .ndo_set_mac_address = sky2_set_mac_address,
4409 .ndo_set_multicast_list = sky2_set_multicast,
4410 .ndo_change_mtu = sky2_change_mtu,
4411 .ndo_tx_timeout = sky2_tx_timeout,
4412 #ifdef SKY2_VLAN_TAG_USED
4413 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4414 #endif
4415 #ifdef CONFIG_NET_POLL_CONTROLLER
4416 .ndo_poll_controller = sky2_netpoll,
4417 #endif
4418 },
4419 {
4420 .ndo_open = sky2_up,
4421 .ndo_stop = sky2_down,
4422 .ndo_start_xmit = sky2_xmit_frame,
4423 .ndo_do_ioctl = sky2_ioctl,
4424 .ndo_validate_addr = eth_validate_addr,
4425 .ndo_set_mac_address = sky2_set_mac_address,
4426 .ndo_set_multicast_list = sky2_set_multicast,
4427 .ndo_change_mtu = sky2_change_mtu,
4428 .ndo_tx_timeout = sky2_tx_timeout,
4429 #ifdef SKY2_VLAN_TAG_USED
4430 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4431 #endif
4432 },
4433 };
4434
4435 /* Initialize network device */
4436 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4437 unsigned port,
4438 int highmem, int wol)
4439 {
4440 struct sky2_port *sky2;
4441 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4442
4443 if (!dev) {
4444 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4445 return NULL;
4446 }
4447
4448 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4449 dev->irq = hw->pdev->irq;
4450 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4451 dev->watchdog_timeo = TX_WATCHDOG;
4452 dev->netdev_ops = &sky2_netdev_ops[port];
4453
4454 sky2 = netdev_priv(dev);
4455 sky2->netdev = dev;
4456 sky2->hw = hw;
4457 sky2->msg_enable = netif_msg_init(debug, default_msg);
4458
4459 /* Auto speed and flow control */
4460 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4461 if (hw->chip_id != CHIP_ID_YUKON_XL)
4462 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4463
4464 sky2->flow_mode = FC_BOTH;
4465
4466 sky2->duplex = -1;
4467 sky2->speed = -1;
4468 sky2->advertising = sky2_supported_modes(hw);
4469 sky2->wol = wol;
4470
4471 spin_lock_init(&sky2->phy_lock);
4472
4473 sky2->tx_pending = TX_DEF_PENDING;
4474 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4475 sky2->rx_pending = RX_DEF_PENDING;
4476
4477 hw->dev[port] = dev;
4478
4479 sky2->port = port;
4480
4481 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4482 if (highmem)
4483 dev->features |= NETIF_F_HIGHDMA;
4484
4485 #ifdef SKY2_VLAN_TAG_USED
4486 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4487 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4488 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4489 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4490 }
4491 #endif
4492
4493 /* read the mac address */
4494 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4495 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4496
4497 return dev;
4498 }
4499
4500 static void __devinit sky2_show_addr(struct net_device *dev)
4501 {
4502 const struct sky2_port *sky2 = netdev_priv(dev);
4503
4504 if (netif_msg_probe(sky2))
4505 printk(KERN_INFO PFX "%s: addr %pM\n",
4506 dev->name, dev->dev_addr);
4507 }
4508
4509 /* Handle software interrupt used during MSI test */
4510 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4511 {
4512 struct sky2_hw *hw = dev_id;
4513 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4514
4515 if (status == 0)
4516 return IRQ_NONE;
4517
4518 if (status & Y2_IS_IRQ_SW) {
4519 hw->flags |= SKY2_HW_USE_MSI;
4520 wake_up(&hw->msi_wait);
4521 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4522 }
4523 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4524
4525 return IRQ_HANDLED;
4526 }
4527
4528 /* Test interrupt path by forcing a a software IRQ */
4529 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4530 {
4531 struct pci_dev *pdev = hw->pdev;
4532 int err;
4533
4534 init_waitqueue_head (&hw->msi_wait);
4535
4536 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4537
4538 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4539 if (err) {
4540 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4541 return err;
4542 }
4543
4544 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4545 sky2_read8(hw, B0_CTST);
4546
4547 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4548
4549 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4550 /* MSI test failed, go back to INTx mode */
4551 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4552 "switching to INTx mode.\n");
4553
4554 err = -EOPNOTSUPP;
4555 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4556 }
4557
4558 sky2_write32(hw, B0_IMSK, 0);
4559 sky2_read32(hw, B0_IMSK);
4560
4561 free_irq(pdev->irq, hw);
4562
4563 return err;
4564 }
4565
4566 /* This driver supports yukon2 chipset only */
4567 static const char *sky2_name(u8 chipid, char *buf, int sz)
4568 {
4569 const char *name[] = {
4570 "XL", /* 0xb3 */
4571 "EC Ultra", /* 0xb4 */
4572 "Extreme", /* 0xb5 */
4573 "EC", /* 0xb6 */
4574 "FE", /* 0xb7 */
4575 "FE+", /* 0xb8 */
4576 "Supreme", /* 0xb9 */
4577 "UL 2", /* 0xba */
4578 "Unknown", /* 0xbb */
4579 "Optima", /* 0xbc */
4580 };
4581
4582 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4583 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4584 else
4585 snprintf(buf, sz, "(chip %#x)", chipid);
4586 return buf;
4587 }
4588
4589 static int __devinit sky2_probe(struct pci_dev *pdev,
4590 const struct pci_device_id *ent)
4591 {
4592 struct net_device *dev;
4593 struct sky2_hw *hw;
4594 int err, using_dac = 0, wol_default;
4595 u32 reg;
4596 char buf1[16];
4597
4598 err = pci_enable_device(pdev);
4599 if (err) {
4600 dev_err(&pdev->dev, "cannot enable PCI device\n");
4601 goto err_out;
4602 }
4603
4604 /* Get configuration information
4605 * Note: only regular PCI config access once to test for HW issues
4606 * other PCI access through shared memory for speed and to
4607 * avoid MMCONFIG problems.
4608 */
4609 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4610 if (err) {
4611 dev_err(&pdev->dev, "PCI read config failed\n");
4612 goto err_out;
4613 }
4614
4615 if (~reg == 0) {
4616 dev_err(&pdev->dev, "PCI configuration read error\n");
4617 goto err_out;
4618 }
4619
4620 err = pci_request_regions(pdev, DRV_NAME);
4621 if (err) {
4622 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4623 goto err_out_disable;
4624 }
4625
4626 pci_set_master(pdev);
4627
4628 if (sizeof(dma_addr_t) > sizeof(u32) &&
4629 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4630 using_dac = 1;
4631 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4632 if (err < 0) {
4633 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4634 "for consistent allocations\n");
4635 goto err_out_free_regions;
4636 }
4637 } else {
4638 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4639 if (err) {
4640 dev_err(&pdev->dev, "no usable DMA configuration\n");
4641 goto err_out_free_regions;
4642 }
4643 }
4644
4645
4646 #ifdef __BIG_ENDIAN
4647 /* The sk98lin vendor driver uses hardware byte swapping but
4648 * this driver uses software swapping.
4649 */
4650 reg &= ~PCI_REV_DESC;
4651 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4652 if (err) {
4653 dev_err(&pdev->dev, "PCI write config failed\n");
4654 goto err_out_free_regions;
4655 }
4656 #endif
4657
4658 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4659
4660 err = -ENOMEM;
4661
4662 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4663 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4664 if (!hw) {
4665 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4666 goto err_out_free_regions;
4667 }
4668
4669 hw->pdev = pdev;
4670 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4671
4672 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4673 if (!hw->regs) {
4674 dev_err(&pdev->dev, "cannot map device registers\n");
4675 goto err_out_free_hw;
4676 }
4677
4678 /* ring for status responses */
4679 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4680 if (!hw->st_le)
4681 goto err_out_iounmap;
4682
4683 err = sky2_init(hw);
4684 if (err)
4685 goto err_out_iounmap;
4686
4687 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4688 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4689
4690 sky2_reset(hw);
4691
4692 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4693 if (!dev) {
4694 err = -ENOMEM;
4695 goto err_out_free_pci;
4696 }
4697
4698 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4699 err = sky2_test_msi(hw);
4700 if (err == -EOPNOTSUPP)
4701 pci_disable_msi(pdev);
4702 else if (err)
4703 goto err_out_free_netdev;
4704 }
4705
4706 err = register_netdev(dev);
4707 if (err) {
4708 dev_err(&pdev->dev, "cannot register net device\n");
4709 goto err_out_free_netdev;
4710 }
4711
4712 netif_carrier_off(dev);
4713
4714 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4715
4716 err = request_irq(pdev->irq, sky2_intr,
4717 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4718 hw->irq_name, hw);
4719 if (err) {
4720 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4721 goto err_out_unregister;
4722 }
4723 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4724 napi_enable(&hw->napi);
4725
4726 sky2_show_addr(dev);
4727
4728 if (hw->ports > 1) {
4729 struct net_device *dev1;
4730
4731 err = -ENOMEM;
4732 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4733 if (dev1 && (err = register_netdev(dev1)) == 0)
4734 sky2_show_addr(dev1);
4735 else {
4736 dev_warn(&pdev->dev,
4737 "register of second port failed (%d)\n", err);
4738 hw->dev[1] = NULL;
4739 hw->ports = 1;
4740 if (dev1)
4741 free_netdev(dev1);
4742 }
4743 }
4744
4745 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4746 INIT_WORK(&hw->restart_work, sky2_restart);
4747
4748 pci_set_drvdata(pdev, hw);
4749 pdev->d3_delay = 150;
4750
4751 return 0;
4752
4753 err_out_unregister:
4754 if (hw->flags & SKY2_HW_USE_MSI)
4755 pci_disable_msi(pdev);
4756 unregister_netdev(dev);
4757 err_out_free_netdev:
4758 free_netdev(dev);
4759 err_out_free_pci:
4760 sky2_write8(hw, B0_CTST, CS_RST_SET);
4761 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4762 err_out_iounmap:
4763 iounmap(hw->regs);
4764 err_out_free_hw:
4765 kfree(hw);
4766 err_out_free_regions:
4767 pci_release_regions(pdev);
4768 err_out_disable:
4769 pci_disable_device(pdev);
4770 err_out:
4771 pci_set_drvdata(pdev, NULL);
4772 return err;
4773 }
4774
4775 static void __devexit sky2_remove(struct pci_dev *pdev)
4776 {
4777 struct sky2_hw *hw = pci_get_drvdata(pdev);
4778 int i;
4779
4780 if (!hw)
4781 return;
4782
4783 del_timer_sync(&hw->watchdog_timer);
4784 cancel_work_sync(&hw->restart_work);
4785
4786 for (i = hw->ports-1; i >= 0; --i)
4787 unregister_netdev(hw->dev[i]);
4788
4789 sky2_write32(hw, B0_IMSK, 0);
4790
4791 sky2_power_aux(hw);
4792
4793 sky2_write8(hw, B0_CTST, CS_RST_SET);
4794 sky2_read8(hw, B0_CTST);
4795
4796 free_irq(pdev->irq, hw);
4797 if (hw->flags & SKY2_HW_USE_MSI)
4798 pci_disable_msi(pdev);
4799 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4800 pci_release_regions(pdev);
4801 pci_disable_device(pdev);
4802
4803 for (i = hw->ports-1; i >= 0; --i)
4804 free_netdev(hw->dev[i]);
4805
4806 iounmap(hw->regs);
4807 kfree(hw);
4808
4809 pci_set_drvdata(pdev, NULL);
4810 }
4811
4812 #ifdef CONFIG_PM
4813 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4814 {
4815 struct sky2_hw *hw = pci_get_drvdata(pdev);
4816 int i, wol = 0;
4817
4818 if (!hw)
4819 return 0;
4820
4821 del_timer_sync(&hw->watchdog_timer);
4822 cancel_work_sync(&hw->restart_work);
4823
4824 rtnl_lock();
4825 for (i = 0; i < hw->ports; i++) {
4826 struct net_device *dev = hw->dev[i];
4827 struct sky2_port *sky2 = netdev_priv(dev);
4828
4829 sky2_detach(dev);
4830
4831 if (sky2->wol)
4832 sky2_wol_init(sky2);
4833
4834 wol |= sky2->wol;
4835 }
4836
4837 sky2_write32(hw, B0_IMSK, 0);
4838 napi_disable(&hw->napi);
4839 sky2_power_aux(hw);
4840 rtnl_unlock();
4841
4842 pci_save_state(pdev);
4843 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4844 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4845
4846 return 0;
4847 }
4848
4849 static int sky2_resume(struct pci_dev *pdev)
4850 {
4851 struct sky2_hw *hw = pci_get_drvdata(pdev);
4852 int i, err;
4853
4854 if (!hw)
4855 return 0;
4856
4857 err = pci_set_power_state(pdev, PCI_D0);
4858 if (err)
4859 goto out;
4860
4861 err = pci_restore_state(pdev);
4862 if (err)
4863 goto out;
4864
4865 pci_enable_wake(pdev, PCI_D0, 0);
4866
4867 /* Re-enable all clocks */
4868 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4869 if (err) {
4870 dev_err(&pdev->dev, "PCI write config failed\n");
4871 goto out;
4872 }
4873
4874 sky2_reset(hw);
4875 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4876 napi_enable(&hw->napi);
4877
4878 rtnl_lock();
4879 for (i = 0; i < hw->ports; i++) {
4880 err = sky2_reattach(hw->dev[i]);
4881 if (err)
4882 goto out;
4883 }
4884 rtnl_unlock();
4885
4886 return 0;
4887 out:
4888 rtnl_unlock();
4889
4890 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4891 pci_disable_device(pdev);
4892 return err;
4893 }
4894 #endif
4895
4896 static void sky2_shutdown(struct pci_dev *pdev)
4897 {
4898 struct sky2_hw *hw = pci_get_drvdata(pdev);
4899 int i, wol = 0;
4900
4901 if (!hw)
4902 return;
4903
4904 rtnl_lock();
4905 del_timer_sync(&hw->watchdog_timer);
4906
4907 for (i = 0; i < hw->ports; i++) {
4908 struct net_device *dev = hw->dev[i];
4909 struct sky2_port *sky2 = netdev_priv(dev);
4910
4911 if (sky2->wol) {
4912 wol = 1;
4913 sky2_wol_init(sky2);
4914 }
4915 }
4916
4917 if (wol)
4918 sky2_power_aux(hw);
4919 rtnl_unlock();
4920
4921 pci_enable_wake(pdev, PCI_D3hot, wol);
4922 pci_enable_wake(pdev, PCI_D3cold, wol);
4923
4924 pci_disable_device(pdev);
4925 pci_set_power_state(pdev, PCI_D3hot);
4926 }
4927
4928 static struct pci_driver sky2_driver = {
4929 .name = DRV_NAME,
4930 .id_table = sky2_id_table,
4931 .probe = sky2_probe,
4932 .remove = __devexit_p(sky2_remove),
4933 #ifdef CONFIG_PM
4934 .suspend = sky2_suspend,
4935 .resume = sky2_resume,
4936 #endif
4937 .shutdown = sky2_shutdown,
4938 };
4939
4940 static int __init sky2_init_module(void)
4941 {
4942 pr_info(PFX "driver version " DRV_VERSION "\n");
4943
4944 sky2_debug_init();
4945 return pci_register_driver(&sky2_driver);
4946 }
4947
4948 static void __exit sky2_cleanup_module(void)
4949 {
4950 pci_unregister_driver(&sky2_driver);
4951 sky2_debug_cleanup();
4952 }
4953
4954 module_init(sky2_init_module);
4955 module_exit(sky2_cleanup_module);
4956
4957 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4958 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4959 MODULE_LICENSE("GPL");
4960 MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)