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Merge branches 'pxa-ian' and 'pxa-xm270' into pxa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include "net_driver.h"
17 #include "bitfield.h"
18 #include "efx.h"
19 #include "mac.h"
20 #include "gmii.h"
21 #include "spi.h"
22 #include "falcon.h"
23 #include "falcon_hwdefs.h"
24 #include "falcon_io.h"
25 #include "mdio_10g.h"
26 #include "phy.h"
27 #include "boards.h"
28 #include "workarounds.h"
29
30 /* Falcon hardware control.
31 * Falcon is the internal codename for the SFC4000 controller that is
32 * present in SFE400X evaluation boards
33 */
34
35 /**
36 * struct falcon_nic_data - Falcon NIC state
37 * @next_buffer_table: First available buffer table id
38 * @pci_dev2: The secondary PCI device if present
39 */
40 struct falcon_nic_data {
41 unsigned next_buffer_table;
42 struct pci_dev *pci_dev2;
43 };
44
45 /**************************************************************************
46 *
47 * Configurable values
48 *
49 **************************************************************************
50 */
51
52 static int disable_dma_stats;
53
54 /* This is set to 16 for a good reason. In summary, if larger than
55 * 16, the descriptor cache holds more than a default socket
56 * buffer's worth of packets (for UDP we can only have at most one
57 * socket buffer's worth outstanding). This combined with the fact
58 * that we only get 1 TX event per descriptor cache means the NIC
59 * goes idle.
60 */
61 #define TX_DC_ENTRIES 16
62 #define TX_DC_ENTRIES_ORDER 0
63 #define TX_DC_BASE 0x130000
64
65 #define RX_DC_ENTRIES 64
66 #define RX_DC_ENTRIES_ORDER 2
67 #define RX_DC_BASE 0x100000
68
69 /* RX FIFO XOFF watermark
70 *
71 * When the amount of the RX FIFO increases used increases past this
72 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
73 * This also has an effect on RX/TX arbitration
74 */
75 static int rx_xoff_thresh_bytes = -1;
76 module_param(rx_xoff_thresh_bytes, int, 0644);
77 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
78
79 /* RX FIFO XON watermark
80 *
81 * When the amount of the RX FIFO used decreases below this
82 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
83 * This also has an effect on RX/TX arbitration
84 */
85 static int rx_xon_thresh_bytes = -1;
86 module_param(rx_xon_thresh_bytes, int, 0644);
87 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
88
89 /* TX descriptor ring size - min 512 max 4k */
90 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
91 #define FALCON_TXD_RING_SIZE 1024
92 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
93
94 /* RX descriptor ring size - min 512 max 4k */
95 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
96 #define FALCON_RXD_RING_SIZE 1024
97 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
98
99 /* Event queue size - max 32k */
100 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
101 #define FALCON_EVQ_SIZE 4096
102 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
103
104 /* Max number of internal errors. After this resets will not be performed */
105 #define FALCON_MAX_INT_ERRORS 4
106
107 /* Maximum period that we wait for flush events. If the flush event
108 * doesn't arrive in this period of time then we check if the queue
109 * was disabled anyway. */
110 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
111
112 /**************************************************************************
113 *
114 * Falcon constants
115 *
116 **************************************************************************
117 */
118
119 /* DMA address mask */
120 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
121
122 /* TX DMA length mask (13-bit) */
123 #define FALCON_TX_DMA_MASK (4096 - 1)
124
125 /* Size and alignment of special buffers (4KB) */
126 #define FALCON_BUF_SIZE 4096
127
128 /* Dummy SRAM size code */
129 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
130
131 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
132 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
133 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
134 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
135 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
136 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
137
138 #define FALCON_IS_DUAL_FUNC(efx) \
139 (falcon_rev(efx) < FALCON_REV_B0)
140
141 /**************************************************************************
142 *
143 * Falcon hardware access
144 *
145 **************************************************************************/
146
147 /* Read the current event from the event queue */
148 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
149 unsigned int index)
150 {
151 return (((efx_qword_t *) (channel->eventq.addr)) + index);
152 }
153
154 /* See if an event is present
155 *
156 * We check both the high and low dword of the event for all ones. We
157 * wrote all ones when we cleared the event, and no valid event can
158 * have all ones in either its high or low dwords. This approach is
159 * robust against reordering.
160 *
161 * Note that using a single 64-bit comparison is incorrect; even
162 * though the CPU read will be atomic, the DMA write may not be.
163 */
164 static inline int falcon_event_present(efx_qword_t *event)
165 {
166 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
167 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
168 }
169
170 /**************************************************************************
171 *
172 * I2C bus - this is a bit-bashing interface using GPIO pins
173 * Note that it uses the output enables to tristate the outputs
174 * SDA is the data pin and SCL is the clock
175 *
176 **************************************************************************
177 */
178 static void falcon_setsdascl(struct efx_i2c_interface *i2c)
179 {
180 efx_oword_t reg;
181
182 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
183 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, (i2c->scl ? 0 : 1));
184 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, (i2c->sda ? 0 : 1));
185 falcon_write(i2c->efx, &reg, GPIO_CTL_REG_KER);
186 }
187
188 static int falcon_getsda(struct efx_i2c_interface *i2c)
189 {
190 efx_oword_t reg;
191
192 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
193 return EFX_OWORD_FIELD(reg, GPIO3_IN);
194 }
195
196 static int falcon_getscl(struct efx_i2c_interface *i2c)
197 {
198 efx_oword_t reg;
199
200 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
201 return EFX_DWORD_FIELD(reg, GPIO0_IN);
202 }
203
204 static struct efx_i2c_bit_operations falcon_i2c_bit_operations = {
205 .setsda = falcon_setsdascl,
206 .setscl = falcon_setsdascl,
207 .getsda = falcon_getsda,
208 .getscl = falcon_getscl,
209 .udelay = 100,
210 .mdelay = 10,
211 };
212
213 /**************************************************************************
214 *
215 * Falcon special buffer handling
216 * Special buffers are used for event queues and the TX and RX
217 * descriptor rings.
218 *
219 *************************************************************************/
220
221 /*
222 * Initialise a Falcon special buffer
223 *
224 * This will define a buffer (previously allocated via
225 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
226 * it to be used for event queues, descriptor rings etc.
227 */
228 static int
229 falcon_init_special_buffer(struct efx_nic *efx,
230 struct efx_special_buffer *buffer)
231 {
232 efx_qword_t buf_desc;
233 int index;
234 dma_addr_t dma_addr;
235 int i;
236
237 EFX_BUG_ON_PARANOID(!buffer->addr);
238
239 /* Write buffer descriptors to NIC */
240 for (i = 0; i < buffer->entries; i++) {
241 index = buffer->index + i;
242 dma_addr = buffer->dma_addr + (i * 4096);
243 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
244 index, (unsigned long long)dma_addr);
245 EFX_POPULATE_QWORD_4(buf_desc,
246 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
247 BUF_ADR_REGION, 0,
248 BUF_ADR_FBUF, (dma_addr >> 12),
249 BUF_OWNER_ID_FBUF, 0);
250 falcon_write_sram(efx, &buf_desc, index);
251 }
252
253 return 0;
254 }
255
256 /* Unmaps a buffer from Falcon and clears the buffer table entries */
257 static void
258 falcon_fini_special_buffer(struct efx_nic *efx,
259 struct efx_special_buffer *buffer)
260 {
261 efx_oword_t buf_tbl_upd;
262 unsigned int start = buffer->index;
263 unsigned int end = (buffer->index + buffer->entries - 1);
264
265 if (!buffer->entries)
266 return;
267
268 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
269 buffer->index, buffer->index + buffer->entries - 1);
270
271 EFX_POPULATE_OWORD_4(buf_tbl_upd,
272 BUF_UPD_CMD, 0,
273 BUF_CLR_CMD, 1,
274 BUF_CLR_END_ID, end,
275 BUF_CLR_START_ID, start);
276 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
277 }
278
279 /*
280 * Allocate a new Falcon special buffer
281 *
282 * This allocates memory for a new buffer, clears it and allocates a
283 * new buffer ID range. It does not write into Falcon's buffer table.
284 *
285 * This call will allocate 4KB buffers, since Falcon can't use 8KB
286 * buffers for event queues and descriptor rings.
287 */
288 static int falcon_alloc_special_buffer(struct efx_nic *efx,
289 struct efx_special_buffer *buffer,
290 unsigned int len)
291 {
292 struct falcon_nic_data *nic_data = efx->nic_data;
293
294 len = ALIGN(len, FALCON_BUF_SIZE);
295
296 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
297 &buffer->dma_addr);
298 if (!buffer->addr)
299 return -ENOMEM;
300 buffer->len = len;
301 buffer->entries = len / FALCON_BUF_SIZE;
302 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
303
304 /* All zeros is a potentially valid event so memset to 0xff */
305 memset(buffer->addr, 0xff, len);
306
307 /* Select new buffer ID */
308 buffer->index = nic_data->next_buffer_table;
309 nic_data->next_buffer_table += buffer->entries;
310
311 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
312 "(virt %p phys %lx)\n", buffer->index,
313 buffer->index + buffer->entries - 1,
314 (unsigned long long)buffer->dma_addr, len,
315 buffer->addr, virt_to_phys(buffer->addr));
316
317 return 0;
318 }
319
320 static void falcon_free_special_buffer(struct efx_nic *efx,
321 struct efx_special_buffer *buffer)
322 {
323 if (!buffer->addr)
324 return;
325
326 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
327 "(virt %p phys %lx)\n", buffer->index,
328 buffer->index + buffer->entries - 1,
329 (unsigned long long)buffer->dma_addr, buffer->len,
330 buffer->addr, virt_to_phys(buffer->addr));
331
332 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
333 buffer->dma_addr);
334 buffer->addr = NULL;
335 buffer->entries = 0;
336 }
337
338 /**************************************************************************
339 *
340 * Falcon generic buffer handling
341 * These buffers are used for interrupt status and MAC stats
342 *
343 **************************************************************************/
344
345 static int falcon_alloc_buffer(struct efx_nic *efx,
346 struct efx_buffer *buffer, unsigned int len)
347 {
348 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
349 &buffer->dma_addr);
350 if (!buffer->addr)
351 return -ENOMEM;
352 buffer->len = len;
353 memset(buffer->addr, 0, len);
354 return 0;
355 }
356
357 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
358 {
359 if (buffer->addr) {
360 pci_free_consistent(efx->pci_dev, buffer->len,
361 buffer->addr, buffer->dma_addr);
362 buffer->addr = NULL;
363 }
364 }
365
366 /**************************************************************************
367 *
368 * Falcon TX path
369 *
370 **************************************************************************/
371
372 /* Returns a pointer to the specified transmit descriptor in the TX
373 * descriptor queue belonging to the specified channel.
374 */
375 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
376 unsigned int index)
377 {
378 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
379 }
380
381 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
382 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
383 {
384 unsigned write_ptr;
385 efx_dword_t reg;
386
387 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
388 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
389 falcon_writel_page(tx_queue->efx, &reg,
390 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
391 }
392
393
394 /* For each entry inserted into the software descriptor ring, create a
395 * descriptor in the hardware TX descriptor ring (in host memory), and
396 * write a doorbell.
397 */
398 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
399 {
400
401 struct efx_tx_buffer *buffer;
402 efx_qword_t *txd;
403 unsigned write_ptr;
404
405 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
406
407 do {
408 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
409 buffer = &tx_queue->buffer[write_ptr];
410 txd = falcon_tx_desc(tx_queue, write_ptr);
411 ++tx_queue->write_count;
412
413 /* Create TX descriptor ring entry */
414 EFX_POPULATE_QWORD_5(*txd,
415 TX_KER_PORT, 0,
416 TX_KER_CONT, buffer->continuation,
417 TX_KER_BYTE_CNT, buffer->len,
418 TX_KER_BUF_REGION, 0,
419 TX_KER_BUF_ADR, buffer->dma_addr);
420 } while (tx_queue->write_count != tx_queue->insert_count);
421
422 wmb(); /* Ensure descriptors are written before they are fetched */
423 falcon_notify_tx_desc(tx_queue);
424 }
425
426 /* Allocate hardware resources for a TX queue */
427 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
428 {
429 struct efx_nic *efx = tx_queue->efx;
430 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
431 FALCON_TXD_RING_SIZE *
432 sizeof(efx_qword_t));
433 }
434
435 int falcon_init_tx(struct efx_tx_queue *tx_queue)
436 {
437 efx_oword_t tx_desc_ptr;
438 struct efx_nic *efx = tx_queue->efx;
439 int rc;
440
441 /* Pin TX descriptor ring */
442 rc = falcon_init_special_buffer(efx, &tx_queue->txd);
443 if (rc)
444 return rc;
445
446 /* Push TX descriptor ring to card */
447 EFX_POPULATE_OWORD_10(tx_desc_ptr,
448 TX_DESCQ_EN, 1,
449 TX_ISCSI_DDIG_EN, 0,
450 TX_ISCSI_HDIG_EN, 0,
451 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
452 TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
453 TX_DESCQ_OWNER_ID, 0,
454 TX_DESCQ_LABEL, tx_queue->queue,
455 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
456 TX_DESCQ_TYPE, 0,
457 TX_NON_IP_DROP_DIS_B0, 1);
458
459 if (falcon_rev(efx) >= FALCON_REV_B0) {
460 int csum = !(efx->net_dev->features & NETIF_F_IP_CSUM);
461 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, csum);
462 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, csum);
463 }
464
465 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
466 tx_queue->queue);
467
468 if (falcon_rev(efx) < FALCON_REV_B0) {
469 efx_oword_t reg;
470
471 BUG_ON(tx_queue->queue >= 128); /* HW limit */
472
473 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
474 if (efx->net_dev->features & NETIF_F_IP_CSUM)
475 clear_bit_le(tx_queue->queue, (void *)&reg);
476 else
477 set_bit_le(tx_queue->queue, (void *)&reg);
478 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
479 }
480
481 return 0;
482 }
483
484 static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
485 {
486 struct efx_nic *efx = tx_queue->efx;
487 struct efx_channel *channel = &efx->channel[0];
488 efx_oword_t tx_flush_descq;
489 unsigned int read_ptr, i;
490
491 /* Post a flush command */
492 EFX_POPULATE_OWORD_2(tx_flush_descq,
493 TX_FLUSH_DESCQ_CMD, 1,
494 TX_FLUSH_DESCQ, tx_queue->queue);
495 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
496 msleep(FALCON_FLUSH_TIMEOUT);
497
498 if (EFX_WORKAROUND_7803(efx))
499 return 0;
500
501 /* Look for a flush completed event */
502 read_ptr = channel->eventq_read_ptr;
503 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
504 efx_qword_t *event = falcon_event(channel, read_ptr);
505 int ev_code, ev_sub_code, ev_queue;
506 if (!falcon_event_present(event))
507 break;
508
509 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
510 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
511 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
512 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
513 (ev_queue == tx_queue->queue)) {
514 EFX_LOG(efx, "tx queue %d flush command succesful\n",
515 tx_queue->queue);
516 return 0;
517 }
518
519 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
520 }
521
522 if (EFX_WORKAROUND_11557(efx)) {
523 efx_oword_t reg;
524 int enabled;
525
526 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
527 tx_queue->queue);
528 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
529 if (!enabled) {
530 EFX_LOG(efx, "tx queue %d disabled without a "
531 "flush event seen\n", tx_queue->queue);
532 return 0;
533 }
534 }
535
536 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
537 return -ETIMEDOUT;
538 }
539
540 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
541 {
542 struct efx_nic *efx = tx_queue->efx;
543 efx_oword_t tx_desc_ptr;
544
545 /* Stop the hardware using the queue */
546 if (falcon_flush_tx_queue(tx_queue))
547 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
548
549 /* Remove TX descriptor ring from card */
550 EFX_ZERO_OWORD(tx_desc_ptr);
551 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
552 tx_queue->queue);
553
554 /* Unpin TX descriptor ring */
555 falcon_fini_special_buffer(efx, &tx_queue->txd);
556 }
557
558 /* Free buffers backing TX queue */
559 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
560 {
561 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
562 }
563
564 /**************************************************************************
565 *
566 * Falcon RX path
567 *
568 **************************************************************************/
569
570 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
571 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
572 unsigned int index)
573 {
574 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
575 }
576
577 /* This creates an entry in the RX descriptor queue */
578 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
579 unsigned index)
580 {
581 struct efx_rx_buffer *rx_buf;
582 efx_qword_t *rxd;
583
584 rxd = falcon_rx_desc(rx_queue, index);
585 rx_buf = efx_rx_buffer(rx_queue, index);
586 EFX_POPULATE_QWORD_3(*rxd,
587 RX_KER_BUF_SIZE,
588 rx_buf->len -
589 rx_queue->efx->type->rx_buffer_padding,
590 RX_KER_BUF_REGION, 0,
591 RX_KER_BUF_ADR, rx_buf->dma_addr);
592 }
593
594 /* This writes to the RX_DESC_WPTR register for the specified receive
595 * descriptor ring.
596 */
597 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
598 {
599 efx_dword_t reg;
600 unsigned write_ptr;
601
602 while (rx_queue->notified_count != rx_queue->added_count) {
603 falcon_build_rx_desc(rx_queue,
604 rx_queue->notified_count &
605 FALCON_RXD_RING_MASK);
606 ++rx_queue->notified_count;
607 }
608
609 wmb();
610 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
611 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
612 falcon_writel_page(rx_queue->efx, &reg,
613 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
614 }
615
616 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
617 {
618 struct efx_nic *efx = rx_queue->efx;
619 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
620 FALCON_RXD_RING_SIZE *
621 sizeof(efx_qword_t));
622 }
623
624 int falcon_init_rx(struct efx_rx_queue *rx_queue)
625 {
626 efx_oword_t rx_desc_ptr;
627 struct efx_nic *efx = rx_queue->efx;
628 int rc;
629 int is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
630 int iscsi_digest_en = is_b0;
631
632 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
633 rx_queue->queue, rx_queue->rxd.index,
634 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
635
636 /* Pin RX descriptor ring */
637 rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
638 if (rc)
639 return rc;
640
641 /* Push RX descriptor ring to card */
642 EFX_POPULATE_OWORD_10(rx_desc_ptr,
643 RX_ISCSI_DDIG_EN, iscsi_digest_en,
644 RX_ISCSI_HDIG_EN, iscsi_digest_en,
645 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
646 RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
647 RX_DESCQ_OWNER_ID, 0,
648 RX_DESCQ_LABEL, rx_queue->queue,
649 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
650 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
651 /* For >=B0 this is scatter so disable */
652 RX_DESCQ_JUMBO, !is_b0,
653 RX_DESCQ_EN, 1);
654 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
655 rx_queue->queue);
656 return 0;
657 }
658
659 static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
660 {
661 struct efx_nic *efx = rx_queue->efx;
662 struct efx_channel *channel = &efx->channel[0];
663 unsigned int read_ptr, i;
664 efx_oword_t rx_flush_descq;
665
666 /* Post a flush command */
667 EFX_POPULATE_OWORD_2(rx_flush_descq,
668 RX_FLUSH_DESCQ_CMD, 1,
669 RX_FLUSH_DESCQ, rx_queue->queue);
670 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
671 msleep(FALCON_FLUSH_TIMEOUT);
672
673 if (EFX_WORKAROUND_7803(efx))
674 return 0;
675
676 /* Look for a flush completed event */
677 read_ptr = channel->eventq_read_ptr;
678 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
679 efx_qword_t *event = falcon_event(channel, read_ptr);
680 int ev_code, ev_sub_code, ev_queue, ev_failed;
681 if (!falcon_event_present(event))
682 break;
683
684 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
685 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
686 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
687 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
688
689 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
690 (ev_queue == rx_queue->queue)) {
691 if (ev_failed) {
692 EFX_INFO(efx, "rx queue %d flush command "
693 "failed\n", rx_queue->queue);
694 return -EAGAIN;
695 } else {
696 EFX_LOG(efx, "rx queue %d flush command "
697 "succesful\n", rx_queue->queue);
698 return 0;
699 }
700 }
701
702 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
703 }
704
705 if (EFX_WORKAROUND_11557(efx)) {
706 efx_oword_t reg;
707 int enabled;
708
709 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
710 rx_queue->queue);
711 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
712 if (!enabled) {
713 EFX_LOG(efx, "rx queue %d disabled without a "
714 "flush event seen\n", rx_queue->queue);
715 return 0;
716 }
717 }
718
719 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
720 return -ETIMEDOUT;
721 }
722
723 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
724 {
725 efx_oword_t rx_desc_ptr;
726 struct efx_nic *efx = rx_queue->efx;
727 int i, rc;
728
729 /* Try and flush the rx queue. This may need to be repeated */
730 for (i = 0; i < 5; i++) {
731 rc = falcon_flush_rx_queue(rx_queue);
732 if (rc == -EAGAIN)
733 continue;
734 break;
735 }
736 if (rc) {
737 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
738 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
739 }
740
741 /* Remove RX descriptor ring from card */
742 EFX_ZERO_OWORD(rx_desc_ptr);
743 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
744 rx_queue->queue);
745
746 /* Unpin RX descriptor ring */
747 falcon_fini_special_buffer(efx, &rx_queue->rxd);
748 }
749
750 /* Free buffers backing RX queue */
751 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
752 {
753 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
754 }
755
756 /**************************************************************************
757 *
758 * Falcon event queue processing
759 * Event queues are processed by per-channel tasklets.
760 *
761 **************************************************************************/
762
763 /* Update a channel's event queue's read pointer (RPTR) register
764 *
765 * This writes the EVQ_RPTR_REG register for the specified channel's
766 * event queue.
767 *
768 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
769 * whereas channel->eventq_read_ptr contains the index of the "next to
770 * read" event.
771 */
772 void falcon_eventq_read_ack(struct efx_channel *channel)
773 {
774 efx_dword_t reg;
775 struct efx_nic *efx = channel->efx;
776
777 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
778 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
779 channel->evqnum);
780 }
781
782 /* Use HW to insert a SW defined event */
783 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
784 {
785 efx_oword_t drv_ev_reg;
786
787 EFX_POPULATE_OWORD_2(drv_ev_reg,
788 DRV_EV_QID, channel->evqnum,
789 DRV_EV_DATA,
790 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
791 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
792 }
793
794 /* Handle a transmit completion event
795 *
796 * Falcon batches TX completion events; the message we receive is of
797 * the form "complete all TX events up to this index".
798 */
799 static inline void falcon_handle_tx_event(struct efx_channel *channel,
800 efx_qword_t *event)
801 {
802 unsigned int tx_ev_desc_ptr;
803 unsigned int tx_ev_q_label;
804 struct efx_tx_queue *tx_queue;
805 struct efx_nic *efx = channel->efx;
806
807 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
808 /* Transmit completion */
809 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
810 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
811 tx_queue = &efx->tx_queue[tx_ev_q_label];
812 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
813 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
814 /* Rewrite the FIFO write pointer */
815 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
816 tx_queue = &efx->tx_queue[tx_ev_q_label];
817
818 if (efx_dev_registered(efx))
819 netif_tx_lock(efx->net_dev);
820 falcon_notify_tx_desc(tx_queue);
821 if (efx_dev_registered(efx))
822 netif_tx_unlock(efx->net_dev);
823 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
824 EFX_WORKAROUND_10727(efx)) {
825 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
826 } else {
827 EFX_ERR(efx, "channel %d unexpected TX event "
828 EFX_QWORD_FMT"\n", channel->channel,
829 EFX_QWORD_VAL(*event));
830 }
831 }
832
833 /* Check received packet's destination MAC address. */
834 static int check_dest_mac(struct efx_rx_queue *rx_queue,
835 const efx_qword_t *event)
836 {
837 struct efx_rx_buffer *rx_buf;
838 struct efx_nic *efx = rx_queue->efx;
839 int rx_ev_desc_ptr;
840 struct ethhdr *eh;
841
842 if (efx->promiscuous)
843 return 1;
844
845 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
846 rx_buf = efx_rx_buffer(rx_queue, rx_ev_desc_ptr);
847 eh = (struct ethhdr *)rx_buf->data;
848 if (memcmp(eh->h_dest, efx->net_dev->dev_addr, ETH_ALEN))
849 return 0;
850 return 1;
851 }
852
853 /* Detect errors included in the rx_evt_pkt_ok bit. */
854 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
855 const efx_qword_t *event,
856 unsigned *rx_ev_pkt_ok,
857 int *discard, int byte_count)
858 {
859 struct efx_nic *efx = rx_queue->efx;
860 unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
861 unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
862 unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
863 unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
864 unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
865 int snap, non_ip;
866
867 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
868 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
869 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
870 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
871 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
872 RX_EV_BUF_OWNER_ID_ERR);
873 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
874 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
875 RX_EV_IP_HDR_CHKSUM_ERR);
876 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
877 RX_EV_TCP_UDP_CHKSUM_ERR);
878 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
879 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
880 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
881 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
882 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
883
884 /* Every error apart from tobe_disc and pause_frm */
885 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
886 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
887 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
888
889 snap = (rx_ev_pkt_type == RX_EV_PKT_TYPE_LLC_DECODE) ||
890 (rx_ev_pkt_type == RX_EV_PKT_TYPE_VLAN_LLC_DECODE);
891 non_ip = (rx_ev_hdr_type == RX_EV_HDR_TYPE_NON_IP_DECODE);
892
893 /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
894 * length field of an LLC frame, which sets TOBE_DISC. We could set
895 * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
896 * protect the RX block).
897 *
898 * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
899 * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
900 * LLC can't encapsulate IP, so by definition
901 * these packets are NON_IP.
902 *
903 * Unicast mismatch will also cause TOBE_DISC, so the driver needs
904 * to check this.
905 */
906 if (EFX_WORKAROUND_5475(efx) && rx_ev_tobe_disc && (snap || non_ip)) {
907 /* If all the other flags are zero then we can state the
908 * entire packet is ok, which will flag to the kernel not
909 * to recalculate checksums.
910 */
911 if (!(non_ip | rx_ev_other_err | rx_ev_pause_frm))
912 *rx_ev_pkt_ok = 1;
913
914 rx_ev_tobe_disc = 0;
915
916 /* TOBE_DISC is set for unicast mismatch. But given that
917 * we can't trust TOBE_DISC here, we must validate the dest
918 * MAC address ourselves.
919 */
920 if (!rx_ev_mcast_pkt && !check_dest_mac(rx_queue, event))
921 rx_ev_tobe_disc = 1;
922 }
923
924 /* Count errors that are not in MAC stats. */
925 if (rx_ev_frm_trunc)
926 ++rx_queue->channel->n_rx_frm_trunc;
927 else if (rx_ev_tobe_disc)
928 ++rx_queue->channel->n_rx_tobe_disc;
929 else if (rx_ev_ip_hdr_chksum_err)
930 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
931 else if (rx_ev_tcp_udp_chksum_err)
932 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
933 if (rx_ev_ip_frag_err)
934 ++rx_queue->channel->n_rx_ip_frag_err;
935
936 /* The frame must be discarded if any of these are true. */
937 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
938 rx_ev_tobe_disc | rx_ev_pause_frm);
939
940 /* TOBE_DISC is expected on unicast mismatches; don't print out an
941 * error message. FRM_TRUNC indicates RXDP dropped the packet due
942 * to a FIFO overflow.
943 */
944 #ifdef EFX_ENABLE_DEBUG
945 if (rx_ev_other_err) {
946 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
947 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s%s\n",
948 rx_queue->queue, EFX_QWORD_VAL(*event),
949 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
950 rx_ev_ip_hdr_chksum_err ?
951 " [IP_HDR_CHKSUM_ERR]" : "",
952 rx_ev_tcp_udp_chksum_err ?
953 " [TCP_UDP_CHKSUM_ERR]" : "",
954 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
955 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
956 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
957 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
958 rx_ev_pause_frm ? " [PAUSE]" : "",
959 snap ? " [SNAP/LLC]" : "");
960 }
961 #endif
962
963 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
964 efx->phy_type == PHY_TYPE_10XPRESS))
965 tenxpress_crc_err(efx);
966 }
967
968 /* Handle receive events that are not in-order. */
969 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
970 unsigned index)
971 {
972 struct efx_nic *efx = rx_queue->efx;
973 unsigned expected, dropped;
974
975 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
976 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
977 FALCON_RXD_RING_MASK);
978 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
979 dropped, index, expected);
980
981 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
982 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
983 }
984
985 /* Handle a packet received event
986 *
987 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
988 * wrong destination address
989 * Also "is multicast" and "matches multicast filter" flags can be used to
990 * discard non-matching multicast packets.
991 */
992 static inline int falcon_handle_rx_event(struct efx_channel *channel,
993 const efx_qword_t *event)
994 {
995 unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
996 unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
997 unsigned expected_ptr;
998 int discard = 0, checksummed;
999 struct efx_rx_queue *rx_queue;
1000 struct efx_nic *efx = channel->efx;
1001
1002 /* Basic packet information */
1003 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
1004 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
1005 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
1006 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
1007 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
1008
1009 rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
1010 rx_queue = &efx->rx_queue[rx_ev_q_label];
1011
1012 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
1013 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
1014 if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
1015 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
1016 return rx_ev_q_label;
1017 }
1018
1019 if (likely(rx_ev_pkt_ok)) {
1020 /* If packet is marked as OK and packet type is TCP/IPv4 or
1021 * UDP/IPv4, then we can rely on the hardware checksum.
1022 */
1023 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
1024 } else {
1025 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
1026 &discard, rx_ev_byte_cnt);
1027 checksummed = 0;
1028 }
1029
1030 /* Detect multicast packets that didn't match the filter */
1031 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
1032 if (rx_ev_mcast_pkt) {
1033 unsigned int rx_ev_mcast_hash_match =
1034 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
1035
1036 if (unlikely(!rx_ev_mcast_hash_match))
1037 discard = 1;
1038 }
1039
1040 /* Handle received packet */
1041 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1042 checksummed, discard);
1043
1044 return rx_ev_q_label;
1045 }
1046
1047 /* Global events are basically PHY events */
1048 static void falcon_handle_global_event(struct efx_channel *channel,
1049 efx_qword_t *event)
1050 {
1051 struct efx_nic *efx = channel->efx;
1052 int is_phy_event = 0, handled = 0;
1053
1054 /* Check for interrupt on either port. Some boards have a
1055 * single PHY wired to the interrupt line for port 1. */
1056 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1057 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1058 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1059 is_phy_event = 1;
1060
1061 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
1062 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1063 is_phy_event = 1;
1064
1065 if (is_phy_event) {
1066 efx->phy_op->clear_interrupt(efx);
1067 queue_work(efx->workqueue, &efx->reconfigure_work);
1068 handled = 1;
1069 }
1070
1071 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1072 EFX_ERR(efx, "channel %d seen global RX_RESET "
1073 "event. Resetting.\n", channel->channel);
1074
1075 atomic_inc(&efx->rx_reset);
1076 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1077 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1078 handled = 1;
1079 }
1080
1081 if (!handled)
1082 EFX_ERR(efx, "channel %d unknown global event "
1083 EFX_QWORD_FMT "\n", channel->channel,
1084 EFX_QWORD_VAL(*event));
1085 }
1086
1087 static void falcon_handle_driver_event(struct efx_channel *channel,
1088 efx_qword_t *event)
1089 {
1090 struct efx_nic *efx = channel->efx;
1091 unsigned int ev_sub_code;
1092 unsigned int ev_sub_data;
1093
1094 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1095 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1096
1097 switch (ev_sub_code) {
1098 case TX_DESCQ_FLS_DONE_EV_DECODE:
1099 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1100 channel->channel, ev_sub_data);
1101 break;
1102 case RX_DESCQ_FLS_DONE_EV_DECODE:
1103 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1104 channel->channel, ev_sub_data);
1105 break;
1106 case EVQ_INIT_DONE_EV_DECODE:
1107 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1108 channel->channel, ev_sub_data);
1109 break;
1110 case SRM_UPD_DONE_EV_DECODE:
1111 EFX_TRACE(efx, "channel %d SRAM update done\n",
1112 channel->channel);
1113 break;
1114 case WAKE_UP_EV_DECODE:
1115 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1116 channel->channel, ev_sub_data);
1117 break;
1118 case TIMER_EV_DECODE:
1119 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1120 channel->channel, ev_sub_data);
1121 break;
1122 case RX_RECOVERY_EV_DECODE:
1123 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1124 "Resetting.\n", channel->channel);
1125 atomic_inc(&efx->rx_reset);
1126 efx_schedule_reset(efx,
1127 EFX_WORKAROUND_6555(efx) ?
1128 RESET_TYPE_RX_RECOVERY :
1129 RESET_TYPE_DISABLE);
1130 break;
1131 case RX_DSC_ERROR_EV_DECODE:
1132 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1133 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1134 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1135 break;
1136 case TX_DSC_ERROR_EV_DECODE:
1137 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1138 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1139 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1140 break;
1141 default:
1142 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1143 "data %04x\n", channel->channel, ev_sub_code,
1144 ev_sub_data);
1145 break;
1146 }
1147 }
1148
1149 int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1150 {
1151 unsigned int read_ptr;
1152 efx_qword_t event, *p_event;
1153 int ev_code;
1154 int rxq;
1155 int rxdmaqs = 0;
1156
1157 read_ptr = channel->eventq_read_ptr;
1158
1159 do {
1160 p_event = falcon_event(channel, read_ptr);
1161 event = *p_event;
1162
1163 if (!falcon_event_present(&event))
1164 /* End of events */
1165 break;
1166
1167 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1168 channel->channel, EFX_QWORD_VAL(event));
1169
1170 /* Clear this event by marking it all ones */
1171 EFX_SET_QWORD(*p_event);
1172
1173 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1174
1175 switch (ev_code) {
1176 case RX_IP_EV_DECODE:
1177 rxq = falcon_handle_rx_event(channel, &event);
1178 rxdmaqs |= (1 << rxq);
1179 (*rx_quota)--;
1180 break;
1181 case TX_IP_EV_DECODE:
1182 falcon_handle_tx_event(channel, &event);
1183 break;
1184 case DRV_GEN_EV_DECODE:
1185 channel->eventq_magic
1186 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1187 EFX_LOG(channel->efx, "channel %d received generated "
1188 "event "EFX_QWORD_FMT"\n", channel->channel,
1189 EFX_QWORD_VAL(event));
1190 break;
1191 case GLOBAL_EV_DECODE:
1192 falcon_handle_global_event(channel, &event);
1193 break;
1194 case DRIVER_EV_DECODE:
1195 falcon_handle_driver_event(channel, &event);
1196 break;
1197 default:
1198 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1199 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1200 ev_code, EFX_QWORD_VAL(event));
1201 }
1202
1203 /* Increment read pointer */
1204 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1205
1206 } while (*rx_quota);
1207
1208 channel->eventq_read_ptr = read_ptr;
1209 return rxdmaqs;
1210 }
1211
1212 void falcon_set_int_moderation(struct efx_channel *channel)
1213 {
1214 efx_dword_t timer_cmd;
1215 struct efx_nic *efx = channel->efx;
1216
1217 /* Set timer register */
1218 if (channel->irq_moderation) {
1219 /* Round to resolution supported by hardware. The value we
1220 * program is based at 0. So actual interrupt moderation
1221 * achieved is ((x + 1) * res).
1222 */
1223 unsigned int res = 5;
1224 channel->irq_moderation -= (channel->irq_moderation % res);
1225 if (channel->irq_moderation < res)
1226 channel->irq_moderation = res;
1227 EFX_POPULATE_DWORD_2(timer_cmd,
1228 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1229 TIMER_VAL,
1230 (channel->irq_moderation / res) - 1);
1231 } else {
1232 EFX_POPULATE_DWORD_2(timer_cmd,
1233 TIMER_MODE, TIMER_MODE_DIS,
1234 TIMER_VAL, 0);
1235 }
1236 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1237 channel->evqnum);
1238
1239 }
1240
1241 /* Allocate buffer table entries for event queue */
1242 int falcon_probe_eventq(struct efx_channel *channel)
1243 {
1244 struct efx_nic *efx = channel->efx;
1245 unsigned int evq_size;
1246
1247 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1248 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1249 }
1250
1251 int falcon_init_eventq(struct efx_channel *channel)
1252 {
1253 efx_oword_t evq_ptr;
1254 struct efx_nic *efx = channel->efx;
1255 int rc;
1256
1257 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1258 channel->channel, channel->eventq.index,
1259 channel->eventq.index + channel->eventq.entries - 1);
1260
1261 /* Pin event queue buffer */
1262 rc = falcon_init_special_buffer(efx, &channel->eventq);
1263 if (rc)
1264 return rc;
1265
1266 /* Fill event queue with all ones (i.e. empty events) */
1267 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1268
1269 /* Push event queue to card */
1270 EFX_POPULATE_OWORD_3(evq_ptr,
1271 EVQ_EN, 1,
1272 EVQ_SIZE, FALCON_EVQ_ORDER,
1273 EVQ_BUF_BASE_ID, channel->eventq.index);
1274 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1275 channel->evqnum);
1276
1277 falcon_set_int_moderation(channel);
1278
1279 return 0;
1280 }
1281
1282 void falcon_fini_eventq(struct efx_channel *channel)
1283 {
1284 efx_oword_t eventq_ptr;
1285 struct efx_nic *efx = channel->efx;
1286
1287 /* Remove event queue from card */
1288 EFX_ZERO_OWORD(eventq_ptr);
1289 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1290 channel->evqnum);
1291
1292 /* Unpin event queue */
1293 falcon_fini_special_buffer(efx, &channel->eventq);
1294 }
1295
1296 /* Free buffers backing event queue */
1297 void falcon_remove_eventq(struct efx_channel *channel)
1298 {
1299 falcon_free_special_buffer(channel->efx, &channel->eventq);
1300 }
1301
1302
1303 /* Generates a test event on the event queue. A subsequent call to
1304 * process_eventq() should pick up the event and place the value of
1305 * "magic" into channel->eventq_magic;
1306 */
1307 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1308 {
1309 efx_qword_t test_event;
1310
1311 EFX_POPULATE_QWORD_2(test_event,
1312 EV_CODE, DRV_GEN_EV_DECODE,
1313 EVQ_MAGIC, magic);
1314 falcon_generate_event(channel, &test_event);
1315 }
1316
1317
1318 /**************************************************************************
1319 *
1320 * Falcon hardware interrupts
1321 * The hardware interrupt handler does very little work; all the event
1322 * queue processing is carried out by per-channel tasklets.
1323 *
1324 **************************************************************************/
1325
1326 /* Enable/disable/generate Falcon interrupts */
1327 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1328 int force)
1329 {
1330 efx_oword_t int_en_reg_ker;
1331
1332 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1333 KER_INT_KER, force,
1334 DRV_INT_EN_KER, enabled);
1335 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1336 }
1337
1338 void falcon_enable_interrupts(struct efx_nic *efx)
1339 {
1340 efx_oword_t int_adr_reg_ker;
1341 struct efx_channel *channel;
1342
1343 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1344 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1345
1346 /* Program address */
1347 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1348 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1349 INT_ADR_KER, efx->irq_status.dma_addr);
1350 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1351
1352 /* Enable interrupts */
1353 falcon_interrupts(efx, 1, 0);
1354
1355 /* Force processing of all the channels to get the EVQ RPTRs up to
1356 date */
1357 efx_for_each_channel_with_interrupt(channel, efx)
1358 efx_schedule_channel(channel);
1359 }
1360
1361 void falcon_disable_interrupts(struct efx_nic *efx)
1362 {
1363 /* Disable interrupts */
1364 falcon_interrupts(efx, 0, 0);
1365 }
1366
1367 /* Generate a Falcon test interrupt
1368 * Interrupt must already have been enabled, otherwise nasty things
1369 * may happen.
1370 */
1371 void falcon_generate_interrupt(struct efx_nic *efx)
1372 {
1373 falcon_interrupts(efx, 1, 1);
1374 }
1375
1376 /* Acknowledge a legacy interrupt from Falcon
1377 *
1378 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1379 *
1380 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1381 * BIU. Interrupt acknowledge is read sensitive so must write instead
1382 * (then read to ensure the BIU collector is flushed)
1383 *
1384 * NB most hardware supports MSI interrupts
1385 */
1386 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1387 {
1388 efx_dword_t reg;
1389
1390 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1391 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1392 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1393 }
1394
1395 /* Process a fatal interrupt
1396 * Disable bus mastering ASAP and schedule a reset
1397 */
1398 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1399 {
1400 struct falcon_nic_data *nic_data = efx->nic_data;
1401 efx_oword_t *int_ker = efx->irq_status.addr;
1402 efx_oword_t fatal_intr;
1403 int error, mem_perr;
1404 static int n_int_errors;
1405
1406 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1407 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1408
1409 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1410 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1411 EFX_OWORD_VAL(fatal_intr),
1412 error ? "disabling bus mastering" : "no recognised error");
1413 if (error == 0)
1414 goto out;
1415
1416 /* If this is a memory parity error dump which blocks are offending */
1417 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1418 if (mem_perr) {
1419 efx_oword_t reg;
1420 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1421 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1422 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1423 }
1424
1425 /* Disable DMA bus mastering on both devices */
1426 pci_disable_device(efx->pci_dev);
1427 if (FALCON_IS_DUAL_FUNC(efx))
1428 pci_disable_device(nic_data->pci_dev2);
1429
1430 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1431 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1432 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1433 } else {
1434 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1435 "NIC will be disabled\n");
1436 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1437 }
1438 out:
1439 return IRQ_HANDLED;
1440 }
1441
1442 /* Handle a legacy interrupt from Falcon
1443 * Acknowledges the interrupt and schedule event queue processing.
1444 */
1445 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1446 {
1447 struct efx_nic *efx = dev_id;
1448 efx_oword_t *int_ker = efx->irq_status.addr;
1449 struct efx_channel *channel;
1450 efx_dword_t reg;
1451 u32 queues;
1452 int syserr;
1453
1454 /* Read the ISR which also ACKs the interrupts */
1455 falcon_readl(efx, &reg, INT_ISR0_B0);
1456 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1457
1458 /* Check to see if we have a serious error condition */
1459 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1460 if (unlikely(syserr))
1461 return falcon_fatal_interrupt(efx);
1462
1463 if (queues == 0)
1464 return IRQ_NONE;
1465
1466 efx->last_irq_cpu = raw_smp_processor_id();
1467 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1468 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1469
1470 /* Schedule processing of any interrupting queues */
1471 channel = &efx->channel[0];
1472 while (queues) {
1473 if (queues & 0x01)
1474 efx_schedule_channel(channel);
1475 channel++;
1476 queues >>= 1;
1477 }
1478
1479 return IRQ_HANDLED;
1480 }
1481
1482
1483 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1484 {
1485 struct efx_nic *efx = dev_id;
1486 efx_oword_t *int_ker = efx->irq_status.addr;
1487 struct efx_channel *channel;
1488 int syserr;
1489 int queues;
1490
1491 /* Check to see if this is our interrupt. If it isn't, we
1492 * exit without having touched the hardware.
1493 */
1494 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1495 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1496 raw_smp_processor_id());
1497 return IRQ_NONE;
1498 }
1499 efx->last_irq_cpu = raw_smp_processor_id();
1500 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1501 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1502
1503 /* Check to see if we have a serious error condition */
1504 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1505 if (unlikely(syserr))
1506 return falcon_fatal_interrupt(efx);
1507
1508 /* Determine interrupting queues, clear interrupt status
1509 * register and acknowledge the device interrupt.
1510 */
1511 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1512 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1513 EFX_ZERO_OWORD(*int_ker);
1514 wmb(); /* Ensure the vector is cleared before interrupt ack */
1515 falcon_irq_ack_a1(efx);
1516
1517 /* Schedule processing of any interrupting queues */
1518 channel = &efx->channel[0];
1519 while (queues) {
1520 if (queues & 0x01)
1521 efx_schedule_channel(channel);
1522 channel++;
1523 queues >>= 1;
1524 }
1525
1526 return IRQ_HANDLED;
1527 }
1528
1529 /* Handle an MSI interrupt from Falcon
1530 *
1531 * Handle an MSI hardware interrupt. This routine schedules event
1532 * queue processing. No interrupt acknowledgement cycle is necessary.
1533 * Also, we never need to check that the interrupt is for us, since
1534 * MSI interrupts cannot be shared.
1535 */
1536 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1537 {
1538 struct efx_channel *channel = dev_id;
1539 struct efx_nic *efx = channel->efx;
1540 efx_oword_t *int_ker = efx->irq_status.addr;
1541 int syserr;
1542
1543 efx->last_irq_cpu = raw_smp_processor_id();
1544 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1545 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1546
1547 /* Check to see if we have a serious error condition */
1548 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1549 if (unlikely(syserr))
1550 return falcon_fatal_interrupt(efx);
1551
1552 /* Schedule processing of the channel */
1553 efx_schedule_channel(channel);
1554
1555 return IRQ_HANDLED;
1556 }
1557
1558
1559 /* Setup RSS indirection table.
1560 * This maps from the hash value of the packet to RXQ
1561 */
1562 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1563 {
1564 int i = 0;
1565 unsigned long offset;
1566 efx_dword_t dword;
1567
1568 if (falcon_rev(efx) < FALCON_REV_B0)
1569 return;
1570
1571 for (offset = RX_RSS_INDIR_TBL_B0;
1572 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1573 offset += 0x10) {
1574 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1575 i % efx->rss_queues);
1576 falcon_writel(efx, &dword, offset);
1577 i++;
1578 }
1579 }
1580
1581 /* Hook interrupt handler(s)
1582 * Try MSI and then legacy interrupts.
1583 */
1584 int falcon_init_interrupt(struct efx_nic *efx)
1585 {
1586 struct efx_channel *channel;
1587 int rc;
1588
1589 if (!EFX_INT_MODE_USE_MSI(efx)) {
1590 irq_handler_t handler;
1591 if (falcon_rev(efx) >= FALCON_REV_B0)
1592 handler = falcon_legacy_interrupt_b0;
1593 else
1594 handler = falcon_legacy_interrupt_a1;
1595
1596 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1597 efx->name, efx);
1598 if (rc) {
1599 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1600 efx->pci_dev->irq);
1601 goto fail1;
1602 }
1603 return 0;
1604 }
1605
1606 /* Hook MSI or MSI-X interrupt */
1607 efx_for_each_channel_with_interrupt(channel, efx) {
1608 rc = request_irq(channel->irq, falcon_msi_interrupt,
1609 IRQF_PROBE_SHARED, /* Not shared */
1610 efx->name, channel);
1611 if (rc) {
1612 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1613 goto fail2;
1614 }
1615 }
1616
1617 return 0;
1618
1619 fail2:
1620 efx_for_each_channel_with_interrupt(channel, efx)
1621 free_irq(channel->irq, channel);
1622 fail1:
1623 return rc;
1624 }
1625
1626 void falcon_fini_interrupt(struct efx_nic *efx)
1627 {
1628 struct efx_channel *channel;
1629 efx_oword_t reg;
1630
1631 /* Disable MSI/MSI-X interrupts */
1632 efx_for_each_channel_with_interrupt(channel, efx) {
1633 if (channel->irq)
1634 free_irq(channel->irq, channel);
1635 }
1636
1637 /* ACK legacy interrupt */
1638 if (falcon_rev(efx) >= FALCON_REV_B0)
1639 falcon_read(efx, &reg, INT_ISR0_B0);
1640 else
1641 falcon_irq_ack_a1(efx);
1642
1643 /* Disable legacy interrupt */
1644 if (efx->legacy_irq)
1645 free_irq(efx->legacy_irq, efx);
1646 }
1647
1648 /**************************************************************************
1649 *
1650 * EEPROM/flash
1651 *
1652 **************************************************************************
1653 */
1654
1655 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1656
1657 /* Wait for SPI command completion */
1658 static int falcon_spi_wait(struct efx_nic *efx)
1659 {
1660 efx_oword_t reg;
1661 int cmd_en, timer_active;
1662 int count;
1663
1664 count = 0;
1665 do {
1666 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1667 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1668 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1669 if (!cmd_en && !timer_active)
1670 return 0;
1671 udelay(10);
1672 } while (++count < 10000); /* wait upto 100msec */
1673 EFX_ERR(efx, "timed out waiting for SPI\n");
1674 return -ETIMEDOUT;
1675 }
1676
1677 static int
1678 falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
1679 unsigned int address, unsigned int addr_len,
1680 void *data, unsigned int len)
1681 {
1682 efx_oword_t reg;
1683 int rc;
1684
1685 BUG_ON(len > FALCON_SPI_MAX_LEN);
1686
1687 /* Check SPI not currently being accessed */
1688 rc = falcon_spi_wait(efx);
1689 if (rc)
1690 return rc;
1691
1692 /* Program address register */
1693 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1694 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1695
1696 /* Issue read command */
1697 EFX_POPULATE_OWORD_7(reg,
1698 EE_SPI_HCMD_CMD_EN, 1,
1699 EE_SPI_HCMD_SF_SEL, device_id,
1700 EE_SPI_HCMD_DABCNT, len,
1701 EE_SPI_HCMD_READ, EE_SPI_READ,
1702 EE_SPI_HCMD_DUBCNT, 0,
1703 EE_SPI_HCMD_ADBCNT, addr_len,
1704 EE_SPI_HCMD_ENC, command);
1705 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1706
1707 /* Wait for read to complete */
1708 rc = falcon_spi_wait(efx);
1709 if (rc)
1710 return rc;
1711
1712 /* Read data */
1713 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1714 memcpy(data, &reg, len);
1715 return 0;
1716 }
1717
1718 /**************************************************************************
1719 *
1720 * MAC wrapper
1721 *
1722 **************************************************************************
1723 */
1724 void falcon_drain_tx_fifo(struct efx_nic *efx)
1725 {
1726 efx_oword_t temp;
1727 int count;
1728
1729 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1730 (efx->loopback_mode != LOOPBACK_NONE))
1731 return;
1732
1733 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1734 /* There is no point in draining more than once */
1735 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1736 return;
1737
1738 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1739 * the drain sequence with the statistics fetch */
1740 spin_lock(&efx->stats_lock);
1741
1742 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1743 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1744
1745 /* Reset the MAC and EM block. */
1746 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1747 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1748 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1749 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1750 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1751
1752 count = 0;
1753 while (1) {
1754 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1755 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1756 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1757 !EFX_OWORD_FIELD(temp, RST_EM)) {
1758 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1759 count);
1760 break;
1761 }
1762 if (count > 20) {
1763 EFX_ERR(efx, "MAC reset failed\n");
1764 break;
1765 }
1766 count++;
1767 udelay(10);
1768 }
1769
1770 spin_unlock(&efx->stats_lock);
1771
1772 /* If we've reset the EM block and the link is up, then
1773 * we'll have to kick the XAUI link so the PHY can recover */
1774 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1775 falcon_reset_xaui(efx);
1776 }
1777
1778 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1779 {
1780 efx_oword_t temp;
1781
1782 if (falcon_rev(efx) < FALCON_REV_B0)
1783 return;
1784
1785 /* Isolate the MAC -> RX */
1786 falcon_read(efx, &temp, RX_CFG_REG_KER);
1787 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1788 falcon_write(efx, &temp, RX_CFG_REG_KER);
1789
1790 if (!efx->link_up)
1791 falcon_drain_tx_fifo(efx);
1792 }
1793
1794 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1795 {
1796 efx_oword_t reg;
1797 int link_speed;
1798 unsigned int tx_fc;
1799
1800 if (efx->link_options & GM_LPA_10000)
1801 link_speed = 0x3;
1802 else if (efx->link_options & GM_LPA_1000)
1803 link_speed = 0x2;
1804 else if (efx->link_options & GM_LPA_100)
1805 link_speed = 0x1;
1806 else
1807 link_speed = 0x0;
1808 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1809 * as advertised. Disable to ensure packets are not
1810 * indefinitely held and TX queue can be flushed at any point
1811 * while the link is down. */
1812 EFX_POPULATE_OWORD_5(reg,
1813 MAC_XOFF_VAL, 0xffff /* max pause time */,
1814 MAC_BCAD_ACPT, 1,
1815 MAC_UC_PROM, efx->promiscuous,
1816 MAC_LINK_STATUS, 1, /* always set */
1817 MAC_SPEED, link_speed);
1818 /* On B0, MAC backpressure can be disabled and packets get
1819 * discarded. */
1820 if (falcon_rev(efx) >= FALCON_REV_B0) {
1821 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1822 !efx->link_up);
1823 }
1824
1825 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1826
1827 /* Restore the multicast hash registers. */
1828 falcon_set_multicast_hash(efx);
1829
1830 /* Transmission of pause frames when RX crosses the threshold is
1831 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1832 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1833 tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
1834 falcon_read(efx, &reg, RX_CFG_REG_KER);
1835 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1836
1837 /* Unisolate the MAC -> RX */
1838 if (falcon_rev(efx) >= FALCON_REV_B0)
1839 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1840 falcon_write(efx, &reg, RX_CFG_REG_KER);
1841 }
1842
1843 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1844 {
1845 efx_oword_t reg;
1846 u32 *dma_done;
1847 int i;
1848
1849 if (disable_dma_stats)
1850 return 0;
1851
1852 /* Statistics fetch will fail if the MAC is in TX drain */
1853 if (falcon_rev(efx) >= FALCON_REV_B0) {
1854 efx_oword_t temp;
1855 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1856 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1857 return 0;
1858 }
1859
1860 dma_done = (efx->stats_buffer.addr + done_offset);
1861 *dma_done = FALCON_STATS_NOT_DONE;
1862 wmb(); /* ensure done flag is clear */
1863
1864 /* Initiate DMA transfer of stats */
1865 EFX_POPULATE_OWORD_2(reg,
1866 MAC_STAT_DMA_CMD, 1,
1867 MAC_STAT_DMA_ADR,
1868 efx->stats_buffer.dma_addr);
1869 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1870
1871 /* Wait for transfer to complete */
1872 for (i = 0; i < 400; i++) {
1873 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1874 return 0;
1875 udelay(10);
1876 }
1877
1878 EFX_ERR(efx, "timed out waiting for statistics\n");
1879 return -ETIMEDOUT;
1880 }
1881
1882 /**************************************************************************
1883 *
1884 * PHY access via GMII
1885 *
1886 **************************************************************************
1887 */
1888
1889 /* Use the top bit of the MII PHY id to indicate the PHY type
1890 * (1G/10G), with the remaining bits as the actual PHY id.
1891 *
1892 * This allows us to avoid leaking information from the mii_if_info
1893 * structure into other data structures.
1894 */
1895 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1896 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1897 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1898 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1899 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1900
1901
1902 /* Packing the clause 45 port and device fields into a single value */
1903 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1904 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1905 #define MD_DEV_ADR_COMP_LBN 0
1906 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1907
1908
1909 /* Wait for GMII access to complete */
1910 static int falcon_gmii_wait(struct efx_nic *efx)
1911 {
1912 efx_dword_t md_stat;
1913 int count;
1914
1915 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
1916 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1917 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1918 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1919 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1920 EFX_ERR(efx, "error from GMII access "
1921 EFX_DWORD_FMT"\n",
1922 EFX_DWORD_VAL(md_stat));
1923 return -EIO;
1924 }
1925 return 0;
1926 }
1927 udelay(10);
1928 }
1929 EFX_ERR(efx, "timed out waiting for GMII\n");
1930 return -ETIMEDOUT;
1931 }
1932
1933 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1934 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
1935 int addr, int value)
1936 {
1937 struct efx_nic *efx = net_dev->priv;
1938 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
1939 efx_oword_t reg;
1940
1941 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1942 * chosen so that the only current user, Falcon, can take the
1943 * packed value and use them directly.
1944 * Fail to build if this assumption is broken.
1945 */
1946 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
1947 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
1948 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
1949 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
1950
1951 if (phy_id2 == PHY_ADDR_INVALID)
1952 return;
1953
1954 /* See falcon_mdio_read for an explanation. */
1955 if (!(phy_id & FALCON_PHY_ID_10G)) {
1956 int mmd = ffs(efx->phy_op->mmds) - 1;
1957 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
1958 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
1959 & FALCON_PHY_ID_ID_MASK;
1960 }
1961
1962 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
1963 addr, value);
1964
1965 spin_lock_bh(&efx->phy_lock);
1966
1967 /* Check MII not currently being accessed */
1968 if (falcon_gmii_wait(efx) != 0)
1969 goto out;
1970
1971 /* Write the address/ID register */
1972 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1973 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1974
1975 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
1976 falcon_write(efx, &reg, MD_ID_REG_KER);
1977
1978 /* Write data */
1979 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
1980 falcon_write(efx, &reg, MD_TXD_REG_KER);
1981
1982 EFX_POPULATE_OWORD_2(reg,
1983 MD_WRC, 1,
1984 MD_GC, 0);
1985 falcon_write(efx, &reg, MD_CS_REG_KER);
1986
1987 /* Wait for data to be written */
1988 if (falcon_gmii_wait(efx) != 0) {
1989 /* Abort the write operation */
1990 EFX_POPULATE_OWORD_2(reg,
1991 MD_WRC, 0,
1992 MD_GC, 1);
1993 falcon_write(efx, &reg, MD_CS_REG_KER);
1994 udelay(10);
1995 }
1996
1997 out:
1998 spin_unlock_bh(&efx->phy_lock);
1999 }
2000
2001 /* Reads a GMII register from a PHY connected to Falcon. If no value
2002 * could be read, -1 will be returned. */
2003 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2004 {
2005 struct efx_nic *efx = net_dev->priv;
2006 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2007 efx_oword_t reg;
2008 int value = -1;
2009
2010 if (phy_addr == PHY_ADDR_INVALID)
2011 return -1;
2012
2013 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2014 * but the generic Linux code does not make any distinction or have
2015 * any state for this.
2016 * We spot the case where someone tried to talk 22 to a 45 PHY and
2017 * redirect the request to the lowest numbered MMD as a clause45
2018 * request. This is enough to allow simple queries like id and link
2019 * state to succeed. TODO: We may need to do more in future.
2020 */
2021 if (!(phy_id & FALCON_PHY_ID_10G)) {
2022 int mmd = ffs(efx->phy_op->mmds) - 1;
2023 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2024 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2025 & FALCON_PHY_ID_ID_MASK;
2026 }
2027
2028 spin_lock_bh(&efx->phy_lock);
2029
2030 /* Check MII not currently being accessed */
2031 if (falcon_gmii_wait(efx) != 0)
2032 goto out;
2033
2034 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2035 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2036
2037 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2038 falcon_write(efx, &reg, MD_ID_REG_KER);
2039
2040 /* Request data to be read */
2041 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2042 falcon_write(efx, &reg, MD_CS_REG_KER);
2043
2044 /* Wait for data to become available */
2045 value = falcon_gmii_wait(efx);
2046 if (value == 0) {
2047 falcon_read(efx, &reg, MD_RXD_REG_KER);
2048 value = EFX_OWORD_FIELD(reg, MD_RXD);
2049 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2050 phy_id, addr, value);
2051 } else {
2052 /* Abort the read operation */
2053 EFX_POPULATE_OWORD_2(reg,
2054 MD_RIC, 0,
2055 MD_GC, 1);
2056 falcon_write(efx, &reg, MD_CS_REG_KER);
2057
2058 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2059 "error %d\n", phy_id, addr, value);
2060 }
2061
2062 out:
2063 spin_unlock_bh(&efx->phy_lock);
2064
2065 return value;
2066 }
2067
2068 static void falcon_init_mdio(struct mii_if_info *gmii)
2069 {
2070 gmii->mdio_read = falcon_mdio_read;
2071 gmii->mdio_write = falcon_mdio_write;
2072 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2073 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2074 }
2075
2076 static int falcon_probe_phy(struct efx_nic *efx)
2077 {
2078 switch (efx->phy_type) {
2079 case PHY_TYPE_10XPRESS:
2080 efx->phy_op = &falcon_tenxpress_phy_ops;
2081 break;
2082 case PHY_TYPE_XFP:
2083 efx->phy_op = &falcon_xfp_phy_ops;
2084 break;
2085 default:
2086 EFX_ERR(efx, "Unknown PHY type %d\n",
2087 efx->phy_type);
2088 return -1;
2089 }
2090
2091 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2092 return 0;
2093 }
2094
2095 /* This call is responsible for hooking in the MAC and PHY operations */
2096 int falcon_probe_port(struct efx_nic *efx)
2097 {
2098 int rc;
2099
2100 /* Hook in PHY operations table */
2101 rc = falcon_probe_phy(efx);
2102 if (rc)
2103 return rc;
2104
2105 /* Set up GMII structure for PHY */
2106 efx->mii.supports_gmii = 1;
2107 falcon_init_mdio(&efx->mii);
2108
2109 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2110 if (falcon_rev(efx) >= FALCON_REV_B0)
2111 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2112 else
2113 efx->flow_control = EFX_FC_RX;
2114
2115 /* Allocate buffer for stats */
2116 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2117 FALCON_MAC_STATS_SIZE);
2118 if (rc)
2119 return rc;
2120 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2121 (unsigned long long)efx->stats_buffer.dma_addr,
2122 efx->stats_buffer.addr,
2123 virt_to_phys(efx->stats_buffer.addr));
2124
2125 return 0;
2126 }
2127
2128 void falcon_remove_port(struct efx_nic *efx)
2129 {
2130 falcon_free_buffer(efx, &efx->stats_buffer);
2131 }
2132
2133 /**************************************************************************
2134 *
2135 * Multicast filtering
2136 *
2137 **************************************************************************
2138 */
2139
2140 void falcon_set_multicast_hash(struct efx_nic *efx)
2141 {
2142 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2143
2144 /* Broadcast packets go through the multicast hash filter.
2145 * ether_crc_le() of the broadcast address is 0xbe2612ff
2146 * so we always add bit 0xff to the mask.
2147 */
2148 set_bit_le(0xff, mc_hash->byte);
2149
2150 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2151 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2152 }
2153
2154 /**************************************************************************
2155 *
2156 * Device reset
2157 *
2158 **************************************************************************
2159 */
2160
2161 /* Resets NIC to known state. This routine must be called in process
2162 * context and is allowed to sleep. */
2163 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2164 {
2165 struct falcon_nic_data *nic_data = efx->nic_data;
2166 efx_oword_t glb_ctl_reg_ker;
2167 int rc;
2168
2169 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2170
2171 /* Initiate device reset */
2172 if (method == RESET_TYPE_WORLD) {
2173 rc = pci_save_state(efx->pci_dev);
2174 if (rc) {
2175 EFX_ERR(efx, "failed to backup PCI state of primary "
2176 "function prior to hardware reset\n");
2177 goto fail1;
2178 }
2179 if (FALCON_IS_DUAL_FUNC(efx)) {
2180 rc = pci_save_state(nic_data->pci_dev2);
2181 if (rc) {
2182 EFX_ERR(efx, "failed to backup PCI state of "
2183 "secondary function prior to "
2184 "hardware reset\n");
2185 goto fail2;
2186 }
2187 }
2188
2189 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2190 EXT_PHY_RST_DUR, 0x7,
2191 SWRST, 1);
2192 } else {
2193 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2194 EXCLUDE_FROM_RESET : 0);
2195
2196 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2197 EXT_PHY_RST_CTL, reset_phy,
2198 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2199 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2200 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2201 EE_RST_CTL, EXCLUDE_FROM_RESET,
2202 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2203 SWRST, 1);
2204 }
2205 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2206
2207 EFX_LOG(efx, "waiting for hardware reset\n");
2208 schedule_timeout_uninterruptible(HZ / 20);
2209
2210 /* Restore PCI configuration if needed */
2211 if (method == RESET_TYPE_WORLD) {
2212 if (FALCON_IS_DUAL_FUNC(efx)) {
2213 rc = pci_restore_state(nic_data->pci_dev2);
2214 if (rc) {
2215 EFX_ERR(efx, "failed to restore PCI config for "
2216 "the secondary function\n");
2217 goto fail3;
2218 }
2219 }
2220 rc = pci_restore_state(efx->pci_dev);
2221 if (rc) {
2222 EFX_ERR(efx, "failed to restore PCI config for the "
2223 "primary function\n");
2224 goto fail4;
2225 }
2226 EFX_LOG(efx, "successfully restored PCI config\n");
2227 }
2228
2229 /* Assert that reset complete */
2230 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2231 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2232 rc = -ETIMEDOUT;
2233 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2234 goto fail5;
2235 }
2236 EFX_LOG(efx, "hardware reset complete\n");
2237
2238 return 0;
2239
2240 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2241 fail2:
2242 fail3:
2243 pci_restore_state(efx->pci_dev);
2244 fail1:
2245 fail4:
2246 fail5:
2247 return rc;
2248 }
2249
2250 /* Zeroes out the SRAM contents. This routine must be called in
2251 * process context and is allowed to sleep.
2252 */
2253 static int falcon_reset_sram(struct efx_nic *efx)
2254 {
2255 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2256 int count;
2257
2258 /* Set the SRAM wake/sleep GPIO appropriately. */
2259 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2260 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2261 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2262 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2263
2264 /* Initiate SRAM reset */
2265 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2266 SRAM_OOB_BT_INIT_EN, 1,
2267 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2268 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2269
2270 /* Wait for SRAM reset to complete */
2271 count = 0;
2272 do {
2273 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2274
2275 /* SRAM reset is slow; expect around 16ms */
2276 schedule_timeout_uninterruptible(HZ / 50);
2277
2278 /* Check for reset complete */
2279 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2280 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2281 EFX_LOG(efx, "SRAM reset complete\n");
2282
2283 return 0;
2284 }
2285 } while (++count < 20); /* wait upto 0.4 sec */
2286
2287 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2288 return -ETIMEDOUT;
2289 }
2290
2291 /* Extract non-volatile configuration */
2292 static int falcon_probe_nvconfig(struct efx_nic *efx)
2293 {
2294 struct falcon_nvconfig *nvconfig;
2295 efx_oword_t nic_stat;
2296 int device_id;
2297 unsigned addr_len;
2298 size_t offset, len;
2299 int magic_num, struct_ver, board_rev;
2300 int rc;
2301
2302 /* Find the boot device. */
2303 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2304 if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
2305 device_id = EE_SPI_FLASH;
2306 addr_len = 3;
2307 } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
2308 device_id = EE_SPI_EEPROM;
2309 addr_len = 2;
2310 } else {
2311 return -ENODEV;
2312 }
2313
2314 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2315
2316 /* Read the whole configuration structure into memory. */
2317 for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
2318 len = min(sizeof(*nvconfig) - offset,
2319 (size_t) FALCON_SPI_MAX_LEN);
2320 rc = falcon_spi_read(efx, device_id, SPI_READ,
2321 NVCONFIG_BASE + offset, addr_len,
2322 (char *)nvconfig + offset, len);
2323 if (rc)
2324 goto out;
2325 }
2326
2327 /* Read the MAC addresses */
2328 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2329
2330 /* Read the board configuration. */
2331 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2332 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2333
2334 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2335 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2336 "therefore using defaults\n", magic_num, struct_ver);
2337 efx->phy_type = PHY_TYPE_NONE;
2338 efx->mii.phy_id = PHY_ADDR_INVALID;
2339 board_rev = 0;
2340 } else {
2341 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2342
2343 efx->phy_type = v2->port0_phy_type;
2344 efx->mii.phy_id = v2->port0_phy_addr;
2345 board_rev = le16_to_cpu(v2->board_revision);
2346 }
2347
2348 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2349
2350 efx_set_board_info(efx, board_rev);
2351
2352 out:
2353 kfree(nvconfig);
2354 return rc;
2355 }
2356
2357 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2358 * count, port speed). Set workaround and feature flags accordingly.
2359 */
2360 static int falcon_probe_nic_variant(struct efx_nic *efx)
2361 {
2362 efx_oword_t altera_build;
2363
2364 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2365 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2366 EFX_ERR(efx, "Falcon FPGA not supported\n");
2367 return -ENODEV;
2368 }
2369
2370 switch (falcon_rev(efx)) {
2371 case FALCON_REV_A0:
2372 case 0xff:
2373 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2374 return -ENODEV;
2375
2376 case FALCON_REV_A1:{
2377 efx_oword_t nic_stat;
2378
2379 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2380
2381 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2382 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2383 return -ENODEV;
2384 }
2385 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2386 EFX_ERR(efx, "1G mode not supported\n");
2387 return -ENODEV;
2388 }
2389 break;
2390 }
2391
2392 case FALCON_REV_B0:
2393 break;
2394
2395 default:
2396 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2397 return -ENODEV;
2398 }
2399
2400 return 0;
2401 }
2402
2403 int falcon_probe_nic(struct efx_nic *efx)
2404 {
2405 struct falcon_nic_data *nic_data;
2406 int rc;
2407
2408 /* Initialise I2C interface state */
2409 efx->i2c.efx = efx;
2410 efx->i2c.op = &falcon_i2c_bit_operations;
2411 efx->i2c.sda = 1;
2412 efx->i2c.scl = 1;
2413
2414 /* Allocate storage for hardware specific data */
2415 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2416 efx->nic_data = nic_data;
2417
2418 /* Determine number of ports etc. */
2419 rc = falcon_probe_nic_variant(efx);
2420 if (rc)
2421 goto fail1;
2422
2423 /* Probe secondary function if expected */
2424 if (FALCON_IS_DUAL_FUNC(efx)) {
2425 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2426
2427 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2428 dev))) {
2429 if (dev->bus == efx->pci_dev->bus &&
2430 dev->devfn == efx->pci_dev->devfn + 1) {
2431 nic_data->pci_dev2 = dev;
2432 break;
2433 }
2434 }
2435 if (!nic_data->pci_dev2) {
2436 EFX_ERR(efx, "failed to find secondary function\n");
2437 rc = -ENODEV;
2438 goto fail2;
2439 }
2440 }
2441
2442 /* Now we can reset the NIC */
2443 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2444 if (rc) {
2445 EFX_ERR(efx, "failed to reset NIC\n");
2446 goto fail3;
2447 }
2448
2449 /* Allocate memory for INT_KER */
2450 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2451 if (rc)
2452 goto fail4;
2453 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2454
2455 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2456 (unsigned long long)efx->irq_status.dma_addr,
2457 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2458
2459 /* Read in the non-volatile configuration */
2460 rc = falcon_probe_nvconfig(efx);
2461 if (rc)
2462 goto fail5;
2463
2464 return 0;
2465
2466 fail5:
2467 falcon_free_buffer(efx, &efx->irq_status);
2468 fail4:
2469 fail3:
2470 if (nic_data->pci_dev2) {
2471 pci_dev_put(nic_data->pci_dev2);
2472 nic_data->pci_dev2 = NULL;
2473 }
2474 fail2:
2475 fail1:
2476 kfree(efx->nic_data);
2477 return rc;
2478 }
2479
2480 /* This call performs hardware-specific global initialisation, such as
2481 * defining the descriptor cache sizes and number of RSS channels.
2482 * It does not set up any buffers, descriptor rings or event queues.
2483 */
2484 int falcon_init_nic(struct efx_nic *efx)
2485 {
2486 efx_oword_t temp;
2487 unsigned thresh;
2488 int rc;
2489
2490 /* Set up the address region register. This is only needed
2491 * for the B0 FPGA, but since we are just pushing in the
2492 * reset defaults this may as well be unconditional. */
2493 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2494 ADR_REGION1, (1 << 16),
2495 ADR_REGION2, (2 << 16),
2496 ADR_REGION3, (3 << 16));
2497 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2498
2499 /* Use on-chip SRAM */
2500 falcon_read(efx, &temp, NIC_STAT_REG);
2501 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2502 falcon_write(efx, &temp, NIC_STAT_REG);
2503
2504 /* Set buffer table mode */
2505 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2506 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2507
2508 rc = falcon_reset_sram(efx);
2509 if (rc)
2510 return rc;
2511
2512 /* Set positions of descriptor caches in SRAM. */
2513 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2514 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2515 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2516 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2517
2518 /* Set TX descriptor cache size. */
2519 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2520 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2521 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2522
2523 /* Set RX descriptor cache size. Set low watermark to size-8, as
2524 * this allows most efficient prefetching.
2525 */
2526 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2527 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2528 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2529 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2530 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2531
2532 /* Clear the parity enables on the TX data fifos as
2533 * they produce false parity errors because of timing issues
2534 */
2535 if (EFX_WORKAROUND_5129(efx)) {
2536 falcon_read(efx, &temp, SPARE_REG_KER);
2537 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2538 falcon_write(efx, &temp, SPARE_REG_KER);
2539 }
2540
2541 /* Enable all the genuinely fatal interrupts. (They are still
2542 * masked by the overall interrupt mask, controlled by
2543 * falcon_interrupts()).
2544 *
2545 * Note: All other fatal interrupts are enabled
2546 */
2547 EFX_POPULATE_OWORD_3(temp,
2548 ILL_ADR_INT_KER_EN, 1,
2549 RBUF_OWN_INT_KER_EN, 1,
2550 TBUF_OWN_INT_KER_EN, 1);
2551 EFX_INVERT_OWORD(temp);
2552 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2553
2554 /* Set number of RSS queues for receive path. */
2555 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2556 if (falcon_rev(efx) >= FALCON_REV_B0)
2557 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2558 else
2559 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2560 if (EFX_WORKAROUND_7244(efx)) {
2561 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2562 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2563 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2564 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2565 }
2566 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2567
2568 falcon_setup_rss_indir_table(efx);
2569
2570 /* Setup RX. Wait for descriptor is broken and must
2571 * be disabled. RXDP recovery shouldn't be needed, but is.
2572 */
2573 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2574 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2575 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2576 if (EFX_WORKAROUND_5583(efx))
2577 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2578 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2579
2580 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2581 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2582 */
2583 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2584 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2585 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2586 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2587 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2588 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2589 /* Enable SW_EV to inherit in char driver - assume harmless here */
2590 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2591 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2592 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2593 /* Squash TX of packets of 16 bytes or less */
2594 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2595 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2596 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2597
2598 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2599 * descriptors (which is bad).
2600 */
2601 falcon_read(efx, &temp, TX_CFG_REG_KER);
2602 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2603 falcon_write(efx, &temp, TX_CFG_REG_KER);
2604
2605 /* RX config */
2606 falcon_read(efx, &temp, RX_CFG_REG_KER);
2607 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2608 if (EFX_WORKAROUND_7575(efx))
2609 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2610 (3 * 4096) / 32);
2611 if (falcon_rev(efx) >= FALCON_REV_B0)
2612 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2613
2614 /* RX FIFO flow control thresholds */
2615 thresh = ((rx_xon_thresh_bytes >= 0) ?
2616 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2617 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2618 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2619 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2620 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2621 /* RX control FIFO thresholds [32 entries] */
2622 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25);
2623 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20);
2624 falcon_write(efx, &temp, RX_CFG_REG_KER);
2625
2626 /* Set destination of both TX and RX Flush events */
2627 if (falcon_rev(efx) >= FALCON_REV_B0) {
2628 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2629 falcon_write(efx, &temp, DP_CTRL_REG);
2630 }
2631
2632 return 0;
2633 }
2634
2635 void falcon_remove_nic(struct efx_nic *efx)
2636 {
2637 struct falcon_nic_data *nic_data = efx->nic_data;
2638
2639 falcon_free_buffer(efx, &efx->irq_status);
2640
2641 falcon_reset_hw(efx, RESET_TYPE_ALL);
2642
2643 /* Release the second function after the reset */
2644 if (nic_data->pci_dev2) {
2645 pci_dev_put(nic_data->pci_dev2);
2646 nic_data->pci_dev2 = NULL;
2647 }
2648
2649 /* Tear down the private nic state */
2650 kfree(efx->nic_data);
2651 efx->nic_data = NULL;
2652 }
2653
2654 void falcon_update_nic_stats(struct efx_nic *efx)
2655 {
2656 efx_oword_t cnt;
2657
2658 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2659 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2660 }
2661
2662 /**************************************************************************
2663 *
2664 * Revision-dependent attributes used by efx.c
2665 *
2666 **************************************************************************
2667 */
2668
2669 struct efx_nic_type falcon_a_nic_type = {
2670 .mem_bar = 2,
2671 .mem_map_size = 0x20000,
2672 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2673 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2674 .buf_tbl_base = BUF_TBL_KER_A1,
2675 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2676 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2677 .txd_ring_mask = FALCON_TXD_RING_MASK,
2678 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2679 .evq_size = FALCON_EVQ_SIZE,
2680 .max_dma_mask = FALCON_DMA_MASK,
2681 .tx_dma_mask = FALCON_TX_DMA_MASK,
2682 .bug5391_mask = 0xf,
2683 .rx_xoff_thresh = 2048,
2684 .rx_xon_thresh = 512,
2685 .rx_buffer_padding = 0x24,
2686 .max_interrupt_mode = EFX_INT_MODE_MSI,
2687 .phys_addr_channels = 4,
2688 };
2689
2690 struct efx_nic_type falcon_b_nic_type = {
2691 .mem_bar = 2,
2692 /* Map everything up to and including the RSS indirection
2693 * table. Don't map MSI-X table, MSI-X PBA since Linux
2694 * requires that they not be mapped. */
2695 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2696 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2697 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2698 .buf_tbl_base = BUF_TBL_KER_B0,
2699 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2700 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2701 .txd_ring_mask = FALCON_TXD_RING_MASK,
2702 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2703 .evq_size = FALCON_EVQ_SIZE,
2704 .max_dma_mask = FALCON_DMA_MASK,
2705 .tx_dma_mask = FALCON_TX_DMA_MASK,
2706 .bug5391_mask = 0,
2707 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2708 .rx_xon_thresh = 27648, /* ~3*max MTU */
2709 .rx_buffer_padding = 0,
2710 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2711 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2712 * interrupt handler only supports 32
2713 * channels */
2714 };
2715
kernel source for telekom puls (alcatel/mediatek)