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IB/mlx4: Add support for XRC domains
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36 #include <linux/cache.h>
37
38 #include "fw.h"
39 #include "icm.h"
40
41 enum {
42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
45 };
46
47 extern void __buggy_use_of_MLX4_GET(void);
48 extern void __buggy_use_of_MLX4_PUT(void);
49
50 static int enable_qos;
51 module_param(enable_qos, bool, 0444);
52 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
54 #define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66 #define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
79 {
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
84 [ 3] = "XRC transport",
85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
92 [12] = "DPDP",
93 [15] = "Big LSO headers",
94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
101 [25] = "Router support",
102 [30] = "IBoE support",
103 [32] = "Unicast loopback support",
104 [38] = "Wake On LAN support",
105 [40] = "UDP RSS support",
106 [41] = "Unicast VEP steering support",
107 [42] = "Multicast VEP steering support",
108 [48] = "Counters support",
109 };
110 int i;
111
112 mlx4_dbg(dev, "DEV_CAP flags:\n");
113 for (i = 0; i < ARRAY_SIZE(fname); ++i)
114 if (fname[i] && (flags & (1LL << i)))
115 mlx4_dbg(dev, " %s\n", fname[i]);
116 }
117
118 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
119 {
120 struct mlx4_cmd_mailbox *mailbox;
121 u32 *inbox;
122 int err = 0;
123
124 #define MOD_STAT_CFG_IN_SIZE 0x100
125
126 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
127 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
128
129 mailbox = mlx4_alloc_cmd_mailbox(dev);
130 if (IS_ERR(mailbox))
131 return PTR_ERR(mailbox);
132 inbox = mailbox->buf;
133
134 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
135
136 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
137 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
138
139 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
140 MLX4_CMD_TIME_CLASS_A);
141
142 mlx4_free_cmd_mailbox(dev, mailbox);
143 return err;
144 }
145
146 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
147 {
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *outbox;
150 u8 field;
151 u32 field32, flags, ext_flags;
152 u16 size;
153 u16 stat_rate;
154 int err;
155 int i;
156
157 #define QUERY_DEV_CAP_OUT_SIZE 0x100
158 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
159 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
160 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
161 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
162 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
163 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
164 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
165 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
166 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
167 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
168 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
169 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
170 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
171 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
172 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
173 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
174 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
175 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
176 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
177 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
178 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
179 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
180 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
181 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
182 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
183 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
184 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
185 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
186 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
187 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
188 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
189 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
190 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
191 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
192 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
193 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
194 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
195 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
196 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
197 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
198 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
199 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
200 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
201 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
202 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
203 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
204 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
205 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
206 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
207 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
208 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
209 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
210 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
211 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
212 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
213 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
214 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
215 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
216 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
217 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
218 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
219 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
220 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
221 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
222 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
223
224 mailbox = mlx4_alloc_cmd_mailbox(dev);
225 if (IS_ERR(mailbox))
226 return PTR_ERR(mailbox);
227 outbox = mailbox->buf;
228
229 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
230 MLX4_CMD_TIME_CLASS_A);
231 if (err)
232 goto out;
233
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
235 dev_cap->reserved_qps = 1 << (field & 0xf);
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
237 dev_cap->max_qps = 1 << (field & 0x1f);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
239 dev_cap->reserved_srqs = 1 << (field >> 4);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
241 dev_cap->max_srqs = 1 << (field & 0x1f);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
243 dev_cap->max_cq_sz = 1 << field;
244 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
245 dev_cap->reserved_cqs = 1 << (field & 0xf);
246 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
247 dev_cap->max_cqs = 1 << (field & 0x1f);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
249 dev_cap->max_mpts = 1 << (field & 0x3f);
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
251 dev_cap->reserved_eqs = field & 0xf;
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
253 dev_cap->max_eqs = 1 << (field & 0xf);
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
255 dev_cap->reserved_mtts = 1 << (field >> 4);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
257 dev_cap->max_mrw_sz = 1 << field;
258 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
259 dev_cap->reserved_mrws = 1 << (field & 0xf);
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
261 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
263 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
265 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
266 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
267 field &= 0x1f;
268 if (!field)
269 dev_cap->max_gso_sz = 0;
270 else
271 dev_cap->max_gso_sz = 1 << field;
272
273 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
274 dev_cap->max_rdma_global = 1 << (field & 0x3f);
275 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
276 dev_cap->local_ca_ack_delay = field & 0x1f;
277 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
278 dev_cap->num_ports = field & 0xf;
279 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
280 dev_cap->max_msg_sz = 1 << (field & 0x1f);
281 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
282 dev_cap->stat_rate_support = stat_rate;
283 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
284 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
285 dev_cap->flags = flags | (u64)ext_flags << 32;
286 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
287 dev_cap->reserved_uars = field >> 4;
288 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
289 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
291 dev_cap->min_page_sz = 1 << field;
292
293 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
294 if (field & 0x80) {
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
296 dev_cap->bf_reg_size = 1 << (field & 0x1f);
297 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
298 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
299 field = 3;
300 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
301 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
302 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
303 } else {
304 dev_cap->bf_reg_size = 0;
305 mlx4_dbg(dev, "BlueFlame not available\n");
306 }
307
308 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
309 dev_cap->max_sq_sg = field;
310 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
311 dev_cap->max_sq_desc_sz = size;
312
313 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
314 dev_cap->max_qp_per_mcg = 1 << field;
315 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
316 dev_cap->reserved_mgms = field & 0xf;
317 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
318 dev_cap->max_mcgs = 1 << field;
319 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
320 dev_cap->reserved_pds = field >> 4;
321 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
322 dev_cap->max_pds = 1 << (field & 0x3f);
323 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
324 dev_cap->reserved_xrcds = field >> 4;
325 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
326 dev_cap->max_xrcds = 1 << (field & 0x1f);
327
328 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
329 dev_cap->rdmarc_entry_sz = size;
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
331 dev_cap->qpc_entry_sz = size;
332 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
333 dev_cap->aux_entry_sz = size;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
335 dev_cap->altc_entry_sz = size;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
337 dev_cap->eqc_entry_sz = size;
338 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
339 dev_cap->cqc_entry_sz = size;
340 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
341 dev_cap->srq_entry_sz = size;
342 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
343 dev_cap->cmpt_entry_sz = size;
344 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
345 dev_cap->mtt_entry_sz = size;
346 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
347 dev_cap->dmpt_entry_sz = size;
348
349 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
350 dev_cap->max_srq_sz = 1 << field;
351 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
352 dev_cap->max_qp_sz = 1 << field;
353 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
354 dev_cap->resize_srq = field & 1;
355 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
356 dev_cap->max_rq_sg = field;
357 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
358 dev_cap->max_rq_desc_sz = size;
359
360 MLX4_GET(dev_cap->bmme_flags, outbox,
361 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
362 MLX4_GET(dev_cap->reserved_lkey, outbox,
363 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
364 MLX4_GET(dev_cap->max_icm_sz, outbox,
365 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
366 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
367 MLX4_GET(dev_cap->max_counters, outbox,
368 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
369
370 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
371 for (i = 1; i <= dev_cap->num_ports; ++i) {
372 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
373 dev_cap->max_vl[i] = field >> 4;
374 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
375 dev_cap->ib_mtu[i] = field >> 4;
376 dev_cap->max_port_width[i] = field & 0xf;
377 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
378 dev_cap->max_gids[i] = 1 << (field & 0xf);
379 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
380 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
381 }
382 } else {
383 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
384 #define QUERY_PORT_MTU_OFFSET 0x01
385 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
386 #define QUERY_PORT_WIDTH_OFFSET 0x06
387 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
388 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
389 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
390 #define QUERY_PORT_MAC_OFFSET 0x10
391 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
392 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
393 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
394
395 for (i = 1; i <= dev_cap->num_ports; ++i) {
396 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
397 MLX4_CMD_TIME_CLASS_B);
398 if (err)
399 goto out;
400
401 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
402 dev_cap->supported_port_types[i] = field & 3;
403 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
404 dev_cap->ib_mtu[i] = field & 0xf;
405 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
406 dev_cap->max_port_width[i] = field & 0xf;
407 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
408 dev_cap->max_gids[i] = 1 << (field >> 4);
409 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
410 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
411 dev_cap->max_vl[i] = field & 0xf;
412 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
413 dev_cap->log_max_macs[i] = field & 0xf;
414 dev_cap->log_max_vlans[i] = field >> 4;
415 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
416 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
417 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
418 dev_cap->trans_type[i] = field32 >> 24;
419 dev_cap->vendor_oui[i] = field32 & 0xffffff;
420 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
421 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
422 }
423 }
424
425 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
426 dev_cap->bmme_flags, dev_cap->reserved_lkey);
427
428 /*
429 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
430 * we can't use any EQs whose doorbell falls on that page,
431 * even if the EQ itself isn't reserved.
432 */
433 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
434 dev_cap->reserved_eqs);
435
436 mlx4_dbg(dev, "Max ICM size %lld MB\n",
437 (unsigned long long) dev_cap->max_icm_sz >> 20);
438 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
439 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
440 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
441 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
442 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
443 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
444 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
445 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
446 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
447 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
448 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
449 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
450 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
451 dev_cap->max_pds, dev_cap->reserved_mgms);
452 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
453 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
454 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
455 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
456 dev_cap->max_port_width[1]);
457 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
458 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
459 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
460 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
461 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
462 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
463
464 dump_dev_cap_flags(dev, dev_cap->flags);
465
466 out:
467 mlx4_free_cmd_mailbox(dev, mailbox);
468 return err;
469 }
470
471 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
472 {
473 struct mlx4_cmd_mailbox *mailbox;
474 struct mlx4_icm_iter iter;
475 __be64 *pages;
476 int lg;
477 int nent = 0;
478 int i;
479 int err = 0;
480 int ts = 0, tc = 0;
481
482 mailbox = mlx4_alloc_cmd_mailbox(dev);
483 if (IS_ERR(mailbox))
484 return PTR_ERR(mailbox);
485 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
486 pages = mailbox->buf;
487
488 for (mlx4_icm_first(icm, &iter);
489 !mlx4_icm_last(&iter);
490 mlx4_icm_next(&iter)) {
491 /*
492 * We have to pass pages that are aligned to their
493 * size, so find the least significant 1 in the
494 * address or size and use that as our log2 size.
495 */
496 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
497 if (lg < MLX4_ICM_PAGE_SHIFT) {
498 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
499 MLX4_ICM_PAGE_SIZE,
500 (unsigned long long) mlx4_icm_addr(&iter),
501 mlx4_icm_size(&iter));
502 err = -EINVAL;
503 goto out;
504 }
505
506 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
507 if (virt != -1) {
508 pages[nent * 2] = cpu_to_be64(virt);
509 virt += 1 << lg;
510 }
511
512 pages[nent * 2 + 1] =
513 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
514 (lg - MLX4_ICM_PAGE_SHIFT));
515 ts += 1 << (lg - 10);
516 ++tc;
517
518 if (++nent == MLX4_MAILBOX_SIZE / 16) {
519 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
520 MLX4_CMD_TIME_CLASS_B);
521 if (err)
522 goto out;
523 nent = 0;
524 }
525 }
526 }
527
528 if (nent)
529 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
530 if (err)
531 goto out;
532
533 switch (op) {
534 case MLX4_CMD_MAP_FA:
535 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
536 break;
537 case MLX4_CMD_MAP_ICM_AUX:
538 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
539 break;
540 case MLX4_CMD_MAP_ICM:
541 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
542 tc, ts, (unsigned long long) virt - (ts << 10));
543 break;
544 }
545
546 out:
547 mlx4_free_cmd_mailbox(dev, mailbox);
548 return err;
549 }
550
551 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
552 {
553 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
554 }
555
556 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
557 {
558 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
559 }
560
561
562 int mlx4_RUN_FW(struct mlx4_dev *dev)
563 {
564 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
565 }
566
567 int mlx4_QUERY_FW(struct mlx4_dev *dev)
568 {
569 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
570 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
571 struct mlx4_cmd_mailbox *mailbox;
572 u32 *outbox;
573 int err = 0;
574 u64 fw_ver;
575 u16 cmd_if_rev;
576 u8 lg;
577
578 #define QUERY_FW_OUT_SIZE 0x100
579 #define QUERY_FW_VER_OFFSET 0x00
580 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
581 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
582 #define QUERY_FW_ERR_START_OFFSET 0x30
583 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
584 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
585
586 #define QUERY_FW_SIZE_OFFSET 0x00
587 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
588 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
589
590 mailbox = mlx4_alloc_cmd_mailbox(dev);
591 if (IS_ERR(mailbox))
592 return PTR_ERR(mailbox);
593 outbox = mailbox->buf;
594
595 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
596 MLX4_CMD_TIME_CLASS_A);
597 if (err)
598 goto out;
599
600 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
601 /*
602 * FW subminor version is at more significant bits than minor
603 * version, so swap here.
604 */
605 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
606 ((fw_ver & 0xffff0000ull) >> 16) |
607 ((fw_ver & 0x0000ffffull) << 16);
608
609 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
610 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
611 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
612 mlx4_err(dev, "Installed FW has unsupported "
613 "command interface revision %d.\n",
614 cmd_if_rev);
615 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
616 (int) (dev->caps.fw_ver >> 32),
617 (int) (dev->caps.fw_ver >> 16) & 0xffff,
618 (int) dev->caps.fw_ver & 0xffff);
619 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
620 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
621 err = -ENODEV;
622 goto out;
623 }
624
625 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
626 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
627
628 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
629 cmd->max_cmds = 1 << lg;
630
631 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
632 (int) (dev->caps.fw_ver >> 32),
633 (int) (dev->caps.fw_ver >> 16) & 0xffff,
634 (int) dev->caps.fw_ver & 0xffff,
635 cmd_if_rev, cmd->max_cmds);
636
637 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
638 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
639 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
640 fw->catas_bar = (fw->catas_bar >> 6) * 2;
641
642 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
643 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
644
645 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
646 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
647 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
648 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
649
650 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
651
652 /*
653 * Round up number of system pages needed in case
654 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
655 */
656 fw->fw_pages =
657 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
658 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
659
660 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
661 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
662
663 out:
664 mlx4_free_cmd_mailbox(dev, mailbox);
665 return err;
666 }
667
668 static void get_board_id(void *vsd, char *board_id)
669 {
670 int i;
671
672 #define VSD_OFFSET_SIG1 0x00
673 #define VSD_OFFSET_SIG2 0xde
674 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
675 #define VSD_OFFSET_TS_BOARD_ID 0x20
676
677 #define VSD_SIGNATURE_TOPSPIN 0x5ad
678
679 memset(board_id, 0, MLX4_BOARD_ID_LEN);
680
681 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
682 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
683 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
684 } else {
685 /*
686 * The board ID is a string but the firmware byte
687 * swaps each 4-byte word before passing it back to
688 * us. Therefore we need to swab it before printing.
689 */
690 for (i = 0; i < 4; ++i)
691 ((u32 *) board_id)[i] =
692 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
693 }
694 }
695
696 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
697 {
698 struct mlx4_cmd_mailbox *mailbox;
699 u32 *outbox;
700 int err;
701
702 #define QUERY_ADAPTER_OUT_SIZE 0x100
703 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
704 #define QUERY_ADAPTER_VSD_OFFSET 0x20
705
706 mailbox = mlx4_alloc_cmd_mailbox(dev);
707 if (IS_ERR(mailbox))
708 return PTR_ERR(mailbox);
709 outbox = mailbox->buf;
710
711 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
712 MLX4_CMD_TIME_CLASS_A);
713 if (err)
714 goto out;
715
716 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
717
718 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
719 adapter->board_id);
720
721 out:
722 mlx4_free_cmd_mailbox(dev, mailbox);
723 return err;
724 }
725
726 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
727 {
728 struct mlx4_cmd_mailbox *mailbox;
729 __be32 *inbox;
730 int err;
731
732 #define INIT_HCA_IN_SIZE 0x200
733 #define INIT_HCA_VERSION_OFFSET 0x000
734 #define INIT_HCA_VERSION 2
735 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
736 #define INIT_HCA_FLAGS_OFFSET 0x014
737 #define INIT_HCA_QPC_OFFSET 0x020
738 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
739 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
740 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
741 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
742 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
743 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
744 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
745 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
746 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
747 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
748 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
749 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
750 #define INIT_HCA_MCAST_OFFSET 0x0c0
751 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
752 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
753 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
754 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
755 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
756 #define INIT_HCA_TPT_OFFSET 0x0f0
757 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
758 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
759 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
760 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
761 #define INIT_HCA_UAR_OFFSET 0x120
762 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
763 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
764
765 mailbox = mlx4_alloc_cmd_mailbox(dev);
766 if (IS_ERR(mailbox))
767 return PTR_ERR(mailbox);
768 inbox = mailbox->buf;
769
770 memset(inbox, 0, INIT_HCA_IN_SIZE);
771
772 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
773
774 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
775 (ilog2(cache_line_size()) - 4) << 5;
776
777 #if defined(__LITTLE_ENDIAN)
778 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
779 #elif defined(__BIG_ENDIAN)
780 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
781 #else
782 #error Host endianness not defined
783 #endif
784 /* Check port for UD address vector: */
785 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
786
787 /* Enable IPoIB checksumming if we can: */
788 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
789 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
790
791 /* Enable QoS support if module parameter set */
792 if (enable_qos)
793 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
794
795 /* enable counters */
796 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
797 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
798
799 /* QPC/EEC/CQC/EQC/RDMARC attributes */
800
801 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
802 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
803 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
804 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
805 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
806 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
807 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
808 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
809 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
810 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
811 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
812 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
813
814 /* multicast attributes */
815
816 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
817 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
818 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
819 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
820 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
821 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
822
823 /* TPT attributes */
824
825 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
826 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
827 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
828 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
829
830 /* UAR attributes */
831
832 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
833 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
834
835 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
836
837 if (err)
838 mlx4_err(dev, "INIT_HCA returns %d\n", err);
839
840 mlx4_free_cmd_mailbox(dev, mailbox);
841 return err;
842 }
843
844 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
845 {
846 struct mlx4_cmd_mailbox *mailbox;
847 u32 *inbox;
848 int err;
849 u32 flags;
850 u16 field;
851
852 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
853 #define INIT_PORT_IN_SIZE 256
854 #define INIT_PORT_FLAGS_OFFSET 0x00
855 #define INIT_PORT_FLAG_SIG (1 << 18)
856 #define INIT_PORT_FLAG_NG (1 << 17)
857 #define INIT_PORT_FLAG_G0 (1 << 16)
858 #define INIT_PORT_VL_SHIFT 4
859 #define INIT_PORT_PORT_WIDTH_SHIFT 8
860 #define INIT_PORT_MTU_OFFSET 0x04
861 #define INIT_PORT_MAX_GID_OFFSET 0x06
862 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
863 #define INIT_PORT_GUID0_OFFSET 0x10
864 #define INIT_PORT_NODE_GUID_OFFSET 0x18
865 #define INIT_PORT_SI_GUID_OFFSET 0x20
866
867 mailbox = mlx4_alloc_cmd_mailbox(dev);
868 if (IS_ERR(mailbox))
869 return PTR_ERR(mailbox);
870 inbox = mailbox->buf;
871
872 memset(inbox, 0, INIT_PORT_IN_SIZE);
873
874 flags = 0;
875 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
876 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
877 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
878
879 field = 128 << dev->caps.ib_mtu_cap[port];
880 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
881 field = dev->caps.gid_table_len[port];
882 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
883 field = dev->caps.pkey_table_len[port];
884 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
885
886 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
887 MLX4_CMD_TIME_CLASS_A);
888
889 mlx4_free_cmd_mailbox(dev, mailbox);
890 } else
891 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
892 MLX4_CMD_TIME_CLASS_A);
893
894 return err;
895 }
896 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
897
898 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
899 {
900 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
901 }
902 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
903
904 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
905 {
906 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
907 }
908
909 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
910 {
911 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
912 MLX4_CMD_SET_ICM_SIZE,
913 MLX4_CMD_TIME_CLASS_A);
914 if (ret)
915 return ret;
916
917 /*
918 * Round up number of system pages needed in case
919 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
920 */
921 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
922 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
923
924 return 0;
925 }
926
927 int mlx4_NOP(struct mlx4_dev *dev)
928 {
929 /* Input modifier of 0x1f means "finish as soon as possible." */
930 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
931 }
932
933 #define MLX4_WOL_SETUP_MODE (5 << 28)
934 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
935 {
936 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
937
938 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
939 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
940 }
941 EXPORT_SYMBOL_GPL(mlx4_wol_read);
942
943 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
944 {
945 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
946
947 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
948 MLX4_CMD_TIME_CLASS_A);
949 }
950 EXPORT_SYMBOL_GPL(mlx4_wol_write);
kernel source for telekom puls (alcatel/mediatek)