2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION
);
58 struct workqueue_struct
*mlx4_wq
;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level
= 0;
63 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
64 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x
, int, 0444);
72 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
81 module_param(num_vfs
, int, 0444);
82 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0");
85 module_param(probe_vf
, int, 0644);
86 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)");
88 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
89 module_param_named(log_num_mgm_entry_size
,
90 mlx4_log_num_mgm_entry_size
, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 7 <="
94 " log_num_mgm_entry_size <= 12."
95 " To activate device managed"
96 " flow steering when available, set to -1");
98 static bool enable_64b_cqe_eqe
;
99 module_param(enable_64b_cqe_eqe
, bool, 0444);
100 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
101 "Enable 64 byte CQEs/EQEs when the the FW supports this");
103 #define HCA_GLOBAL_CAP_MASK 0
105 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
107 static char mlx4_version
[] =
108 DRV_NAME
": Mellanox ConnectX core driver v"
109 DRV_VERSION
" (" DRV_RELDATE
")\n";
111 static struct mlx4_profile default_profile
= {
114 .rdmarc_per_qp
= 1 << 4,
118 .num_mtt
= 1 << 20, /* It is really num mtt segements */
121 static int log_num_mac
= 7;
122 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
123 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
125 static int log_num_vlan
;
126 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
127 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
128 /* Log2 max number of VLANs per ETH port (0-7) */
129 #define MLX4_LOG_NUM_VLANS 7
131 static bool use_prio
;
132 module_param_named(use_prio
, use_prio
, bool, 0444);
133 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports "
136 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
137 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
138 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
140 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
141 static int arr_argc
= 2;
142 module_param_array(port_type_array
, int, &arr_argc
, 0444);
143 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
146 struct mlx4_port_config
{
147 struct list_head list
;
148 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
149 struct pci_dev
*pdev
;
152 int mlx4_check_port_params(struct mlx4_dev
*dev
,
153 enum mlx4_port_type
*port_type
)
157 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
158 if (port_type
[i
] != port_type
[i
+ 1]) {
159 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
160 mlx4_err(dev
, "Only same port types supported "
161 "on this HCA, aborting.\n");
167 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
168 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
169 mlx4_err(dev
, "Requested port type for port %d is not "
170 "supported on this HCA\n", i
+ 1);
177 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
181 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
182 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
185 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
190 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
192 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
196 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
197 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap
->min_page_sz
, PAGE_SIZE
);
202 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
203 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
205 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
209 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
210 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
213 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
217 dev
->caps
.num_ports
= dev_cap
->num_ports
;
218 dev
->phys_caps
.num_phys_eqs
= MLX4_MAX_EQ_NUM
;
219 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
220 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
221 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
222 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
223 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
226 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
227 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
228 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
229 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
230 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
231 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
232 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
233 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
234 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
235 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
236 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
237 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
240 dev
->caps
.uar_page_size
= PAGE_SIZE
;
241 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
242 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
243 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
244 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
245 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
246 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
247 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
248 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
249 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
250 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
251 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
252 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
253 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
259 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
260 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
261 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
262 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
263 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
265 /* The first 128 UARs are used for EQ doorbells */
266 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
267 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
268 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
269 dev_cap
->reserved_xrcds
: 0;
270 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
271 dev_cap
->max_xrcds
: 0;
272 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
274 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
275 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
276 dev
->caps
.flags
= dev_cap
->flags
;
277 dev
->caps
.flags2
= dev_cap
->flags2
;
278 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
279 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
280 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
281 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
282 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
286 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev
))
289 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
291 dev
->caps
.log_num_macs
= log_num_mac
;
292 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
293 dev
->caps
.log_num_prios
= use_prio
? 3 : 0;
295 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
296 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
297 if (dev
->caps
.supported_type
[i
]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
300 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
301 /* if only IB is supported, assign IB */
302 else if (dev
->caps
.supported_type
[i
] ==
304 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
310 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
311 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
313 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
322 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
323 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
324 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
325 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
332 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
333 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
334 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
335 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
336 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
337 dev
->caps
.port_type
[i
] = sensed_port
;
339 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
342 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
343 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
344 mlx4_warn(dev
, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i
, 1 << dev
->caps
.log_num_macs
);
348 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
349 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
350 mlx4_warn(dev
, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i
, 1 << dev
->caps
.log_num_vlans
);
356 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
358 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
359 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
360 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
361 (1 << dev
->caps
.log_num_macs
) *
362 (1 << dev
->caps
.log_num_vlans
) *
363 (1 << dev
->caps
.log_num_prios
) *
365 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
367 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
368 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
369 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
370 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
372 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
374 if (!enable_64b_cqe_eqe
) {
376 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
377 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
379 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
383 if ((dev
->caps
.flags
&
384 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
386 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
390 /*The function checks if there are live vf, return the num of them*/
391 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
393 struct mlx4_priv
*priv
= mlx4_priv(dev
);
394 struct mlx4_slave_state
*s_state
;
398 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
399 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
400 if (s_state
->active
&& s_state
->last_cmd
!=
401 MLX4_COMM_CMD_RESET
) {
402 mlx4_warn(dev
, "%s: slave: %d is still active\n",
410 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
412 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
414 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
415 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
418 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
420 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
422 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
426 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
428 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
430 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
432 if (!mlx4_is_master(dev
))
435 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
437 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
439 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
441 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
443 if (!mlx4_is_master(dev
))
446 priv
->slave_node_guids
[slave
] = guid
;
448 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
450 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
452 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
454 if (!mlx4_is_master(dev
))
457 return priv
->slave_node_guids
[slave
];
459 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
461 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
463 struct mlx4_priv
*priv
= mlx4_priv(dev
);
464 struct mlx4_slave_state
*s_slave
;
466 if (!mlx4_is_master(dev
))
469 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
470 return !!s_slave
->active
;
472 EXPORT_SYMBOL(mlx4_is_slave_active
);
474 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
475 struct mlx4_dev_cap
*dev_cap
,
476 struct mlx4_init_hca_param
*hca_param
)
478 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
479 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
480 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
481 dev
->caps
.fs_log_max_ucast_qp_range_size
=
482 dev_cap
->fs_log_max_ucast_qp_range_size
;
484 dev
->caps
.num_qp_per_mgm
=
485 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
487 mlx4_dbg(dev
, "Steering mode is: %s\n",
488 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
491 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
495 struct mlx4_dev_cap dev_cap
;
496 struct mlx4_func_cap func_cap
;
497 struct mlx4_init_hca_param hca_param
;
500 memset(&hca_param
, 0, sizeof(hca_param
));
501 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
503 mlx4_err(dev
, "QUERY_HCA command failed, aborting.\n");
507 /*fail if the hca has an unknown capability */
508 if ((hca_param
.global_caps
| HCA_GLOBAL_CAP_MASK
) !=
509 HCA_GLOBAL_CAP_MASK
) {
510 mlx4_err(dev
, "Unknown hca global capabilities\n");
514 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
516 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
518 memset(&dev_cap
, 0, sizeof(dev_cap
));
519 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
520 err
= mlx4_dev_cap(dev
, &dev_cap
);
522 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
526 err
= mlx4_QUERY_FW(dev
);
528 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version.\n");
530 page_size
= ~dev
->caps
.page_size_cap
+ 1;
531 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
532 if (page_size
> PAGE_SIZE
) {
533 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
534 "kernel PAGE_SIZE of %ld, aborting.\n",
535 page_size
, PAGE_SIZE
);
539 /* slave gets uar page size from QUERY_HCA fw command */
540 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
542 /* TODO: relax this assumption */
543 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
544 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
545 dev
->caps
.uar_page_size
, PAGE_SIZE
);
549 memset(&func_cap
, 0, sizeof(func_cap
));
550 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
552 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
557 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
558 PF_CONTEXT_BEHAVIOUR_MASK
) {
559 mlx4_err(dev
, "Unknown pf context behaviour\n");
563 dev
->caps
.num_ports
= func_cap
.num_ports
;
564 dev
->caps
.num_qps
= func_cap
.qp_quota
;
565 dev
->caps
.num_srqs
= func_cap
.srq_quota
;
566 dev
->caps
.num_cqs
= func_cap
.cq_quota
;
567 dev
->caps
.num_eqs
= func_cap
.max_eq
;
568 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
569 dev
->caps
.num_mpts
= func_cap
.mpt_quota
;
570 dev
->caps
.num_mtts
= func_cap
.mtt_quota
;
571 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
572 dev
->caps
.num_mgms
= 0;
573 dev
->caps
.num_amgms
= 0;
575 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
576 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
577 "aborting.\n", dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
581 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
582 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
583 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
584 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
586 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
587 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
) {
592 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
593 err
= mlx4_QUERY_FUNC_CAP(dev
, (u32
) i
, &func_cap
);
595 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for"
596 " port %d, aborting (%d).\n", i
, err
);
599 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
600 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
601 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
602 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
603 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
604 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
605 &dev
->caps
.gid_table_len
[i
],
606 &dev
->caps
.pkey_table_len
[i
]))
610 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
611 dev
->caps
.reserved_uars
) >
612 pci_resource_len(dev
->pdev
, 2)) {
613 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than "
614 "PCI resource 2 size of 0x%llx, aborting.\n",
615 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
616 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
620 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
621 dev
->caps
.eqe_size
= 64;
622 dev
->caps
.eqe_factor
= 1;
624 dev
->caps
.eqe_size
= 32;
625 dev
->caps
.eqe_factor
= 0;
628 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
629 dev
->caps
.cqe_size
= 64;
630 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_64B_CQE
;
632 dev
->caps
.cqe_size
= 32;
635 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
640 kfree(dev
->caps
.qp0_tunnel
);
641 kfree(dev
->caps
.qp0_proxy
);
642 kfree(dev
->caps
.qp1_tunnel
);
643 kfree(dev
->caps
.qp1_proxy
);
644 dev
->caps
.qp0_tunnel
= dev
->caps
.qp0_proxy
=
645 dev
->caps
.qp1_tunnel
= dev
->caps
.qp1_proxy
= NULL
;
651 * Change the port configuration of the device.
652 * Every user of this function must hold the port mutex.
654 int mlx4_change_port_types(struct mlx4_dev
*dev
,
655 enum mlx4_port_type
*port_types
)
661 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
662 /* Change the port type only if the new type is different
663 * from the current, and not set to Auto */
664 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
668 mlx4_unregister_device(dev
);
669 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
670 mlx4_CLOSE_PORT(dev
, port
);
671 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
672 err
= mlx4_SET_PORT(dev
, port
, -1);
674 mlx4_err(dev
, "Failed to set port %d, "
679 mlx4_set_port_mask(dev
);
680 err
= mlx4_register_device(dev
);
687 static ssize_t
show_port_type(struct device
*dev
,
688 struct device_attribute
*attr
,
691 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
693 struct mlx4_dev
*mdev
= info
->dev
;
697 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
699 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
700 sprintf(buf
, "auto (%s)\n", type
);
702 sprintf(buf
, "%s\n", type
);
707 static ssize_t
set_port_type(struct device
*dev
,
708 struct device_attribute
*attr
,
709 const char *buf
, size_t count
)
711 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
713 struct mlx4_dev
*mdev
= info
->dev
;
714 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
715 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
716 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
720 if (!strcmp(buf
, "ib\n"))
721 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
722 else if (!strcmp(buf
, "eth\n"))
723 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
724 else if (!strcmp(buf
, "auto\n"))
725 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
727 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
731 mlx4_stop_sense(mdev
);
732 mutex_lock(&priv
->port_mutex
);
733 /* Possible type is always the one that was delivered */
734 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
736 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
737 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
738 mdev
->caps
.possible_type
[i
+1];
739 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
740 types
[i
] = mdev
->caps
.port_type
[i
+1];
743 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
744 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
745 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
746 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
747 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
753 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. "
754 "Set only 'eth' or 'ib' for both ports "
755 "(should be the same)\n");
759 mlx4_do_sense_ports(mdev
, new_types
, types
);
761 err
= mlx4_check_port_params(mdev
, new_types
);
765 /* We are about to apply the changes after the configuration
766 * was verified, no need to remember the temporary types
768 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
769 priv
->port
[i
+ 1].tmp_type
= 0;
771 err
= mlx4_change_port_types(mdev
, new_types
);
774 mlx4_start_sense(mdev
);
775 mutex_unlock(&priv
->port_mutex
);
776 return err
? err
: count
;
787 static inline int int_to_ibta_mtu(int mtu
)
790 case 256: return IB_MTU_256
;
791 case 512: return IB_MTU_512
;
792 case 1024: return IB_MTU_1024
;
793 case 2048: return IB_MTU_2048
;
794 case 4096: return IB_MTU_4096
;
799 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
802 case IB_MTU_256
: return 256;
803 case IB_MTU_512
: return 512;
804 case IB_MTU_1024
: return 1024;
805 case IB_MTU_2048
: return 2048;
806 case IB_MTU_4096
: return 4096;
811 static ssize_t
show_port_ib_mtu(struct device
*dev
,
812 struct device_attribute
*attr
,
815 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
817 struct mlx4_dev
*mdev
= info
->dev
;
819 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
820 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
823 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
827 static ssize_t
set_port_ib_mtu(struct device
*dev
,
828 struct device_attribute
*attr
,
829 const char *buf
, size_t count
)
831 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
833 struct mlx4_dev
*mdev
= info
->dev
;
834 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
835 int err
, port
, mtu
, ibta_mtu
= -1;
837 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
838 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
842 err
= sscanf(buf
, "%d", &mtu
);
844 ibta_mtu
= int_to_ibta_mtu(mtu
);
846 if (err
<= 0 || ibta_mtu
< 0) {
847 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
851 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
853 mlx4_stop_sense(mdev
);
854 mutex_lock(&priv
->port_mutex
);
855 mlx4_unregister_device(mdev
);
856 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
857 mlx4_CLOSE_PORT(mdev
, port
);
858 err
= mlx4_SET_PORT(mdev
, port
, -1);
860 mlx4_err(mdev
, "Failed to set port %d, "
865 err
= mlx4_register_device(mdev
);
867 mutex_unlock(&priv
->port_mutex
);
868 mlx4_start_sense(mdev
);
869 return err
? err
: count
;
872 static int mlx4_load_fw(struct mlx4_dev
*dev
)
874 struct mlx4_priv
*priv
= mlx4_priv(dev
);
877 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
878 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
879 if (!priv
->fw
.fw_icm
) {
880 mlx4_err(dev
, "Couldn't allocate FW area, aborting.\n");
884 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
886 mlx4_err(dev
, "MAP_FA command failed, aborting.\n");
890 err
= mlx4_RUN_FW(dev
);
892 mlx4_err(dev
, "RUN_FW command failed, aborting.\n");
902 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
906 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
909 struct mlx4_priv
*priv
= mlx4_priv(dev
);
913 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
915 ((u64
) (MLX4_CMPT_TYPE_QP
*
916 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
917 cmpt_entry_sz
, dev
->caps
.num_qps
,
918 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
923 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
925 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
926 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
927 cmpt_entry_sz
, dev
->caps
.num_srqs
,
928 dev
->caps
.reserved_srqs
, 0, 0);
932 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
934 ((u64
) (MLX4_CMPT_TYPE_CQ
*
935 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
936 cmpt_entry_sz
, dev
->caps
.num_cqs
,
937 dev
->caps
.reserved_cqs
, 0, 0);
941 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
943 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
945 ((u64
) (MLX4_CMPT_TYPE_EQ
*
946 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
947 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
954 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
957 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
960 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
966 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
967 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
969 struct mlx4_priv
*priv
= mlx4_priv(dev
);
974 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
976 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting.\n");
980 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory.\n",
981 (unsigned long long) icm_size
>> 10,
982 (unsigned long long) aux_pages
<< 2);
984 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
985 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
986 if (!priv
->fw
.aux_icm
) {
987 mlx4_err(dev
, "Couldn't allocate aux memory, aborting.\n");
991 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
993 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting.\n");
997 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
999 mlx4_err(dev
, "Failed to map cMPT context memory, aborting.\n");
1004 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1006 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1007 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1008 num_eqs
, num_eqs
, 0, 0);
1010 mlx4_err(dev
, "Failed to map EQ context memory, aborting.\n");
1011 goto err_unmap_cmpt
;
1015 * Reserved MTT entries must be aligned up to a cacheline
1016 * boundary, since the FW will write to them, while the driver
1017 * writes to all other MTT entries. (The variable
1018 * dev->caps.mtt_entry_sz below is really the MTT segment
1019 * size, not the raw entry size)
1021 dev
->caps
.reserved_mtts
=
1022 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1023 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1025 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1027 dev
->caps
.mtt_entry_sz
,
1029 dev
->caps
.reserved_mtts
, 1, 0);
1031 mlx4_err(dev
, "Failed to map MTT context memory, aborting.\n");
1035 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1036 init_hca
->dmpt_base
,
1037 dev_cap
->dmpt_entry_sz
,
1039 dev
->caps
.reserved_mrws
, 1, 1);
1041 mlx4_err(dev
, "Failed to map dMPT context memory, aborting.\n");
1045 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1047 dev_cap
->qpc_entry_sz
,
1049 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1052 mlx4_err(dev
, "Failed to map QP context memory, aborting.\n");
1053 goto err_unmap_dmpt
;
1056 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1057 init_hca
->auxc_base
,
1058 dev_cap
->aux_entry_sz
,
1060 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1063 mlx4_err(dev
, "Failed to map AUXC context memory, aborting.\n");
1067 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1068 init_hca
->altc_base
,
1069 dev_cap
->altc_entry_sz
,
1071 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1074 mlx4_err(dev
, "Failed to map ALTC context memory, aborting.\n");
1075 goto err_unmap_auxc
;
1078 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1079 init_hca
->rdmarc_base
,
1080 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1082 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1085 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1086 goto err_unmap_altc
;
1089 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1091 dev_cap
->cqc_entry_sz
,
1093 dev
->caps
.reserved_cqs
, 0, 0);
1095 mlx4_err(dev
, "Failed to map CQ context memory, aborting.\n");
1096 goto err_unmap_rdmarc
;
1099 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1100 init_hca
->srqc_base
,
1101 dev_cap
->srq_entry_sz
,
1103 dev
->caps
.reserved_srqs
, 0, 0);
1105 mlx4_err(dev
, "Failed to map SRQ context memory, aborting.\n");
1110 * For flow steering device managed mode it is required to use
1111 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1112 * required, but for simplicity just map the whole multicast
1113 * group table now. The table isn't very big and it's a lot
1114 * easier than trying to track ref counts.
1116 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1118 mlx4_get_mgm_entry_size(dev
),
1119 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1120 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1123 mlx4_err(dev
, "Failed to map MCG context memory, aborting.\n");
1130 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1133 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1136 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1139 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1142 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1145 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1148 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1151 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1154 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1157 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1158 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1159 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1160 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1163 mlx4_UNMAP_ICM_AUX(dev
);
1166 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1171 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1173 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1175 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1176 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1177 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1178 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1179 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1180 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1181 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1182 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1183 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1184 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1185 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1186 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1187 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1188 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1190 mlx4_UNMAP_ICM_AUX(dev
);
1191 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1194 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1196 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1198 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1199 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1200 mlx4_warn(dev
, "Failed to close slave function.\n");
1201 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1204 static int map_bf_area(struct mlx4_dev
*dev
)
1206 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1207 resource_size_t bf_start
;
1208 resource_size_t bf_len
;
1211 if (!dev
->caps
.bf_reg_size
)
1214 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1215 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1216 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1217 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1218 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1219 if (!priv
->bf_mapping
)
1225 static void unmap_bf_area(struct mlx4_dev
*dev
)
1227 if (mlx4_priv(dev
)->bf_mapping
)
1228 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1231 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1233 u32 clockhi
, clocklo
, clockhi1
;
1236 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1238 for (i
= 0; i
< 10; i
++) {
1239 clockhi
= swab32(readl(priv
->clock_mapping
));
1240 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1241 clockhi1
= swab32(readl(priv
->clock_mapping
));
1242 if (clockhi
== clockhi1
)
1246 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1250 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1253 static int map_internal_clock(struct mlx4_dev
*dev
)
1255 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1257 priv
->clock_mapping
=
1258 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1259 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1261 if (!priv
->clock_mapping
)
1267 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1269 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1271 if (priv
->clock_mapping
)
1272 iounmap(priv
->clock_mapping
);
1275 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1277 unmap_internal_clock(dev
);
1279 if (mlx4_is_slave(dev
))
1280 mlx4_slave_exit(dev
);
1282 mlx4_CLOSE_HCA(dev
, 0);
1283 mlx4_free_icms(dev
);
1285 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1289 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1291 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1292 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1293 int num_of_reset_retries
= NUM_OF_RESET_RETRIES
;
1294 int ret_from_reset
= 0;
1296 u32 cmd_channel_ver
;
1298 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1299 priv
->cmd
.max_cmds
= 1;
1300 mlx4_warn(dev
, "Sending reset\n");
1301 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1303 /* if we are in the middle of flr the slave will try
1304 * NUM_OF_RESET_RETRIES times before leaving.*/
1305 if (ret_from_reset
) {
1306 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1307 msleep(SLEEP_TIME_IN_RESET
);
1308 while (ret_from_reset
&& num_of_reset_retries
) {
1309 mlx4_warn(dev
, "slave is currently in the"
1310 "middle of FLR. retrying..."
1312 (NUM_OF_RESET_RETRIES
-
1313 num_of_reset_retries
+ 1));
1315 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
,
1317 num_of_reset_retries
= num_of_reset_retries
- 1;
1323 /* check the driver version - the slave I/F revision
1324 * must match the master's */
1325 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1326 cmd_channel_ver
= mlx4_comm_get_version();
1328 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1329 MLX4_COMM_GET_IF_REV(slave_read
)) {
1330 mlx4_err(dev
, "slave driver version is not supported"
1331 " by the master\n");
1335 mlx4_warn(dev
, "Sending vhcr0\n");
1336 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1339 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1342 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1345 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1348 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1352 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1353 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1357 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1361 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1362 dev
->caps
.gid_table_len
[i
] = 1;
1363 dev
->caps
.pkey_table_len
[i
] =
1364 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1368 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1370 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1372 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1374 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1378 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1381 static void choose_steering_mode(struct mlx4_dev
*dev
,
1382 struct mlx4_dev_cap
*dev_cap
)
1384 if (mlx4_log_num_mgm_entry_size
== -1 &&
1385 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1386 (!mlx4_is_mfunc(dev
) ||
1387 (dev_cap
->fs_max_num_qp_per_entry
>= (num_vfs
+ 1))) &&
1388 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1389 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1390 dev
->oper_log_mgm_entry_size
=
1391 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1392 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1393 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1394 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1395 dev_cap
->fs_log_max_ucast_qp_range_size
;
1397 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1398 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1399 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1401 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1403 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1404 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1405 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags "
1406 "set to use B0 steering. Falling back to A0 steering mode.\n");
1408 dev
->oper_log_mgm_entry_size
=
1409 mlx4_log_num_mgm_entry_size
> 0 ?
1410 mlx4_log_num_mgm_entry_size
:
1411 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1412 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1414 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1415 "modparam log_num_mgm_entry_size = %d\n",
1416 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1417 dev
->oper_log_mgm_entry_size
,
1418 mlx4_log_num_mgm_entry_size
);
1421 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1423 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1424 struct mlx4_adapter adapter
;
1425 struct mlx4_dev_cap dev_cap
;
1426 struct mlx4_mod_stat_cfg mlx4_cfg
;
1427 struct mlx4_profile profile
;
1428 struct mlx4_init_hca_param init_hca
;
1432 if (!mlx4_is_slave(dev
)) {
1433 err
= mlx4_QUERY_FW(dev
);
1436 mlx4_info(dev
, "non-primary physical function, skipping.\n");
1438 mlx4_err(dev
, "QUERY_FW command failed, aborting.\n");
1442 err
= mlx4_load_fw(dev
);
1444 mlx4_err(dev
, "Failed to start FW, aborting.\n");
1448 mlx4_cfg
.log_pg_sz_m
= 1;
1449 mlx4_cfg
.log_pg_sz
= 0;
1450 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1452 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1454 err
= mlx4_dev_cap(dev
, &dev_cap
);
1456 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
1460 choose_steering_mode(dev
, &dev_cap
);
1462 if (mlx4_is_master(dev
))
1463 mlx4_parav_master_pf_caps(dev
);
1465 profile
= default_profile
;
1466 if (dev
->caps
.steering_mode
==
1467 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1468 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1470 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1472 if ((long long) icm_size
< 0) {
1477 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1479 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1480 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1481 init_hca
.mw_enabled
= 0;
1482 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1483 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1484 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1486 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1490 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1492 mlx4_err(dev
, "INIT_HCA command failed, aborting.\n");
1496 * If TS is supported by FW
1497 * read HCA frequency by QUERY_HCA command
1499 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1500 memset(&init_hca
, 0, sizeof(init_hca
));
1501 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1503 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp.\n");
1504 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1506 dev
->caps
.hca_core_clock
=
1507 init_hca
.hca_core_clock
;
1510 /* In case we got HCA frequency 0 - disable timestamping
1511 * to avoid dividing by zero
1513 if (!dev
->caps
.hca_core_clock
) {
1514 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1516 "HCA frequency is 0. Timestamping is not supported.");
1517 } else if (map_internal_clock(dev
)) {
1519 * Map internal clock,
1520 * in case of failure disable timestamping
1522 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1523 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported.\n");
1527 err
= mlx4_init_slave(dev
);
1529 mlx4_err(dev
, "Failed to initialize slave\n");
1533 err
= mlx4_slave_cap(dev
);
1535 mlx4_err(dev
, "Failed to obtain slave caps\n");
1540 if (map_bf_area(dev
))
1541 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1543 /*Only the master set the ports, all the rest got it from it.*/
1544 if (!mlx4_is_slave(dev
))
1545 mlx4_set_port_mask(dev
);
1547 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1549 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting.\n");
1553 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1554 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1559 unmap_internal_clock(dev
);
1563 if (mlx4_is_slave(dev
))
1564 mlx4_slave_exit(dev
);
1566 mlx4_CLOSE_HCA(dev
, 0);
1569 if (!mlx4_is_slave(dev
))
1570 mlx4_free_icms(dev
);
1573 if (!mlx4_is_slave(dev
)) {
1575 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1580 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1582 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1585 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1588 nent
= dev
->caps
.max_counters
;
1589 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1592 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1594 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1597 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1599 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1601 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1604 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1611 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1616 if (mlx4_is_mfunc(dev
)) {
1617 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1618 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1619 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1621 *idx
= get_param_l(&out_param
);
1625 return __mlx4_counter_alloc(dev
, idx
);
1627 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1629 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1631 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
);
1635 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1639 if (mlx4_is_mfunc(dev
)) {
1640 set_param_l(&in_param
, idx
);
1641 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1642 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1646 __mlx4_counter_free(dev
, idx
);
1648 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1650 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1652 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1655 __be32 ib_port_default_caps
;
1657 err
= mlx4_init_uar_table(dev
);
1659 mlx4_err(dev
, "Failed to initialize "
1660 "user access region table, aborting.\n");
1664 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1666 mlx4_err(dev
, "Failed to allocate driver access region, "
1668 goto err_uar_table_free
;
1671 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1673 mlx4_err(dev
, "Couldn't map kernel access region, "
1679 err
= mlx4_init_pd_table(dev
);
1681 mlx4_err(dev
, "Failed to initialize "
1682 "protection domain table, aborting.\n");
1686 err
= mlx4_init_xrcd_table(dev
);
1688 mlx4_err(dev
, "Failed to initialize "
1689 "reliable connection domain table, aborting.\n");
1690 goto err_pd_table_free
;
1693 err
= mlx4_init_mr_table(dev
);
1695 mlx4_err(dev
, "Failed to initialize "
1696 "memory region table, aborting.\n");
1697 goto err_xrcd_table_free
;
1700 err
= mlx4_init_eq_table(dev
);
1702 mlx4_err(dev
, "Failed to initialize "
1703 "event queue table, aborting.\n");
1704 goto err_mr_table_free
;
1707 err
= mlx4_cmd_use_events(dev
);
1709 mlx4_err(dev
, "Failed to switch to event-driven "
1710 "firmware commands, aborting.\n");
1711 goto err_eq_table_free
;
1714 err
= mlx4_NOP(dev
);
1716 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
1717 mlx4_warn(dev
, "NOP command failed to generate MSI-X "
1718 "interrupt IRQ %d).\n",
1719 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1720 mlx4_warn(dev
, "Trying again without MSI-X.\n");
1722 mlx4_err(dev
, "NOP command failed to generate interrupt "
1723 "(IRQ %d), aborting.\n",
1724 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1725 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
1731 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
1733 err
= mlx4_init_cq_table(dev
);
1735 mlx4_err(dev
, "Failed to initialize "
1736 "completion queue table, aborting.\n");
1740 err
= mlx4_init_srq_table(dev
);
1742 mlx4_err(dev
, "Failed to initialize "
1743 "shared receive queue table, aborting.\n");
1744 goto err_cq_table_free
;
1747 err
= mlx4_init_qp_table(dev
);
1749 mlx4_err(dev
, "Failed to initialize "
1750 "queue pair table, aborting.\n");
1751 goto err_srq_table_free
;
1754 if (!mlx4_is_slave(dev
)) {
1755 err
= mlx4_init_mcg_table(dev
);
1757 mlx4_err(dev
, "Failed to initialize "
1758 "multicast group table, aborting.\n");
1759 goto err_qp_table_free
;
1763 err
= mlx4_init_counters_table(dev
);
1764 if (err
&& err
!= -ENOENT
) {
1765 mlx4_err(dev
, "Failed to initialize counters table, aborting.\n");
1766 goto err_mcg_table_free
;
1769 if (!mlx4_is_slave(dev
)) {
1770 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
1771 ib_port_default_caps
= 0;
1772 err
= mlx4_get_port_ib_caps(dev
, port
,
1773 &ib_port_default_caps
);
1775 mlx4_warn(dev
, "failed to get port %d default "
1776 "ib capabilities (%d). Continuing "
1777 "with caps = 0\n", port
, err
);
1778 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
1780 /* initialize per-slave default ib port capabilities */
1781 if (mlx4_is_master(dev
)) {
1783 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1784 if (i
== mlx4_master_func_num(dev
))
1786 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
1787 ib_port_default_caps
;
1791 if (mlx4_is_mfunc(dev
))
1792 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
1794 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
1796 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
1797 dev
->caps
.pkey_table_len
[port
] : -1);
1799 mlx4_err(dev
, "Failed to set port %d, aborting\n",
1801 goto err_counters_table_free
;
1808 err_counters_table_free
:
1809 mlx4_cleanup_counters_table(dev
);
1812 mlx4_cleanup_mcg_table(dev
);
1815 mlx4_cleanup_qp_table(dev
);
1818 mlx4_cleanup_srq_table(dev
);
1821 mlx4_cleanup_cq_table(dev
);
1824 mlx4_cmd_use_polling(dev
);
1827 mlx4_cleanup_eq_table(dev
);
1830 mlx4_cleanup_mr_table(dev
);
1832 err_xrcd_table_free
:
1833 mlx4_cleanup_xrcd_table(dev
);
1836 mlx4_cleanup_pd_table(dev
);
1842 mlx4_uar_free(dev
, &priv
->driver_uar
);
1845 mlx4_cleanup_uar_table(dev
);
1849 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
1851 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1852 struct msix_entry
*entries
;
1853 int nreq
= min_t(int, dev
->caps
.num_ports
*
1854 min_t(int, netif_get_num_default_rss_queues() + 1,
1855 MAX_MSIX_P_PORT
) + MSIX_LEGACY_SZ
, MAX_MSIX
);
1860 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
1863 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
1867 for (i
= 0; i
< nreq
; ++i
)
1868 entries
[i
].entry
= i
;
1871 err
= pci_enable_msix(dev
->pdev
, entries
, nreq
);
1873 /* Try again if at least 2 vectors are available */
1875 mlx4_info(dev
, "Requested %d vectors, "
1876 "but only %d MSI-X vectors available, "
1877 "trying again\n", nreq
, err
);
1886 MSIX_LEGACY_SZ
+ dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
1887 /*Working in legacy mode , all EQ's shared*/
1888 dev
->caps
.comp_pool
= 0;
1889 dev
->caps
.num_comp_vectors
= nreq
- 1;
1891 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
1892 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
1894 for (i
= 0; i
< nreq
; ++i
)
1895 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
1897 dev
->flags
|= MLX4_FLAG_MSI_X
;
1904 dev
->caps
.num_comp_vectors
= 1;
1905 dev
->caps
.comp_pool
= 0;
1907 for (i
= 0; i
< 2; ++i
)
1908 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
1911 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
1913 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
1918 if (!mlx4_is_slave(dev
)) {
1919 mlx4_init_mac_table(dev
, &info
->mac_table
);
1920 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
1921 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
1924 sprintf(info
->dev_name
, "mlx4_port%d", port
);
1925 info
->port_attr
.attr
.name
= info
->dev_name
;
1926 if (mlx4_is_mfunc(dev
))
1927 info
->port_attr
.attr
.mode
= S_IRUGO
;
1929 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
1930 info
->port_attr
.store
= set_port_type
;
1932 info
->port_attr
.show
= show_port_type
;
1933 sysfs_attr_init(&info
->port_attr
.attr
);
1935 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
1937 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
1941 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
1942 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
1943 if (mlx4_is_mfunc(dev
))
1944 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
1946 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
1947 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
1949 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
1950 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
1952 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
1954 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
1955 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
1962 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
1967 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
1968 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
1971 static int mlx4_init_steering(struct mlx4_dev
*dev
)
1973 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1974 int num_entries
= dev
->caps
.num_ports
;
1977 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
1981 for (i
= 0; i
< num_entries
; i
++)
1982 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
1983 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
1984 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
1989 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
1991 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1992 struct mlx4_steer_index
*entry
, *tmp_entry
;
1993 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
1994 int num_entries
= dev
->caps
.num_ports
;
1997 for (i
= 0; i
< num_entries
; i
++) {
1998 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
1999 list_for_each_entry_safe(pqp
, tmp_pqp
,
2000 &priv
->steer
[i
].promisc_qps
[j
],
2002 list_del(&pqp
->list
);
2005 list_for_each_entry_safe(entry
, tmp_entry
,
2006 &priv
->steer
[i
].steer_entries
[j
],
2008 list_del(&entry
->list
);
2009 list_for_each_entry_safe(pqp
, tmp_pqp
,
2012 list_del(&pqp
->list
);
2022 static int extended_func_num(struct pci_dev
*pdev
)
2024 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2027 #define MLX4_OWNER_BASE 0x8069c
2028 #define MLX4_OWNER_SIZE 4
2030 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2032 void __iomem
*owner
;
2035 if (pci_channel_offline(dev
->pdev
))
2038 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2041 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2050 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2052 void __iomem
*owner
;
2054 if (pci_channel_offline(dev
->pdev
))
2057 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2060 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2068 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
)
2070 struct mlx4_priv
*priv
;
2071 struct mlx4_dev
*dev
;
2075 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2077 err
= pci_enable_device(pdev
);
2079 dev_err(&pdev
->dev
, "Cannot enable PCI device, "
2083 if (num_vfs
> MLX4_MAX_NUM_VF
) {
2084 printk(KERN_ERR
"There are more VF's (%d) than allowed(%d)\n",
2085 num_vfs
, MLX4_MAX_NUM_VF
);
2091 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2092 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2093 dev_err(&pdev
->dev
, "Missing DCS, aborting."
2094 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2095 pci_dev_data
, pci_resource_flags(pdev
, 0));
2097 goto err_disable_pdev
;
2099 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2100 dev_err(&pdev
->dev
, "Missing UAR, aborting.\n");
2102 goto err_disable_pdev
;
2105 err
= pci_request_regions(pdev
, DRV_NAME
);
2107 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2108 goto err_disable_pdev
;
2111 pci_set_master(pdev
);
2113 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2115 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2116 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2118 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting.\n");
2119 goto err_release_regions
;
2122 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2124 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit "
2125 "consistent PCI DMA mask.\n");
2126 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2128 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, "
2130 goto err_release_regions
;
2134 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2135 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2137 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2140 goto err_release_regions
;
2145 INIT_LIST_HEAD(&priv
->ctx_list
);
2146 spin_lock_init(&priv
->ctx_lock
);
2148 mutex_init(&priv
->port_mutex
);
2150 INIT_LIST_HEAD(&priv
->pgdir_list
);
2151 mutex_init(&priv
->pgdir_mutex
);
2153 INIT_LIST_HEAD(&priv
->bf_list
);
2154 mutex_init(&priv
->bf_mutex
);
2156 dev
->rev_id
= pdev
->revision
;
2157 /* Detect if this device is a virtual function */
2158 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2159 /* When acting as pf, we normally skip vfs unless explicitly
2160 * requested to probe them. */
2161 if (num_vfs
&& extended_func_num(pdev
) > probe_vf
) {
2162 mlx4_warn(dev
, "Skipping virtual function:%d\n",
2163 extended_func_num(pdev
));
2167 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2168 dev
->flags
|= MLX4_FLAG_SLAVE
;
2170 /* We reset the device and enable SRIOV only for physical
2171 * devices. Try to claim ownership on the device;
2172 * if already taken, skip -- do not allow multiple PFs */
2173 err
= mlx4_get_ownership(dev
);
2178 mlx4_warn(dev
, "Multiple PFs not yet supported."
2186 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n", num_vfs
);
2187 err
= pci_enable_sriov(pdev
, num_vfs
);
2189 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2193 mlx4_warn(dev
, "Running in master mode\n");
2194 dev
->flags
|= MLX4_FLAG_SRIOV
|
2196 dev
->num_vfs
= num_vfs
;
2201 * Now reset the HCA before we touch the PCI capabilities or
2202 * attempt a firmware command, since a boot ROM may have left
2203 * the HCA in an undefined state.
2205 err
= mlx4_reset(dev
);
2207 mlx4_err(dev
, "Failed to reset HCA, aborting.\n");
2213 err
= mlx4_cmd_init(dev
);
2215 mlx4_err(dev
, "Failed to init command interface, aborting.\n");
2219 /* In slave functions, the communication channel must be initialized
2220 * before posting commands. Also, init num_slaves before calling
2222 if (mlx4_is_mfunc(dev
)) {
2223 if (mlx4_is_master(dev
))
2224 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2226 dev
->num_slaves
= 0;
2227 err
= mlx4_multi_func_init(dev
);
2229 mlx4_err(dev
, "Failed to init slave mfunc"
2230 " interface, aborting.\n");
2236 err
= mlx4_init_hca(dev
);
2238 if (err
== -EACCES
) {
2239 /* Not primary Physical function
2240 * Running in slave mode */
2241 mlx4_cmd_cleanup(dev
);
2242 dev
->flags
|= MLX4_FLAG_SLAVE
;
2243 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2249 /* In master functions, the communication channel must be initialized
2250 * after obtaining its address from fw */
2251 if (mlx4_is_master(dev
)) {
2252 err
= mlx4_multi_func_init(dev
);
2254 mlx4_err(dev
, "Failed to init master mfunc"
2255 "interface, aborting.\n");
2260 err
= mlx4_alloc_eq_table(dev
);
2262 goto err_master_mfunc
;
2264 priv
->msix_ctl
.pool_bm
= 0;
2265 mutex_init(&priv
->msix_ctl
.pool_lock
);
2267 mlx4_enable_msi_x(dev
);
2268 if ((mlx4_is_mfunc(dev
)) &&
2269 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2271 mlx4_err(dev
, "INTx is not supported in multi-function mode."
2276 if (!mlx4_is_slave(dev
)) {
2277 err
= mlx4_init_steering(dev
);
2282 err
= mlx4_setup_hca(dev
);
2283 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2284 !mlx4_is_mfunc(dev
)) {
2285 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2286 dev
->caps
.num_comp_vectors
= 1;
2287 dev
->caps
.comp_pool
= 0;
2288 pci_disable_msix(pdev
);
2289 err
= mlx4_setup_hca(dev
);
2295 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2296 err
= mlx4_init_port_info(dev
, port
);
2301 err
= mlx4_register_device(dev
);
2305 mlx4_sense_init(dev
);
2306 mlx4_start_sense(dev
);
2308 priv
->pci_dev_data
= pci_dev_data
;
2309 pci_set_drvdata(pdev
, dev
);
2314 for (--port
; port
>= 1; --port
)
2315 mlx4_cleanup_port_info(&priv
->port
[port
]);
2317 mlx4_cleanup_counters_table(dev
);
2318 mlx4_cleanup_mcg_table(dev
);
2319 mlx4_cleanup_qp_table(dev
);
2320 mlx4_cleanup_srq_table(dev
);
2321 mlx4_cleanup_cq_table(dev
);
2322 mlx4_cmd_use_polling(dev
);
2323 mlx4_cleanup_eq_table(dev
);
2324 mlx4_cleanup_mr_table(dev
);
2325 mlx4_cleanup_xrcd_table(dev
);
2326 mlx4_cleanup_pd_table(dev
);
2327 mlx4_cleanup_uar_table(dev
);
2330 if (!mlx4_is_slave(dev
))
2331 mlx4_clear_steering(dev
);
2334 mlx4_free_eq_table(dev
);
2337 if (mlx4_is_master(dev
))
2338 mlx4_multi_func_cleanup(dev
);
2341 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2342 pci_disable_msix(pdev
);
2344 mlx4_close_hca(dev
);
2347 if (mlx4_is_slave(dev
))
2348 mlx4_multi_func_cleanup(dev
);
2351 mlx4_cmd_cleanup(dev
);
2354 if (dev
->flags
& MLX4_FLAG_SRIOV
)
2355 pci_disable_sriov(pdev
);
2358 if (!mlx4_is_slave(dev
))
2359 mlx4_free_ownership(dev
);
2364 err_release_regions
:
2365 pci_release_regions(pdev
);
2368 pci_disable_device(pdev
);
2369 pci_set_drvdata(pdev
, NULL
);
2373 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2375 printk_once(KERN_INFO
"%s", mlx4_version
);
2377 return __mlx4_init_one(pdev
, id
->driver_data
);
2380 static void mlx4_remove_one(struct pci_dev
*pdev
)
2382 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2383 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2387 /* in SRIOV it is not allowed to unload the pf's
2388 * driver while there are alive vf's */
2389 if (mlx4_is_master(dev
)) {
2390 if (mlx4_how_many_lives_vf(dev
))
2391 printk(KERN_ERR
"Removing PF when there are assigned VF's !!!\n");
2393 mlx4_stop_sense(dev
);
2394 mlx4_unregister_device(dev
);
2396 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2397 mlx4_cleanup_port_info(&priv
->port
[p
]);
2398 mlx4_CLOSE_PORT(dev
, p
);
2401 if (mlx4_is_master(dev
))
2402 mlx4_free_resource_tracker(dev
,
2403 RES_TR_FREE_SLAVES_ONLY
);
2405 mlx4_cleanup_counters_table(dev
);
2406 mlx4_cleanup_mcg_table(dev
);
2407 mlx4_cleanup_qp_table(dev
);
2408 mlx4_cleanup_srq_table(dev
);
2409 mlx4_cleanup_cq_table(dev
);
2410 mlx4_cmd_use_polling(dev
);
2411 mlx4_cleanup_eq_table(dev
);
2412 mlx4_cleanup_mr_table(dev
);
2413 mlx4_cleanup_xrcd_table(dev
);
2414 mlx4_cleanup_pd_table(dev
);
2416 if (mlx4_is_master(dev
))
2417 mlx4_free_resource_tracker(dev
,
2418 RES_TR_FREE_STRUCTS_ONLY
);
2421 mlx4_uar_free(dev
, &priv
->driver_uar
);
2422 mlx4_cleanup_uar_table(dev
);
2423 if (!mlx4_is_slave(dev
))
2424 mlx4_clear_steering(dev
);
2425 mlx4_free_eq_table(dev
);
2426 if (mlx4_is_master(dev
))
2427 mlx4_multi_func_cleanup(dev
);
2428 mlx4_close_hca(dev
);
2429 if (mlx4_is_slave(dev
))
2430 mlx4_multi_func_cleanup(dev
);
2431 mlx4_cmd_cleanup(dev
);
2433 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2434 pci_disable_msix(pdev
);
2435 if (dev
->flags
& MLX4_FLAG_SRIOV
) {
2436 mlx4_warn(dev
, "Disabling SR-IOV\n");
2437 pci_disable_sriov(pdev
);
2440 if (!mlx4_is_slave(dev
))
2441 mlx4_free_ownership(dev
);
2443 kfree(dev
->caps
.qp0_tunnel
);
2444 kfree(dev
->caps
.qp0_proxy
);
2445 kfree(dev
->caps
.qp1_tunnel
);
2446 kfree(dev
->caps
.qp1_proxy
);
2449 pci_release_regions(pdev
);
2450 pci_disable_device(pdev
);
2451 pci_set_drvdata(pdev
, NULL
);
2455 int mlx4_restart_one(struct pci_dev
*pdev
)
2457 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2458 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2461 pci_dev_data
= priv
->pci_dev_data
;
2462 mlx4_remove_one(pdev
);
2463 return __mlx4_init_one(pdev
, pci_dev_data
);
2466 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table
) = {
2467 /* MT25408 "Hermon" SDR */
2468 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2469 /* MT25408 "Hermon" DDR */
2470 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2471 /* MT25408 "Hermon" QDR */
2472 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2473 /* MT25408 "Hermon" DDR PCIe gen2 */
2474 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2475 /* MT25408 "Hermon" QDR PCIe gen2 */
2476 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2477 /* MT25408 "Hermon" EN 10GigE */
2478 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2479 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2480 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2481 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2482 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2483 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2484 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2485 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2486 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2487 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2488 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2489 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2490 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2491 /* MT25400 Family [ConnectX-2 Virtual Function] */
2492 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
2493 /* MT27500 Family [ConnectX-3] */
2494 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
2495 /* MT27500 Family [ConnectX-3 Virtual Function] */
2496 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
2497 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
2498 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
2499 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
2500 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
2501 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
2502 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
2503 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
2504 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
2505 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
2506 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
2507 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
2508 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
2512 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
2514 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
2515 pci_channel_state_t state
)
2517 mlx4_remove_one(pdev
);
2519 return state
== pci_channel_io_perm_failure
?
2520 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
2523 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
2525 int ret
= __mlx4_init_one(pdev
, 0);
2527 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
2530 static const struct pci_error_handlers mlx4_err_handler
= {
2531 .error_detected
= mlx4_pci_err_detected
,
2532 .slot_reset
= mlx4_pci_slot_reset
,
2535 static struct pci_driver mlx4_driver
= {
2537 .id_table
= mlx4_pci_table
,
2538 .probe
= mlx4_init_one
,
2539 .remove
= mlx4_remove_one
,
2540 .err_handler
= &mlx4_err_handler
,
2543 static int __init
mlx4_verify_params(void)
2545 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
2546 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac
);
2550 if (log_num_vlan
!= 0)
2551 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2552 MLX4_LOG_NUM_VLANS
);
2554 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
2555 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg
);
2559 /* Check if module param for ports type has legal combination */
2560 if (port_type_array
[0] == false && port_type_array
[1] == true) {
2561 printk(KERN_WARNING
"Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2562 port_type_array
[0] = true;
2565 if (mlx4_log_num_mgm_entry_size
!= -1 &&
2566 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
2567 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
2568 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2569 "in legal range (-1 or %d..%d)\n",
2570 mlx4_log_num_mgm_entry_size
,
2571 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
2572 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
2579 static int __init
mlx4_init(void)
2583 if (mlx4_verify_params())
2588 mlx4_wq
= create_singlethread_workqueue("mlx4");
2592 ret
= pci_register_driver(&mlx4_driver
);
2593 return ret
< 0 ? ret
: 0;
2596 static void __exit
mlx4_cleanup(void)
2598 pci_unregister_driver(&mlx4_driver
);
2599 destroy_workqueue(mlx4_wq
);
2602 module_init(mlx4_init
);
2603 module_exit(mlx4_cleanup
);