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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
45
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
48
49 #include "mlx4.h"
50 #include "fw.h"
51 #include "icm.h"
52
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
57
58 struct workqueue_struct *mlx4_wq;
59
60 #ifdef CONFIG_MLX4_DEBUG
61
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66 #endif /* CONFIG_MLX4_DEBUG */
67
68 #ifdef CONFIG_PCI_MSI
69
70 static int msi_x = 1;
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74 #else /* CONFIG_PCI_MSI */
75
76 #define msi_x (0)
77
78 #endif /* CONFIG_PCI_MSI */
79
80 static int num_vfs;
81 module_param(num_vfs, int, 0444);
82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
83
84 static int probe_vf;
85 module_param(probe_vf, int, 0644);
86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
87
88 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
89 module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 7 <="
94 " log_num_mgm_entry_size <= 12."
95 " To activate device managed"
96 " flow steering when available, set to -1");
97
98 static bool enable_64b_cqe_eqe;
99 module_param(enable_64b_cqe_eqe, bool, 0444);
100 MODULE_PARM_DESC(enable_64b_cqe_eqe,
101 "Enable 64 byte CQEs/EQEs when the the FW supports this");
102
103 #define HCA_GLOBAL_CAP_MASK 0
104
105 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
106
107 static char mlx4_version[] =
108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
110
111 static struct mlx4_profile default_profile = {
112 .num_qp = 1 << 18,
113 .num_srq = 1 << 16,
114 .rdmarc_per_qp = 1 << 4,
115 .num_cq = 1 << 16,
116 .num_mcg = 1 << 13,
117 .num_mpt = 1 << 19,
118 .num_mtt = 1 << 20, /* It is really num mtt segements */
119 };
120
121 static int log_num_mac = 7;
122 module_param_named(log_num_mac, log_num_mac, int, 0444);
123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
124
125 static int log_num_vlan;
126 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
128 /* Log2 max number of VLANs per ETH port (0-7) */
129 #define MLX4_LOG_NUM_VLANS 7
130
131 static bool use_prio;
132 module_param_named(use_prio, use_prio, bool, 0444);
133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
134 "(0/1, default 0)");
135
136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
139
140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
141 static int arr_argc = 2;
142 module_param_array(port_type_array, int, &arr_argc, 0444);
143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
145
146 struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
150 };
151
152 int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
154 {
155 int i;
156
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
162 return -EINVAL;
163 }
164 }
165 }
166
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
171 return -EINVAL;
172 }
173 }
174 return 0;
175 }
176
177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
178 {
179 int i;
180
181 for (i = 1; i <= dev->caps.num_ports; ++i)
182 dev->caps.port_mask[i] = dev->caps.port_type[i];
183 }
184
185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
186 {
187 int err;
188 int i;
189
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
191 if (err) {
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
193 return err;
194 }
195
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
200 return -ENODEV;
201 }
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
204 "aborting.\n",
205 dev_cap->num_ports, MLX4_MAX_PORTS);
206 return -ENODEV;
207 }
208
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
212 dev_cap->uar_size,
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
214 return -ENODEV;
215 }
216
217 dev->caps.num_ports = dev_cap->num_ports;
218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
238 }
239
240 dev->caps.uar_page_size = PAGE_SIZE;
241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
254 /*
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
258 */
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
264
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
267 dev->caps.reserved_pds = dev_cap->reserved_pds;
268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
273
274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
277 dev->caps.flags2 = dev_cap->flags2;
278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
283
284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev))
289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
290
291 dev->caps.log_num_macs = log_num_mac;
292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
293 dev->caps.log_num_prios = use_prio ? 3 : 0;
294
295 for (i = 1; i <= dev->caps.num_ports; ++i) {
296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
297 if (dev->caps.supported_type[i]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
301 /* if only IB is supported, assign IB */
302 else if (dev->caps.supported_type[i] ==
303 MLX4_PORT_TYPE_IB)
304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
305 else {
306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
312 else
313 dev->caps.port_type[i] = port_type_array[i - 1];
314 }
315 }
316 /*
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
321 */
322 mlx4_priv(dev)->sense.sense_allowed[i] =
323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
326
327 /*
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
331 */
332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
335 mlx4_SENSE_PORT(dev, i, &sensed_port);
336 if (sensed_port != MLX4_PORT_TYPE_NONE)
337 dev->caps.port_type[i] = sensed_port;
338 } else {
339 dev->caps.possible_type[i] = dev->caps.port_type[i];
340 }
341
342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
343 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
344 mlx4_warn(dev, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i, 1 << dev->caps.log_num_macs);
347 }
348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
350 mlx4_warn(dev, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_vlans);
353 }
354 }
355
356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
357
358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
361 (1 << dev->caps.log_num_macs) *
362 (1 << dev->caps.log_num_vlans) *
363 (1 << dev->caps.log_num_prios) *
364 dev->caps.num_ports;
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
366
367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
371
372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
373
374 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
375 if (dev_cap->flags &
376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
380 }
381 }
382
383 if ((dev->caps.flags &
384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
385 mlx4_is_master(dev))
386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
387
388 return 0;
389 }
390 /*The function checks if there are live vf, return the num of them*/
391 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
392 {
393 struct mlx4_priv *priv = mlx4_priv(dev);
394 struct mlx4_slave_state *s_state;
395 int i;
396 int ret = 0;
397
398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
399 s_state = &priv->mfunc.master.slave_state[i];
400 if (s_state->active && s_state->last_cmd !=
401 MLX4_COMM_CMD_RESET) {
402 mlx4_warn(dev, "%s: slave: %d is still active\n",
403 __func__, i);
404 ret++;
405 }
406 }
407 return ret;
408 }
409
410 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
411 {
412 u32 qk = MLX4_RESERVED_QKEY_BASE;
413
414 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
415 qpn < dev->phys_caps.base_proxy_sqpn)
416 return -EINVAL;
417
418 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
419 /* tunnel qp */
420 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
421 else
422 qk += qpn - dev->phys_caps.base_proxy_sqpn;
423 *qkey = qk;
424 return 0;
425 }
426 EXPORT_SYMBOL(mlx4_get_parav_qkey);
427
428 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
429 {
430 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
431
432 if (!mlx4_is_master(dev))
433 return;
434
435 priv->virt2phys_pkey[slave][port - 1][i] = val;
436 }
437 EXPORT_SYMBOL(mlx4_sync_pkey_table);
438
439 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
440 {
441 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
442
443 if (!mlx4_is_master(dev))
444 return;
445
446 priv->slave_node_guids[slave] = guid;
447 }
448 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
449
450 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
451 {
452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
453
454 if (!mlx4_is_master(dev))
455 return 0;
456
457 return priv->slave_node_guids[slave];
458 }
459 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
460
461 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
462 {
463 struct mlx4_priv *priv = mlx4_priv(dev);
464 struct mlx4_slave_state *s_slave;
465
466 if (!mlx4_is_master(dev))
467 return 0;
468
469 s_slave = &priv->mfunc.master.slave_state[slave];
470 return !!s_slave->active;
471 }
472 EXPORT_SYMBOL(mlx4_is_slave_active);
473
474 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
475 struct mlx4_dev_cap *dev_cap,
476 struct mlx4_init_hca_param *hca_param)
477 {
478 dev->caps.steering_mode = hca_param->steering_mode;
479 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
480 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
481 dev->caps.fs_log_max_ucast_qp_range_size =
482 dev_cap->fs_log_max_ucast_qp_range_size;
483 } else
484 dev->caps.num_qp_per_mgm =
485 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
486
487 mlx4_dbg(dev, "Steering mode is: %s\n",
488 mlx4_steering_mode_str(dev->caps.steering_mode));
489 }
490
491 static int mlx4_slave_cap(struct mlx4_dev *dev)
492 {
493 int err;
494 u32 page_size;
495 struct mlx4_dev_cap dev_cap;
496 struct mlx4_func_cap func_cap;
497 struct mlx4_init_hca_param hca_param;
498 int i;
499
500 memset(&hca_param, 0, sizeof(hca_param));
501 err = mlx4_QUERY_HCA(dev, &hca_param);
502 if (err) {
503 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
504 return err;
505 }
506
507 /*fail if the hca has an unknown capability */
508 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
509 HCA_GLOBAL_CAP_MASK) {
510 mlx4_err(dev, "Unknown hca global capabilities\n");
511 return -ENOSYS;
512 }
513
514 dev->caps.hca_core_clock = hca_param.hca_core_clock;
515
516 memset(&dev_cap, 0, sizeof(dev_cap));
517 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
518 err = mlx4_dev_cap(dev, &dev_cap);
519 if (err) {
520 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
521 return err;
522 }
523
524 err = mlx4_QUERY_FW(dev);
525 if (err)
526 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
527
528 page_size = ~dev->caps.page_size_cap + 1;
529 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
530 if (page_size > PAGE_SIZE) {
531 mlx4_err(dev, "HCA minimum page size of %d bigger than "
532 "kernel PAGE_SIZE of %ld, aborting.\n",
533 page_size, PAGE_SIZE);
534 return -ENODEV;
535 }
536
537 /* slave gets uar page size from QUERY_HCA fw command */
538 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
539
540 /* TODO: relax this assumption */
541 if (dev->caps.uar_page_size != PAGE_SIZE) {
542 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
543 dev->caps.uar_page_size, PAGE_SIZE);
544 return -ENODEV;
545 }
546
547 memset(&func_cap, 0, sizeof(func_cap));
548 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
549 if (err) {
550 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
551 err);
552 return err;
553 }
554
555 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
556 PF_CONTEXT_BEHAVIOUR_MASK) {
557 mlx4_err(dev, "Unknown pf context behaviour\n");
558 return -ENOSYS;
559 }
560
561 dev->caps.num_ports = func_cap.num_ports;
562 dev->caps.num_qps = func_cap.qp_quota;
563 dev->caps.num_srqs = func_cap.srq_quota;
564 dev->caps.num_cqs = func_cap.cq_quota;
565 dev->caps.num_eqs = func_cap.max_eq;
566 dev->caps.reserved_eqs = func_cap.reserved_eq;
567 dev->caps.num_mpts = func_cap.mpt_quota;
568 dev->caps.num_mtts = func_cap.mtt_quota;
569 dev->caps.num_pds = MLX4_NUM_PDS;
570 dev->caps.num_mgms = 0;
571 dev->caps.num_amgms = 0;
572
573 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
574 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
575 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
576 return -ENODEV;
577 }
578
579 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
580 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
581 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
582 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
583
584 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
585 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
586 err = -ENOMEM;
587 goto err_mem;
588 }
589
590 for (i = 1; i <= dev->caps.num_ports; ++i) {
591 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
592 if (err) {
593 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
594 " port %d, aborting (%d).\n", i, err);
595 goto err_mem;
596 }
597 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
598 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
599 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
600 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
601 dev->caps.port_mask[i] = dev->caps.port_type[i];
602 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
603 &dev->caps.gid_table_len[i],
604 &dev->caps.pkey_table_len[i]))
605 goto err_mem;
606 }
607
608 if (dev->caps.uar_page_size * (dev->caps.num_uars -
609 dev->caps.reserved_uars) >
610 pci_resource_len(dev->pdev, 2)) {
611 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
612 "PCI resource 2 size of 0x%llx, aborting.\n",
613 dev->caps.uar_page_size * dev->caps.num_uars,
614 (unsigned long long) pci_resource_len(dev->pdev, 2));
615 goto err_mem;
616 }
617
618 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
619 dev->caps.eqe_size = 64;
620 dev->caps.eqe_factor = 1;
621 } else {
622 dev->caps.eqe_size = 32;
623 dev->caps.eqe_factor = 0;
624 }
625
626 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
627 dev->caps.cqe_size = 64;
628 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
629 } else {
630 dev->caps.cqe_size = 32;
631 }
632
633 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
634 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
635
636 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
637
638 return 0;
639
640 err_mem:
641 kfree(dev->caps.qp0_tunnel);
642 kfree(dev->caps.qp0_proxy);
643 kfree(dev->caps.qp1_tunnel);
644 kfree(dev->caps.qp1_proxy);
645 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
646 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
647
648 return err;
649 }
650
651 /*
652 * Change the port configuration of the device.
653 * Every user of this function must hold the port mutex.
654 */
655 int mlx4_change_port_types(struct mlx4_dev *dev,
656 enum mlx4_port_type *port_types)
657 {
658 int err = 0;
659 int change = 0;
660 int port;
661
662 for (port = 0; port < dev->caps.num_ports; port++) {
663 /* Change the port type only if the new type is different
664 * from the current, and not set to Auto */
665 if (port_types[port] != dev->caps.port_type[port + 1])
666 change = 1;
667 }
668 if (change) {
669 mlx4_unregister_device(dev);
670 for (port = 1; port <= dev->caps.num_ports; port++) {
671 mlx4_CLOSE_PORT(dev, port);
672 dev->caps.port_type[port] = port_types[port - 1];
673 err = mlx4_SET_PORT(dev, port, -1);
674 if (err) {
675 mlx4_err(dev, "Failed to set port %d, "
676 "aborting\n", port);
677 goto out;
678 }
679 }
680 mlx4_set_port_mask(dev);
681 err = mlx4_register_device(dev);
682 }
683
684 out:
685 return err;
686 }
687
688 static ssize_t show_port_type(struct device *dev,
689 struct device_attribute *attr,
690 char *buf)
691 {
692 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
693 port_attr);
694 struct mlx4_dev *mdev = info->dev;
695 char type[8];
696
697 sprintf(type, "%s",
698 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
699 "ib" : "eth");
700 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
701 sprintf(buf, "auto (%s)\n", type);
702 else
703 sprintf(buf, "%s\n", type);
704
705 return strlen(buf);
706 }
707
708 static ssize_t set_port_type(struct device *dev,
709 struct device_attribute *attr,
710 const char *buf, size_t count)
711 {
712 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
713 port_attr);
714 struct mlx4_dev *mdev = info->dev;
715 struct mlx4_priv *priv = mlx4_priv(mdev);
716 enum mlx4_port_type types[MLX4_MAX_PORTS];
717 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
718 int i;
719 int err = 0;
720
721 if (!strcmp(buf, "ib\n"))
722 info->tmp_type = MLX4_PORT_TYPE_IB;
723 else if (!strcmp(buf, "eth\n"))
724 info->tmp_type = MLX4_PORT_TYPE_ETH;
725 else if (!strcmp(buf, "auto\n"))
726 info->tmp_type = MLX4_PORT_TYPE_AUTO;
727 else {
728 mlx4_err(mdev, "%s is not supported port type\n", buf);
729 return -EINVAL;
730 }
731
732 mlx4_stop_sense(mdev);
733 mutex_lock(&priv->port_mutex);
734 /* Possible type is always the one that was delivered */
735 mdev->caps.possible_type[info->port] = info->tmp_type;
736
737 for (i = 0; i < mdev->caps.num_ports; i++) {
738 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
739 mdev->caps.possible_type[i+1];
740 if (types[i] == MLX4_PORT_TYPE_AUTO)
741 types[i] = mdev->caps.port_type[i+1];
742 }
743
744 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
745 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
746 for (i = 1; i <= mdev->caps.num_ports; i++) {
747 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
748 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
749 err = -EINVAL;
750 }
751 }
752 }
753 if (err) {
754 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
755 "Set only 'eth' or 'ib' for both ports "
756 "(should be the same)\n");
757 goto out;
758 }
759
760 mlx4_do_sense_ports(mdev, new_types, types);
761
762 err = mlx4_check_port_params(mdev, new_types);
763 if (err)
764 goto out;
765
766 /* We are about to apply the changes after the configuration
767 * was verified, no need to remember the temporary types
768 * any more */
769 for (i = 0; i < mdev->caps.num_ports; i++)
770 priv->port[i + 1].tmp_type = 0;
771
772 err = mlx4_change_port_types(mdev, new_types);
773
774 out:
775 mlx4_start_sense(mdev);
776 mutex_unlock(&priv->port_mutex);
777 return err ? err : count;
778 }
779
780 enum ibta_mtu {
781 IB_MTU_256 = 1,
782 IB_MTU_512 = 2,
783 IB_MTU_1024 = 3,
784 IB_MTU_2048 = 4,
785 IB_MTU_4096 = 5
786 };
787
788 static inline int int_to_ibta_mtu(int mtu)
789 {
790 switch (mtu) {
791 case 256: return IB_MTU_256;
792 case 512: return IB_MTU_512;
793 case 1024: return IB_MTU_1024;
794 case 2048: return IB_MTU_2048;
795 case 4096: return IB_MTU_4096;
796 default: return -1;
797 }
798 }
799
800 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
801 {
802 switch (mtu) {
803 case IB_MTU_256: return 256;
804 case IB_MTU_512: return 512;
805 case IB_MTU_1024: return 1024;
806 case IB_MTU_2048: return 2048;
807 case IB_MTU_4096: return 4096;
808 default: return -1;
809 }
810 }
811
812 static ssize_t show_port_ib_mtu(struct device *dev,
813 struct device_attribute *attr,
814 char *buf)
815 {
816 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
817 port_mtu_attr);
818 struct mlx4_dev *mdev = info->dev;
819
820 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
821 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
822
823 sprintf(buf, "%d\n",
824 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
825 return strlen(buf);
826 }
827
828 static ssize_t set_port_ib_mtu(struct device *dev,
829 struct device_attribute *attr,
830 const char *buf, size_t count)
831 {
832 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
833 port_mtu_attr);
834 struct mlx4_dev *mdev = info->dev;
835 struct mlx4_priv *priv = mlx4_priv(mdev);
836 int err, port, mtu, ibta_mtu = -1;
837
838 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
839 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
840 return -EINVAL;
841 }
842
843 err = sscanf(buf, "%d", &mtu);
844 if (err > 0)
845 ibta_mtu = int_to_ibta_mtu(mtu);
846
847 if (err <= 0 || ibta_mtu < 0) {
848 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
849 return -EINVAL;
850 }
851
852 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
853
854 mlx4_stop_sense(mdev);
855 mutex_lock(&priv->port_mutex);
856 mlx4_unregister_device(mdev);
857 for (port = 1; port <= mdev->caps.num_ports; port++) {
858 mlx4_CLOSE_PORT(mdev, port);
859 err = mlx4_SET_PORT(mdev, port, -1);
860 if (err) {
861 mlx4_err(mdev, "Failed to set port %d, "
862 "aborting\n", port);
863 goto err_set_port;
864 }
865 }
866 err = mlx4_register_device(mdev);
867 err_set_port:
868 mutex_unlock(&priv->port_mutex);
869 mlx4_start_sense(mdev);
870 return err ? err : count;
871 }
872
873 static int mlx4_load_fw(struct mlx4_dev *dev)
874 {
875 struct mlx4_priv *priv = mlx4_priv(dev);
876 int err;
877
878 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
879 GFP_HIGHUSER | __GFP_NOWARN, 0);
880 if (!priv->fw.fw_icm) {
881 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
882 return -ENOMEM;
883 }
884
885 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
886 if (err) {
887 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
888 goto err_free;
889 }
890
891 err = mlx4_RUN_FW(dev);
892 if (err) {
893 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
894 goto err_unmap_fa;
895 }
896
897 return 0;
898
899 err_unmap_fa:
900 mlx4_UNMAP_FA(dev);
901
902 err_free:
903 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
904 return err;
905 }
906
907 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
908 int cmpt_entry_sz)
909 {
910 struct mlx4_priv *priv = mlx4_priv(dev);
911 int err;
912 int num_eqs;
913
914 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
915 cmpt_base +
916 ((u64) (MLX4_CMPT_TYPE_QP *
917 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
918 cmpt_entry_sz, dev->caps.num_qps,
919 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
920 0, 0);
921 if (err)
922 goto err;
923
924 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
925 cmpt_base +
926 ((u64) (MLX4_CMPT_TYPE_SRQ *
927 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
928 cmpt_entry_sz, dev->caps.num_srqs,
929 dev->caps.reserved_srqs, 0, 0);
930 if (err)
931 goto err_qp;
932
933 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
934 cmpt_base +
935 ((u64) (MLX4_CMPT_TYPE_CQ *
936 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
937 cmpt_entry_sz, dev->caps.num_cqs,
938 dev->caps.reserved_cqs, 0, 0);
939 if (err)
940 goto err_srq;
941
942 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
943 dev->caps.num_eqs;
944 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
945 cmpt_base +
946 ((u64) (MLX4_CMPT_TYPE_EQ *
947 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
948 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
949 if (err)
950 goto err_cq;
951
952 return 0;
953
954 err_cq:
955 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
956
957 err_srq:
958 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
959
960 err_qp:
961 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
962
963 err:
964 return err;
965 }
966
967 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
968 struct mlx4_init_hca_param *init_hca, u64 icm_size)
969 {
970 struct mlx4_priv *priv = mlx4_priv(dev);
971 u64 aux_pages;
972 int num_eqs;
973 int err;
974
975 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
976 if (err) {
977 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
978 return err;
979 }
980
981 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
982 (unsigned long long) icm_size >> 10,
983 (unsigned long long) aux_pages << 2);
984
985 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
986 GFP_HIGHUSER | __GFP_NOWARN, 0);
987 if (!priv->fw.aux_icm) {
988 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
989 return -ENOMEM;
990 }
991
992 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
993 if (err) {
994 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
995 goto err_free_aux;
996 }
997
998 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
999 if (err) {
1000 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1001 goto err_unmap_aux;
1002 }
1003
1004
1005 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1006 dev->caps.num_eqs;
1007 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1008 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1009 num_eqs, num_eqs, 0, 0);
1010 if (err) {
1011 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1012 goto err_unmap_cmpt;
1013 }
1014
1015 /*
1016 * Reserved MTT entries must be aligned up to a cacheline
1017 * boundary, since the FW will write to them, while the driver
1018 * writes to all other MTT entries. (The variable
1019 * dev->caps.mtt_entry_sz below is really the MTT segment
1020 * size, not the raw entry size)
1021 */
1022 dev->caps.reserved_mtts =
1023 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1024 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1025
1026 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1027 init_hca->mtt_base,
1028 dev->caps.mtt_entry_sz,
1029 dev->caps.num_mtts,
1030 dev->caps.reserved_mtts, 1, 0);
1031 if (err) {
1032 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1033 goto err_unmap_eq;
1034 }
1035
1036 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1037 init_hca->dmpt_base,
1038 dev_cap->dmpt_entry_sz,
1039 dev->caps.num_mpts,
1040 dev->caps.reserved_mrws, 1, 1);
1041 if (err) {
1042 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1043 goto err_unmap_mtt;
1044 }
1045
1046 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1047 init_hca->qpc_base,
1048 dev_cap->qpc_entry_sz,
1049 dev->caps.num_qps,
1050 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1051 0, 0);
1052 if (err) {
1053 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1054 goto err_unmap_dmpt;
1055 }
1056
1057 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1058 init_hca->auxc_base,
1059 dev_cap->aux_entry_sz,
1060 dev->caps.num_qps,
1061 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1062 0, 0);
1063 if (err) {
1064 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1065 goto err_unmap_qp;
1066 }
1067
1068 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1069 init_hca->altc_base,
1070 dev_cap->altc_entry_sz,
1071 dev->caps.num_qps,
1072 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1073 0, 0);
1074 if (err) {
1075 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1076 goto err_unmap_auxc;
1077 }
1078
1079 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1080 init_hca->rdmarc_base,
1081 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1082 dev->caps.num_qps,
1083 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1084 0, 0);
1085 if (err) {
1086 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1087 goto err_unmap_altc;
1088 }
1089
1090 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1091 init_hca->cqc_base,
1092 dev_cap->cqc_entry_sz,
1093 dev->caps.num_cqs,
1094 dev->caps.reserved_cqs, 0, 0);
1095 if (err) {
1096 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1097 goto err_unmap_rdmarc;
1098 }
1099
1100 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1101 init_hca->srqc_base,
1102 dev_cap->srq_entry_sz,
1103 dev->caps.num_srqs,
1104 dev->caps.reserved_srqs, 0, 0);
1105 if (err) {
1106 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1107 goto err_unmap_cq;
1108 }
1109
1110 /*
1111 * For flow steering device managed mode it is required to use
1112 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1113 * required, but for simplicity just map the whole multicast
1114 * group table now. The table isn't very big and it's a lot
1115 * easier than trying to track ref counts.
1116 */
1117 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1118 init_hca->mc_base,
1119 mlx4_get_mgm_entry_size(dev),
1120 dev->caps.num_mgms + dev->caps.num_amgms,
1121 dev->caps.num_mgms + dev->caps.num_amgms,
1122 0, 0);
1123 if (err) {
1124 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1125 goto err_unmap_srq;
1126 }
1127
1128 return 0;
1129
1130 err_unmap_srq:
1131 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1132
1133 err_unmap_cq:
1134 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1135
1136 err_unmap_rdmarc:
1137 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1138
1139 err_unmap_altc:
1140 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1141
1142 err_unmap_auxc:
1143 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1144
1145 err_unmap_qp:
1146 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1147
1148 err_unmap_dmpt:
1149 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1150
1151 err_unmap_mtt:
1152 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1153
1154 err_unmap_eq:
1155 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1156
1157 err_unmap_cmpt:
1158 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1159 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1160 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1161 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1162
1163 err_unmap_aux:
1164 mlx4_UNMAP_ICM_AUX(dev);
1165
1166 err_free_aux:
1167 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1168
1169 return err;
1170 }
1171
1172 static void mlx4_free_icms(struct mlx4_dev *dev)
1173 {
1174 struct mlx4_priv *priv = mlx4_priv(dev);
1175
1176 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1177 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1178 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1179 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1180 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1181 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1182 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1183 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1184 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1185 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1186 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1187 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1188 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1189 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1190
1191 mlx4_UNMAP_ICM_AUX(dev);
1192 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1193 }
1194
1195 static void mlx4_slave_exit(struct mlx4_dev *dev)
1196 {
1197 struct mlx4_priv *priv = mlx4_priv(dev);
1198
1199 mutex_lock(&priv->cmd.slave_cmd_mutex);
1200 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1201 mlx4_warn(dev, "Failed to close slave function.\n");
1202 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1203 }
1204
1205 static int map_bf_area(struct mlx4_dev *dev)
1206 {
1207 struct mlx4_priv *priv = mlx4_priv(dev);
1208 resource_size_t bf_start;
1209 resource_size_t bf_len;
1210 int err = 0;
1211
1212 if (!dev->caps.bf_reg_size)
1213 return -ENXIO;
1214
1215 bf_start = pci_resource_start(dev->pdev, 2) +
1216 (dev->caps.num_uars << PAGE_SHIFT);
1217 bf_len = pci_resource_len(dev->pdev, 2) -
1218 (dev->caps.num_uars << PAGE_SHIFT);
1219 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1220 if (!priv->bf_mapping)
1221 err = -ENOMEM;
1222
1223 return err;
1224 }
1225
1226 static void unmap_bf_area(struct mlx4_dev *dev)
1227 {
1228 if (mlx4_priv(dev)->bf_mapping)
1229 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1230 }
1231
1232 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1233 {
1234 u32 clockhi, clocklo, clockhi1;
1235 cycle_t cycles;
1236 int i;
1237 struct mlx4_priv *priv = mlx4_priv(dev);
1238
1239 for (i = 0; i < 10; i++) {
1240 clockhi = swab32(readl(priv->clock_mapping));
1241 clocklo = swab32(readl(priv->clock_mapping + 4));
1242 clockhi1 = swab32(readl(priv->clock_mapping));
1243 if (clockhi == clockhi1)
1244 break;
1245 }
1246
1247 cycles = (u64) clockhi << 32 | (u64) clocklo;
1248
1249 return cycles;
1250 }
1251 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1252
1253
1254 static int map_internal_clock(struct mlx4_dev *dev)
1255 {
1256 struct mlx4_priv *priv = mlx4_priv(dev);
1257
1258 priv->clock_mapping =
1259 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1260 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1261
1262 if (!priv->clock_mapping)
1263 return -ENOMEM;
1264
1265 return 0;
1266 }
1267
1268 static void unmap_internal_clock(struct mlx4_dev *dev)
1269 {
1270 struct mlx4_priv *priv = mlx4_priv(dev);
1271
1272 if (priv->clock_mapping)
1273 iounmap(priv->clock_mapping);
1274 }
1275
1276 static void mlx4_close_hca(struct mlx4_dev *dev)
1277 {
1278 unmap_internal_clock(dev);
1279 unmap_bf_area(dev);
1280 if (mlx4_is_slave(dev))
1281 mlx4_slave_exit(dev);
1282 else {
1283 mlx4_CLOSE_HCA(dev, 0);
1284 mlx4_free_icms(dev);
1285 mlx4_UNMAP_FA(dev);
1286 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1287 }
1288 }
1289
1290 static int mlx4_init_slave(struct mlx4_dev *dev)
1291 {
1292 struct mlx4_priv *priv = mlx4_priv(dev);
1293 u64 dma = (u64) priv->mfunc.vhcr_dma;
1294 int ret_from_reset = 0;
1295 u32 slave_read;
1296 u32 cmd_channel_ver;
1297
1298 mutex_lock(&priv->cmd.slave_cmd_mutex);
1299 priv->cmd.max_cmds = 1;
1300 mlx4_warn(dev, "Sending reset\n");
1301 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1302 MLX4_COMM_TIME);
1303 /* if we are in the middle of flr the slave will try
1304 * NUM_OF_RESET_RETRIES times before leaving.*/
1305 if (ret_from_reset) {
1306 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1307 mlx4_warn(dev, "slave is currently in the "
1308 "middle of FLR. Deferring probe.\n");
1309 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1310 return -EPROBE_DEFER;
1311 } else
1312 goto err;
1313 }
1314
1315 /* check the driver version - the slave I/F revision
1316 * must match the master's */
1317 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1318 cmd_channel_ver = mlx4_comm_get_version();
1319
1320 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1321 MLX4_COMM_GET_IF_REV(slave_read)) {
1322 mlx4_err(dev, "slave driver version is not supported"
1323 " by the master\n");
1324 goto err;
1325 }
1326
1327 mlx4_warn(dev, "Sending vhcr0\n");
1328 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1329 MLX4_COMM_TIME))
1330 goto err;
1331 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1332 MLX4_COMM_TIME))
1333 goto err;
1334 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1335 MLX4_COMM_TIME))
1336 goto err;
1337 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1338 goto err;
1339
1340 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1341 return 0;
1342
1343 err:
1344 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1345 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1346 return -EIO;
1347 }
1348
1349 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1350 {
1351 int i;
1352
1353 for (i = 1; i <= dev->caps.num_ports; i++) {
1354 dev->caps.gid_table_len[i] = 1;
1355 dev->caps.pkey_table_len[i] =
1356 dev->phys_caps.pkey_phys_table_len[i] - 1;
1357 }
1358 }
1359
1360 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1361 {
1362 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1363
1364 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1365 i++) {
1366 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1367 break;
1368 }
1369
1370 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1371 }
1372
1373 static void choose_steering_mode(struct mlx4_dev *dev,
1374 struct mlx4_dev_cap *dev_cap)
1375 {
1376 if (mlx4_log_num_mgm_entry_size == -1 &&
1377 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1378 (!mlx4_is_mfunc(dev) ||
1379 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1380 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1381 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1382 dev->oper_log_mgm_entry_size =
1383 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1384 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1385 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1386 dev->caps.fs_log_max_ucast_qp_range_size =
1387 dev_cap->fs_log_max_ucast_qp_range_size;
1388 } else {
1389 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1390 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1391 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1392 else {
1393 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1394
1395 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1396 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1397 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1398 "set to use B0 steering. Falling back to A0 steering mode.\n");
1399 }
1400 dev->oper_log_mgm_entry_size =
1401 mlx4_log_num_mgm_entry_size > 0 ?
1402 mlx4_log_num_mgm_entry_size :
1403 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1404 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1405 }
1406 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1407 "modparam log_num_mgm_entry_size = %d\n",
1408 mlx4_steering_mode_str(dev->caps.steering_mode),
1409 dev->oper_log_mgm_entry_size,
1410 mlx4_log_num_mgm_entry_size);
1411 }
1412
1413 static int mlx4_init_hca(struct mlx4_dev *dev)
1414 {
1415 struct mlx4_priv *priv = mlx4_priv(dev);
1416 struct mlx4_adapter adapter;
1417 struct mlx4_dev_cap dev_cap;
1418 struct mlx4_mod_stat_cfg mlx4_cfg;
1419 struct mlx4_profile profile;
1420 struct mlx4_init_hca_param init_hca;
1421 u64 icm_size;
1422 int err;
1423
1424 if (!mlx4_is_slave(dev)) {
1425 err = mlx4_QUERY_FW(dev);
1426 if (err) {
1427 if (err == -EACCES)
1428 mlx4_info(dev, "non-primary physical function, skipping.\n");
1429 else
1430 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1431 return err;
1432 }
1433
1434 err = mlx4_load_fw(dev);
1435 if (err) {
1436 mlx4_err(dev, "Failed to start FW, aborting.\n");
1437 return err;
1438 }
1439
1440 mlx4_cfg.log_pg_sz_m = 1;
1441 mlx4_cfg.log_pg_sz = 0;
1442 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1443 if (err)
1444 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1445
1446 err = mlx4_dev_cap(dev, &dev_cap);
1447 if (err) {
1448 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1449 goto err_stop_fw;
1450 }
1451
1452 choose_steering_mode(dev, &dev_cap);
1453
1454 if (mlx4_is_master(dev))
1455 mlx4_parav_master_pf_caps(dev);
1456
1457 profile = default_profile;
1458 if (dev->caps.steering_mode ==
1459 MLX4_STEERING_MODE_DEVICE_MANAGED)
1460 profile.num_mcg = MLX4_FS_NUM_MCG;
1461
1462 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1463 &init_hca);
1464 if ((long long) icm_size < 0) {
1465 err = icm_size;
1466 goto err_stop_fw;
1467 }
1468
1469 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1470
1471 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1472 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1473 init_hca.mw_enabled = 0;
1474 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1475 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1476 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1477
1478 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1479 if (err)
1480 goto err_stop_fw;
1481
1482 err = mlx4_INIT_HCA(dev, &init_hca);
1483 if (err) {
1484 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1485 goto err_free_icm;
1486 }
1487 /*
1488 * If TS is supported by FW
1489 * read HCA frequency by QUERY_HCA command
1490 */
1491 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1492 memset(&init_hca, 0, sizeof(init_hca));
1493 err = mlx4_QUERY_HCA(dev, &init_hca);
1494 if (err) {
1495 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1496 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1497 } else {
1498 dev->caps.hca_core_clock =
1499 init_hca.hca_core_clock;
1500 }
1501
1502 /* In case we got HCA frequency 0 - disable timestamping
1503 * to avoid dividing by zero
1504 */
1505 if (!dev->caps.hca_core_clock) {
1506 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1507 mlx4_err(dev,
1508 "HCA frequency is 0. Timestamping is not supported.");
1509 } else if (map_internal_clock(dev)) {
1510 /*
1511 * Map internal clock,
1512 * in case of failure disable timestamping
1513 */
1514 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1515 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1516 }
1517 }
1518 } else {
1519 err = mlx4_init_slave(dev);
1520 if (err) {
1521 if (err != -EPROBE_DEFER)
1522 mlx4_err(dev, "Failed to initialize slave\n");
1523 return err;
1524 }
1525
1526 err = mlx4_slave_cap(dev);
1527 if (err) {
1528 mlx4_err(dev, "Failed to obtain slave caps\n");
1529 goto err_close;
1530 }
1531 }
1532
1533 if (map_bf_area(dev))
1534 mlx4_dbg(dev, "Failed to map blue flame area\n");
1535
1536 /*Only the master set the ports, all the rest got it from it.*/
1537 if (!mlx4_is_slave(dev))
1538 mlx4_set_port_mask(dev);
1539
1540 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1541 if (err) {
1542 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1543 goto unmap_bf;
1544 }
1545
1546 priv->eq_table.inta_pin = adapter.inta_pin;
1547 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1548
1549 return 0;
1550
1551 unmap_bf:
1552 unmap_internal_clock(dev);
1553 unmap_bf_area(dev);
1554
1555 err_close:
1556 if (mlx4_is_slave(dev))
1557 mlx4_slave_exit(dev);
1558 else
1559 mlx4_CLOSE_HCA(dev, 0);
1560
1561 err_free_icm:
1562 if (!mlx4_is_slave(dev))
1563 mlx4_free_icms(dev);
1564
1565 err_stop_fw:
1566 if (!mlx4_is_slave(dev)) {
1567 mlx4_UNMAP_FA(dev);
1568 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1569 }
1570 return err;
1571 }
1572
1573 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1574 {
1575 struct mlx4_priv *priv = mlx4_priv(dev);
1576 int nent;
1577
1578 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1579 return -ENOENT;
1580
1581 nent = dev->caps.max_counters;
1582 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1583 }
1584
1585 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1586 {
1587 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1588 }
1589
1590 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1591 {
1592 struct mlx4_priv *priv = mlx4_priv(dev);
1593
1594 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1595 return -ENOENT;
1596
1597 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1598 if (*idx == -1)
1599 return -ENOMEM;
1600
1601 return 0;
1602 }
1603
1604 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1605 {
1606 u64 out_param;
1607 int err;
1608
1609 if (mlx4_is_mfunc(dev)) {
1610 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1611 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1612 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1613 if (!err)
1614 *idx = get_param_l(&out_param);
1615
1616 return err;
1617 }
1618 return __mlx4_counter_alloc(dev, idx);
1619 }
1620 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1621
1622 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1623 {
1624 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1625 return;
1626 }
1627
1628 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1629 {
1630 u64 in_param = 0;
1631
1632 if (mlx4_is_mfunc(dev)) {
1633 set_param_l(&in_param, idx);
1634 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1635 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1636 MLX4_CMD_WRAPPED);
1637 return;
1638 }
1639 __mlx4_counter_free(dev, idx);
1640 }
1641 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1642
1643 static int mlx4_setup_hca(struct mlx4_dev *dev)
1644 {
1645 struct mlx4_priv *priv = mlx4_priv(dev);
1646 int err;
1647 int port;
1648 __be32 ib_port_default_caps;
1649
1650 err = mlx4_init_uar_table(dev);
1651 if (err) {
1652 mlx4_err(dev, "Failed to initialize "
1653 "user access region table, aborting.\n");
1654 return err;
1655 }
1656
1657 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1658 if (err) {
1659 mlx4_err(dev, "Failed to allocate driver access region, "
1660 "aborting.\n");
1661 goto err_uar_table_free;
1662 }
1663
1664 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1665 if (!priv->kar) {
1666 mlx4_err(dev, "Couldn't map kernel access region, "
1667 "aborting.\n");
1668 err = -ENOMEM;
1669 goto err_uar_free;
1670 }
1671
1672 err = mlx4_init_pd_table(dev);
1673 if (err) {
1674 mlx4_err(dev, "Failed to initialize "
1675 "protection domain table, aborting.\n");
1676 goto err_kar_unmap;
1677 }
1678
1679 err = mlx4_init_xrcd_table(dev);
1680 if (err) {
1681 mlx4_err(dev, "Failed to initialize "
1682 "reliable connection domain table, aborting.\n");
1683 goto err_pd_table_free;
1684 }
1685
1686 err = mlx4_init_mr_table(dev);
1687 if (err) {
1688 mlx4_err(dev, "Failed to initialize "
1689 "memory region table, aborting.\n");
1690 goto err_xrcd_table_free;
1691 }
1692
1693 err = mlx4_init_eq_table(dev);
1694 if (err) {
1695 mlx4_err(dev, "Failed to initialize "
1696 "event queue table, aborting.\n");
1697 goto err_mr_table_free;
1698 }
1699
1700 err = mlx4_cmd_use_events(dev);
1701 if (err) {
1702 mlx4_err(dev, "Failed to switch to event-driven "
1703 "firmware commands, aborting.\n");
1704 goto err_eq_table_free;
1705 }
1706
1707 err = mlx4_NOP(dev);
1708 if (err) {
1709 if (dev->flags & MLX4_FLAG_MSI_X) {
1710 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1711 "interrupt IRQ %d).\n",
1712 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1713 mlx4_warn(dev, "Trying again without MSI-X.\n");
1714 } else {
1715 mlx4_err(dev, "NOP command failed to generate interrupt "
1716 "(IRQ %d), aborting.\n",
1717 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1718 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1719 }
1720
1721 goto err_cmd_poll;
1722 }
1723
1724 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1725
1726 err = mlx4_init_cq_table(dev);
1727 if (err) {
1728 mlx4_err(dev, "Failed to initialize "
1729 "completion queue table, aborting.\n");
1730 goto err_cmd_poll;
1731 }
1732
1733 err = mlx4_init_srq_table(dev);
1734 if (err) {
1735 mlx4_err(dev, "Failed to initialize "
1736 "shared receive queue table, aborting.\n");
1737 goto err_cq_table_free;
1738 }
1739
1740 err = mlx4_init_qp_table(dev);
1741 if (err) {
1742 mlx4_err(dev, "Failed to initialize "
1743 "queue pair table, aborting.\n");
1744 goto err_srq_table_free;
1745 }
1746
1747 if (!mlx4_is_slave(dev)) {
1748 err = mlx4_init_mcg_table(dev);
1749 if (err) {
1750 mlx4_err(dev, "Failed to initialize "
1751 "multicast group table, aborting.\n");
1752 goto err_qp_table_free;
1753 }
1754 }
1755
1756 err = mlx4_init_counters_table(dev);
1757 if (err && err != -ENOENT) {
1758 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1759 goto err_mcg_table_free;
1760 }
1761
1762 if (!mlx4_is_slave(dev)) {
1763 for (port = 1; port <= dev->caps.num_ports; port++) {
1764 ib_port_default_caps = 0;
1765 err = mlx4_get_port_ib_caps(dev, port,
1766 &ib_port_default_caps);
1767 if (err)
1768 mlx4_warn(dev, "failed to get port %d default "
1769 "ib capabilities (%d). Continuing "
1770 "with caps = 0\n", port, err);
1771 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1772
1773 /* initialize per-slave default ib port capabilities */
1774 if (mlx4_is_master(dev)) {
1775 int i;
1776 for (i = 0; i < dev->num_slaves; i++) {
1777 if (i == mlx4_master_func_num(dev))
1778 continue;
1779 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1780 ib_port_default_caps;
1781 }
1782 }
1783
1784 if (mlx4_is_mfunc(dev))
1785 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1786 else
1787 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1788
1789 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1790 dev->caps.pkey_table_len[port] : -1);
1791 if (err) {
1792 mlx4_err(dev, "Failed to set port %d, aborting\n",
1793 port);
1794 goto err_counters_table_free;
1795 }
1796 }
1797 }
1798
1799 return 0;
1800
1801 err_counters_table_free:
1802 mlx4_cleanup_counters_table(dev);
1803
1804 err_mcg_table_free:
1805 mlx4_cleanup_mcg_table(dev);
1806
1807 err_qp_table_free:
1808 mlx4_cleanup_qp_table(dev);
1809
1810 err_srq_table_free:
1811 mlx4_cleanup_srq_table(dev);
1812
1813 err_cq_table_free:
1814 mlx4_cleanup_cq_table(dev);
1815
1816 err_cmd_poll:
1817 mlx4_cmd_use_polling(dev);
1818
1819 err_eq_table_free:
1820 mlx4_cleanup_eq_table(dev);
1821
1822 err_mr_table_free:
1823 mlx4_cleanup_mr_table(dev);
1824
1825 err_xrcd_table_free:
1826 mlx4_cleanup_xrcd_table(dev);
1827
1828 err_pd_table_free:
1829 mlx4_cleanup_pd_table(dev);
1830
1831 err_kar_unmap:
1832 iounmap(priv->kar);
1833
1834 err_uar_free:
1835 mlx4_uar_free(dev, &priv->driver_uar);
1836
1837 err_uar_table_free:
1838 mlx4_cleanup_uar_table(dev);
1839 return err;
1840 }
1841
1842 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1843 {
1844 struct mlx4_priv *priv = mlx4_priv(dev);
1845 struct msix_entry *entries;
1846 int nreq = min_t(int, dev->caps.num_ports *
1847 min_t(int, netif_get_num_default_rss_queues() + 1,
1848 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1849 int err;
1850 int i;
1851
1852 if (msi_x) {
1853 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1854 nreq);
1855
1856 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1857 if (!entries)
1858 goto no_msi;
1859
1860 for (i = 0; i < nreq; ++i)
1861 entries[i].entry = i;
1862
1863 retry:
1864 err = pci_enable_msix(dev->pdev, entries, nreq);
1865 if (err) {
1866 /* Try again if at least 2 vectors are available */
1867 if (err > 1) {
1868 mlx4_info(dev, "Requested %d vectors, "
1869 "but only %d MSI-X vectors available, "
1870 "trying again\n", nreq, err);
1871 nreq = err;
1872 goto retry;
1873 }
1874 kfree(entries);
1875 goto no_msi;
1876 }
1877
1878 if (nreq <
1879 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1880 /*Working in legacy mode , all EQ's shared*/
1881 dev->caps.comp_pool = 0;
1882 dev->caps.num_comp_vectors = nreq - 1;
1883 } else {
1884 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1885 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1886 }
1887 for (i = 0; i < nreq; ++i)
1888 priv->eq_table.eq[i].irq = entries[i].vector;
1889
1890 dev->flags |= MLX4_FLAG_MSI_X;
1891
1892 kfree(entries);
1893 return;
1894 }
1895
1896 no_msi:
1897 dev->caps.num_comp_vectors = 1;
1898 dev->caps.comp_pool = 0;
1899
1900 for (i = 0; i < 2; ++i)
1901 priv->eq_table.eq[i].irq = dev->pdev->irq;
1902 }
1903
1904 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1905 {
1906 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1907 int err = 0;
1908
1909 info->dev = dev;
1910 info->port = port;
1911 if (!mlx4_is_slave(dev)) {
1912 mlx4_init_mac_table(dev, &info->mac_table);
1913 mlx4_init_vlan_table(dev, &info->vlan_table);
1914 info->base_qpn = mlx4_get_base_qpn(dev, port);
1915 }
1916
1917 sprintf(info->dev_name, "mlx4_port%d", port);
1918 info->port_attr.attr.name = info->dev_name;
1919 if (mlx4_is_mfunc(dev))
1920 info->port_attr.attr.mode = S_IRUGO;
1921 else {
1922 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1923 info->port_attr.store = set_port_type;
1924 }
1925 info->port_attr.show = show_port_type;
1926 sysfs_attr_init(&info->port_attr.attr);
1927
1928 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1929 if (err) {
1930 mlx4_err(dev, "Failed to create file for port %d\n", port);
1931 info->port = -1;
1932 }
1933
1934 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1935 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1936 if (mlx4_is_mfunc(dev))
1937 info->port_mtu_attr.attr.mode = S_IRUGO;
1938 else {
1939 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1940 info->port_mtu_attr.store = set_port_ib_mtu;
1941 }
1942 info->port_mtu_attr.show = show_port_ib_mtu;
1943 sysfs_attr_init(&info->port_mtu_attr.attr);
1944
1945 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1946 if (err) {
1947 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1948 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1949 info->port = -1;
1950 }
1951
1952 return err;
1953 }
1954
1955 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1956 {
1957 if (info->port < 0)
1958 return;
1959
1960 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1961 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1962 }
1963
1964 static int mlx4_init_steering(struct mlx4_dev *dev)
1965 {
1966 struct mlx4_priv *priv = mlx4_priv(dev);
1967 int num_entries = dev->caps.num_ports;
1968 int i, j;
1969
1970 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1971 if (!priv->steer)
1972 return -ENOMEM;
1973
1974 for (i = 0; i < num_entries; i++)
1975 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1976 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1977 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1978 }
1979 return 0;
1980 }
1981
1982 static void mlx4_clear_steering(struct mlx4_dev *dev)
1983 {
1984 struct mlx4_priv *priv = mlx4_priv(dev);
1985 struct mlx4_steer_index *entry, *tmp_entry;
1986 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1987 int num_entries = dev->caps.num_ports;
1988 int i, j;
1989
1990 for (i = 0; i < num_entries; i++) {
1991 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1992 list_for_each_entry_safe(pqp, tmp_pqp,
1993 &priv->steer[i].promisc_qps[j],
1994 list) {
1995 list_del(&pqp->list);
1996 kfree(pqp);
1997 }
1998 list_for_each_entry_safe(entry, tmp_entry,
1999 &priv->steer[i].steer_entries[j],
2000 list) {
2001 list_del(&entry->list);
2002 list_for_each_entry_safe(pqp, tmp_pqp,
2003 &entry->duplicates,
2004 list) {
2005 list_del(&pqp->list);
2006 kfree(pqp);
2007 }
2008 kfree(entry);
2009 }
2010 }
2011 }
2012 kfree(priv->steer);
2013 }
2014
2015 static int extended_func_num(struct pci_dev *pdev)
2016 {
2017 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2018 }
2019
2020 #define MLX4_OWNER_BASE 0x8069c
2021 #define MLX4_OWNER_SIZE 4
2022
2023 static int mlx4_get_ownership(struct mlx4_dev *dev)
2024 {
2025 void __iomem *owner;
2026 u32 ret;
2027
2028 if (pci_channel_offline(dev->pdev))
2029 return -EIO;
2030
2031 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2032 MLX4_OWNER_SIZE);
2033 if (!owner) {
2034 mlx4_err(dev, "Failed to obtain ownership bit\n");
2035 return -ENOMEM;
2036 }
2037
2038 ret = readl(owner);
2039 iounmap(owner);
2040 return (int) !!ret;
2041 }
2042
2043 static void mlx4_free_ownership(struct mlx4_dev *dev)
2044 {
2045 void __iomem *owner;
2046
2047 if (pci_channel_offline(dev->pdev))
2048 return;
2049
2050 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2051 MLX4_OWNER_SIZE);
2052 if (!owner) {
2053 mlx4_err(dev, "Failed to obtain ownership bit\n");
2054 return;
2055 }
2056 writel(0, owner);
2057 msleep(1000);
2058 iounmap(owner);
2059 }
2060
2061 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2062 {
2063 struct mlx4_priv *priv;
2064 struct mlx4_dev *dev;
2065 int err;
2066 int port;
2067
2068 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2069
2070 err = pci_enable_device(pdev);
2071 if (err) {
2072 dev_err(&pdev->dev, "Cannot enable PCI device, "
2073 "aborting.\n");
2074 return err;
2075 }
2076 if (num_vfs > MLX4_MAX_NUM_VF) {
2077 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
2078 num_vfs, MLX4_MAX_NUM_VF);
2079 return -EINVAL;
2080 }
2081 /*
2082 * Check for BARs.
2083 */
2084 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2085 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2086 dev_err(&pdev->dev, "Missing DCS, aborting."
2087 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2088 pci_dev_data, pci_resource_flags(pdev, 0));
2089 err = -ENODEV;
2090 goto err_disable_pdev;
2091 }
2092 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2093 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2094 err = -ENODEV;
2095 goto err_disable_pdev;
2096 }
2097
2098 err = pci_request_regions(pdev, DRV_NAME);
2099 if (err) {
2100 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2101 goto err_disable_pdev;
2102 }
2103
2104 pci_set_master(pdev);
2105
2106 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2107 if (err) {
2108 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2109 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2110 if (err) {
2111 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2112 goto err_release_regions;
2113 }
2114 }
2115 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2116 if (err) {
2117 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2118 "consistent PCI DMA mask.\n");
2119 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2120 if (err) {
2121 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2122 "aborting.\n");
2123 goto err_release_regions;
2124 }
2125 }
2126
2127 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2128 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2129
2130 dev = pci_get_drvdata(pdev);
2131 priv = mlx4_priv(dev);
2132 dev->pdev = pdev;
2133 INIT_LIST_HEAD(&priv->ctx_list);
2134 spin_lock_init(&priv->ctx_lock);
2135
2136 mutex_init(&priv->port_mutex);
2137
2138 INIT_LIST_HEAD(&priv->pgdir_list);
2139 mutex_init(&priv->pgdir_mutex);
2140
2141 INIT_LIST_HEAD(&priv->bf_list);
2142 mutex_init(&priv->bf_mutex);
2143
2144 dev->rev_id = pdev->revision;
2145 /* Detect if this device is a virtual function */
2146 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2147 /* When acting as pf, we normally skip vfs unless explicitly
2148 * requested to probe them. */
2149 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2150 mlx4_warn(dev, "Skipping virtual function:%d\n",
2151 extended_func_num(pdev));
2152 err = -ENODEV;
2153 goto err_free_dev;
2154 }
2155 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2156 dev->flags |= MLX4_FLAG_SLAVE;
2157 } else {
2158 /* We reset the device and enable SRIOV only for physical
2159 * devices. Try to claim ownership on the device;
2160 * if already taken, skip -- do not allow multiple PFs */
2161 err = mlx4_get_ownership(dev);
2162 if (err) {
2163 if (err < 0)
2164 goto err_free_dev;
2165 else {
2166 mlx4_warn(dev, "Multiple PFs not yet supported."
2167 " Skipping PF.\n");
2168 err = -EINVAL;
2169 goto err_free_dev;
2170 }
2171 }
2172
2173 if (num_vfs) {
2174 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2175 err = pci_enable_sriov(pdev, num_vfs);
2176 if (err) {
2177 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2178 err);
2179 err = 0;
2180 } else {
2181 mlx4_warn(dev, "Running in master mode\n");
2182 dev->flags |= MLX4_FLAG_SRIOV |
2183 MLX4_FLAG_MASTER;
2184 dev->num_vfs = num_vfs;
2185 }
2186 }
2187
2188 /*
2189 * Now reset the HCA before we touch the PCI capabilities or
2190 * attempt a firmware command, since a boot ROM may have left
2191 * the HCA in an undefined state.
2192 */
2193 err = mlx4_reset(dev);
2194 if (err) {
2195 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2196 goto err_rel_own;
2197 }
2198 }
2199
2200 slave_start:
2201 err = mlx4_cmd_init(dev);
2202 if (err) {
2203 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2204 goto err_sriov;
2205 }
2206
2207 /* In slave functions, the communication channel must be initialized
2208 * before posting commands. Also, init num_slaves before calling
2209 * mlx4_init_hca */
2210 if (mlx4_is_mfunc(dev)) {
2211 if (mlx4_is_master(dev))
2212 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2213 else {
2214 dev->num_slaves = 0;
2215 err = mlx4_multi_func_init(dev);
2216 if (err) {
2217 mlx4_err(dev, "Failed to init slave mfunc"
2218 " interface, aborting.\n");
2219 goto err_cmd;
2220 }
2221 }
2222 }
2223
2224 err = mlx4_init_hca(dev);
2225 if (err) {
2226 if (err == -EACCES) {
2227 /* Not primary Physical function
2228 * Running in slave mode */
2229 mlx4_cmd_cleanup(dev);
2230 dev->flags |= MLX4_FLAG_SLAVE;
2231 dev->flags &= ~MLX4_FLAG_MASTER;
2232 goto slave_start;
2233 } else
2234 goto err_mfunc;
2235 }
2236
2237 /* In master functions, the communication channel must be initialized
2238 * after obtaining its address from fw */
2239 if (mlx4_is_master(dev)) {
2240 err = mlx4_multi_func_init(dev);
2241 if (err) {
2242 mlx4_err(dev, "Failed to init master mfunc"
2243 "interface, aborting.\n");
2244 goto err_close;
2245 }
2246 }
2247
2248 err = mlx4_alloc_eq_table(dev);
2249 if (err)
2250 goto err_master_mfunc;
2251
2252 priv->msix_ctl.pool_bm = 0;
2253 mutex_init(&priv->msix_ctl.pool_lock);
2254
2255 mlx4_enable_msi_x(dev);
2256 if ((mlx4_is_mfunc(dev)) &&
2257 !(dev->flags & MLX4_FLAG_MSI_X)) {
2258 err = -ENOSYS;
2259 mlx4_err(dev, "INTx is not supported in multi-function mode."
2260 " aborting.\n");
2261 goto err_free_eq;
2262 }
2263
2264 if (!mlx4_is_slave(dev)) {
2265 err = mlx4_init_steering(dev);
2266 if (err)
2267 goto err_free_eq;
2268 }
2269
2270 err = mlx4_setup_hca(dev);
2271 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2272 !mlx4_is_mfunc(dev)) {
2273 dev->flags &= ~MLX4_FLAG_MSI_X;
2274 dev->caps.num_comp_vectors = 1;
2275 dev->caps.comp_pool = 0;
2276 pci_disable_msix(pdev);
2277 err = mlx4_setup_hca(dev);
2278 }
2279
2280 if (err)
2281 goto err_steer;
2282
2283 for (port = 1; port <= dev->caps.num_ports; port++) {
2284 err = mlx4_init_port_info(dev, port);
2285 if (err)
2286 goto err_port;
2287 }
2288
2289 err = mlx4_register_device(dev);
2290 if (err)
2291 goto err_port;
2292
2293 mlx4_sense_init(dev);
2294 mlx4_start_sense(dev);
2295
2296 priv->removed = 0;
2297
2298 return 0;
2299
2300 err_port:
2301 for (--port; port >= 1; --port)
2302 mlx4_cleanup_port_info(&priv->port[port]);
2303
2304 mlx4_cleanup_counters_table(dev);
2305 mlx4_cleanup_mcg_table(dev);
2306 mlx4_cleanup_qp_table(dev);
2307 mlx4_cleanup_srq_table(dev);
2308 mlx4_cleanup_cq_table(dev);
2309 mlx4_cmd_use_polling(dev);
2310 mlx4_cleanup_eq_table(dev);
2311 mlx4_cleanup_mr_table(dev);
2312 mlx4_cleanup_xrcd_table(dev);
2313 mlx4_cleanup_pd_table(dev);
2314 mlx4_cleanup_uar_table(dev);
2315
2316 err_steer:
2317 if (!mlx4_is_slave(dev))
2318 mlx4_clear_steering(dev);
2319
2320 err_free_eq:
2321 mlx4_free_eq_table(dev);
2322
2323 err_master_mfunc:
2324 if (mlx4_is_master(dev))
2325 mlx4_multi_func_cleanup(dev);
2326
2327 err_close:
2328 if (dev->flags & MLX4_FLAG_MSI_X)
2329 pci_disable_msix(pdev);
2330
2331 mlx4_close_hca(dev);
2332
2333 err_mfunc:
2334 if (mlx4_is_slave(dev))
2335 mlx4_multi_func_cleanup(dev);
2336
2337 err_cmd:
2338 mlx4_cmd_cleanup(dev);
2339
2340 err_sriov:
2341 if (dev->flags & MLX4_FLAG_SRIOV)
2342 pci_disable_sriov(pdev);
2343
2344 err_rel_own:
2345 if (!mlx4_is_slave(dev))
2346 mlx4_free_ownership(dev);
2347
2348 err_free_dev:
2349 kfree(priv);
2350
2351 err_release_regions:
2352 pci_release_regions(pdev);
2353
2354 err_disable_pdev:
2355 pci_disable_device(pdev);
2356 pci_set_drvdata(pdev, NULL);
2357 return err;
2358 }
2359
2360 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2361 {
2362 struct mlx4_priv *priv;
2363 struct mlx4_dev *dev;
2364
2365 printk_once(KERN_INFO "%s", mlx4_version);
2366
2367 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2368 if (!priv)
2369 return -ENOMEM;
2370
2371 dev = &priv->dev;
2372 pci_set_drvdata(pdev, dev);
2373 priv->pci_dev_data = id->driver_data;
2374
2375 return __mlx4_init_one(pdev, id->driver_data);
2376 }
2377
2378 static void __mlx4_remove_one(struct pci_dev *pdev)
2379 {
2380 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2381 struct mlx4_priv *priv = mlx4_priv(dev);
2382 int pci_dev_data;
2383 int p;
2384
2385 if (priv->removed)
2386 return;
2387
2388 pci_dev_data = priv->pci_dev_data;
2389
2390 /* in SRIOV it is not allowed to unload the pf's
2391 * driver while there are alive vf's */
2392 if (mlx4_is_master(dev)) {
2393 if (mlx4_how_many_lives_vf(dev))
2394 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2395 }
2396 mlx4_stop_sense(dev);
2397 mlx4_unregister_device(dev);
2398
2399 for (p = 1; p <= dev->caps.num_ports; p++) {
2400 mlx4_cleanup_port_info(&priv->port[p]);
2401 mlx4_CLOSE_PORT(dev, p);
2402 }
2403
2404 if (mlx4_is_master(dev))
2405 mlx4_free_resource_tracker(dev,
2406 RES_TR_FREE_SLAVES_ONLY);
2407
2408 mlx4_cleanup_counters_table(dev);
2409 mlx4_cleanup_qp_table(dev);
2410 mlx4_cleanup_srq_table(dev);
2411 mlx4_cleanup_cq_table(dev);
2412 mlx4_cmd_use_polling(dev);
2413 mlx4_cleanup_eq_table(dev);
2414 mlx4_cleanup_mcg_table(dev);
2415 mlx4_cleanup_mr_table(dev);
2416 mlx4_cleanup_xrcd_table(dev);
2417 mlx4_cleanup_pd_table(dev);
2418
2419 if (mlx4_is_master(dev))
2420 mlx4_free_resource_tracker(dev,
2421 RES_TR_FREE_STRUCTS_ONLY);
2422
2423 iounmap(priv->kar);
2424 mlx4_uar_free(dev, &priv->driver_uar);
2425 mlx4_cleanup_uar_table(dev);
2426 if (!mlx4_is_slave(dev))
2427 mlx4_clear_steering(dev);
2428 mlx4_free_eq_table(dev);
2429 if (mlx4_is_master(dev))
2430 mlx4_multi_func_cleanup(dev);
2431 mlx4_close_hca(dev);
2432 if (mlx4_is_slave(dev))
2433 mlx4_multi_func_cleanup(dev);
2434 mlx4_cmd_cleanup(dev);
2435
2436 if (dev->flags & MLX4_FLAG_MSI_X)
2437 pci_disable_msix(pdev);
2438 if (dev->flags & MLX4_FLAG_SRIOV) {
2439 mlx4_warn(dev, "Disabling SR-IOV\n");
2440 pci_disable_sriov(pdev);
2441 }
2442
2443 if (!mlx4_is_slave(dev))
2444 mlx4_free_ownership(dev);
2445
2446 kfree(dev->caps.qp0_tunnel);
2447 kfree(dev->caps.qp0_proxy);
2448 kfree(dev->caps.qp1_tunnel);
2449 kfree(dev->caps.qp1_proxy);
2450
2451 pci_release_regions(pdev);
2452 pci_disable_device(pdev);
2453 memset(priv, 0, sizeof(*priv));
2454 priv->pci_dev_data = pci_dev_data;
2455 priv->removed = 1;
2456 }
2457
2458 static void mlx4_remove_one(struct pci_dev *pdev)
2459 {
2460 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2461 struct mlx4_priv *priv = mlx4_priv(dev);
2462
2463 __mlx4_remove_one(pdev);
2464 kfree(priv);
2465 pci_set_drvdata(pdev, NULL);
2466 }
2467
2468 int mlx4_restart_one(struct pci_dev *pdev)
2469 {
2470 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2471 struct mlx4_priv *priv = mlx4_priv(dev);
2472 int pci_dev_data;
2473
2474 pci_dev_data = priv->pci_dev_data;
2475 __mlx4_remove_one(pdev);
2476 return __mlx4_init_one(pdev, pci_dev_data);
2477 }
2478
2479 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2480 /* MT25408 "Hermon" SDR */
2481 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2482 /* MT25408 "Hermon" DDR */
2483 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2484 /* MT25408 "Hermon" QDR */
2485 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2486 /* MT25408 "Hermon" DDR PCIe gen2 */
2487 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2488 /* MT25408 "Hermon" QDR PCIe gen2 */
2489 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2490 /* MT25408 "Hermon" EN 10GigE */
2491 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2492 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2493 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2494 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2495 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2496 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2497 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2498 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2499 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2500 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2501 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2502 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2503 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2504 /* MT25400 Family [ConnectX-2 Virtual Function] */
2505 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2506 /* MT27500 Family [ConnectX-3] */
2507 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2508 /* MT27500 Family [ConnectX-3 Virtual Function] */
2509 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2510 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2511 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2512 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2513 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2514 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2515 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2516 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2517 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2518 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2519 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2520 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2521 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2522 { 0, }
2523 };
2524
2525 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2526
2527 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2528 pci_channel_state_t state)
2529 {
2530 __mlx4_remove_one(pdev);
2531
2532 return state == pci_channel_io_perm_failure ?
2533 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2534 }
2535
2536 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2537 {
2538 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2539 struct mlx4_priv *priv = mlx4_priv(dev);
2540 int ret;
2541
2542 ret = __mlx4_init_one(pdev, priv->pci_dev_data);
2543
2544 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2545 }
2546
2547 static const struct pci_error_handlers mlx4_err_handler = {
2548 .error_detected = mlx4_pci_err_detected,
2549 .slot_reset = mlx4_pci_slot_reset,
2550 };
2551
2552 static struct pci_driver mlx4_driver = {
2553 .name = DRV_NAME,
2554 .id_table = mlx4_pci_table,
2555 .probe = mlx4_init_one,
2556 .remove = mlx4_remove_one,
2557 .err_handler = &mlx4_err_handler,
2558 };
2559
2560 static int __init mlx4_verify_params(void)
2561 {
2562 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2563 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2564 return -1;
2565 }
2566
2567 if (log_num_vlan != 0)
2568 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2569 MLX4_LOG_NUM_VLANS);
2570
2571 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2572 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2573 return -1;
2574 }
2575
2576 /* Check if module param for ports type has legal combination */
2577 if (port_type_array[0] == false && port_type_array[1] == true) {
2578 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2579 port_type_array[0] = true;
2580 }
2581
2582 if (mlx4_log_num_mgm_entry_size != -1 &&
2583 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2584 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2585 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2586 "in legal range (-1 or %d..%d)\n",
2587 mlx4_log_num_mgm_entry_size,
2588 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2589 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2590 return -1;
2591 }
2592
2593 return 0;
2594 }
2595
2596 static int __init mlx4_init(void)
2597 {
2598 int ret;
2599
2600 if (mlx4_verify_params())
2601 return -EINVAL;
2602
2603 mlx4_catas_init();
2604
2605 mlx4_wq = create_singlethread_workqueue("mlx4");
2606 if (!mlx4_wq)
2607 return -ENOMEM;
2608
2609 ret = pci_register_driver(&mlx4_driver);
2610 return ret < 0 ? ret : 0;
2611 }
2612
2613 static void __exit mlx4_cleanup(void)
2614 {
2615 pci_unregister_driver(&mlx4_driver);
2616 destroy_workqueue(mlx4_wq);
2617 }
2618
2619 module_init(mlx4_init);
2620 module_exit(mlx4_cleanup);
kernel source for telekom puls (alcatel/mediatek)