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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / marvell / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47
48 #include <asm/irq.h>
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.30"
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 63
72
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
76
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
78
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static int legacy_pme = 0;
99 module_param(legacy_pme, int, 0);
100 MODULE_PARM_DESC(legacy_pme, "Legacy power management");
101
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
145 { 0 }
146 };
147
148 MODULE_DEVICE_TABLE(pci, sky2_id_table);
149
150 /* Avoid conditionals by using array */
151 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
152 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
153 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
154
155 static void sky2_set_multicast(struct net_device *dev);
156 static irqreturn_t sky2_intr(int irq, void *dev_id);
157
158 /* Access to PHY via serial interconnect */
159 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
160 {
161 int i;
162
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
166
167 for (i = 0; i < PHY_RETRIES; i++) {
168 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
169 if (ctrl == 0xffff)
170 goto io_error;
171
172 if (!(ctrl & GM_SMI_CT_BUSY))
173 return 0;
174
175 udelay(10);
176 }
177
178 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
179 return -ETIMEDOUT;
180
181 io_error:
182 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
183 return -EIO;
184 }
185
186 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
187 {
188 int i;
189
190 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
191 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
192
193 for (i = 0; i < PHY_RETRIES; i++) {
194 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
195 if (ctrl == 0xffff)
196 goto io_error;
197
198 if (ctrl & GM_SMI_CT_RD_VAL) {
199 *val = gma_read16(hw, port, GM_SMI_DATA);
200 return 0;
201 }
202
203 udelay(10);
204 }
205
206 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
207 return -ETIMEDOUT;
208 io_error:
209 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
210 return -EIO;
211 }
212
213 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
214 {
215 u16 v;
216 __gm_phy_read(hw, port, reg, &v);
217 return v;
218 }
219
220
221 static void sky2_power_on(struct sky2_hw *hw)
222 {
223 /* switch power to VCC (WA for VAUX problem) */
224 sky2_write8(hw, B0_POWER_CTRL,
225 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
226
227 /* disable Core Clock Division, */
228 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
229
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
231 /* enable bits are inverted */
232 sky2_write8(hw, B2_Y2_CLK_GATE,
233 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
234 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
235 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
236 else
237 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
238
239 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
240 u32 reg;
241
242 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
243
244 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
245 /* set all bits to 0 except bits 15..12 and 8 */
246 reg &= P_ASPM_CONTROL_MSK;
247 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
248
249 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
250 /* set all bits to 0 except bits 28 & 27 */
251 reg &= P_CTL_TIM_VMAIN_AV_MSK;
252 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
253
254 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
255
256 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
257
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
262
263 sky2_read32(hw, B2_GP_IO);
264 }
265
266 /* Turn on "driver loaded" LED */
267 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
268 }
269
270 static void sky2_power_aux(struct sky2_hw *hw)
271 {
272 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
273 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
274 else
275 /* enable bits are inverted */
276 sky2_write8(hw, B2_Y2_CLK_GATE,
277 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
278 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
279 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
280
281 /* switch power to VAUX if supported and PME from D3cold */
282 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
283 pci_pme_capable(hw->pdev, PCI_D3cold))
284 sky2_write8(hw, B0_POWER_CTRL,
285 (PC_VAUX_ENA | PC_VCC_ENA |
286 PC_VAUX_ON | PC_VCC_OFF));
287
288 /* turn off "driver loaded LED" */
289 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
290 }
291
292 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
293 {
294 u16 reg;
295
296 /* disable all GMAC IRQ's */
297 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
298
299 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
300 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
302 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
303
304 reg = gma_read16(hw, port, GM_RX_CTRL);
305 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
306 gma_write16(hw, port, GM_RX_CTRL, reg);
307 }
308
309 /* flow control to advertise bits */
310 static const u16 copper_fc_adv[] = {
311 [FC_NONE] = 0,
312 [FC_TX] = PHY_M_AN_ASP,
313 [FC_RX] = PHY_M_AN_PC,
314 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
315 };
316
317 /* flow control to advertise bits when using 1000BaseX */
318 static const u16 fiber_fc_adv[] = {
319 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
320 [FC_TX] = PHY_M_P_ASYM_MD_X,
321 [FC_RX] = PHY_M_P_SYM_MD_X,
322 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
323 };
324
325 /* flow control to GMA disable bits */
326 static const u16 gm_fc_disable[] = {
327 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
328 [FC_TX] = GM_GPCR_FC_RX_DIS,
329 [FC_RX] = GM_GPCR_FC_TX_DIS,
330 [FC_BOTH] = 0,
331 };
332
333
334 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
335 {
336 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
337 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
338
339 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
340 !(hw->flags & SKY2_HW_NEWER_PHY)) {
341 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
342
343 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
344 PHY_M_EC_MAC_S_MSK);
345 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
346
347 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
348 if (hw->chip_id == CHIP_ID_YUKON_EC)
349 /* set downshift counter to 3x and enable downshift */
350 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
351 else
352 /* set master & slave downshift counter to 1x */
353 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
354
355 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
356 }
357
358 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
359 if (sky2_is_copper(hw)) {
360 if (!(hw->flags & SKY2_HW_GIGABIT)) {
361 /* enable automatic crossover */
362 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
363
364 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
365 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
366 u16 spec;
367
368 /* Enable Class A driver for FE+ A0 */
369 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
370 spec |= PHY_M_FESC_SEL_CL_A;
371 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
372 }
373 } else {
374 /* disable energy detect */
375 ctrl &= ~PHY_M_PC_EN_DET_MSK;
376
377 /* enable automatic crossover */
378 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
379
380 /* downshift on PHY 88E1112 and 88E1149 is changed */
381 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
382 (hw->flags & SKY2_HW_NEWER_PHY)) {
383 /* set downshift counter to 3x and enable downshift */
384 ctrl &= ~PHY_M_PC_DSC_MSK;
385 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
386 }
387 }
388 } else {
389 /* workaround for deviation #4.88 (CRC errors) */
390 /* disable Automatic Crossover */
391
392 ctrl &= ~PHY_M_PC_MDIX_MSK;
393 }
394
395 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396
397 /* special setup for PHY 88E1112 Fiber */
398 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
399 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
400
401 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
402 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
403 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
404 ctrl &= ~PHY_M_MAC_MD_MSK;
405 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
406 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
407
408 if (hw->pmd_type == 'P') {
409 /* select page 1 to access Fiber registers */
410 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
411
412 /* for SFP-module set SIGDET polarity to low */
413 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
414 ctrl |= PHY_M_FIB_SIGD_POL;
415 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
416 }
417
418 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
419 }
420
421 ctrl = PHY_CT_RESET;
422 ct1000 = 0;
423 adv = PHY_AN_CSMA;
424 reg = 0;
425
426 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
427 if (sky2_is_copper(hw)) {
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 ct1000 |= PHY_M_1000C_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 ct1000 |= PHY_M_1000C_AHD;
432 if (sky2->advertising & ADVERTISED_100baseT_Full)
433 adv |= PHY_M_AN_100_FD;
434 if (sky2->advertising & ADVERTISED_100baseT_Half)
435 adv |= PHY_M_AN_100_HD;
436 if (sky2->advertising & ADVERTISED_10baseT_Full)
437 adv |= PHY_M_AN_10_FD;
438 if (sky2->advertising & ADVERTISED_10baseT_Half)
439 adv |= PHY_M_AN_10_HD;
440
441 } else { /* special defines for FIBER (88E1040S only) */
442 if (sky2->advertising & ADVERTISED_1000baseT_Full)
443 adv |= PHY_M_AN_1000X_AFD;
444 if (sky2->advertising & ADVERTISED_1000baseT_Half)
445 adv |= PHY_M_AN_1000X_AHD;
446 }
447
448 /* Restart Auto-negotiation */
449 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
450 } else {
451 /* forced speed/duplex settings */
452 ct1000 = PHY_M_1000C_MSE;
453
454 /* Disable auto update for duplex flow control and duplex */
455 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
456
457 switch (sky2->speed) {
458 case SPEED_1000:
459 ctrl |= PHY_CT_SP1000;
460 reg |= GM_GPCR_SPEED_1000;
461 break;
462 case SPEED_100:
463 ctrl |= PHY_CT_SP100;
464 reg |= GM_GPCR_SPEED_100;
465 break;
466 }
467
468 if (sky2->duplex == DUPLEX_FULL) {
469 reg |= GM_GPCR_DUP_FULL;
470 ctrl |= PHY_CT_DUP_MD;
471 } else if (sky2->speed < SPEED_1000)
472 sky2->flow_mode = FC_NONE;
473 }
474
475 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
476 if (sky2_is_copper(hw))
477 adv |= copper_fc_adv[sky2->flow_mode];
478 else
479 adv |= fiber_fc_adv[sky2->flow_mode];
480 } else {
481 reg |= GM_GPCR_AU_FCT_DIS;
482 reg |= gm_fc_disable[sky2->flow_mode];
483
484 /* Forward pause packets to GMAC? */
485 if (sky2->flow_mode & FC_RX)
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
487 else
488 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
489 }
490
491 gma_write16(hw, port, GM_GP_CTRL, reg);
492
493 if (hw->flags & SKY2_HW_GIGABIT)
494 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
495
496 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
497 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
498
499 /* Setup Phy LED's */
500 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
501 ledover = 0;
502
503 switch (hw->chip_id) {
504 case CHIP_ID_YUKON_FE:
505 /* on 88E3082 these bits are at 11..9 (shifted left) */
506 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
507
508 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
509
510 /* delete ACT LED control bits */
511 ctrl &= ~PHY_M_FELP_LED1_MSK;
512 /* change ACT LED control to blink mode */
513 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
514 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 break;
516
517 case CHIP_ID_YUKON_FE_P:
518 /* Enable Link Partner Next Page */
519 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
520 ctrl |= PHY_M_PC_ENA_LIP_NP;
521
522 /* disable Energy Detect and enable scrambler */
523 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
524 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
525
526 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
527 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
528 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
529 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
530
531 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
532 break;
533
534 case CHIP_ID_YUKON_XL:
535 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
536
537 /* select page 3 to access LED control register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
539
540 /* set LED Function Control register */
541 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
542 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
543 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
544 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
545 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
546
547 /* set Polarity Control register */
548 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
549 (PHY_M_POLC_LS1_P_MIX(4) |
550 PHY_M_POLC_IS0_P_MIX(4) |
551 PHY_M_POLC_LOS_CTRL(2) |
552 PHY_M_POLC_INIT_CTRL(2) |
553 PHY_M_POLC_STA1_CTRL(2) |
554 PHY_M_POLC_STA0_CTRL(2)));
555
556 /* restore page register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
558 break;
559
560 case CHIP_ID_YUKON_EC_U:
561 case CHIP_ID_YUKON_EX:
562 case CHIP_ID_YUKON_SUPR:
563 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
564
565 /* select page 3 to access LED control register */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
567
568 /* set LED Function Control register */
569 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
570 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
571 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
572 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
573 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
574
575 /* set Blink Rate in LED Timer Control Register */
576 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
577 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
578 /* restore page register */
579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
580 break;
581
582 default:
583 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
584 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
585
586 /* turn off the Rx LED (LED_RX) */
587 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
588 }
589
590 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
591 /* apply fixes in PHY AFE */
592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
593
594 /* increase differential signal amplitude in 10BASE-T */
595 gm_phy_write(hw, port, 0x18, 0xaa99);
596 gm_phy_write(hw, port, 0x17, 0x2011);
597
598 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
599 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
600 gm_phy_write(hw, port, 0x18, 0xa204);
601 gm_phy_write(hw, port, 0x17, 0x2002);
602 }
603
604 /* set page register to 0 */
605 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
606 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
607 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
608 /* apply workaround for integrated resistors calibration */
609 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
610 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
611 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
612 /* apply fixes in PHY AFE */
613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
614
615 /* apply RDAC termination workaround */
616 gm_phy_write(hw, port, 24, 0x2800);
617 gm_phy_write(hw, port, 23, 0x2001);
618
619 /* set page register back to 0 */
620 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
621 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
622 hw->chip_id < CHIP_ID_YUKON_SUPR) {
623 /* no effect on Yukon-XL */
624 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
625
626 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
627 sky2->speed == SPEED_100) {
628 /* turn on 100 Mbps LED (LED_LINK100) */
629 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
630 }
631
632 if (ledover)
633 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
634
635 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
636 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
637 int i;
638 /* This a phy register setup workaround copied from vendor driver. */
639 static const struct {
640 u16 reg, val;
641 } eee_afe[] = {
642 { 0x156, 0x58ce },
643 { 0x153, 0x99eb },
644 { 0x141, 0x8064 },
645 /* { 0x155, 0x130b },*/
646 { 0x000, 0x0000 },
647 { 0x151, 0x8433 },
648 { 0x14b, 0x8c44 },
649 { 0x14c, 0x0f90 },
650 { 0x14f, 0x39aa },
651 /* { 0x154, 0x2f39 },*/
652 { 0x14d, 0xba33 },
653 { 0x144, 0x0048 },
654 { 0x152, 0x2010 },
655 /* { 0x158, 0x1223 },*/
656 { 0x140, 0x4444 },
657 { 0x154, 0x2f3b },
658 { 0x158, 0xb203 },
659 { 0x157, 0x2029 },
660 };
661
662 /* Start Workaround for OptimaEEE Rev.Z0 */
663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
664
665 gm_phy_write(hw, port, 1, 0x4099);
666 gm_phy_write(hw, port, 3, 0x1120);
667 gm_phy_write(hw, port, 11, 0x113c);
668 gm_phy_write(hw, port, 14, 0x8100);
669 gm_phy_write(hw, port, 15, 0x112a);
670 gm_phy_write(hw, port, 17, 0x1008);
671
672 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
673 gm_phy_write(hw, port, 1, 0x20b0);
674
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
676
677 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
678 /* apply AFE settings */
679 gm_phy_write(hw, port, 17, eee_afe[i].val);
680 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
681 }
682
683 /* End Workaround for OptimaEEE */
684 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
685
686 /* Enable 10Base-Te (EEE) */
687 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
688 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
689 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
690 reg | PHY_M_10B_TE_ENABLE);
691 }
692 }
693
694 /* Enable phy interrupt on auto-negotiation complete (or link up) */
695 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
696 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
697 else
698 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
699 }
700
701 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
702 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
703
704 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
705 {
706 u32 reg1;
707
708 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
709 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
710 reg1 &= ~phy_power[port];
711
712 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
713 reg1 |= coma_mode[port];
714
715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
717 sky2_pci_read32(hw, PCI_DEV_REG1);
718
719 if (hw->chip_id == CHIP_ID_YUKON_FE)
720 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
721 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
722 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
723 }
724
725 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
726 {
727 u32 reg1;
728 u16 ctrl;
729
730 /* release GPHY Control reset */
731 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
732
733 /* release GMAC reset */
734 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
735
736 if (hw->flags & SKY2_HW_NEWER_PHY) {
737 /* select page 2 to access MAC control register */
738 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
739
740 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
741 /* allow GMII Power Down */
742 ctrl &= ~PHY_M_MAC_GMIF_PUP;
743 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
744
745 /* set page register back to 0 */
746 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
747 }
748
749 /* setup General Purpose Control Register */
750 gma_write16(hw, port, GM_GP_CTRL,
751 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
752 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
753 GM_GPCR_AU_SPD_DIS);
754
755 if (hw->chip_id != CHIP_ID_YUKON_EC) {
756 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
757 /* select page 2 to access MAC control register */
758 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
759
760 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
761 /* enable Power Down */
762 ctrl |= PHY_M_PC_POW_D_ENA;
763 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
764
765 /* set page register back to 0 */
766 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
767 }
768
769 /* set IEEE compatible Power Down Mode (dev. #4.99) */
770 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
771 }
772
773 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
774 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
775 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
776 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
777 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
778 }
779
780 /* configure IPG according to used link speed */
781 static void sky2_set_ipg(struct sky2_port *sky2)
782 {
783 u16 reg;
784
785 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
786 reg &= ~GM_SMOD_IPG_MSK;
787 if (sky2->speed > SPEED_100)
788 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
789 else
790 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
791 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
792 }
793
794 /* Enable Rx/Tx */
795 static void sky2_enable_rx_tx(struct sky2_port *sky2)
796 {
797 struct sky2_hw *hw = sky2->hw;
798 unsigned port = sky2->port;
799 u16 reg;
800
801 reg = gma_read16(hw, port, GM_GP_CTRL);
802 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
803 gma_write16(hw, port, GM_GP_CTRL, reg);
804 }
805
806 /* Force a renegotiation */
807 static void sky2_phy_reinit(struct sky2_port *sky2)
808 {
809 spin_lock_bh(&sky2->phy_lock);
810 sky2_phy_init(sky2->hw, sky2->port);
811 sky2_enable_rx_tx(sky2);
812 spin_unlock_bh(&sky2->phy_lock);
813 }
814
815 /* Put device in state to listen for Wake On Lan */
816 static void sky2_wol_init(struct sky2_port *sky2)
817 {
818 struct sky2_hw *hw = sky2->hw;
819 unsigned port = sky2->port;
820 enum flow_control save_mode;
821 u16 ctrl;
822
823 /* Bring hardware out of reset */
824 sky2_write16(hw, B0_CTST, CS_RST_CLR);
825 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
826
827 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
828 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
829
830 /* Force to 10/100
831 * sky2_reset will re-enable on resume
832 */
833 save_mode = sky2->flow_mode;
834 ctrl = sky2->advertising;
835
836 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
837 sky2->flow_mode = FC_NONE;
838
839 spin_lock_bh(&sky2->phy_lock);
840 sky2_phy_power_up(hw, port);
841 sky2_phy_init(hw, port);
842 spin_unlock_bh(&sky2->phy_lock);
843
844 sky2->flow_mode = save_mode;
845 sky2->advertising = ctrl;
846
847 /* Set GMAC to no flow control and auto update for speed/duplex */
848 gma_write16(hw, port, GM_GP_CTRL,
849 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
850 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
851
852 /* Set WOL address */
853 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
854 sky2->netdev->dev_addr, ETH_ALEN);
855
856 /* Turn on appropriate WOL control bits */
857 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
858 ctrl = 0;
859 if (sky2->wol & WAKE_PHY)
860 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
861 else
862 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
863
864 if (sky2->wol & WAKE_MAGIC)
865 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
866 else
867 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
868
869 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
870 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
871
872 /* Disable PiG firmware */
873 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
874
875 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
876 if (legacy_pme) {
877 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
878 reg1 |= PCI_Y2_PME_LEGACY;
879 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
880 }
881
882 /* block receiver */
883 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
884 sky2_read32(hw, B0_CTST);
885 }
886
887 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
888 {
889 struct net_device *dev = hw->dev[port];
890
891 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
892 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
893 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
894 /* Yukon-Extreme B0 and further Extreme devices */
895 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
896 } else if (dev->mtu > ETH_DATA_LEN) {
897 /* set Tx GMAC FIFO Almost Empty Threshold */
898 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
899 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
900
901 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
902 } else
903 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
904 }
905
906 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
907 {
908 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
909 u16 reg;
910 u32 rx_reg;
911 int i;
912 const u8 *addr = hw->dev[port]->dev_addr;
913
914 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
915 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
916
917 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
918
919 if (hw->chip_id == CHIP_ID_YUKON_XL &&
920 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
921 port == 1) {
922 /* WA DEV_472 -- looks like crossed wires on port 2 */
923 /* clear GMAC 1 Control reset */
924 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
925 do {
926 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
927 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
928 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
929 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
930 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
931 }
932
933 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
934
935 /* Enable Transmit FIFO Underrun */
936 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
937
938 spin_lock_bh(&sky2->phy_lock);
939 sky2_phy_power_up(hw, port);
940 sky2_phy_init(hw, port);
941 spin_unlock_bh(&sky2->phy_lock);
942
943 /* MIB clear */
944 reg = gma_read16(hw, port, GM_PHY_ADDR);
945 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
946
947 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
948 gma_read16(hw, port, i);
949 gma_write16(hw, port, GM_PHY_ADDR, reg);
950
951 /* transmit control */
952 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
953
954 /* receive control reg: unicast + multicast + no FCS */
955 gma_write16(hw, port, GM_RX_CTRL,
956 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
957
958 /* transmit flow control */
959 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
960
961 /* transmit parameter */
962 gma_write16(hw, port, GM_TX_PARAM,
963 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
964 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
965 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
966 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
967
968 /* serial mode register */
969 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
970 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
971
972 if (hw->dev[port]->mtu > ETH_DATA_LEN)
973 reg |= GM_SMOD_JUMBO_ENA;
974
975 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
976 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
977 reg |= GM_NEW_FLOW_CTRL;
978
979 gma_write16(hw, port, GM_SERIAL_MODE, reg);
980
981 /* virtual address for data */
982 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
983
984 /* physical address: used for pause frames */
985 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
986
987 /* ignore counter overflows */
988 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
989 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
990 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
991
992 /* Configure Rx MAC FIFO */
993 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
994 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
995 if (hw->chip_id == CHIP_ID_YUKON_EX ||
996 hw->chip_id == CHIP_ID_YUKON_FE_P)
997 rx_reg |= GMF_RX_OVER_ON;
998
999 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
1000
1001 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1002 /* Hardware errata - clear flush mask */
1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1004 } else {
1005 /* Flush Rx MAC FIFO on any flow control or error */
1006 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1007 }
1008
1009 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1010 reg = RX_GMF_FL_THR_DEF + 1;
1011 /* Another magic mystery workaround from sk98lin */
1012 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1013 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1014 reg = 0x178;
1015 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1016
1017 /* Configure Tx MAC FIFO */
1018 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1019 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1020
1021 /* On chips without ram buffer, pause is controlled by MAC level */
1022 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1023 /* Pause threshold is scaled by 8 in bytes */
1024 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1025 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1026 reg = 1568 / 8;
1027 else
1028 reg = 1024 / 8;
1029 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1030 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1031
1032 sky2_set_tx_stfwd(hw, port);
1033 }
1034
1035 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1036 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1037 /* disable dynamic watermark */
1038 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1039 reg &= ~TX_DYN_WM_ENA;
1040 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1041 }
1042 }
1043
1044 /* Assign Ram Buffer allocation to queue */
1045 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1046 {
1047 u32 end;
1048
1049 /* convert from K bytes to qwords used for hw register */
1050 start *= 1024/8;
1051 space *= 1024/8;
1052 end = start + space - 1;
1053
1054 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1055 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1056 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1057 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1058 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1059
1060 if (q == Q_R1 || q == Q_R2) {
1061 u32 tp = space - space/4;
1062
1063 /* On receive queue's set the thresholds
1064 * give receiver priority when > 3/4 full
1065 * send pause when down to 2K
1066 */
1067 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1068 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1069
1070 tp = space - 8192/8;
1071 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1072 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1073 } else {
1074 /* Enable store & forward on Tx queue's because
1075 * Tx FIFO is only 1K on Yukon
1076 */
1077 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1078 }
1079
1080 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1081 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1082 }
1083
1084 /* Setup Bus Memory Interface */
1085 static void sky2_qset(struct sky2_hw *hw, u16 q)
1086 {
1087 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1088 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1089 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1090 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1091 }
1092
1093 /* Setup prefetch unit registers. This is the interface between
1094 * hardware and driver list elements
1095 */
1096 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1097 dma_addr_t addr, u32 last)
1098 {
1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1100 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1103 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1105
1106 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1107 }
1108
1109 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1110 {
1111 struct sky2_tx_le *le = sky2->tx_le + *slot;
1112
1113 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1114 le->ctrl = 0;
1115 return le;
1116 }
1117
1118 static void tx_init(struct sky2_port *sky2)
1119 {
1120 struct sky2_tx_le *le;
1121
1122 sky2->tx_prod = sky2->tx_cons = 0;
1123 sky2->tx_tcpsum = 0;
1124 sky2->tx_last_mss = 0;
1125 netdev_reset_queue(sky2->netdev);
1126
1127 le = get_tx_le(sky2, &sky2->tx_prod);
1128 le->addr = 0;
1129 le->opcode = OP_ADDR64 | HW_OWNER;
1130 sky2->tx_last_upper = 0;
1131 }
1132
1133 /* Update chip's next pointer */
1134 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1135 {
1136 /* Make sure write' to descriptors are complete before we tell hardware */
1137 wmb();
1138 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1139
1140 /* Synchronize I/O on since next processor may write to tail */
1141 mmiowb();
1142 }
1143
1144
1145 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1146 {
1147 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1148 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1149 le->ctrl = 0;
1150 return le;
1151 }
1152
1153 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1154 {
1155 unsigned size;
1156
1157 /* Space needed for frame data + headers rounded up */
1158 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1159
1160 /* Stopping point for hardware truncation */
1161 return (size - 8) / sizeof(u32);
1162 }
1163
1164 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1165 {
1166 struct rx_ring_info *re;
1167 unsigned size;
1168
1169 /* Space needed for frame data + headers rounded up */
1170 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1171
1172 sky2->rx_nfrags = size >> PAGE_SHIFT;
1173 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1174
1175 /* Compute residue after pages */
1176 size -= sky2->rx_nfrags << PAGE_SHIFT;
1177
1178 /* Optimize to handle small packets and headers */
1179 if (size < copybreak)
1180 size = copybreak;
1181 if (size < ETH_HLEN)
1182 size = ETH_HLEN;
1183
1184 return size;
1185 }
1186
1187 /* Build description to hardware for one receive segment */
1188 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1189 dma_addr_t map, unsigned len)
1190 {
1191 struct sky2_rx_le *le;
1192
1193 if (sizeof(dma_addr_t) > sizeof(u32)) {
1194 le = sky2_next_rx(sky2);
1195 le->addr = cpu_to_le32(upper_32_bits(map));
1196 le->opcode = OP_ADDR64 | HW_OWNER;
1197 }
1198
1199 le = sky2_next_rx(sky2);
1200 le->addr = cpu_to_le32(lower_32_bits(map));
1201 le->length = cpu_to_le16(len);
1202 le->opcode = op | HW_OWNER;
1203 }
1204
1205 /* Build description to hardware for one possibly fragmented skb */
1206 static void sky2_rx_submit(struct sky2_port *sky2,
1207 const struct rx_ring_info *re)
1208 {
1209 int i;
1210
1211 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1212
1213 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1214 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1215 }
1216
1217
1218 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1219 unsigned size)
1220 {
1221 struct sk_buff *skb = re->skb;
1222 int i;
1223
1224 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1225 if (pci_dma_mapping_error(pdev, re->data_addr))
1226 goto mapping_error;
1227
1228 dma_unmap_len_set(re, data_size, size);
1229
1230 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1231 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1232
1233 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1234 skb_frag_size(frag),
1235 DMA_FROM_DEVICE);
1236
1237 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1238 goto map_page_error;
1239 }
1240 return 0;
1241
1242 map_page_error:
1243 while (--i >= 0) {
1244 pci_unmap_page(pdev, re->frag_addr[i],
1245 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1246 PCI_DMA_FROMDEVICE);
1247 }
1248
1249 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1250 PCI_DMA_FROMDEVICE);
1251
1252 mapping_error:
1253 if (net_ratelimit())
1254 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1255 skb->dev->name);
1256 return -EIO;
1257 }
1258
1259 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1260 {
1261 struct sk_buff *skb = re->skb;
1262 int i;
1263
1264 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1265 PCI_DMA_FROMDEVICE);
1266
1267 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1268 pci_unmap_page(pdev, re->frag_addr[i],
1269 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1270 PCI_DMA_FROMDEVICE);
1271 }
1272
1273 /* Tell chip where to start receive checksum.
1274 * Actually has two checksums, but set both same to avoid possible byte
1275 * order problems.
1276 */
1277 static void rx_set_checksum(struct sky2_port *sky2)
1278 {
1279 struct sky2_rx_le *le = sky2_next_rx(sky2);
1280
1281 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1282 le->ctrl = 0;
1283 le->opcode = OP_TCPSTART | HW_OWNER;
1284
1285 sky2_write32(sky2->hw,
1286 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1287 (sky2->netdev->features & NETIF_F_RXCSUM)
1288 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1289 }
1290
1291 /*
1292 * Fixed initial key as seed to RSS.
1293 */
1294 static const uint32_t rss_init_key[10] = {
1295 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43,
1296 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1297 };
1298
1299 /* Enable/disable receive hash calculation (RSS) */
1300 static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1301 {
1302 struct sky2_port *sky2 = netdev_priv(dev);
1303 struct sky2_hw *hw = sky2->hw;
1304 int i, nkeys = 4;
1305
1306 /* Supports IPv6 and other modes */
1307 if (hw->flags & SKY2_HW_NEW_LE) {
1308 nkeys = 10;
1309 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1310 }
1311
1312 /* Program RSS initial values */
1313 if (features & NETIF_F_RXHASH) {
1314 for (i = 0; i < nkeys; i++)
1315 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1316 rss_init_key[i]);
1317
1318 /* Need to turn on (undocumented) flag to make hashing work */
1319 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1320 RX_STFW_ENA);
1321
1322 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1323 BMU_ENA_RX_RSS_HASH);
1324 } else
1325 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1326 BMU_DIS_RX_RSS_HASH);
1327 }
1328
1329 /*
1330 * The RX Stop command will not work for Yukon-2 if the BMU does not
1331 * reach the end of packet and since we can't make sure that we have
1332 * incoming data, we must reset the BMU while it is not doing a DMA
1333 * transfer. Since it is possible that the RX path is still active,
1334 * the RX RAM buffer will be stopped first, so any possible incoming
1335 * data will not trigger a DMA. After the RAM buffer is stopped, the
1336 * BMU is polled until any DMA in progress is ended and only then it
1337 * will be reset.
1338 */
1339 static void sky2_rx_stop(struct sky2_port *sky2)
1340 {
1341 struct sky2_hw *hw = sky2->hw;
1342 unsigned rxq = rxqaddr[sky2->port];
1343 int i;
1344
1345 /* disable the RAM Buffer receive queue */
1346 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1347
1348 for (i = 0; i < 0xffff; i++)
1349 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1350 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1351 goto stopped;
1352
1353 netdev_warn(sky2->netdev, "receiver stop failed\n");
1354 stopped:
1355 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1356
1357 /* reset the Rx prefetch unit */
1358 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1359 mmiowb();
1360 }
1361
1362 /* Clean out receive buffer area, assumes receiver hardware stopped */
1363 static void sky2_rx_clean(struct sky2_port *sky2)
1364 {
1365 unsigned i;
1366
1367 memset(sky2->rx_le, 0, RX_LE_BYTES);
1368 for (i = 0; i < sky2->rx_pending; i++) {
1369 struct rx_ring_info *re = sky2->rx_ring + i;
1370
1371 if (re->skb) {
1372 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1373 kfree_skb(re->skb);
1374 re->skb = NULL;
1375 }
1376 }
1377 }
1378
1379 /* Basic MII support */
1380 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1381 {
1382 struct mii_ioctl_data *data = if_mii(ifr);
1383 struct sky2_port *sky2 = netdev_priv(dev);
1384 struct sky2_hw *hw = sky2->hw;
1385 int err = -EOPNOTSUPP;
1386
1387 if (!netif_running(dev))
1388 return -ENODEV; /* Phy still in reset */
1389
1390 switch (cmd) {
1391 case SIOCGMIIPHY:
1392 data->phy_id = PHY_ADDR_MARV;
1393
1394 /* fallthru */
1395 case SIOCGMIIREG: {
1396 u16 val = 0;
1397
1398 spin_lock_bh(&sky2->phy_lock);
1399 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1400 spin_unlock_bh(&sky2->phy_lock);
1401
1402 data->val_out = val;
1403 break;
1404 }
1405
1406 case SIOCSMIIREG:
1407 spin_lock_bh(&sky2->phy_lock);
1408 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1409 data->val_in);
1410 spin_unlock_bh(&sky2->phy_lock);
1411 break;
1412 }
1413 return err;
1414 }
1415
1416 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1417
1418 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1419 {
1420 struct sky2_port *sky2 = netdev_priv(dev);
1421 struct sky2_hw *hw = sky2->hw;
1422 u16 port = sky2->port;
1423
1424 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1425 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1426 RX_VLAN_STRIP_ON);
1427 else
1428 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1429 RX_VLAN_STRIP_OFF);
1430
1431 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1432 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1433 TX_VLAN_TAG_ON);
1434
1435 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1436 } else {
1437 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1438 TX_VLAN_TAG_OFF);
1439
1440 /* Can't do transmit offload of vlan without hw vlan */
1441 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1442 }
1443 }
1444
1445 /* Amount of required worst case padding in rx buffer */
1446 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1447 {
1448 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1449 }
1450
1451 /*
1452 * Allocate an skb for receiving. If the MTU is large enough
1453 * make the skb non-linear with a fragment list of pages.
1454 */
1455 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1456 {
1457 struct sk_buff *skb;
1458 int i;
1459
1460 skb = __netdev_alloc_skb(sky2->netdev,
1461 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1462 gfp);
1463 if (!skb)
1464 goto nomem;
1465
1466 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1467 unsigned char *start;
1468 /*
1469 * Workaround for a bug in FIFO that cause hang
1470 * if the FIFO if the receive buffer is not 64 byte aligned.
1471 * The buffer returned from netdev_alloc_skb is
1472 * aligned except if slab debugging is enabled.
1473 */
1474 start = PTR_ALIGN(skb->data, 8);
1475 skb_reserve(skb, start - skb->data);
1476 } else
1477 skb_reserve(skb, NET_IP_ALIGN);
1478
1479 for (i = 0; i < sky2->rx_nfrags; i++) {
1480 struct page *page = alloc_page(gfp);
1481
1482 if (!page)
1483 goto free_partial;
1484 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1485 }
1486
1487 return skb;
1488 free_partial:
1489 kfree_skb(skb);
1490 nomem:
1491 return NULL;
1492 }
1493
1494 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1495 {
1496 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1497 }
1498
1499 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1500 {
1501 struct sky2_hw *hw = sky2->hw;
1502 unsigned i;
1503
1504 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1505
1506 /* Fill Rx ring */
1507 for (i = 0; i < sky2->rx_pending; i++) {
1508 struct rx_ring_info *re = sky2->rx_ring + i;
1509
1510 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1511 if (!re->skb)
1512 return -ENOMEM;
1513
1514 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1515 dev_kfree_skb(re->skb);
1516 re->skb = NULL;
1517 return -ENOMEM;
1518 }
1519 }
1520 return 0;
1521 }
1522
1523 /*
1524 * Setup receiver buffer pool.
1525 * Normal case this ends up creating one list element for skb
1526 * in the receive ring. Worst case if using large MTU and each
1527 * allocation falls on a different 64 bit region, that results
1528 * in 6 list elements per ring entry.
1529 * One element is used for checksum enable/disable, and one
1530 * extra to avoid wrap.
1531 */
1532 static void sky2_rx_start(struct sky2_port *sky2)
1533 {
1534 struct sky2_hw *hw = sky2->hw;
1535 struct rx_ring_info *re;
1536 unsigned rxq = rxqaddr[sky2->port];
1537 unsigned i, thresh;
1538
1539 sky2->rx_put = sky2->rx_next = 0;
1540 sky2_qset(hw, rxq);
1541
1542 /* On PCI express lowering the watermark gives better performance */
1543 if (pci_is_pcie(hw->pdev))
1544 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1545
1546 /* These chips have no ram buffer?
1547 * MAC Rx RAM Read is controlled by hardware */
1548 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1549 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1550 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1551
1552 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1553
1554 if (!(hw->flags & SKY2_HW_NEW_LE))
1555 rx_set_checksum(sky2);
1556
1557 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1558 rx_set_rss(sky2->netdev, sky2->netdev->features);
1559
1560 /* submit Rx ring */
1561 for (i = 0; i < sky2->rx_pending; i++) {
1562 re = sky2->rx_ring + i;
1563 sky2_rx_submit(sky2, re);
1564 }
1565
1566 /*
1567 * The receiver hangs if it receives frames larger than the
1568 * packet buffer. As a workaround, truncate oversize frames, but
1569 * the register is limited to 9 bits, so if you do frames > 2052
1570 * you better get the MTU right!
1571 */
1572 thresh = sky2_get_rx_threshold(sky2);
1573 if (thresh > 0x1ff)
1574 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1575 else {
1576 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1577 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1578 }
1579
1580 /* Tell chip about available buffers */
1581 sky2_rx_update(sky2, rxq);
1582
1583 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1584 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1585 /*
1586 * Disable flushing of non ASF packets;
1587 * must be done after initializing the BMUs;
1588 * drivers without ASF support should do this too, otherwise
1589 * it may happen that they cannot run on ASF devices;
1590 * remember that the MAC FIFO isn't reset during initialization.
1591 */
1592 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1593 }
1594
1595 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1596 /* Enable RX Home Address & Routing Header checksum fix */
1597 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1598 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1599
1600 /* Enable TX Home Address & Routing Header checksum fix */
1601 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1602 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1603 }
1604 }
1605
1606 static int sky2_alloc_buffers(struct sky2_port *sky2)
1607 {
1608 struct sky2_hw *hw = sky2->hw;
1609
1610 /* must be power of 2 */
1611 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1612 sky2->tx_ring_size *
1613 sizeof(struct sky2_tx_le),
1614 &sky2->tx_le_map);
1615 if (!sky2->tx_le)
1616 goto nomem;
1617
1618 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1619 GFP_KERNEL);
1620 if (!sky2->tx_ring)
1621 goto nomem;
1622
1623 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1624 &sky2->rx_le_map);
1625 if (!sky2->rx_le)
1626 goto nomem;
1627 memset(sky2->rx_le, 0, RX_LE_BYTES);
1628
1629 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1630 GFP_KERNEL);
1631 if (!sky2->rx_ring)
1632 goto nomem;
1633
1634 return sky2_alloc_rx_skbs(sky2);
1635 nomem:
1636 return -ENOMEM;
1637 }
1638
1639 static void sky2_free_buffers(struct sky2_port *sky2)
1640 {
1641 struct sky2_hw *hw = sky2->hw;
1642
1643 sky2_rx_clean(sky2);
1644
1645 if (sky2->rx_le) {
1646 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1647 sky2->rx_le, sky2->rx_le_map);
1648 sky2->rx_le = NULL;
1649 }
1650 if (sky2->tx_le) {
1651 pci_free_consistent(hw->pdev,
1652 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1653 sky2->tx_le, sky2->tx_le_map);
1654 sky2->tx_le = NULL;
1655 }
1656 kfree(sky2->tx_ring);
1657 kfree(sky2->rx_ring);
1658
1659 sky2->tx_ring = NULL;
1660 sky2->rx_ring = NULL;
1661 }
1662
1663 static void sky2_hw_up(struct sky2_port *sky2)
1664 {
1665 struct sky2_hw *hw = sky2->hw;
1666 unsigned port = sky2->port;
1667 u32 ramsize;
1668 int cap;
1669 struct net_device *otherdev = hw->dev[sky2->port^1];
1670
1671 tx_init(sky2);
1672
1673 /*
1674 * On dual port PCI-X card, there is an problem where status
1675 * can be received out of order due to split transactions
1676 */
1677 if (otherdev && netif_running(otherdev) &&
1678 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1679 u16 cmd;
1680
1681 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1682 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1683 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1684 }
1685
1686 sky2_mac_init(hw, port);
1687
1688 /* Register is number of 4K blocks on internal RAM buffer. */
1689 ramsize = sky2_read8(hw, B2_E_0) * 4;
1690 if (ramsize > 0) {
1691 u32 rxspace;
1692
1693 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1694 if (ramsize < 16)
1695 rxspace = ramsize / 2;
1696 else
1697 rxspace = 8 + (2*(ramsize - 16))/3;
1698
1699 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1700 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1701
1702 /* Make sure SyncQ is disabled */
1703 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1704 RB_RST_SET);
1705 }
1706
1707 sky2_qset(hw, txqaddr[port]);
1708
1709 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1710 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1711 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1712
1713 /* Set almost empty threshold */
1714 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1715 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1716 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1717
1718 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1719 sky2->tx_ring_size - 1);
1720
1721 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1722 netdev_update_features(sky2->netdev);
1723
1724 sky2_rx_start(sky2);
1725 }
1726
1727 /* Setup device IRQ and enable napi to process */
1728 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1729 {
1730 struct pci_dev *pdev = hw->pdev;
1731 int err;
1732
1733 err = request_irq(pdev->irq, sky2_intr,
1734 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1735 name, hw);
1736 if (err)
1737 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1738 else {
1739 hw->flags |= SKY2_HW_IRQ_SETUP;
1740
1741 napi_enable(&hw->napi);
1742 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1743 sky2_read32(hw, B0_IMSK);
1744 }
1745
1746 return err;
1747 }
1748
1749
1750 /* Bring up network interface. */
1751 static int sky2_open(struct net_device *dev)
1752 {
1753 struct sky2_port *sky2 = netdev_priv(dev);
1754 struct sky2_hw *hw = sky2->hw;
1755 unsigned port = sky2->port;
1756 u32 imask;
1757 int err;
1758
1759 netif_carrier_off(dev);
1760
1761 err = sky2_alloc_buffers(sky2);
1762 if (err)
1763 goto err_out;
1764
1765 /* With single port, IRQ is setup when device is brought up */
1766 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1767 goto err_out;
1768
1769 sky2_hw_up(sky2);
1770
1771 /* Enable interrupts from phy/mac for port */
1772 imask = sky2_read32(hw, B0_IMSK);
1773
1774 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1775 hw->chip_id == CHIP_ID_YUKON_PRM ||
1776 hw->chip_id == CHIP_ID_YUKON_OP_2)
1777 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1778
1779 imask |= portirq_msk[port];
1780 sky2_write32(hw, B0_IMSK, imask);
1781 sky2_read32(hw, B0_IMSK);
1782
1783 netif_info(sky2, ifup, dev, "enabling interface\n");
1784
1785 return 0;
1786
1787 err_out:
1788 sky2_free_buffers(sky2);
1789 return err;
1790 }
1791
1792 /* Modular subtraction in ring */
1793 static inline int tx_inuse(const struct sky2_port *sky2)
1794 {
1795 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1796 }
1797
1798 /* Number of list elements available for next tx */
1799 static inline int tx_avail(const struct sky2_port *sky2)
1800 {
1801 return sky2->tx_pending - tx_inuse(sky2);
1802 }
1803
1804 /* Estimate of number of transmit list elements required */
1805 static unsigned tx_le_req(const struct sk_buff *skb)
1806 {
1807 unsigned count;
1808
1809 count = (skb_shinfo(skb)->nr_frags + 1)
1810 * (sizeof(dma_addr_t) / sizeof(u32));
1811
1812 if (skb_is_gso(skb))
1813 ++count;
1814 else if (sizeof(dma_addr_t) == sizeof(u32))
1815 ++count; /* possible vlan */
1816
1817 if (skb->ip_summed == CHECKSUM_PARTIAL)
1818 ++count;
1819
1820 return count;
1821 }
1822
1823 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1824 {
1825 if (re->flags & TX_MAP_SINGLE)
1826 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1827 dma_unmap_len(re, maplen),
1828 PCI_DMA_TODEVICE);
1829 else if (re->flags & TX_MAP_PAGE)
1830 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1831 dma_unmap_len(re, maplen),
1832 PCI_DMA_TODEVICE);
1833 re->flags = 0;
1834 }
1835
1836 /*
1837 * Put one packet in ring for transmit.
1838 * A single packet can generate multiple list elements, and
1839 * the number of ring elements will probably be less than the number
1840 * of list elements used.
1841 */
1842 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1843 struct net_device *dev)
1844 {
1845 struct sky2_port *sky2 = netdev_priv(dev);
1846 struct sky2_hw *hw = sky2->hw;
1847 struct sky2_tx_le *le = NULL;
1848 struct tx_ring_info *re;
1849 unsigned i, len;
1850 dma_addr_t mapping;
1851 u32 upper;
1852 u16 slot;
1853 u16 mss;
1854 u8 ctrl;
1855
1856 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1857 return NETDEV_TX_BUSY;
1858
1859 len = skb_headlen(skb);
1860 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1861
1862 if (pci_dma_mapping_error(hw->pdev, mapping))
1863 goto mapping_error;
1864
1865 slot = sky2->tx_prod;
1866 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1867 "tx queued, slot %u, len %d\n", slot, skb->len);
1868
1869 /* Send high bits if needed */
1870 upper = upper_32_bits(mapping);
1871 if (upper != sky2->tx_last_upper) {
1872 le = get_tx_le(sky2, &slot);
1873 le->addr = cpu_to_le32(upper);
1874 sky2->tx_last_upper = upper;
1875 le->opcode = OP_ADDR64 | HW_OWNER;
1876 }
1877
1878 /* Check for TCP Segmentation Offload */
1879 mss = skb_shinfo(skb)->gso_size;
1880 if (mss != 0) {
1881
1882 if (!(hw->flags & SKY2_HW_NEW_LE))
1883 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1884
1885 if (mss != sky2->tx_last_mss) {
1886 le = get_tx_le(sky2, &slot);
1887 le->addr = cpu_to_le32(mss);
1888
1889 if (hw->flags & SKY2_HW_NEW_LE)
1890 le->opcode = OP_MSS | HW_OWNER;
1891 else
1892 le->opcode = OP_LRGLEN | HW_OWNER;
1893 sky2->tx_last_mss = mss;
1894 }
1895 }
1896
1897 ctrl = 0;
1898
1899 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1900 if (vlan_tx_tag_present(skb)) {
1901 if (!le) {
1902 le = get_tx_le(sky2, &slot);
1903 le->addr = 0;
1904 le->opcode = OP_VLAN|HW_OWNER;
1905 } else
1906 le->opcode |= OP_VLAN;
1907 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1908 ctrl |= INS_VLAN;
1909 }
1910
1911 /* Handle TCP checksum offload */
1912 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1913 /* On Yukon EX (some versions) encoding change. */
1914 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1915 ctrl |= CALSUM; /* auto checksum */
1916 else {
1917 const unsigned offset = skb_transport_offset(skb);
1918 u32 tcpsum;
1919
1920 tcpsum = offset << 16; /* sum start */
1921 tcpsum |= offset + skb->csum_offset; /* sum write */
1922
1923 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1924 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1925 ctrl |= UDPTCP;
1926
1927 if (tcpsum != sky2->tx_tcpsum) {
1928 sky2->tx_tcpsum = tcpsum;
1929
1930 le = get_tx_le(sky2, &slot);
1931 le->addr = cpu_to_le32(tcpsum);
1932 le->length = 0; /* initial checksum value */
1933 le->ctrl = 1; /* one packet */
1934 le->opcode = OP_TCPLISW | HW_OWNER;
1935 }
1936 }
1937 }
1938
1939 re = sky2->tx_ring + slot;
1940 re->flags = TX_MAP_SINGLE;
1941 dma_unmap_addr_set(re, mapaddr, mapping);
1942 dma_unmap_len_set(re, maplen, len);
1943
1944 le = get_tx_le(sky2, &slot);
1945 le->addr = cpu_to_le32(lower_32_bits(mapping));
1946 le->length = cpu_to_le16(len);
1947 le->ctrl = ctrl;
1948 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1949
1950
1951 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1952 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1953
1954 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1955 skb_frag_size(frag), DMA_TO_DEVICE);
1956
1957 if (dma_mapping_error(&hw->pdev->dev, mapping))
1958 goto mapping_unwind;
1959
1960 upper = upper_32_bits(mapping);
1961 if (upper != sky2->tx_last_upper) {
1962 le = get_tx_le(sky2, &slot);
1963 le->addr = cpu_to_le32(upper);
1964 sky2->tx_last_upper = upper;
1965 le->opcode = OP_ADDR64 | HW_OWNER;
1966 }
1967
1968 re = sky2->tx_ring + slot;
1969 re->flags = TX_MAP_PAGE;
1970 dma_unmap_addr_set(re, mapaddr, mapping);
1971 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1972
1973 le = get_tx_le(sky2, &slot);
1974 le->addr = cpu_to_le32(lower_32_bits(mapping));
1975 le->length = cpu_to_le16(skb_frag_size(frag));
1976 le->ctrl = ctrl;
1977 le->opcode = OP_BUFFER | HW_OWNER;
1978 }
1979
1980 re->skb = skb;
1981 le->ctrl |= EOP;
1982
1983 sky2->tx_prod = slot;
1984
1985 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1986 netif_stop_queue(dev);
1987
1988 netdev_sent_queue(dev, skb->len);
1989 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1990
1991 return NETDEV_TX_OK;
1992
1993 mapping_unwind:
1994 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1995 re = sky2->tx_ring + i;
1996
1997 sky2_tx_unmap(hw->pdev, re);
1998 }
1999
2000 mapping_error:
2001 if (net_ratelimit())
2002 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2003 dev_kfree_skb(skb);
2004 return NETDEV_TX_OK;
2005 }
2006
2007 /*
2008 * Free ring elements from starting at tx_cons until "done"
2009 *
2010 * NB:
2011 * 1. The hardware will tell us about partial completion of multi-part
2012 * buffers so make sure not to free skb to early.
2013 * 2. This may run in parallel start_xmit because the it only
2014 * looks at the tail of the queue of FIFO (tx_cons), not
2015 * the head (tx_prod)
2016 */
2017 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2018 {
2019 struct net_device *dev = sky2->netdev;
2020 u16 idx;
2021 unsigned int bytes_compl = 0, pkts_compl = 0;
2022
2023 BUG_ON(done >= sky2->tx_ring_size);
2024
2025 for (idx = sky2->tx_cons; idx != done;
2026 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2027 struct tx_ring_info *re = sky2->tx_ring + idx;
2028 struct sk_buff *skb = re->skb;
2029
2030 sky2_tx_unmap(sky2->hw->pdev, re);
2031
2032 if (skb) {
2033 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2034 "tx done %u\n", idx);
2035
2036 pkts_compl++;
2037 bytes_compl += skb->len;
2038
2039 re->skb = NULL;
2040 dev_kfree_skb_any(skb);
2041
2042 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2043 }
2044 }
2045
2046 sky2->tx_cons = idx;
2047 smp_mb();
2048
2049 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2050
2051 u64_stats_update_begin(&sky2->tx_stats.syncp);
2052 sky2->tx_stats.packets += pkts_compl;
2053 sky2->tx_stats.bytes += bytes_compl;
2054 u64_stats_update_end(&sky2->tx_stats.syncp);
2055 }
2056
2057 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2058 {
2059 /* Disable Force Sync bit and Enable Alloc bit */
2060 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2061 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2062
2063 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2064 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2065 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2066
2067 /* Reset the PCI FIFO of the async Tx queue */
2068 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2069 BMU_RST_SET | BMU_FIFO_RST);
2070
2071 /* Reset the Tx prefetch units */
2072 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2073 PREF_UNIT_RST_SET);
2074
2075 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2076 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2077
2078 sky2_read32(hw, B0_CTST);
2079 }
2080
2081 static void sky2_hw_down(struct sky2_port *sky2)
2082 {
2083 struct sky2_hw *hw = sky2->hw;
2084 unsigned port = sky2->port;
2085 u16 ctrl;
2086
2087 /* Force flow control off */
2088 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2089
2090 /* Stop transmitter */
2091 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2092 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2093
2094 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2095 RB_RST_SET | RB_DIS_OP_MD);
2096
2097 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2098 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2099 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2100
2101 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2102
2103 /* Workaround shared GMAC reset */
2104 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2105 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2106 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2107
2108 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2109
2110 /* Force any delayed status interrupt and NAPI */
2111 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2112 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2113 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2114 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2115
2116 sky2_rx_stop(sky2);
2117
2118 spin_lock_bh(&sky2->phy_lock);
2119 sky2_phy_power_down(hw, port);
2120 spin_unlock_bh(&sky2->phy_lock);
2121
2122 sky2_tx_reset(hw, port);
2123
2124 /* Free any pending frames stuck in HW queue */
2125 sky2_tx_complete(sky2, sky2->tx_prod);
2126 }
2127
2128 /* Network shutdown */
2129 static int sky2_close(struct net_device *dev)
2130 {
2131 struct sky2_port *sky2 = netdev_priv(dev);
2132 struct sky2_hw *hw = sky2->hw;
2133
2134 /* Never really got started! */
2135 if (!sky2->tx_le)
2136 return 0;
2137
2138 netif_info(sky2, ifdown, dev, "disabling interface\n");
2139
2140 if (hw->ports == 1) {
2141 sky2_write32(hw, B0_IMSK, 0);
2142 sky2_read32(hw, B0_IMSK);
2143
2144 napi_disable(&hw->napi);
2145 free_irq(hw->pdev->irq, hw);
2146 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2147 } else {
2148 u32 imask;
2149
2150 /* Disable port IRQ */
2151 imask = sky2_read32(hw, B0_IMSK);
2152 imask &= ~portirq_msk[sky2->port];
2153 sky2_write32(hw, B0_IMSK, imask);
2154 sky2_read32(hw, B0_IMSK);
2155
2156 synchronize_irq(hw->pdev->irq);
2157 napi_synchronize(&hw->napi);
2158 }
2159
2160 sky2_hw_down(sky2);
2161
2162 sky2_free_buffers(sky2);
2163
2164 return 0;
2165 }
2166
2167 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2168 {
2169 if (hw->flags & SKY2_HW_FIBRE_PHY)
2170 return SPEED_1000;
2171
2172 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2173 if (aux & PHY_M_PS_SPEED_100)
2174 return SPEED_100;
2175 else
2176 return SPEED_10;
2177 }
2178
2179 switch (aux & PHY_M_PS_SPEED_MSK) {
2180 case PHY_M_PS_SPEED_1000:
2181 return SPEED_1000;
2182 case PHY_M_PS_SPEED_100:
2183 return SPEED_100;
2184 default:
2185 return SPEED_10;
2186 }
2187 }
2188
2189 static void sky2_link_up(struct sky2_port *sky2)
2190 {
2191 struct sky2_hw *hw = sky2->hw;
2192 unsigned port = sky2->port;
2193 static const char *fc_name[] = {
2194 [FC_NONE] = "none",
2195 [FC_TX] = "tx",
2196 [FC_RX] = "rx",
2197 [FC_BOTH] = "both",
2198 };
2199
2200 sky2_set_ipg(sky2);
2201
2202 sky2_enable_rx_tx(sky2);
2203
2204 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2205
2206 netif_carrier_on(sky2->netdev);
2207
2208 mod_timer(&hw->watchdog_timer, jiffies + 1);
2209
2210 /* Turn on link LED */
2211 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2212 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2213
2214 netif_info(sky2, link, sky2->netdev,
2215 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2216 sky2->speed,
2217 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2218 fc_name[sky2->flow_status]);
2219 }
2220
2221 static void sky2_link_down(struct sky2_port *sky2)
2222 {
2223 struct sky2_hw *hw = sky2->hw;
2224 unsigned port = sky2->port;
2225 u16 reg;
2226
2227 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2228
2229 reg = gma_read16(hw, port, GM_GP_CTRL);
2230 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2231 gma_write16(hw, port, GM_GP_CTRL, reg);
2232
2233 netif_carrier_off(sky2->netdev);
2234
2235 /* Turn off link LED */
2236 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2237
2238 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2239
2240 sky2_phy_init(hw, port);
2241 }
2242
2243 static enum flow_control sky2_flow(int rx, int tx)
2244 {
2245 if (rx)
2246 return tx ? FC_BOTH : FC_RX;
2247 else
2248 return tx ? FC_TX : FC_NONE;
2249 }
2250
2251 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2252 {
2253 struct sky2_hw *hw = sky2->hw;
2254 unsigned port = sky2->port;
2255 u16 advert, lpa;
2256
2257 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2258 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2259 if (lpa & PHY_M_AN_RF) {
2260 netdev_err(sky2->netdev, "remote fault\n");
2261 return -1;
2262 }
2263
2264 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2265 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2266 return -1;
2267 }
2268
2269 sky2->speed = sky2_phy_speed(hw, aux);
2270 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2271
2272 /* Since the pause result bits seem to in different positions on
2273 * different chips. look at registers.
2274 */
2275 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2276 /* Shift for bits in fiber PHY */
2277 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2278 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2279
2280 if (advert & ADVERTISE_1000XPAUSE)
2281 advert |= ADVERTISE_PAUSE_CAP;
2282 if (advert & ADVERTISE_1000XPSE_ASYM)
2283 advert |= ADVERTISE_PAUSE_ASYM;
2284 if (lpa & LPA_1000XPAUSE)
2285 lpa |= LPA_PAUSE_CAP;
2286 if (lpa & LPA_1000XPAUSE_ASYM)
2287 lpa |= LPA_PAUSE_ASYM;
2288 }
2289
2290 sky2->flow_status = FC_NONE;
2291 if (advert & ADVERTISE_PAUSE_CAP) {
2292 if (lpa & LPA_PAUSE_CAP)
2293 sky2->flow_status = FC_BOTH;
2294 else if (advert & ADVERTISE_PAUSE_ASYM)
2295 sky2->flow_status = FC_RX;
2296 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2297 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2298 sky2->flow_status = FC_TX;
2299 }
2300
2301 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2302 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2303 sky2->flow_status = FC_NONE;
2304
2305 if (sky2->flow_status & FC_TX)
2306 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2307 else
2308 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2309
2310 return 0;
2311 }
2312
2313 /* Interrupt from PHY */
2314 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2315 {
2316 struct net_device *dev = hw->dev[port];
2317 struct sky2_port *sky2 = netdev_priv(dev);
2318 u16 istatus, phystat;
2319
2320 if (!netif_running(dev))
2321 return;
2322
2323 spin_lock(&sky2->phy_lock);
2324 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2325 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2326
2327 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2328 istatus, phystat);
2329
2330 if (istatus & PHY_M_IS_AN_COMPL) {
2331 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2332 !netif_carrier_ok(dev))
2333 sky2_link_up(sky2);
2334 goto out;
2335 }
2336
2337 if (istatus & PHY_M_IS_LSP_CHANGE)
2338 sky2->speed = sky2_phy_speed(hw, phystat);
2339
2340 if (istatus & PHY_M_IS_DUP_CHANGE)
2341 sky2->duplex =
2342 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2343
2344 if (istatus & PHY_M_IS_LST_CHANGE) {
2345 if (phystat & PHY_M_PS_LINK_UP)
2346 sky2_link_up(sky2);
2347 else
2348 sky2_link_down(sky2);
2349 }
2350 out:
2351 spin_unlock(&sky2->phy_lock);
2352 }
2353
2354 /* Special quick link interrupt (Yukon-2 Optima only) */
2355 static void sky2_qlink_intr(struct sky2_hw *hw)
2356 {
2357 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2358 u32 imask;
2359 u16 phy;
2360
2361 /* disable irq */
2362 imask = sky2_read32(hw, B0_IMSK);
2363 imask &= ~Y2_IS_PHY_QLNK;
2364 sky2_write32(hw, B0_IMSK, imask);
2365
2366 /* reset PHY Link Detect */
2367 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2368 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2369 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2370 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2371
2372 sky2_link_up(sky2);
2373 }
2374
2375 /* Transmit timeout is only called if we are running, carrier is up
2376 * and tx queue is full (stopped).
2377 */
2378 static void sky2_tx_timeout(struct net_device *dev)
2379 {
2380 struct sky2_port *sky2 = netdev_priv(dev);
2381 struct sky2_hw *hw = sky2->hw;
2382
2383 netif_err(sky2, timer, dev, "tx timeout\n");
2384
2385 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2386 sky2->tx_cons, sky2->tx_prod,
2387 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2388 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2389
2390 /* can't restart safely under softirq */
2391 schedule_work(&hw->restart_work);
2392 }
2393
2394 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2395 {
2396 struct sky2_port *sky2 = netdev_priv(dev);
2397 struct sky2_hw *hw = sky2->hw;
2398 unsigned port = sky2->port;
2399 int err;
2400 u16 ctl, mode;
2401 u32 imask;
2402
2403 /* MTU size outside the spec */
2404 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2405 return -EINVAL;
2406
2407 /* MTU > 1500 on yukon FE and FE+ not allowed */
2408 if (new_mtu > ETH_DATA_LEN &&
2409 (hw->chip_id == CHIP_ID_YUKON_FE ||
2410 hw->chip_id == CHIP_ID_YUKON_FE_P))
2411 return -EINVAL;
2412
2413 if (!netif_running(dev)) {
2414 dev->mtu = new_mtu;
2415 netdev_update_features(dev);
2416 return 0;
2417 }
2418
2419 imask = sky2_read32(hw, B0_IMSK);
2420 sky2_write32(hw, B0_IMSK, 0);
2421
2422 dev->trans_start = jiffies; /* prevent tx timeout */
2423 napi_disable(&hw->napi);
2424 netif_tx_disable(dev);
2425
2426 synchronize_irq(hw->pdev->irq);
2427
2428 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2429 sky2_set_tx_stfwd(hw, port);
2430
2431 ctl = gma_read16(hw, port, GM_GP_CTRL);
2432 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2433 sky2_rx_stop(sky2);
2434 sky2_rx_clean(sky2);
2435
2436 dev->mtu = new_mtu;
2437 netdev_update_features(dev);
2438
2439 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2440 if (sky2->speed > SPEED_100)
2441 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2442 else
2443 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2444
2445 if (dev->mtu > ETH_DATA_LEN)
2446 mode |= GM_SMOD_JUMBO_ENA;
2447
2448 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2449
2450 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2451
2452 err = sky2_alloc_rx_skbs(sky2);
2453 if (!err)
2454 sky2_rx_start(sky2);
2455 else
2456 sky2_rx_clean(sky2);
2457 sky2_write32(hw, B0_IMSK, imask);
2458
2459 sky2_read32(hw, B0_Y2_SP_LISR);
2460 napi_enable(&hw->napi);
2461
2462 if (err)
2463 dev_close(dev);
2464 else {
2465 gma_write16(hw, port, GM_GP_CTRL, ctl);
2466
2467 netif_wake_queue(dev);
2468 }
2469
2470 return err;
2471 }
2472
2473 static inline bool needs_copy(const struct rx_ring_info *re,
2474 unsigned length)
2475 {
2476 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2477 /* Some architectures need the IP header to be aligned */
2478 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2479 return true;
2480 #endif
2481 return length < copybreak;
2482 }
2483
2484 /* For small just reuse existing skb for next receive */
2485 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2486 const struct rx_ring_info *re,
2487 unsigned length)
2488 {
2489 struct sk_buff *skb;
2490
2491 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2492 if (likely(skb)) {
2493 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2494 length, PCI_DMA_FROMDEVICE);
2495 skb_copy_from_linear_data(re->skb, skb->data, length);
2496 skb->ip_summed = re->skb->ip_summed;
2497 skb->csum = re->skb->csum;
2498 skb->rxhash = re->skb->rxhash;
2499 skb->vlan_proto = re->skb->vlan_proto;
2500 skb->vlan_tci = re->skb->vlan_tci;
2501
2502 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2503 length, PCI_DMA_FROMDEVICE);
2504 re->skb->vlan_proto = 0;
2505 re->skb->vlan_tci = 0;
2506 re->skb->rxhash = 0;
2507 re->skb->ip_summed = CHECKSUM_NONE;
2508 skb_put(skb, length);
2509 }
2510 return skb;
2511 }
2512
2513 /* Adjust length of skb with fragments to match received data */
2514 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2515 unsigned int length)
2516 {
2517 int i, num_frags;
2518 unsigned int size;
2519
2520 /* put header into skb */
2521 size = min(length, hdr_space);
2522 skb->tail += size;
2523 skb->len += size;
2524 length -= size;
2525
2526 num_frags = skb_shinfo(skb)->nr_frags;
2527 for (i = 0; i < num_frags; i++) {
2528 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2529
2530 if (length == 0) {
2531 /* don't need this page */
2532 __skb_frag_unref(frag);
2533 --skb_shinfo(skb)->nr_frags;
2534 } else {
2535 size = min(length, (unsigned) PAGE_SIZE);
2536
2537 skb_frag_size_set(frag, size);
2538 skb->data_len += size;
2539 skb->truesize += PAGE_SIZE;
2540 skb->len += size;
2541 length -= size;
2542 }
2543 }
2544 }
2545
2546 /* Normal packet - take skb from ring element and put in a new one */
2547 static struct sk_buff *receive_new(struct sky2_port *sky2,
2548 struct rx_ring_info *re,
2549 unsigned int length)
2550 {
2551 struct sk_buff *skb;
2552 struct rx_ring_info nre;
2553 unsigned hdr_space = sky2->rx_data_size;
2554
2555 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2556 if (unlikely(!nre.skb))
2557 goto nobuf;
2558
2559 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2560 goto nomap;
2561
2562 skb = re->skb;
2563 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2564 prefetch(skb->data);
2565 *re = nre;
2566
2567 if (skb_shinfo(skb)->nr_frags)
2568 skb_put_frags(skb, hdr_space, length);
2569 else
2570 skb_put(skb, length);
2571 return skb;
2572
2573 nomap:
2574 dev_kfree_skb(nre.skb);
2575 nobuf:
2576 return NULL;
2577 }
2578
2579 /*
2580 * Receive one packet.
2581 * For larger packets, get new buffer.
2582 */
2583 static struct sk_buff *sky2_receive(struct net_device *dev,
2584 u16 length, u32 status)
2585 {
2586 struct sky2_port *sky2 = netdev_priv(dev);
2587 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2588 struct sk_buff *skb = NULL;
2589 u16 count = (status & GMR_FS_LEN) >> 16;
2590
2591 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2592 "rx slot %u status 0x%x len %d\n",
2593 sky2->rx_next, status, length);
2594
2595 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2596 prefetch(sky2->rx_ring + sky2->rx_next);
2597
2598 if (vlan_tx_tag_present(re->skb))
2599 count -= VLAN_HLEN; /* Account for vlan tag */
2600
2601 /* This chip has hardware problems that generates bogus status.
2602 * So do only marginal checking and expect higher level protocols
2603 * to handle crap frames.
2604 */
2605 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2606 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2607 length != count)
2608 goto okay;
2609
2610 if (status & GMR_FS_ANY_ERR)
2611 goto error;
2612
2613 if (!(status & GMR_FS_RX_OK))
2614 goto resubmit;
2615
2616 /* if length reported by DMA does not match PHY, packet was truncated */
2617 if (length != count)
2618 goto error;
2619
2620 okay:
2621 if (needs_copy(re, length))
2622 skb = receive_copy(sky2, re, length);
2623 else
2624 skb = receive_new(sky2, re, length);
2625
2626 dev->stats.rx_dropped += (skb == NULL);
2627
2628 resubmit:
2629 sky2_rx_submit(sky2, re);
2630
2631 return skb;
2632
2633 error:
2634 ++dev->stats.rx_errors;
2635
2636 if (net_ratelimit())
2637 netif_info(sky2, rx_err, dev,
2638 "rx error, status 0x%x length %d\n", status, length);
2639
2640 goto resubmit;
2641 }
2642
2643 /* Transmit complete */
2644 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2645 {
2646 struct sky2_port *sky2 = netdev_priv(dev);
2647
2648 if (netif_running(dev)) {
2649 sky2_tx_complete(sky2, last);
2650
2651 /* Wake unless it's detached, and called e.g. from sky2_close() */
2652 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2653 netif_wake_queue(dev);
2654 }
2655 }
2656
2657 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2658 struct sk_buff *skb)
2659 {
2660 if (skb->ip_summed == CHECKSUM_NONE)
2661 netif_receive_skb(skb);
2662 else
2663 napi_gro_receive(&sky2->hw->napi, skb);
2664 }
2665
2666 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2667 unsigned packets, unsigned bytes)
2668 {
2669 struct net_device *dev = hw->dev[port];
2670 struct sky2_port *sky2 = netdev_priv(dev);
2671
2672 if (packets == 0)
2673 return;
2674
2675 u64_stats_update_begin(&sky2->rx_stats.syncp);
2676 sky2->rx_stats.packets += packets;
2677 sky2->rx_stats.bytes += bytes;
2678 u64_stats_update_end(&sky2->rx_stats.syncp);
2679
2680 dev->last_rx = jiffies;
2681 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2682 }
2683
2684 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2685 {
2686 /* If this happens then driver assuming wrong format for chip type */
2687 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2688
2689 /* Both checksum counters are programmed to start at
2690 * the same offset, so unless there is a problem they
2691 * should match. This failure is an early indication that
2692 * hardware receive checksumming won't work.
2693 */
2694 if (likely((u16)(status >> 16) == (u16)status)) {
2695 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2696 skb->ip_summed = CHECKSUM_COMPLETE;
2697 skb->csum = le16_to_cpu(status);
2698 } else {
2699 dev_notice(&sky2->hw->pdev->dev,
2700 "%s: receive checksum problem (status = %#x)\n",
2701 sky2->netdev->name, status);
2702
2703 /* Disable checksum offload
2704 * It will be reenabled on next ndo_set_features, but if it's
2705 * really broken, will get disabled again
2706 */
2707 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2708 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2709 BMU_DIS_RX_CHKSUM);
2710 }
2711 }
2712
2713 static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2714 {
2715 struct sk_buff *skb;
2716
2717 skb = sky2->rx_ring[sky2->rx_next].skb;
2718 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2719 }
2720
2721 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2722 {
2723 struct sk_buff *skb;
2724
2725 skb = sky2->rx_ring[sky2->rx_next].skb;
2726 skb->rxhash = le32_to_cpu(status);
2727 }
2728
2729 /* Process status response ring */
2730 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2731 {
2732 int work_done = 0;
2733 unsigned int total_bytes[2] = { 0 };
2734 unsigned int total_packets[2] = { 0 };
2735
2736 rmb();
2737 do {
2738 struct sky2_port *sky2;
2739 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2740 unsigned port;
2741 struct net_device *dev;
2742 struct sk_buff *skb;
2743 u32 status;
2744 u16 length;
2745 u8 opcode = le->opcode;
2746
2747 if (!(opcode & HW_OWNER))
2748 break;
2749
2750 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2751
2752 port = le->css & CSS_LINK_BIT;
2753 dev = hw->dev[port];
2754 sky2 = netdev_priv(dev);
2755 length = le16_to_cpu(le->length);
2756 status = le32_to_cpu(le->status);
2757
2758 le->opcode = 0;
2759 switch (opcode & ~HW_OWNER) {
2760 case OP_RXSTAT:
2761 total_packets[port]++;
2762 total_bytes[port] += length;
2763
2764 skb = sky2_receive(dev, length, status);
2765 if (!skb)
2766 break;
2767
2768 /* This chip reports checksum status differently */
2769 if (hw->flags & SKY2_HW_NEW_LE) {
2770 if ((dev->features & NETIF_F_RXCSUM) &&
2771 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2772 (le->css & CSS_TCPUDPCSOK))
2773 skb->ip_summed = CHECKSUM_UNNECESSARY;
2774 else
2775 skb->ip_summed = CHECKSUM_NONE;
2776 }
2777
2778 skb->protocol = eth_type_trans(skb, dev);
2779 sky2_skb_rx(sky2, skb);
2780
2781 /* Stop after net poll weight */
2782 if (++work_done >= to_do)
2783 goto exit_loop;
2784 break;
2785
2786 case OP_RXVLAN:
2787 sky2_rx_tag(sky2, length);
2788 break;
2789
2790 case OP_RXCHKSVLAN:
2791 sky2_rx_tag(sky2, length);
2792 /* fall through */
2793 case OP_RXCHKS:
2794 if (likely(dev->features & NETIF_F_RXCSUM))
2795 sky2_rx_checksum(sky2, status);
2796 break;
2797
2798 case OP_RSS_HASH:
2799 sky2_rx_hash(sky2, status);
2800 break;
2801
2802 case OP_TXINDEXLE:
2803 /* TX index reports status for both ports */
2804 sky2_tx_done(hw->dev[0], status & 0xfff);
2805 if (hw->dev[1])
2806 sky2_tx_done(hw->dev[1],
2807 ((status >> 24) & 0xff)
2808 | (u16)(length & 0xf) << 8);
2809 break;
2810
2811 default:
2812 if (net_ratelimit())
2813 pr_warning("unknown status opcode 0x%x\n", opcode);
2814 }
2815 } while (hw->st_idx != idx);
2816
2817 /* Fully processed status ring so clear irq */
2818 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2819
2820 exit_loop:
2821 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2822 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2823
2824 return work_done;
2825 }
2826
2827 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2828 {
2829 struct net_device *dev = hw->dev[port];
2830
2831 if (net_ratelimit())
2832 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2833
2834 if (status & Y2_IS_PAR_RD1) {
2835 if (net_ratelimit())
2836 netdev_err(dev, "ram data read parity error\n");
2837 /* Clear IRQ */
2838 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2839 }
2840
2841 if (status & Y2_IS_PAR_WR1) {
2842 if (net_ratelimit())
2843 netdev_err(dev, "ram data write parity error\n");
2844
2845 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2846 }
2847
2848 if (status & Y2_IS_PAR_MAC1) {
2849 if (net_ratelimit())
2850 netdev_err(dev, "MAC parity error\n");
2851 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2852 }
2853
2854 if (status & Y2_IS_PAR_RX1) {
2855 if (net_ratelimit())
2856 netdev_err(dev, "RX parity error\n");
2857 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2858 }
2859
2860 if (status & Y2_IS_TCP_TXA1) {
2861 if (net_ratelimit())
2862 netdev_err(dev, "TCP segmentation error\n");
2863 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2864 }
2865 }
2866
2867 static void sky2_hw_intr(struct sky2_hw *hw)
2868 {
2869 struct pci_dev *pdev = hw->pdev;
2870 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2871 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2872
2873 status &= hwmsk;
2874
2875 if (status & Y2_IS_TIST_OV)
2876 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2877
2878 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2879 u16 pci_err;
2880
2881 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2882 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2883 if (net_ratelimit())
2884 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2885 pci_err);
2886
2887 sky2_pci_write16(hw, PCI_STATUS,
2888 pci_err | PCI_STATUS_ERROR_BITS);
2889 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2890 }
2891
2892 if (status & Y2_IS_PCI_EXP) {
2893 /* PCI-Express uncorrectable Error occurred */
2894 u32 err;
2895
2896 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2897 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2898 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2899 0xfffffffful);
2900 if (net_ratelimit())
2901 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2902
2903 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2904 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2905 }
2906
2907 if (status & Y2_HWE_L1_MASK)
2908 sky2_hw_error(hw, 0, status);
2909 status >>= 8;
2910 if (status & Y2_HWE_L1_MASK)
2911 sky2_hw_error(hw, 1, status);
2912 }
2913
2914 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2915 {
2916 struct net_device *dev = hw->dev[port];
2917 struct sky2_port *sky2 = netdev_priv(dev);
2918 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2919
2920 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2921
2922 if (status & GM_IS_RX_CO_OV)
2923 gma_read16(hw, port, GM_RX_IRQ_SRC);
2924
2925 if (status & GM_IS_TX_CO_OV)
2926 gma_read16(hw, port, GM_TX_IRQ_SRC);
2927
2928 if (status & GM_IS_RX_FF_OR) {
2929 ++dev->stats.rx_fifo_errors;
2930 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2931 }
2932
2933 if (status & GM_IS_TX_FF_UR) {
2934 ++dev->stats.tx_fifo_errors;
2935 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2936 }
2937 }
2938
2939 /* This should never happen it is a bug. */
2940 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2941 {
2942 struct net_device *dev = hw->dev[port];
2943 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2944
2945 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2946 dev->name, (unsigned) q, (unsigned) idx,
2947 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2948
2949 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2950 }
2951
2952 static int sky2_rx_hung(struct net_device *dev)
2953 {
2954 struct sky2_port *sky2 = netdev_priv(dev);
2955 struct sky2_hw *hw = sky2->hw;
2956 unsigned port = sky2->port;
2957 unsigned rxq = rxqaddr[port];
2958 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2959 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2960 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2961 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2962
2963 /* If idle and MAC or PCI is stuck */
2964 if (sky2->check.last == dev->last_rx &&
2965 ((mac_rp == sky2->check.mac_rp &&
2966 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2967 /* Check if the PCI RX hang */
2968 (fifo_rp == sky2->check.fifo_rp &&
2969 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2970 netdev_printk(KERN_DEBUG, dev,
2971 "hung mac %d:%d fifo %d (%d:%d)\n",
2972 mac_lev, mac_rp, fifo_lev,
2973 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2974 return 1;
2975 } else {
2976 sky2->check.last = dev->last_rx;
2977 sky2->check.mac_rp = mac_rp;
2978 sky2->check.mac_lev = mac_lev;
2979 sky2->check.fifo_rp = fifo_rp;
2980 sky2->check.fifo_lev = fifo_lev;
2981 return 0;
2982 }
2983 }
2984
2985 static void sky2_watchdog(unsigned long arg)
2986 {
2987 struct sky2_hw *hw = (struct sky2_hw *) arg;
2988
2989 /* Check for lost IRQ once a second */
2990 if (sky2_read32(hw, B0_ISRC)) {
2991 napi_schedule(&hw->napi);
2992 } else {
2993 int i, active = 0;
2994
2995 for (i = 0; i < hw->ports; i++) {
2996 struct net_device *dev = hw->dev[i];
2997 if (!netif_running(dev))
2998 continue;
2999 ++active;
3000
3001 /* For chips with Rx FIFO, check if stuck */
3002 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
3003 sky2_rx_hung(dev)) {
3004 netdev_info(dev, "receiver hang detected\n");
3005 schedule_work(&hw->restart_work);
3006 return;
3007 }
3008 }
3009
3010 if (active == 0)
3011 return;
3012 }
3013
3014 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
3015 }
3016
3017 /* Hardware/software error handling */
3018 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
3019 {
3020 if (net_ratelimit())
3021 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3022
3023 if (status & Y2_IS_HW_ERR)
3024 sky2_hw_intr(hw);
3025
3026 if (status & Y2_IS_IRQ_MAC1)
3027 sky2_mac_intr(hw, 0);
3028
3029 if (status & Y2_IS_IRQ_MAC2)
3030 sky2_mac_intr(hw, 1);
3031
3032 if (status & Y2_IS_CHK_RX1)
3033 sky2_le_error(hw, 0, Q_R1);
3034
3035 if (status & Y2_IS_CHK_RX2)
3036 sky2_le_error(hw, 1, Q_R2);
3037
3038 if (status & Y2_IS_CHK_TXA1)
3039 sky2_le_error(hw, 0, Q_XA1);
3040
3041 if (status & Y2_IS_CHK_TXA2)
3042 sky2_le_error(hw, 1, Q_XA2);
3043 }
3044
3045 static int sky2_poll(struct napi_struct *napi, int work_limit)
3046 {
3047 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3048 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3049 int work_done = 0;
3050 u16 idx;
3051
3052 if (unlikely(status & Y2_IS_ERROR))
3053 sky2_err_intr(hw, status);
3054
3055 if (status & Y2_IS_IRQ_PHY1)
3056 sky2_phy_intr(hw, 0);
3057
3058 if (status & Y2_IS_IRQ_PHY2)
3059 sky2_phy_intr(hw, 1);
3060
3061 if (status & Y2_IS_PHY_QLNK)
3062 sky2_qlink_intr(hw);
3063
3064 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3065 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3066
3067 if (work_done >= work_limit)
3068 goto done;
3069 }
3070
3071 napi_complete(napi);
3072 sky2_read32(hw, B0_Y2_SP_LISR);
3073 done:
3074
3075 return work_done;
3076 }
3077
3078 static irqreturn_t sky2_intr(int irq, void *dev_id)
3079 {
3080 struct sky2_hw *hw = dev_id;
3081 u32 status;
3082
3083 /* Reading this mask interrupts as side effect */
3084 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3085 if (status == 0 || status == ~0) {
3086 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3087 return IRQ_NONE;
3088 }
3089
3090 prefetch(&hw->st_le[hw->st_idx]);
3091
3092 napi_schedule(&hw->napi);
3093
3094 return IRQ_HANDLED;
3095 }
3096
3097 #ifdef CONFIG_NET_POLL_CONTROLLER
3098 static void sky2_netpoll(struct net_device *dev)
3099 {
3100 struct sky2_port *sky2 = netdev_priv(dev);
3101
3102 napi_schedule(&sky2->hw->napi);
3103 }
3104 #endif
3105
3106 /* Chip internal frequency for clock calculations */
3107 static u32 sky2_mhz(const struct sky2_hw *hw)
3108 {
3109 switch (hw->chip_id) {
3110 case CHIP_ID_YUKON_EC:
3111 case CHIP_ID_YUKON_EC_U:
3112 case CHIP_ID_YUKON_EX:
3113 case CHIP_ID_YUKON_SUPR:
3114 case CHIP_ID_YUKON_UL_2:
3115 case CHIP_ID_YUKON_OPT:
3116 case CHIP_ID_YUKON_PRM:
3117 case CHIP_ID_YUKON_OP_2:
3118 return 125;
3119
3120 case CHIP_ID_YUKON_FE:
3121 return 100;
3122
3123 case CHIP_ID_YUKON_FE_P:
3124 return 50;
3125
3126 case CHIP_ID_YUKON_XL:
3127 return 156;
3128
3129 default:
3130 BUG();
3131 }
3132 }
3133
3134 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3135 {
3136 return sky2_mhz(hw) * us;
3137 }
3138
3139 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3140 {
3141 return clk / sky2_mhz(hw);
3142 }
3143
3144
3145 static int sky2_init(struct sky2_hw *hw)
3146 {
3147 u8 t8;
3148
3149 /* Enable all clocks and check for bad PCI access */
3150 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3151
3152 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3153
3154 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3155 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3156
3157 switch (hw->chip_id) {
3158 case CHIP_ID_YUKON_XL:
3159 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3160 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3161 hw->flags |= SKY2_HW_RSS_BROKEN;
3162 break;
3163
3164 case CHIP_ID_YUKON_EC_U:
3165 hw->flags = SKY2_HW_GIGABIT
3166 | SKY2_HW_NEWER_PHY
3167 | SKY2_HW_ADV_POWER_CTL;
3168 break;
3169
3170 case CHIP_ID_YUKON_EX:
3171 hw->flags = SKY2_HW_GIGABIT
3172 | SKY2_HW_NEWER_PHY
3173 | SKY2_HW_NEW_LE
3174 | SKY2_HW_ADV_POWER_CTL
3175 | SKY2_HW_RSS_CHKSUM;
3176
3177 /* New transmit checksum */
3178 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3179 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3180 break;
3181
3182 case CHIP_ID_YUKON_EC:
3183 /* This rev is really old, and requires untested workarounds */
3184 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3185 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3186 return -EOPNOTSUPP;
3187 }
3188 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3189 break;
3190
3191 case CHIP_ID_YUKON_FE:
3192 hw->flags = SKY2_HW_RSS_BROKEN;
3193 break;
3194
3195 case CHIP_ID_YUKON_FE_P:
3196 hw->flags = SKY2_HW_NEWER_PHY
3197 | SKY2_HW_NEW_LE
3198 | SKY2_HW_AUTO_TX_SUM
3199 | SKY2_HW_ADV_POWER_CTL;
3200
3201 /* The workaround for status conflicts VLAN tag detection. */
3202 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3203 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3204 break;
3205
3206 case CHIP_ID_YUKON_SUPR:
3207 hw->flags = SKY2_HW_GIGABIT
3208 | SKY2_HW_NEWER_PHY
3209 | SKY2_HW_NEW_LE
3210 | SKY2_HW_AUTO_TX_SUM
3211 | SKY2_HW_ADV_POWER_CTL;
3212
3213 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3214 hw->flags |= SKY2_HW_RSS_CHKSUM;
3215 break;
3216
3217 case CHIP_ID_YUKON_UL_2:
3218 hw->flags = SKY2_HW_GIGABIT
3219 | SKY2_HW_ADV_POWER_CTL;
3220 break;
3221
3222 case CHIP_ID_YUKON_OPT:
3223 case CHIP_ID_YUKON_PRM:
3224 case CHIP_ID_YUKON_OP_2:
3225 hw->flags = SKY2_HW_GIGABIT
3226 | SKY2_HW_NEW_LE
3227 | SKY2_HW_ADV_POWER_CTL;
3228 break;
3229
3230 default:
3231 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3232 hw->chip_id);
3233 return -EOPNOTSUPP;
3234 }
3235
3236 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3237 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3238 hw->flags |= SKY2_HW_FIBRE_PHY;
3239
3240 hw->ports = 1;
3241 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3242 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3243 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3244 ++hw->ports;
3245 }
3246
3247 if (sky2_read8(hw, B2_E_0))
3248 hw->flags |= SKY2_HW_RAM_BUFFER;
3249
3250 return 0;
3251 }
3252
3253 static void sky2_reset(struct sky2_hw *hw)
3254 {
3255 struct pci_dev *pdev = hw->pdev;
3256 u16 status;
3257 int i;
3258 u32 hwe_mask = Y2_HWE_ALL_MASK;
3259
3260 /* disable ASF */
3261 if (hw->chip_id == CHIP_ID_YUKON_EX
3262 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3263 sky2_write32(hw, CPU_WDOG, 0);
3264 status = sky2_read16(hw, HCU_CCSR);
3265 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3266 HCU_CCSR_UC_STATE_MSK);
3267 /*
3268 * CPU clock divider shouldn't be used because
3269 * - ASF firmware may malfunction
3270 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3271 */
3272 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3273 sky2_write16(hw, HCU_CCSR, status);
3274 sky2_write32(hw, CPU_WDOG, 0);
3275 } else
3276 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3277 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3278
3279 /* do a SW reset */
3280 sky2_write8(hw, B0_CTST, CS_RST_SET);
3281 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3282
3283 /* allow writes to PCI config */
3284 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3285
3286 /* clear PCI errors, if any */
3287 status = sky2_pci_read16(hw, PCI_STATUS);
3288 status |= PCI_STATUS_ERROR_BITS;
3289 sky2_pci_write16(hw, PCI_STATUS, status);
3290
3291 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3292
3293 if (pci_is_pcie(pdev)) {
3294 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3295 0xfffffffful);
3296
3297 /* If error bit is stuck on ignore it */
3298 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3299 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3300 else
3301 hwe_mask |= Y2_IS_PCI_EXP;
3302 }
3303
3304 sky2_power_on(hw);
3305 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3306
3307 for (i = 0; i < hw->ports; i++) {
3308 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3309 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3310
3311 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3312 hw->chip_id == CHIP_ID_YUKON_SUPR)
3313 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3314 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3315 | GMC_BYP_RETR_ON);
3316
3317 }
3318
3319 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3320 /* enable MACSec clock gating */
3321 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3322 }
3323
3324 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3325 hw->chip_id == CHIP_ID_YUKON_PRM ||
3326 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3327 u16 reg;
3328
3329 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3330 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3331 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3332
3333 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3334 reg = 10;
3335
3336 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3337 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3338 } else {
3339 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3340 reg = 3;
3341 }
3342
3343 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3344 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3345
3346 /* reset PHY Link Detect */
3347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3348 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3349
3350 /* check if PSMv2 was running before */
3351 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3352 if (reg & PCI_EXP_LNKCTL_ASPMC)
3353 /* restore the PCIe Link Control register */
3354 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3355 reg);
3356
3357 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3358 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3359 /* change PHY Interrupt polarity to low active */
3360 reg = sky2_read16(hw, GPHY_CTRL);
3361 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3362
3363 /* adapt HW for low active PHY Interrupt */
3364 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3365 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3366 }
3367
3368 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3369
3370 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3371 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3372 }
3373
3374 /* Clear I2C IRQ noise */
3375 sky2_write32(hw, B2_I2C_IRQ, 1);
3376
3377 /* turn off hardware timer (unused) */
3378 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3379 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3380
3381 /* Turn off descriptor polling */
3382 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3383
3384 /* Turn off receive timestamp */
3385 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3386 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3387
3388 /* enable the Tx Arbiters */
3389 for (i = 0; i < hw->ports; i++)
3390 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3391
3392 /* Initialize ram interface */
3393 for (i = 0; i < hw->ports; i++) {
3394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3395
3396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3408 }
3409
3410 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3411
3412 for (i = 0; i < hw->ports; i++)
3413 sky2_gmac_reset(hw, i);
3414
3415 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3416 hw->st_idx = 0;
3417
3418 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3419 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3420
3421 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3422 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3423
3424 /* Set the list last index */
3425 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3426
3427 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3428 sky2_write8(hw, STAT_FIFO_WM, 16);
3429
3430 /* set Status-FIFO ISR watermark */
3431 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3432 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3433 else
3434 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3435
3436 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3437 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3438 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3439
3440 /* enable status unit */
3441 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3442
3443 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3444 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3445 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3446 }
3447
3448 /* Take device down (offline).
3449 * Equivalent to doing dev_stop() but this does not
3450 * inform upper layers of the transition.
3451 */
3452 static void sky2_detach(struct net_device *dev)
3453 {
3454 if (netif_running(dev)) {
3455 netif_tx_lock(dev);
3456 netif_device_detach(dev); /* stop txq */
3457 netif_tx_unlock(dev);
3458 sky2_close(dev);
3459 }
3460 }
3461
3462 /* Bring device back after doing sky2_detach */
3463 static int sky2_reattach(struct net_device *dev)
3464 {
3465 int err = 0;
3466
3467 if (netif_running(dev)) {
3468 err = sky2_open(dev);
3469 if (err) {
3470 netdev_info(dev, "could not restart %d\n", err);
3471 dev_close(dev);
3472 } else {
3473 netif_device_attach(dev);
3474 sky2_set_multicast(dev);
3475 }
3476 }
3477
3478 return err;
3479 }
3480
3481 static void sky2_all_down(struct sky2_hw *hw)
3482 {
3483 int i;
3484
3485 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3486 sky2_read32(hw, B0_IMSK);
3487 sky2_write32(hw, B0_IMSK, 0);
3488
3489 synchronize_irq(hw->pdev->irq);
3490 napi_disable(&hw->napi);
3491 }
3492
3493 for (i = 0; i < hw->ports; i++) {
3494 struct net_device *dev = hw->dev[i];
3495 struct sky2_port *sky2 = netdev_priv(dev);
3496
3497 if (!netif_running(dev))
3498 continue;
3499
3500 netif_carrier_off(dev);
3501 netif_tx_disable(dev);
3502 sky2_hw_down(sky2);
3503 }
3504 }
3505
3506 static void sky2_all_up(struct sky2_hw *hw)
3507 {
3508 u32 imask = Y2_IS_BASE;
3509 int i;
3510
3511 for (i = 0; i < hw->ports; i++) {
3512 struct net_device *dev = hw->dev[i];
3513 struct sky2_port *sky2 = netdev_priv(dev);
3514
3515 if (!netif_running(dev))
3516 continue;
3517
3518 sky2_hw_up(sky2);
3519 sky2_set_multicast(dev);
3520 imask |= portirq_msk[i];
3521 netif_wake_queue(dev);
3522 }
3523
3524 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3525 sky2_write32(hw, B0_IMSK, imask);
3526 sky2_read32(hw, B0_IMSK);
3527 sky2_read32(hw, B0_Y2_SP_LISR);
3528 napi_enable(&hw->napi);
3529 }
3530 }
3531
3532 static void sky2_restart(struct work_struct *work)
3533 {
3534 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3535
3536 rtnl_lock();
3537
3538 sky2_all_down(hw);
3539 sky2_reset(hw);
3540 sky2_all_up(hw);
3541
3542 rtnl_unlock();
3543 }
3544
3545 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3546 {
3547 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3548 }
3549
3550 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3551 {
3552 const struct sky2_port *sky2 = netdev_priv(dev);
3553
3554 wol->supported = sky2_wol_supported(sky2->hw);
3555 wol->wolopts = sky2->wol;
3556 }
3557
3558 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3559 {
3560 struct sky2_port *sky2 = netdev_priv(dev);
3561 struct sky2_hw *hw = sky2->hw;
3562 bool enable_wakeup = false;
3563 int i;
3564
3565 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3566 !device_can_wakeup(&hw->pdev->dev))
3567 return -EOPNOTSUPP;
3568
3569 sky2->wol = wol->wolopts;
3570
3571 for (i = 0; i < hw->ports; i++) {
3572 struct net_device *dev = hw->dev[i];
3573 struct sky2_port *sky2 = netdev_priv(dev);
3574
3575 if (sky2->wol)
3576 enable_wakeup = true;
3577 }
3578 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3579
3580 return 0;
3581 }
3582
3583 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3584 {
3585 if (sky2_is_copper(hw)) {
3586 u32 modes = SUPPORTED_10baseT_Half
3587 | SUPPORTED_10baseT_Full
3588 | SUPPORTED_100baseT_Half
3589 | SUPPORTED_100baseT_Full;
3590
3591 if (hw->flags & SKY2_HW_GIGABIT)
3592 modes |= SUPPORTED_1000baseT_Half
3593 | SUPPORTED_1000baseT_Full;
3594 return modes;
3595 } else
3596 return SUPPORTED_1000baseT_Half
3597 | SUPPORTED_1000baseT_Full;
3598 }
3599
3600 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3601 {
3602 struct sky2_port *sky2 = netdev_priv(dev);
3603 struct sky2_hw *hw = sky2->hw;
3604
3605 ecmd->transceiver = XCVR_INTERNAL;
3606 ecmd->supported = sky2_supported_modes(hw);
3607 ecmd->phy_address = PHY_ADDR_MARV;
3608 if (sky2_is_copper(hw)) {
3609 ecmd->port = PORT_TP;
3610 ethtool_cmd_speed_set(ecmd, sky2->speed);
3611 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3612 } else {
3613 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3614 ecmd->port = PORT_FIBRE;
3615 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3616 }
3617
3618 ecmd->advertising = sky2->advertising;
3619 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3620 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3621 ecmd->duplex = sky2->duplex;
3622 return 0;
3623 }
3624
3625 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3626 {
3627 struct sky2_port *sky2 = netdev_priv(dev);
3628 const struct sky2_hw *hw = sky2->hw;
3629 u32 supported = sky2_supported_modes(hw);
3630
3631 if (ecmd->autoneg == AUTONEG_ENABLE) {
3632 if (ecmd->advertising & ~supported)
3633 return -EINVAL;
3634
3635 if (sky2_is_copper(hw))
3636 sky2->advertising = ecmd->advertising |
3637 ADVERTISED_TP |
3638 ADVERTISED_Autoneg;
3639 else
3640 sky2->advertising = ecmd->advertising |
3641 ADVERTISED_FIBRE |
3642 ADVERTISED_Autoneg;
3643
3644 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3645 sky2->duplex = -1;
3646 sky2->speed = -1;
3647 } else {
3648 u32 setting;
3649 u32 speed = ethtool_cmd_speed(ecmd);
3650
3651 switch (speed) {
3652 case SPEED_1000:
3653 if (ecmd->duplex == DUPLEX_FULL)
3654 setting = SUPPORTED_1000baseT_Full;
3655 else if (ecmd->duplex == DUPLEX_HALF)
3656 setting = SUPPORTED_1000baseT_Half;
3657 else
3658 return -EINVAL;
3659 break;
3660 case SPEED_100:
3661 if (ecmd->duplex == DUPLEX_FULL)
3662 setting = SUPPORTED_100baseT_Full;
3663 else if (ecmd->duplex == DUPLEX_HALF)
3664 setting = SUPPORTED_100baseT_Half;
3665 else
3666 return -EINVAL;
3667 break;
3668
3669 case SPEED_10:
3670 if (ecmd->duplex == DUPLEX_FULL)
3671 setting = SUPPORTED_10baseT_Full;
3672 else if (ecmd->duplex == DUPLEX_HALF)
3673 setting = SUPPORTED_10baseT_Half;
3674 else
3675 return -EINVAL;
3676 break;
3677 default:
3678 return -EINVAL;
3679 }
3680
3681 if ((setting & supported) == 0)
3682 return -EINVAL;
3683
3684 sky2->speed = speed;
3685 sky2->duplex = ecmd->duplex;
3686 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3687 }
3688
3689 if (netif_running(dev)) {
3690 sky2_phy_reinit(sky2);
3691 sky2_set_multicast(dev);
3692 }
3693
3694 return 0;
3695 }
3696
3697 static void sky2_get_drvinfo(struct net_device *dev,
3698 struct ethtool_drvinfo *info)
3699 {
3700 struct sky2_port *sky2 = netdev_priv(dev);
3701
3702 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3703 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3704 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3705 sizeof(info->bus_info));
3706 }
3707
3708 static const struct sky2_stat {
3709 char name[ETH_GSTRING_LEN];
3710 u16 offset;
3711 } sky2_stats[] = {
3712 { "tx_bytes", GM_TXO_OK_HI },
3713 { "rx_bytes", GM_RXO_OK_HI },
3714 { "tx_broadcast", GM_TXF_BC_OK },
3715 { "rx_broadcast", GM_RXF_BC_OK },
3716 { "tx_multicast", GM_TXF_MC_OK },
3717 { "rx_multicast", GM_RXF_MC_OK },
3718 { "tx_unicast", GM_TXF_UC_OK },
3719 { "rx_unicast", GM_RXF_UC_OK },
3720 { "tx_mac_pause", GM_TXF_MPAUSE },
3721 { "rx_mac_pause", GM_RXF_MPAUSE },
3722 { "collisions", GM_TXF_COL },
3723 { "late_collision",GM_TXF_LAT_COL },
3724 { "aborted", GM_TXF_ABO_COL },
3725 { "single_collisions", GM_TXF_SNG_COL },
3726 { "multi_collisions", GM_TXF_MUL_COL },
3727
3728 { "rx_short", GM_RXF_SHT },
3729 { "rx_runt", GM_RXE_FRAG },
3730 { "rx_64_byte_packets", GM_RXF_64B },
3731 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3732 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3733 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3734 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3735 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3736 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3737 { "rx_too_long", GM_RXF_LNG_ERR },
3738 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3739 { "rx_jabber", GM_RXF_JAB_PKT },
3740 { "rx_fcs_error", GM_RXF_FCS_ERR },
3741
3742 { "tx_64_byte_packets", GM_TXF_64B },
3743 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3744 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3745 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3746 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3747 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3748 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3749 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3750 };
3751
3752 static u32 sky2_get_msglevel(struct net_device *netdev)
3753 {
3754 struct sky2_port *sky2 = netdev_priv(netdev);
3755 return sky2->msg_enable;
3756 }
3757
3758 static int sky2_nway_reset(struct net_device *dev)
3759 {
3760 struct sky2_port *sky2 = netdev_priv(dev);
3761
3762 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3763 return -EINVAL;
3764
3765 sky2_phy_reinit(sky2);
3766 sky2_set_multicast(dev);
3767
3768 return 0;
3769 }
3770
3771 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3772 {
3773 struct sky2_hw *hw = sky2->hw;
3774 unsigned port = sky2->port;
3775 int i;
3776
3777 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3778 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3779
3780 for (i = 2; i < count; i++)
3781 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3782 }
3783
3784 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3785 {
3786 struct sky2_port *sky2 = netdev_priv(netdev);
3787 sky2->msg_enable = value;
3788 }
3789
3790 static int sky2_get_sset_count(struct net_device *dev, int sset)
3791 {
3792 switch (sset) {
3793 case ETH_SS_STATS:
3794 return ARRAY_SIZE(sky2_stats);
3795 default:
3796 return -EOPNOTSUPP;
3797 }
3798 }
3799
3800 static void sky2_get_ethtool_stats(struct net_device *dev,
3801 struct ethtool_stats *stats, u64 * data)
3802 {
3803 struct sky2_port *sky2 = netdev_priv(dev);
3804
3805 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3806 }
3807
3808 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3809 {
3810 int i;
3811
3812 switch (stringset) {
3813 case ETH_SS_STATS:
3814 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3815 memcpy(data + i * ETH_GSTRING_LEN,
3816 sky2_stats[i].name, ETH_GSTRING_LEN);
3817 break;
3818 }
3819 }
3820
3821 static int sky2_set_mac_address(struct net_device *dev, void *p)
3822 {
3823 struct sky2_port *sky2 = netdev_priv(dev);
3824 struct sky2_hw *hw = sky2->hw;
3825 unsigned port = sky2->port;
3826 const struct sockaddr *addr = p;
3827
3828 if (!is_valid_ether_addr(addr->sa_data))
3829 return -EADDRNOTAVAIL;
3830
3831 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3832 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3833 dev->dev_addr, ETH_ALEN);
3834 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3835 dev->dev_addr, ETH_ALEN);
3836
3837 /* virtual address for data */
3838 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3839
3840 /* physical address: used for pause frames */
3841 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3842
3843 return 0;
3844 }
3845
3846 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3847 {
3848 u32 bit;
3849
3850 bit = ether_crc(ETH_ALEN, addr) & 63;
3851 filter[bit >> 3] |= 1 << (bit & 7);
3852 }
3853
3854 static void sky2_set_multicast(struct net_device *dev)
3855 {
3856 struct sky2_port *sky2 = netdev_priv(dev);
3857 struct sky2_hw *hw = sky2->hw;
3858 unsigned port = sky2->port;
3859 struct netdev_hw_addr *ha;
3860 u16 reg;
3861 u8 filter[8];
3862 int rx_pause;
3863 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3864
3865 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3866 memset(filter, 0, sizeof(filter));
3867
3868 reg = gma_read16(hw, port, GM_RX_CTRL);
3869 reg |= GM_RXCR_UCF_ENA;
3870
3871 if (dev->flags & IFF_PROMISC) /* promiscuous */
3872 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3873 else if (dev->flags & IFF_ALLMULTI)
3874 memset(filter, 0xff, sizeof(filter));
3875 else if (netdev_mc_empty(dev) && !rx_pause)
3876 reg &= ~GM_RXCR_MCF_ENA;
3877 else {
3878 reg |= GM_RXCR_MCF_ENA;
3879
3880 if (rx_pause)
3881 sky2_add_filter(filter, pause_mc_addr);
3882
3883 netdev_for_each_mc_addr(ha, dev)
3884 sky2_add_filter(filter, ha->addr);
3885 }
3886
3887 gma_write16(hw, port, GM_MC_ADDR_H1,
3888 (u16) filter[0] | ((u16) filter[1] << 8));
3889 gma_write16(hw, port, GM_MC_ADDR_H2,
3890 (u16) filter[2] | ((u16) filter[3] << 8));
3891 gma_write16(hw, port, GM_MC_ADDR_H3,
3892 (u16) filter[4] | ((u16) filter[5] << 8));
3893 gma_write16(hw, port, GM_MC_ADDR_H4,
3894 (u16) filter[6] | ((u16) filter[7] << 8));
3895
3896 gma_write16(hw, port, GM_RX_CTRL, reg);
3897 }
3898
3899 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3900 struct rtnl_link_stats64 *stats)
3901 {
3902 struct sky2_port *sky2 = netdev_priv(dev);
3903 struct sky2_hw *hw = sky2->hw;
3904 unsigned port = sky2->port;
3905 unsigned int start;
3906 u64 _bytes, _packets;
3907
3908 do {
3909 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3910 _bytes = sky2->rx_stats.bytes;
3911 _packets = sky2->rx_stats.packets;
3912 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3913
3914 stats->rx_packets = _packets;
3915 stats->rx_bytes = _bytes;
3916
3917 do {
3918 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3919 _bytes = sky2->tx_stats.bytes;
3920 _packets = sky2->tx_stats.packets;
3921 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3922
3923 stats->tx_packets = _packets;
3924 stats->tx_bytes = _bytes;
3925
3926 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3927 + get_stats32(hw, port, GM_RXF_BC_OK);
3928
3929 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3930
3931 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3932 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3933 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3934 + get_stats32(hw, port, GM_RXE_FRAG);
3935 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3936
3937 stats->rx_dropped = dev->stats.rx_dropped;
3938 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3939 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3940
3941 return stats;
3942 }
3943
3944 /* Can have one global because blinking is controlled by
3945 * ethtool and that is always under RTNL mutex
3946 */
3947 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3948 {
3949 struct sky2_hw *hw = sky2->hw;
3950 unsigned port = sky2->port;
3951
3952 spin_lock_bh(&sky2->phy_lock);
3953 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3954 hw->chip_id == CHIP_ID_YUKON_EX ||
3955 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3956 u16 pg;
3957 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3958 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3959
3960 switch (mode) {
3961 case MO_LED_OFF:
3962 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3963 PHY_M_LEDC_LOS_CTRL(8) |
3964 PHY_M_LEDC_INIT_CTRL(8) |
3965 PHY_M_LEDC_STA1_CTRL(8) |
3966 PHY_M_LEDC_STA0_CTRL(8));
3967 break;
3968 case MO_LED_ON:
3969 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3970 PHY_M_LEDC_LOS_CTRL(9) |
3971 PHY_M_LEDC_INIT_CTRL(9) |
3972 PHY_M_LEDC_STA1_CTRL(9) |
3973 PHY_M_LEDC_STA0_CTRL(9));
3974 break;
3975 case MO_LED_BLINK:
3976 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3977 PHY_M_LEDC_LOS_CTRL(0xa) |
3978 PHY_M_LEDC_INIT_CTRL(0xa) |
3979 PHY_M_LEDC_STA1_CTRL(0xa) |
3980 PHY_M_LEDC_STA0_CTRL(0xa));
3981 break;
3982 case MO_LED_NORM:
3983 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3984 PHY_M_LEDC_LOS_CTRL(1) |
3985 PHY_M_LEDC_INIT_CTRL(8) |
3986 PHY_M_LEDC_STA1_CTRL(7) |
3987 PHY_M_LEDC_STA0_CTRL(7));
3988 }
3989
3990 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3991 } else
3992 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3993 PHY_M_LED_MO_DUP(mode) |
3994 PHY_M_LED_MO_10(mode) |
3995 PHY_M_LED_MO_100(mode) |
3996 PHY_M_LED_MO_1000(mode) |
3997 PHY_M_LED_MO_RX(mode) |
3998 PHY_M_LED_MO_TX(mode));
3999
4000 spin_unlock_bh(&sky2->phy_lock);
4001 }
4002
4003 /* blink LED's for finding board */
4004 static int sky2_set_phys_id(struct net_device *dev,
4005 enum ethtool_phys_id_state state)
4006 {
4007 struct sky2_port *sky2 = netdev_priv(dev);
4008
4009 switch (state) {
4010 case ETHTOOL_ID_ACTIVE:
4011 return 1; /* cycle on/off once per second */
4012 case ETHTOOL_ID_INACTIVE:
4013 sky2_led(sky2, MO_LED_NORM);
4014 break;
4015 case ETHTOOL_ID_ON:
4016 sky2_led(sky2, MO_LED_ON);
4017 break;
4018 case ETHTOOL_ID_OFF:
4019 sky2_led(sky2, MO_LED_OFF);
4020 break;
4021 }
4022
4023 return 0;
4024 }
4025
4026 static void sky2_get_pauseparam(struct net_device *dev,
4027 struct ethtool_pauseparam *ecmd)
4028 {
4029 struct sky2_port *sky2 = netdev_priv(dev);
4030
4031 switch (sky2->flow_mode) {
4032 case FC_NONE:
4033 ecmd->tx_pause = ecmd->rx_pause = 0;
4034 break;
4035 case FC_TX:
4036 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4037 break;
4038 case FC_RX:
4039 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4040 break;
4041 case FC_BOTH:
4042 ecmd->tx_pause = ecmd->rx_pause = 1;
4043 }
4044
4045 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4046 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4047 }
4048
4049 static int sky2_set_pauseparam(struct net_device *dev,
4050 struct ethtool_pauseparam *ecmd)
4051 {
4052 struct sky2_port *sky2 = netdev_priv(dev);
4053
4054 if (ecmd->autoneg == AUTONEG_ENABLE)
4055 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4056 else
4057 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4058
4059 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4060
4061 if (netif_running(dev))
4062 sky2_phy_reinit(sky2);
4063
4064 return 0;
4065 }
4066
4067 static int sky2_get_coalesce(struct net_device *dev,
4068 struct ethtool_coalesce *ecmd)
4069 {
4070 struct sky2_port *sky2 = netdev_priv(dev);
4071 struct sky2_hw *hw = sky2->hw;
4072
4073 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4074 ecmd->tx_coalesce_usecs = 0;
4075 else {
4076 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4077 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4078 }
4079 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4080
4081 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4082 ecmd->rx_coalesce_usecs = 0;
4083 else {
4084 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4085 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4086 }
4087 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4088
4089 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4090 ecmd->rx_coalesce_usecs_irq = 0;
4091 else {
4092 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4093 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4094 }
4095
4096 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4097
4098 return 0;
4099 }
4100
4101 /* Note: this affect both ports */
4102 static int sky2_set_coalesce(struct net_device *dev,
4103 struct ethtool_coalesce *ecmd)
4104 {
4105 struct sky2_port *sky2 = netdev_priv(dev);
4106 struct sky2_hw *hw = sky2->hw;
4107 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4108
4109 if (ecmd->tx_coalesce_usecs > tmax ||
4110 ecmd->rx_coalesce_usecs > tmax ||
4111 ecmd->rx_coalesce_usecs_irq > tmax)
4112 return -EINVAL;
4113
4114 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4115 return -EINVAL;
4116 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4117 return -EINVAL;
4118 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4119 return -EINVAL;
4120
4121 if (ecmd->tx_coalesce_usecs == 0)
4122 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4123 else {
4124 sky2_write32(hw, STAT_TX_TIMER_INI,
4125 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4126 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4127 }
4128 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4129
4130 if (ecmd->rx_coalesce_usecs == 0)
4131 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4132 else {
4133 sky2_write32(hw, STAT_LEV_TIMER_INI,
4134 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4135 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4136 }
4137 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4138
4139 if (ecmd->rx_coalesce_usecs_irq == 0)
4140 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4141 else {
4142 sky2_write32(hw, STAT_ISR_TIMER_INI,
4143 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4144 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4145 }
4146 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4147 return 0;
4148 }
4149
4150 /*
4151 * Hardware is limited to min of 128 and max of 2048 for ring size
4152 * and rounded up to next power of two
4153 * to avoid division in modulus calclation
4154 */
4155 static unsigned long roundup_ring_size(unsigned long pending)
4156 {
4157 return max(128ul, roundup_pow_of_two(pending+1));
4158 }
4159
4160 static void sky2_get_ringparam(struct net_device *dev,
4161 struct ethtool_ringparam *ering)
4162 {
4163 struct sky2_port *sky2 = netdev_priv(dev);
4164
4165 ering->rx_max_pending = RX_MAX_PENDING;
4166 ering->tx_max_pending = TX_MAX_PENDING;
4167
4168 ering->rx_pending = sky2->rx_pending;
4169 ering->tx_pending = sky2->tx_pending;
4170 }
4171
4172 static int sky2_set_ringparam(struct net_device *dev,
4173 struct ethtool_ringparam *ering)
4174 {
4175 struct sky2_port *sky2 = netdev_priv(dev);
4176
4177 if (ering->rx_pending > RX_MAX_PENDING ||
4178 ering->rx_pending < 8 ||
4179 ering->tx_pending < TX_MIN_PENDING ||
4180 ering->tx_pending > TX_MAX_PENDING)
4181 return -EINVAL;
4182
4183 sky2_detach(dev);
4184
4185 sky2->rx_pending = ering->rx_pending;
4186 sky2->tx_pending = ering->tx_pending;
4187 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4188
4189 return sky2_reattach(dev);
4190 }
4191
4192 static int sky2_get_regs_len(struct net_device *dev)
4193 {
4194 return 0x4000;
4195 }
4196
4197 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4198 {
4199 /* This complicated switch statement is to make sure and
4200 * only access regions that are unreserved.
4201 * Some blocks are only valid on dual port cards.
4202 */
4203 switch (b) {
4204 /* second port */
4205 case 5: /* Tx Arbiter 2 */
4206 case 9: /* RX2 */
4207 case 14 ... 15: /* TX2 */
4208 case 17: case 19: /* Ram Buffer 2 */
4209 case 22 ... 23: /* Tx Ram Buffer 2 */
4210 case 25: /* Rx MAC Fifo 1 */
4211 case 27: /* Tx MAC Fifo 2 */
4212 case 31: /* GPHY 2 */
4213 case 40 ... 47: /* Pattern Ram 2 */
4214 case 52: case 54: /* TCP Segmentation 2 */
4215 case 112 ... 116: /* GMAC 2 */
4216 return hw->ports > 1;
4217
4218 case 0: /* Control */
4219 case 2: /* Mac address */
4220 case 4: /* Tx Arbiter 1 */
4221 case 7: /* PCI express reg */
4222 case 8: /* RX1 */
4223 case 12 ... 13: /* TX1 */
4224 case 16: case 18:/* Rx Ram Buffer 1 */
4225 case 20 ... 21: /* Tx Ram Buffer 1 */
4226 case 24: /* Rx MAC Fifo 1 */
4227 case 26: /* Tx MAC Fifo 1 */
4228 case 28 ... 29: /* Descriptor and status unit */
4229 case 30: /* GPHY 1*/
4230 case 32 ... 39: /* Pattern Ram 1 */
4231 case 48: case 50: /* TCP Segmentation 1 */
4232 case 56 ... 60: /* PCI space */
4233 case 80 ... 84: /* GMAC 1 */
4234 return 1;
4235
4236 default:
4237 return 0;
4238 }
4239 }
4240
4241 /*
4242 * Returns copy of control register region
4243 * Note: ethtool_get_regs always provides full size (16k) buffer
4244 */
4245 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4246 void *p)
4247 {
4248 const struct sky2_port *sky2 = netdev_priv(dev);
4249 const void __iomem *io = sky2->hw->regs;
4250 unsigned int b;
4251
4252 regs->version = 1;
4253
4254 for (b = 0; b < 128; b++) {
4255 /* skip poisonous diagnostic ram region in block 3 */
4256 if (b == 3)
4257 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4258 else if (sky2_reg_access_ok(sky2->hw, b))
4259 memcpy_fromio(p, io, 128);
4260 else
4261 memset(p, 0, 128);
4262
4263 p += 128;
4264 io += 128;
4265 }
4266 }
4267
4268 static int sky2_get_eeprom_len(struct net_device *dev)
4269 {
4270 struct sky2_port *sky2 = netdev_priv(dev);
4271 struct sky2_hw *hw = sky2->hw;
4272 u16 reg2;
4273
4274 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4275 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4276 }
4277
4278 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4279 {
4280 unsigned long start = jiffies;
4281
4282 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4283 /* Can take up to 10.6 ms for write */
4284 if (time_after(jiffies, start + HZ/4)) {
4285 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4286 return -ETIMEDOUT;
4287 }
4288 mdelay(1);
4289 }
4290
4291 return 0;
4292 }
4293
4294 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4295 u16 offset, size_t length)
4296 {
4297 int rc = 0;
4298
4299 while (length > 0) {
4300 u32 val;
4301
4302 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4303 rc = sky2_vpd_wait(hw, cap, 0);
4304 if (rc)
4305 break;
4306
4307 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4308
4309 memcpy(data, &val, min(sizeof(val), length));
4310 offset += sizeof(u32);
4311 data += sizeof(u32);
4312 length -= sizeof(u32);
4313 }
4314
4315 return rc;
4316 }
4317
4318 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4319 u16 offset, unsigned int length)
4320 {
4321 unsigned int i;
4322 int rc = 0;
4323
4324 for (i = 0; i < length; i += sizeof(u32)) {
4325 u32 val = *(u32 *)(data + i);
4326
4327 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4328 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4329
4330 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4331 if (rc)
4332 break;
4333 }
4334 return rc;
4335 }
4336
4337 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4338 u8 *data)
4339 {
4340 struct sky2_port *sky2 = netdev_priv(dev);
4341 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4342
4343 if (!cap)
4344 return -EINVAL;
4345
4346 eeprom->magic = SKY2_EEPROM_MAGIC;
4347
4348 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4349 }
4350
4351 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4352 u8 *data)
4353 {
4354 struct sky2_port *sky2 = netdev_priv(dev);
4355 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4356
4357 if (!cap)
4358 return -EINVAL;
4359
4360 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4361 return -EINVAL;
4362
4363 /* Partial writes not supported */
4364 if ((eeprom->offset & 3) || (eeprom->len & 3))
4365 return -EINVAL;
4366
4367 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4368 }
4369
4370 static netdev_features_t sky2_fix_features(struct net_device *dev,
4371 netdev_features_t features)
4372 {
4373 const struct sky2_port *sky2 = netdev_priv(dev);
4374 const struct sky2_hw *hw = sky2->hw;
4375
4376 /* In order to do Jumbo packets on these chips, need to turn off the
4377 * transmit store/forward. Therefore checksum offload won't work.
4378 */
4379 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4380 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4381 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4382 }
4383
4384 /* Some hardware requires receive checksum for RSS to work. */
4385 if ( (features & NETIF_F_RXHASH) &&
4386 !(features & NETIF_F_RXCSUM) &&
4387 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4388 netdev_info(dev, "receive hashing forces receive checksum\n");
4389 features |= NETIF_F_RXCSUM;
4390 }
4391
4392 return features;
4393 }
4394
4395 static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4396 {
4397 struct sky2_port *sky2 = netdev_priv(dev);
4398 netdev_features_t changed = dev->features ^ features;
4399
4400 if ((changed & NETIF_F_RXCSUM) &&
4401 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4402 sky2_write32(sky2->hw,
4403 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4404 (features & NETIF_F_RXCSUM)
4405 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4406 }
4407
4408 if (changed & NETIF_F_RXHASH)
4409 rx_set_rss(dev, features);
4410
4411 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4412 sky2_vlan_mode(dev, features);
4413
4414 return 0;
4415 }
4416
4417 static const struct ethtool_ops sky2_ethtool_ops = {
4418 .get_settings = sky2_get_settings,
4419 .set_settings = sky2_set_settings,
4420 .get_drvinfo = sky2_get_drvinfo,
4421 .get_wol = sky2_get_wol,
4422 .set_wol = sky2_set_wol,
4423 .get_msglevel = sky2_get_msglevel,
4424 .set_msglevel = sky2_set_msglevel,
4425 .nway_reset = sky2_nway_reset,
4426 .get_regs_len = sky2_get_regs_len,
4427 .get_regs = sky2_get_regs,
4428 .get_link = ethtool_op_get_link,
4429 .get_eeprom_len = sky2_get_eeprom_len,
4430 .get_eeprom = sky2_get_eeprom,
4431 .set_eeprom = sky2_set_eeprom,
4432 .get_strings = sky2_get_strings,
4433 .get_coalesce = sky2_get_coalesce,
4434 .set_coalesce = sky2_set_coalesce,
4435 .get_ringparam = sky2_get_ringparam,
4436 .set_ringparam = sky2_set_ringparam,
4437 .get_pauseparam = sky2_get_pauseparam,
4438 .set_pauseparam = sky2_set_pauseparam,
4439 .set_phys_id = sky2_set_phys_id,
4440 .get_sset_count = sky2_get_sset_count,
4441 .get_ethtool_stats = sky2_get_ethtool_stats,
4442 };
4443
4444 #ifdef CONFIG_SKY2_DEBUG
4445
4446 static struct dentry *sky2_debug;
4447
4448
4449 /*
4450 * Read and parse the first part of Vital Product Data
4451 */
4452 #define VPD_SIZE 128
4453 #define VPD_MAGIC 0x82
4454
4455 static const struct vpd_tag {
4456 char tag[2];
4457 char *label;
4458 } vpd_tags[] = {
4459 { "PN", "Part Number" },
4460 { "EC", "Engineering Level" },
4461 { "MN", "Manufacturer" },
4462 { "SN", "Serial Number" },
4463 { "YA", "Asset Tag" },
4464 { "VL", "First Error Log Message" },
4465 { "VF", "Second Error Log Message" },
4466 { "VB", "Boot Agent ROM Configuration" },
4467 { "VE", "EFI UNDI Configuration" },
4468 };
4469
4470 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4471 {
4472 size_t vpd_size;
4473 loff_t offs;
4474 u8 len;
4475 unsigned char *buf;
4476 u16 reg2;
4477
4478 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4479 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4480
4481 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4482 buf = kmalloc(vpd_size, GFP_KERNEL);
4483 if (!buf) {
4484 seq_puts(seq, "no memory!\n");
4485 return;
4486 }
4487
4488 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4489 seq_puts(seq, "VPD read failed\n");
4490 goto out;
4491 }
4492
4493 if (buf[0] != VPD_MAGIC) {
4494 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4495 goto out;
4496 }
4497 len = buf[1];
4498 if (len == 0 || len > vpd_size - 4) {
4499 seq_printf(seq, "Invalid id length: %d\n", len);
4500 goto out;
4501 }
4502
4503 seq_printf(seq, "%.*s\n", len, buf + 3);
4504 offs = len + 3;
4505
4506 while (offs < vpd_size - 4) {
4507 int i;
4508
4509 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4510 break;
4511 len = buf[offs + 2];
4512 if (offs + len + 3 >= vpd_size)
4513 break;
4514
4515 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4516 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4517 seq_printf(seq, " %s: %.*s\n",
4518 vpd_tags[i].label, len, buf + offs + 3);
4519 break;
4520 }
4521 }
4522 offs += len + 3;
4523 }
4524 out:
4525 kfree(buf);
4526 }
4527
4528 static int sky2_debug_show(struct seq_file *seq, void *v)
4529 {
4530 struct net_device *dev = seq->private;
4531 const struct sky2_port *sky2 = netdev_priv(dev);
4532 struct sky2_hw *hw = sky2->hw;
4533 unsigned port = sky2->port;
4534 unsigned idx, last;
4535 int sop;
4536
4537 sky2_show_vpd(seq, hw);
4538
4539 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4540 sky2_read32(hw, B0_ISRC),
4541 sky2_read32(hw, B0_IMSK),
4542 sky2_read32(hw, B0_Y2_SP_ICR));
4543
4544 if (!netif_running(dev)) {
4545 seq_printf(seq, "network not running\n");
4546 return 0;
4547 }
4548
4549 napi_disable(&hw->napi);
4550 last = sky2_read16(hw, STAT_PUT_IDX);
4551
4552 seq_printf(seq, "Status ring %u\n", hw->st_size);
4553 if (hw->st_idx == last)
4554 seq_puts(seq, "Status ring (empty)\n");
4555 else {
4556 seq_puts(seq, "Status ring\n");
4557 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4558 idx = RING_NEXT(idx, hw->st_size)) {
4559 const struct sky2_status_le *le = hw->st_le + idx;
4560 seq_printf(seq, "[%d] %#x %d %#x\n",
4561 idx, le->opcode, le->length, le->status);
4562 }
4563 seq_puts(seq, "\n");
4564 }
4565
4566 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4567 sky2->tx_cons, sky2->tx_prod,
4568 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4569 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4570
4571 /* Dump contents of tx ring */
4572 sop = 1;
4573 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4574 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4575 const struct sky2_tx_le *le = sky2->tx_le + idx;
4576 u32 a = le32_to_cpu(le->addr);
4577
4578 if (sop)
4579 seq_printf(seq, "%u:", idx);
4580 sop = 0;
4581
4582 switch (le->opcode & ~HW_OWNER) {
4583 case OP_ADDR64:
4584 seq_printf(seq, " %#x:", a);
4585 break;
4586 case OP_LRGLEN:
4587 seq_printf(seq, " mtu=%d", a);
4588 break;
4589 case OP_VLAN:
4590 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4591 break;
4592 case OP_TCPLISW:
4593 seq_printf(seq, " csum=%#x", a);
4594 break;
4595 case OP_LARGESEND:
4596 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4597 break;
4598 case OP_PACKET:
4599 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4600 break;
4601 case OP_BUFFER:
4602 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4603 break;
4604 default:
4605 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4606 a, le16_to_cpu(le->length));
4607 }
4608
4609 if (le->ctrl & EOP) {
4610 seq_putc(seq, '\n');
4611 sop = 1;
4612 }
4613 }
4614
4615 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4616 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4617 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4618 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4619
4620 sky2_read32(hw, B0_Y2_SP_LISR);
4621 napi_enable(&hw->napi);
4622 return 0;
4623 }
4624
4625 static int sky2_debug_open(struct inode *inode, struct file *file)
4626 {
4627 return single_open(file, sky2_debug_show, inode->i_private);
4628 }
4629
4630 static const struct file_operations sky2_debug_fops = {
4631 .owner = THIS_MODULE,
4632 .open = sky2_debug_open,
4633 .read = seq_read,
4634 .llseek = seq_lseek,
4635 .release = single_release,
4636 };
4637
4638 /*
4639 * Use network device events to create/remove/rename
4640 * debugfs file entries
4641 */
4642 static int sky2_device_event(struct notifier_block *unused,
4643 unsigned long event, void *ptr)
4644 {
4645 struct net_device *dev = ptr;
4646 struct sky2_port *sky2 = netdev_priv(dev);
4647
4648 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4649 return NOTIFY_DONE;
4650
4651 switch (event) {
4652 case NETDEV_CHANGENAME:
4653 if (sky2->debugfs) {
4654 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4655 sky2_debug, dev->name);
4656 }
4657 break;
4658
4659 case NETDEV_GOING_DOWN:
4660 if (sky2->debugfs) {
4661 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4662 debugfs_remove(sky2->debugfs);
4663 sky2->debugfs = NULL;
4664 }
4665 break;
4666
4667 case NETDEV_UP:
4668 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4669 sky2_debug, dev,
4670 &sky2_debug_fops);
4671 if (IS_ERR(sky2->debugfs))
4672 sky2->debugfs = NULL;
4673 }
4674
4675 return NOTIFY_DONE;
4676 }
4677
4678 static struct notifier_block sky2_notifier = {
4679 .notifier_call = sky2_device_event,
4680 };
4681
4682
4683 static __init void sky2_debug_init(void)
4684 {
4685 struct dentry *ent;
4686
4687 ent = debugfs_create_dir("sky2", NULL);
4688 if (!ent || IS_ERR(ent))
4689 return;
4690
4691 sky2_debug = ent;
4692 register_netdevice_notifier(&sky2_notifier);
4693 }
4694
4695 static __exit void sky2_debug_cleanup(void)
4696 {
4697 if (sky2_debug) {
4698 unregister_netdevice_notifier(&sky2_notifier);
4699 debugfs_remove(sky2_debug);
4700 sky2_debug = NULL;
4701 }
4702 }
4703
4704 #else
4705 #define sky2_debug_init()
4706 #define sky2_debug_cleanup()
4707 #endif
4708
4709 /* Two copies of network device operations to handle special case of
4710 not allowing netpoll on second port */
4711 static const struct net_device_ops sky2_netdev_ops[2] = {
4712 {
4713 .ndo_open = sky2_open,
4714 .ndo_stop = sky2_close,
4715 .ndo_start_xmit = sky2_xmit_frame,
4716 .ndo_do_ioctl = sky2_ioctl,
4717 .ndo_validate_addr = eth_validate_addr,
4718 .ndo_set_mac_address = sky2_set_mac_address,
4719 .ndo_set_rx_mode = sky2_set_multicast,
4720 .ndo_change_mtu = sky2_change_mtu,
4721 .ndo_fix_features = sky2_fix_features,
4722 .ndo_set_features = sky2_set_features,
4723 .ndo_tx_timeout = sky2_tx_timeout,
4724 .ndo_get_stats64 = sky2_get_stats,
4725 #ifdef CONFIG_NET_POLL_CONTROLLER
4726 .ndo_poll_controller = sky2_netpoll,
4727 #endif
4728 },
4729 {
4730 .ndo_open = sky2_open,
4731 .ndo_stop = sky2_close,
4732 .ndo_start_xmit = sky2_xmit_frame,
4733 .ndo_do_ioctl = sky2_ioctl,
4734 .ndo_validate_addr = eth_validate_addr,
4735 .ndo_set_mac_address = sky2_set_mac_address,
4736 .ndo_set_rx_mode = sky2_set_multicast,
4737 .ndo_change_mtu = sky2_change_mtu,
4738 .ndo_fix_features = sky2_fix_features,
4739 .ndo_set_features = sky2_set_features,
4740 .ndo_tx_timeout = sky2_tx_timeout,
4741 .ndo_get_stats64 = sky2_get_stats,
4742 },
4743 };
4744
4745 /* Initialize network device */
4746 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4747 int highmem, int wol)
4748 {
4749 struct sky2_port *sky2;
4750 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4751
4752 if (!dev)
4753 return NULL;
4754
4755 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4756 dev->irq = hw->pdev->irq;
4757 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4758 dev->watchdog_timeo = TX_WATCHDOG;
4759 dev->netdev_ops = &sky2_netdev_ops[port];
4760
4761 sky2 = netdev_priv(dev);
4762 sky2->netdev = dev;
4763 sky2->hw = hw;
4764 sky2->msg_enable = netif_msg_init(debug, default_msg);
4765
4766 /* Auto speed and flow control */
4767 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4768 if (hw->chip_id != CHIP_ID_YUKON_XL)
4769 dev->hw_features |= NETIF_F_RXCSUM;
4770
4771 sky2->flow_mode = FC_BOTH;
4772
4773 sky2->duplex = -1;
4774 sky2->speed = -1;
4775 sky2->advertising = sky2_supported_modes(hw);
4776 sky2->wol = wol;
4777
4778 spin_lock_init(&sky2->phy_lock);
4779
4780 sky2->tx_pending = TX_DEF_PENDING;
4781 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4782 sky2->rx_pending = RX_DEF_PENDING;
4783
4784 hw->dev[port] = dev;
4785
4786 sky2->port = port;
4787
4788 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4789
4790 if (highmem)
4791 dev->features |= NETIF_F_HIGHDMA;
4792
4793 /* Enable receive hashing unless hardware is known broken */
4794 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4795 dev->hw_features |= NETIF_F_RXHASH;
4796
4797 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4798 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4799 NETIF_F_HW_VLAN_CTAG_RX;
4800 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4801 }
4802
4803 dev->features |= dev->hw_features;
4804
4805 /* read the mac address */
4806 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4807
4808 return dev;
4809 }
4810
4811 static void sky2_show_addr(struct net_device *dev)
4812 {
4813 const struct sky2_port *sky2 = netdev_priv(dev);
4814
4815 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4816 }
4817
4818 /* Handle software interrupt used during MSI test */
4819 static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4820 {
4821 struct sky2_hw *hw = dev_id;
4822 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4823
4824 if (status == 0)
4825 return IRQ_NONE;
4826
4827 if (status & Y2_IS_IRQ_SW) {
4828 hw->flags |= SKY2_HW_USE_MSI;
4829 wake_up(&hw->msi_wait);
4830 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4831 }
4832 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4833
4834 return IRQ_HANDLED;
4835 }
4836
4837 /* Test interrupt path by forcing a a software IRQ */
4838 static int sky2_test_msi(struct sky2_hw *hw)
4839 {
4840 struct pci_dev *pdev = hw->pdev;
4841 int err;
4842
4843 init_waitqueue_head(&hw->msi_wait);
4844
4845 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4846 if (err) {
4847 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4848 return err;
4849 }
4850
4851 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4852
4853 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4854 sky2_read8(hw, B0_CTST);
4855
4856 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4857
4858 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4859 /* MSI test failed, go back to INTx mode */
4860 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4861 "switching to INTx mode.\n");
4862
4863 err = -EOPNOTSUPP;
4864 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4865 }
4866
4867 sky2_write32(hw, B0_IMSK, 0);
4868 sky2_read32(hw, B0_IMSK);
4869
4870 free_irq(pdev->irq, hw);
4871
4872 return err;
4873 }
4874
4875 /* This driver supports yukon2 chipset only */
4876 static const char *sky2_name(u8 chipid, char *buf, int sz)
4877 {
4878 const char *name[] = {
4879 "XL", /* 0xb3 */
4880 "EC Ultra", /* 0xb4 */
4881 "Extreme", /* 0xb5 */
4882 "EC", /* 0xb6 */
4883 "FE", /* 0xb7 */
4884 "FE+", /* 0xb8 */
4885 "Supreme", /* 0xb9 */
4886 "UL 2", /* 0xba */
4887 "Unknown", /* 0xbb */
4888 "Optima", /* 0xbc */
4889 "OptimaEEE", /* 0xbd */
4890 "Optima 2", /* 0xbe */
4891 };
4892
4893 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4894 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4895 else
4896 snprintf(buf, sz, "(chip %#x)", chipid);
4897 return buf;
4898 }
4899
4900 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4901 {
4902 struct net_device *dev, *dev1;
4903 struct sky2_hw *hw;
4904 int err, using_dac = 0, wol_default;
4905 u32 reg;
4906 char buf1[16];
4907
4908 err = pci_enable_device(pdev);
4909 if (err) {
4910 dev_err(&pdev->dev, "cannot enable PCI device\n");
4911 goto err_out;
4912 }
4913
4914 /* Get configuration information
4915 * Note: only regular PCI config access once to test for HW issues
4916 * other PCI access through shared memory for speed and to
4917 * avoid MMCONFIG problems.
4918 */
4919 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4920 if (err) {
4921 dev_err(&pdev->dev, "PCI read config failed\n");
4922 goto err_out_disable;
4923 }
4924
4925 if (~reg == 0) {
4926 dev_err(&pdev->dev, "PCI configuration read error\n");
4927 err = -EIO;
4928 goto err_out_disable;
4929 }
4930
4931 err = pci_request_regions(pdev, DRV_NAME);
4932 if (err) {
4933 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4934 goto err_out_disable;
4935 }
4936
4937 pci_set_master(pdev);
4938
4939 if (sizeof(dma_addr_t) > sizeof(u32) &&
4940 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4941 using_dac = 1;
4942 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4943 if (err < 0) {
4944 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4945 "for consistent allocations\n");
4946 goto err_out_free_regions;
4947 }
4948 } else {
4949 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4950 if (err) {
4951 dev_err(&pdev->dev, "no usable DMA configuration\n");
4952 goto err_out_free_regions;
4953 }
4954 }
4955
4956
4957 #ifdef __BIG_ENDIAN
4958 /* The sk98lin vendor driver uses hardware byte swapping but
4959 * this driver uses software swapping.
4960 */
4961 reg &= ~PCI_REV_DESC;
4962 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4963 if (err) {
4964 dev_err(&pdev->dev, "PCI write config failed\n");
4965 goto err_out_free_regions;
4966 }
4967 #endif
4968
4969 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4970
4971 err = -ENOMEM;
4972
4973 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4974 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4975 if (!hw)
4976 goto err_out_free_regions;
4977
4978 hw->pdev = pdev;
4979 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4980
4981 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4982 if (!hw->regs) {
4983 dev_err(&pdev->dev, "cannot map device registers\n");
4984 goto err_out_free_hw;
4985 }
4986
4987 err = sky2_init(hw);
4988 if (err)
4989 goto err_out_iounmap;
4990
4991 /* ring for status responses */
4992 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4993 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4994 &hw->st_dma);
4995 if (!hw->st_le) {
4996 err = -ENOMEM;
4997 goto err_out_reset;
4998 }
4999
5000 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
5001 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
5002
5003 sky2_reset(hw);
5004
5005 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
5006 if (!dev) {
5007 err = -ENOMEM;
5008 goto err_out_free_pci;
5009 }
5010
5011 if (!disable_msi && pci_enable_msi(pdev) == 0) {
5012 err = sky2_test_msi(hw);
5013 if (err) {
5014 pci_disable_msi(pdev);
5015 if (err != -EOPNOTSUPP)
5016 goto err_out_free_netdev;
5017 }
5018 }
5019
5020 err = register_netdev(dev);
5021 if (err) {
5022 dev_err(&pdev->dev, "cannot register net device\n");
5023 goto err_out_free_netdev;
5024 }
5025
5026 netif_carrier_off(dev);
5027
5028 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5029
5030 sky2_show_addr(dev);
5031
5032 if (hw->ports > 1) {
5033 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5034 if (!dev1) {
5035 err = -ENOMEM;
5036 goto err_out_unregister;
5037 }
5038
5039 err = register_netdev(dev1);
5040 if (err) {
5041 dev_err(&pdev->dev, "cannot register second net device\n");
5042 goto err_out_free_dev1;
5043 }
5044
5045 err = sky2_setup_irq(hw, hw->irq_name);
5046 if (err)
5047 goto err_out_unregister_dev1;
5048
5049 sky2_show_addr(dev1);
5050 }
5051
5052 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
5053 INIT_WORK(&hw->restart_work, sky2_restart);
5054
5055 pci_set_drvdata(pdev, hw);
5056 pdev->d3_delay = 150;
5057
5058 return 0;
5059
5060 err_out_unregister_dev1:
5061 unregister_netdev(dev1);
5062 err_out_free_dev1:
5063 free_netdev(dev1);
5064 err_out_unregister:
5065 unregister_netdev(dev);
5066 err_out_free_netdev:
5067 if (hw->flags & SKY2_HW_USE_MSI)
5068 pci_disable_msi(pdev);
5069 free_netdev(dev);
5070 err_out_free_pci:
5071 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5072 hw->st_le, hw->st_dma);
5073 err_out_reset:
5074 sky2_write8(hw, B0_CTST, CS_RST_SET);
5075 err_out_iounmap:
5076 iounmap(hw->regs);
5077 err_out_free_hw:
5078 kfree(hw);
5079 err_out_free_regions:
5080 pci_release_regions(pdev);
5081 err_out_disable:
5082 pci_disable_device(pdev);
5083 err_out:
5084 pci_set_drvdata(pdev, NULL);
5085 return err;
5086 }
5087
5088 static void sky2_remove(struct pci_dev *pdev)
5089 {
5090 struct sky2_hw *hw = pci_get_drvdata(pdev);
5091 int i;
5092
5093 if (!hw)
5094 return;
5095
5096 del_timer_sync(&hw->watchdog_timer);
5097 cancel_work_sync(&hw->restart_work);
5098
5099 for (i = hw->ports-1; i >= 0; --i)
5100 unregister_netdev(hw->dev[i]);
5101
5102 sky2_write32(hw, B0_IMSK, 0);
5103 sky2_read32(hw, B0_IMSK);
5104
5105 sky2_power_aux(hw);
5106
5107 sky2_write8(hw, B0_CTST, CS_RST_SET);
5108 sky2_read8(hw, B0_CTST);
5109
5110 if (hw->ports > 1) {
5111 napi_disable(&hw->napi);
5112 free_irq(pdev->irq, hw);
5113 }
5114
5115 if (hw->flags & SKY2_HW_USE_MSI)
5116 pci_disable_msi(pdev);
5117 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5118 hw->st_le, hw->st_dma);
5119 pci_release_regions(pdev);
5120 pci_disable_device(pdev);
5121
5122 for (i = hw->ports-1; i >= 0; --i)
5123 free_netdev(hw->dev[i]);
5124
5125 iounmap(hw->regs);
5126 kfree(hw);
5127
5128 pci_set_drvdata(pdev, NULL);
5129 }
5130
5131 static int sky2_suspend(struct device *dev)
5132 {
5133 struct pci_dev *pdev = to_pci_dev(dev);
5134 struct sky2_hw *hw = pci_get_drvdata(pdev);
5135 int i;
5136
5137 if (!hw)
5138 return 0;
5139
5140 del_timer_sync(&hw->watchdog_timer);
5141 cancel_work_sync(&hw->restart_work);
5142
5143 rtnl_lock();
5144
5145 sky2_all_down(hw);
5146 for (i = 0; i < hw->ports; i++) {
5147 struct net_device *dev = hw->dev[i];
5148 struct sky2_port *sky2 = netdev_priv(dev);
5149
5150 if (sky2->wol)
5151 sky2_wol_init(sky2);
5152 }
5153
5154 sky2_power_aux(hw);
5155 rtnl_unlock();
5156
5157 return 0;
5158 }
5159
5160 #ifdef CONFIG_PM_SLEEP
5161 static int sky2_resume(struct device *dev)
5162 {
5163 struct pci_dev *pdev = to_pci_dev(dev);
5164 struct sky2_hw *hw = pci_get_drvdata(pdev);
5165 int err;
5166
5167 if (!hw)
5168 return 0;
5169
5170 /* Re-enable all clocks */
5171 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5172 if (err) {
5173 dev_err(&pdev->dev, "PCI write config failed\n");
5174 goto out;
5175 }
5176
5177 rtnl_lock();
5178 sky2_reset(hw);
5179 sky2_all_up(hw);
5180 rtnl_unlock();
5181
5182 return 0;
5183 out:
5184
5185 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5186 pci_disable_device(pdev);
5187 return err;
5188 }
5189
5190 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5191 #define SKY2_PM_OPS (&sky2_pm_ops)
5192
5193 #else
5194
5195 #define SKY2_PM_OPS NULL
5196 #endif
5197
5198 static void sky2_shutdown(struct pci_dev *pdev)
5199 {
5200 sky2_suspend(&pdev->dev);
5201 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5202 pci_set_power_state(pdev, PCI_D3hot);
5203 }
5204
5205 static struct pci_driver sky2_driver = {
5206 .name = DRV_NAME,
5207 .id_table = sky2_id_table,
5208 .probe = sky2_probe,
5209 .remove = sky2_remove,
5210 .shutdown = sky2_shutdown,
5211 .driver.pm = SKY2_PM_OPS,
5212 };
5213
5214 static int __init sky2_init_module(void)
5215 {
5216 pr_info("driver version " DRV_VERSION "\n");
5217
5218 sky2_debug_init();
5219 return pci_register_driver(&sky2_driver);
5220 }
5221
5222 static void __exit sky2_cleanup_module(void)
5223 {
5224 pci_unregister_driver(&sky2_driver);
5225 sky2_debug_cleanup();
5226 }
5227
5228 module_init(sky2_init_module);
5229 module_exit(sky2_cleanup_module);
5230
5231 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5232 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5233 MODULE_LICENSE("GPL");
5234 MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)