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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.11.33-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 /* required last entry */
116 {0, }
117 };
118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
120 #ifdef CONFIG_IXGBE_DCA
121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
122 void *p);
123 static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127 };
128 #endif
129
130 #ifdef CONFIG_PCI_IOV
131 static unsigned int max_vfs;
132 module_param(max_vfs, uint, 0);
133 MODULE_PARM_DESC(max_vfs,
134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
135 #endif /* CONFIG_PCI_IOV */
136
137 static unsigned int allow_unsupported_sfp;
138 module_param(allow_unsupported_sfp, uint, 0);
139 MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143 static int debug = -1;
144 module_param(debug, int, 0);
145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149 MODULE_LICENSE("GPL");
150 MODULE_VERSION(DRV_VERSION);
151
152 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
153 {
154 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
155 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
156 schedule_work(&adapter->service_task);
157 }
158
159 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
160 {
161 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
162
163 /* flush memory to make sure state is correct before next watchdog */
164 smp_mb__before_clear_bit();
165 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
166 }
167
168 struct ixgbe_reg_info {
169 u32 ofs;
170 char *name;
171 };
172
173 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
174
175 /* General Registers */
176 {IXGBE_CTRL, "CTRL"},
177 {IXGBE_STATUS, "STATUS"},
178 {IXGBE_CTRL_EXT, "CTRL_EXT"},
179
180 /* Interrupt Registers */
181 {IXGBE_EICR, "EICR"},
182
183 /* RX Registers */
184 {IXGBE_SRRCTL(0), "SRRCTL"},
185 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
186 {IXGBE_RDLEN(0), "RDLEN"},
187 {IXGBE_RDH(0), "RDH"},
188 {IXGBE_RDT(0), "RDT"},
189 {IXGBE_RXDCTL(0), "RXDCTL"},
190 {IXGBE_RDBAL(0), "RDBAL"},
191 {IXGBE_RDBAH(0), "RDBAH"},
192
193 /* TX Registers */
194 {IXGBE_TDBAL(0), "TDBAL"},
195 {IXGBE_TDBAH(0), "TDBAH"},
196 {IXGBE_TDLEN(0), "TDLEN"},
197 {IXGBE_TDH(0), "TDH"},
198 {IXGBE_TDT(0), "TDT"},
199 {IXGBE_TXDCTL(0), "TXDCTL"},
200
201 /* List Terminator */
202 {}
203 };
204
205
206 /*
207 * ixgbe_regdump - register printout routine
208 */
209 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
210 {
211 int i = 0, j = 0;
212 char rname[16];
213 u32 regs[64];
214
215 switch (reginfo->ofs) {
216 case IXGBE_SRRCTL(0):
217 for (i = 0; i < 64; i++)
218 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
219 break;
220 case IXGBE_DCA_RXCTRL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
223 break;
224 case IXGBE_RDLEN(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
227 break;
228 case IXGBE_RDH(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
231 break;
232 case IXGBE_RDT(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
235 break;
236 case IXGBE_RXDCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
239 break;
240 case IXGBE_RDBAL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
243 break;
244 case IXGBE_RDBAH(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
247 break;
248 case IXGBE_TDBAL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
251 break;
252 case IXGBE_TDBAH(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
255 break;
256 case IXGBE_TDLEN(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
259 break;
260 case IXGBE_TDH(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
263 break;
264 case IXGBE_TDT(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
267 break;
268 case IXGBE_TXDCTL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
271 break;
272 default:
273 pr_info("%-15s %08x\n", reginfo->name,
274 IXGBE_READ_REG(hw, reginfo->ofs));
275 return;
276 }
277
278 for (i = 0; i < 8; i++) {
279 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
280 pr_err("%-15s", rname);
281 for (j = 0; j < 8; j++)
282 pr_cont(" %08x", regs[i*8+j]);
283 pr_cont("\n");
284 }
285
286 }
287
288 /*
289 * ixgbe_dump - Print registers, tx-rings and rx-rings
290 */
291 static void ixgbe_dump(struct ixgbe_adapter *adapter)
292 {
293 struct net_device *netdev = adapter->netdev;
294 struct ixgbe_hw *hw = &adapter->hw;
295 struct ixgbe_reg_info *reginfo;
296 int n = 0;
297 struct ixgbe_ring *tx_ring;
298 struct ixgbe_tx_buffer *tx_buffer;
299 union ixgbe_adv_tx_desc *tx_desc;
300 struct my_u0 { u64 a; u64 b; } *u0;
301 struct ixgbe_ring *rx_ring;
302 union ixgbe_adv_rx_desc *rx_desc;
303 struct ixgbe_rx_buffer *rx_buffer_info;
304 u32 staterr;
305 int i = 0;
306
307 if (!netif_msg_hw(adapter))
308 return;
309
310 /* Print netdevice Info */
311 if (netdev) {
312 dev_info(&adapter->pdev->dev, "Net device Info\n");
313 pr_info("Device Name state "
314 "trans_start last_rx\n");
315 pr_info("%-15s %016lX %016lX %016lX\n",
316 netdev->name,
317 netdev->state,
318 netdev->trans_start,
319 netdev->last_rx);
320 }
321
322 /* Print Registers */
323 dev_info(&adapter->pdev->dev, "Register Dump\n");
324 pr_info(" Register Name Value\n");
325 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
326 reginfo->name; reginfo++) {
327 ixgbe_regdump(hw, reginfo);
328 }
329
330 /* Print TX Ring Summary */
331 if (!netdev || !netif_running(netdev))
332 goto exit;
333
334 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
335 pr_info(" %s %s %s %s\n",
336 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
337 "leng", "ntw", "timestamp");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * 82598 Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 *
365 * 82598 Advanced Transmit Descriptor (Write-Back Format)
366 * +--------------------------------------------------------------+
367 * 0 | RSV [63:0] |
368 * +--------------------------------------------------------------+
369 * 8 | RSV | STA | NXTSEQ |
370 * +--------------------------------------------------------------+
371 * 63 36 35 32 31 0
372 *
373 * 82599+ Advanced Transmit Descriptor
374 * +--------------------------------------------------------------+
375 * 0 | Buffer Address [63:0] |
376 * +--------------------------------------------------------------+
377 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
378 * +--------------------------------------------------------------+
379 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
380 *
381 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
382 * +--------------------------------------------------------------+
383 * 0 | RSV [63:0] |
384 * +--------------------------------------------------------------+
385 * 8 | RSV | STA | RSV |
386 * +--------------------------------------------------------------+
387 * 63 36 35 32 31 0
388 */
389
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 tx_ring = adapter->tx_ring[n];
392 pr_info("------------------------------------\n");
393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
394 pr_info("------------------------------------\n");
395 pr_info("%s%s %s %s %s %s\n",
396 "T [desc] [address 63:0 ] ",
397 "[PlPOIdStDDt Ln] [bi->dma ] ",
398 "leng", "ntw", "timestamp", "bi->skb");
399
400 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
401 tx_desc = IXGBE_TX_DESC(tx_ring, i);
402 tx_buffer = &tx_ring->tx_buffer_info[i];
403 u0 = (struct my_u0 *)tx_desc;
404 if (dma_unmap_len(tx_buffer, len) > 0) {
405 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
406 i,
407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
409 (u64)dma_unmap_addr(tx_buffer, dma),
410 dma_unmap_len(tx_buffer, len),
411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
416 pr_cont(" NTC/U\n");
417 else if (i == tx_ring->next_to_use)
418 pr_cont(" NTU\n");
419 else if (i == tx_ring->next_to_clean)
420 pr_cont(" NTC\n");
421 else
422 pr_cont("\n");
423
424 if (netif_msg_pktdata(adapter) &&
425 tx_buffer->skb)
426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
428 tx_buffer->skb->data,
429 dma_unmap_len(tx_buffer, len),
430 true);
431 }
432 }
433 }
434
435 /* Print RX Rings Summary */
436 rx_ring_summary:
437 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
438 pr_info("Queue [NTU] [NTC]\n");
439 for (n = 0; n < adapter->num_rx_queues; n++) {
440 rx_ring = adapter->rx_ring[n];
441 pr_info("%5d %5X %5X\n",
442 n, rx_ring->next_to_use, rx_ring->next_to_clean);
443 }
444
445 /* Print RX Rings */
446 if (!netif_msg_rx_status(adapter))
447 goto exit;
448
449 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
450
451 /* Receive Descriptor Formats
452 *
453 * 82598 Advanced Receive Descriptor (Read) Format
454 * 63 1 0
455 * +-----------------------------------------------------+
456 * 0 | Packet Buffer Address [63:1] |A0/NSE|
457 * +----------------------------------------------+------+
458 * 8 | Header Buffer Address [63:1] | DD |
459 * +-----------------------------------------------------+
460 *
461 *
462 * 82598 Advanced Receive Descriptor (Write-Back) Format
463 *
464 * 63 48 47 32 31 30 21 20 16 15 4 3 0
465 * +------------------------------------------------------+
466 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
467 * | Packet | IP | | | | Type | Type |
468 * | Checksum | Ident | | | | | |
469 * +------------------------------------------------------+
470 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
471 * +------------------------------------------------------+
472 * 63 48 47 32 31 20 19 0
473 *
474 * 82599+ Advanced Receive Descriptor (Read) Format
475 * 63 1 0
476 * +-----------------------------------------------------+
477 * 0 | Packet Buffer Address [63:1] |A0/NSE|
478 * +----------------------------------------------+------+
479 * 8 | Header Buffer Address [63:1] | DD |
480 * +-----------------------------------------------------+
481 *
482 *
483 * 82599+ Advanced Receive Descriptor (Write-Back) Format
484 *
485 * 63 48 47 32 31 30 21 20 17 16 4 3 0
486 * +------------------------------------------------------+
487 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
488 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
489 * |/ Flow Dir Flt ID | | | | | |
490 * +------------------------------------------------------+
491 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
492 * +------------------------------------------------------+
493 * 63 48 47 32 31 20 19 0
494 */
495
496 for (n = 0; n < adapter->num_rx_queues; n++) {
497 rx_ring = adapter->rx_ring[n];
498 pr_info("------------------------------------\n");
499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
500 pr_info("------------------------------------\n");
501 pr_info("%s%s%s",
502 "R [desc] [ PktBuf A0] ",
503 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
504 "<-- Adv Rx Read format\n");
505 pr_info("%s%s%s",
506 "RWB[desc] [PcsmIpSHl PtRs] ",
507 "[vl er S cks ln] ---------------- [bi->skb ] ",
508 "<-- Adv Rx Write-Back format\n");
509
510 for (i = 0; i < rx_ring->count; i++) {
511 rx_buffer_info = &rx_ring->rx_buffer_info[i];
512 rx_desc = IXGBE_RX_DESC(rx_ring, i);
513 u0 = (struct my_u0 *)rx_desc;
514 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
515 if (staterr & IXGBE_RXD_STAT_DD) {
516 /* Descriptor Done */
517 pr_info("RWB[0x%03X] %016llX "
518 "%016llX ---------------- %p", i,
519 le64_to_cpu(u0->a),
520 le64_to_cpu(u0->b),
521 rx_buffer_info->skb);
522 } else {
523 pr_info("R [0x%03X] %016llX "
524 "%016llX %016llX %p", i,
525 le64_to_cpu(u0->a),
526 le64_to_cpu(u0->b),
527 (u64)rx_buffer_info->dma,
528 rx_buffer_info->skb);
529
530 if (netif_msg_pktdata(adapter) &&
531 rx_buffer_info->dma) {
532 print_hex_dump(KERN_INFO, "",
533 DUMP_PREFIX_ADDRESS, 16, 1,
534 page_address(rx_buffer_info->page) +
535 rx_buffer_info->page_offset,
536 ixgbe_rx_bufsz(rx_ring), true);
537 }
538 }
539
540 if (i == rx_ring->next_to_use)
541 pr_cont(" NTU\n");
542 else if (i == rx_ring->next_to_clean)
543 pr_cont(" NTC\n");
544 else
545 pr_cont("\n");
546
547 }
548 }
549
550 exit:
551 return;
552 }
553
554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555 {
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
562 }
563
564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565 {
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
572 }
573
574 /**
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
583 u8 queue, u8 msix_vector)
584 {
585 u32 ivar, index;
586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
599 case ixgbe_mac_X540:
600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
622 }
623
624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
625 u64 qmask)
626 {
627 u32 mask;
628
629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
633 break;
634 case ixgbe_mac_82599EB:
635 case ixgbe_mac_X540:
636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
640 break;
641 default:
642 break;
643 }
644 }
645
646 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
648 {
649 if (tx_buffer->skb) {
650 dev_kfree_skb_any(tx_buffer->skb);
651 if (dma_unmap_len(tx_buffer, len))
652 dma_unmap_single(ring->dev,
653 dma_unmap_addr(tx_buffer, dma),
654 dma_unmap_len(tx_buffer, len),
655 DMA_TO_DEVICE);
656 } else if (dma_unmap_len(tx_buffer, len)) {
657 dma_unmap_page(ring->dev,
658 dma_unmap_addr(tx_buffer, dma),
659 dma_unmap_len(tx_buffer, len),
660 DMA_TO_DEVICE);
661 }
662 tx_buffer->next_to_watch = NULL;
663 tx_buffer->skb = NULL;
664 dma_unmap_len_set(tx_buffer, len, 0);
665 /* tx_buffer must be completely set up in the transmit path */
666 }
667
668 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
669 {
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 int i;
673 u32 data;
674
675 if ((hw->fc.current_mode != ixgbe_fc_full) &&
676 (hw->fc.current_mode != ixgbe_fc_rx_pause))
677 return;
678
679 switch (hw->mac.type) {
680 case ixgbe_mac_82598EB:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
682 break;
683 default:
684 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
685 }
686 hwstats->lxoffrxc += data;
687
688 /* refill credits (no tx hang) if we received xoff */
689 if (!data)
690 return;
691
692 for (i = 0; i < adapter->num_tx_queues; i++)
693 clear_bit(__IXGBE_HANG_CHECK_ARMED,
694 &adapter->tx_ring[i]->state);
695 }
696
697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698 {
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 xoff[8] = {0};
702 u8 tc;
703 int i;
704 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
705
706 if (adapter->ixgbe_ieee_pfc)
707 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
708
709 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
710 ixgbe_update_xoff_rx_lfc(adapter);
711 return;
712 }
713
714 /* update stats for each tc, only valid with PFC enabled */
715 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
716 u32 pxoffrxc;
717
718 switch (hw->mac.type) {
719 case ixgbe_mac_82598EB:
720 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
721 break;
722 default:
723 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
724 }
725 hwstats->pxoffrxc[i] += pxoffrxc;
726 /* Get the TC for given UP */
727 tc = netdev_get_prio_tc_map(adapter->netdev, i);
728 xoff[tc] += pxoffrxc;
729 }
730
731 /* disarm tx queues that have received xoff frames */
732 for (i = 0; i < adapter->num_tx_queues; i++) {
733 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
734
735 tc = tx_ring->dcb_tc;
736 if (xoff[tc])
737 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
738 }
739 }
740
741 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
742 {
743 return ring->stats.packets;
744 }
745
746 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
747 {
748 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
749 struct ixgbe_hw *hw = &adapter->hw;
750
751 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
752 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
753
754 if (head != tail)
755 return (head < tail) ?
756 tail - head : (tail + ring->count - head);
757
758 return 0;
759 }
760
761 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
762 {
763 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
764 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
765 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
766 bool ret = false;
767
768 clear_check_for_tx_hang(tx_ring);
769
770 /*
771 * Check for a hung queue, but be thorough. This verifies
772 * that a transmit has been completed since the previous
773 * check AND there is at least one packet pending. The
774 * ARMED bit is set to indicate a potential hang. The
775 * bit is cleared if a pause frame is received to remove
776 * false hang detection due to PFC or 802.3x frames. By
777 * requiring this to fail twice we avoid races with
778 * pfc clearing the ARMED bit and conditions where we
779 * run the check_tx_hang logic with a transmit completion
780 * pending but without time to complete it yet.
781 */
782 if ((tx_done_old == tx_done) && tx_pending) {
783 /* make sure it is true for two checks in a row */
784 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
785 &tx_ring->state);
786 } else {
787 /* update completed stats and continue */
788 tx_ring->tx_stats.tx_done_old = tx_done;
789 /* reset the countdown */
790 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
791 }
792
793 return ret;
794 }
795
796 /**
797 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
798 * @adapter: driver private struct
799 **/
800 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
801 {
802
803 /* Do the reset outside of interrupt context */
804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
805 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
806 e_warn(drv, "initiating reset due to tx timeout\n");
807 ixgbe_service_event_schedule(adapter);
808 }
809 }
810
811 /**
812 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
813 * @q_vector: structure containing interrupt and ring information
814 * @tx_ring: tx ring to clean
815 **/
816 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
817 struct ixgbe_ring *tx_ring)
818 {
819 struct ixgbe_adapter *adapter = q_vector->adapter;
820 struct ixgbe_tx_buffer *tx_buffer;
821 union ixgbe_adv_tx_desc *tx_desc;
822 unsigned int total_bytes = 0, total_packets = 0;
823 unsigned int budget = q_vector->tx.work_limit;
824 unsigned int i = tx_ring->next_to_clean;
825
826 if (test_bit(__IXGBE_DOWN, &adapter->state))
827 return true;
828
829 tx_buffer = &tx_ring->tx_buffer_info[i];
830 tx_desc = IXGBE_TX_DESC(tx_ring, i);
831 i -= tx_ring->count;
832
833 do {
834 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
835
836 /* if next_to_watch is not set then there is no work pending */
837 if (!eop_desc)
838 break;
839
840 /* prevent any other reads prior to eop_desc */
841 read_barrier_depends();
842
843 /* if DD is not set pending work has not been completed */
844 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
845 break;
846
847 /* clear next_to_watch to prevent false hangs */
848 tx_buffer->next_to_watch = NULL;
849
850 /* update the statistics for this packet */
851 total_bytes += tx_buffer->bytecount;
852 total_packets += tx_buffer->gso_segs;
853
854 /* free the skb */
855 dev_kfree_skb_any(tx_buffer->skb);
856
857 /* unmap skb header data */
858 dma_unmap_single(tx_ring->dev,
859 dma_unmap_addr(tx_buffer, dma),
860 dma_unmap_len(tx_buffer, len),
861 DMA_TO_DEVICE);
862
863 /* clear tx_buffer data */
864 tx_buffer->skb = NULL;
865 dma_unmap_len_set(tx_buffer, len, 0);
866
867 /* unmap remaining buffers */
868 while (tx_desc != eop_desc) {
869 tx_buffer++;
870 tx_desc++;
871 i++;
872 if (unlikely(!i)) {
873 i -= tx_ring->count;
874 tx_buffer = tx_ring->tx_buffer_info;
875 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
876 }
877
878 /* unmap any remaining paged data */
879 if (dma_unmap_len(tx_buffer, len)) {
880 dma_unmap_page(tx_ring->dev,
881 dma_unmap_addr(tx_buffer, dma),
882 dma_unmap_len(tx_buffer, len),
883 DMA_TO_DEVICE);
884 dma_unmap_len_set(tx_buffer, len, 0);
885 }
886 }
887
888 /* move us one more past the eop_desc for start of next pkt */
889 tx_buffer++;
890 tx_desc++;
891 i++;
892 if (unlikely(!i)) {
893 i -= tx_ring->count;
894 tx_buffer = tx_ring->tx_buffer_info;
895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
896 }
897
898 /* issue prefetch for next Tx descriptor */
899 prefetch(tx_desc);
900
901 /* update budget accounting */
902 budget--;
903 } while (likely(budget));
904
905 i += tx_ring->count;
906 tx_ring->next_to_clean = i;
907 u64_stats_update_begin(&tx_ring->syncp);
908 tx_ring->stats.bytes += total_bytes;
909 tx_ring->stats.packets += total_packets;
910 u64_stats_update_end(&tx_ring->syncp);
911 q_vector->tx.total_bytes += total_bytes;
912 q_vector->tx.total_packets += total_packets;
913
914 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
915 /* schedule immediate reset if we believe we hung */
916 struct ixgbe_hw *hw = &adapter->hw;
917 e_err(drv, "Detected Tx Unit Hang\n"
918 " Tx Queue <%d>\n"
919 " TDH, TDT <%x>, <%x>\n"
920 " next_to_use <%x>\n"
921 " next_to_clean <%x>\n"
922 "tx_buffer_info[next_to_clean]\n"
923 " time_stamp <%lx>\n"
924 " jiffies <%lx>\n",
925 tx_ring->queue_index,
926 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
927 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
928 tx_ring->next_to_use, i,
929 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
930
931 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
932
933 e_info(probe,
934 "tx hang %d detected on queue %d, resetting adapter\n",
935 adapter->tx_timeout_count + 1, tx_ring->queue_index);
936
937 /* schedule immediate reset if we believe we hung */
938 ixgbe_tx_timeout_reset(adapter);
939
940 /* the adapter is about to reset, no point in enabling stuff */
941 return true;
942 }
943
944 netdev_tx_completed_queue(txring_txq(tx_ring),
945 total_packets, total_bytes);
946
947 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
948 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
949 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
950 /* Make sure that anybody stopping the queue after this
951 * sees the new next_to_clean.
952 */
953 smp_mb();
954 if (__netif_subqueue_stopped(tx_ring->netdev,
955 tx_ring->queue_index)
956 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
957 netif_wake_subqueue(tx_ring->netdev,
958 tx_ring->queue_index);
959 ++tx_ring->tx_stats.restart_queue;
960 }
961 }
962
963 return !!budget;
964 }
965
966 #ifdef CONFIG_IXGBE_DCA
967 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
968 struct ixgbe_ring *tx_ring,
969 int cpu)
970 {
971 struct ixgbe_hw *hw = &adapter->hw;
972 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
973 u16 reg_offset;
974
975 switch (hw->mac.type) {
976 case ixgbe_mac_82598EB:
977 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
978 break;
979 case ixgbe_mac_82599EB:
980 case ixgbe_mac_X540:
981 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
982 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
983 break;
984 default:
985 /* for unknown hardware do not write register */
986 return;
987 }
988
989 /*
990 * We can enable relaxed ordering for reads, but not writes when
991 * DCA is enabled. This is due to a known issue in some chipsets
992 * which will cause the DCA tag to be cleared.
993 */
994 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
995 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
996 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
997
998 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
999 }
1000
1001 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1002 struct ixgbe_ring *rx_ring,
1003 int cpu)
1004 {
1005 struct ixgbe_hw *hw = &adapter->hw;
1006 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1007 u8 reg_idx = rx_ring->reg_idx;
1008
1009
1010 switch (hw->mac.type) {
1011 case ixgbe_mac_82599EB:
1012 case ixgbe_mac_X540:
1013 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1014 break;
1015 default:
1016 break;
1017 }
1018
1019 /*
1020 * We can enable relaxed ordering for reads, but not writes when
1021 * DCA is enabled. This is due to a known issue in some chipsets
1022 * which will cause the DCA tag to be cleared.
1023 */
1024 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1025 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1026
1027 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1028 }
1029
1030 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1031 {
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
1033 struct ixgbe_ring *ring;
1034 int cpu = get_cpu();
1035
1036 if (q_vector->cpu == cpu)
1037 goto out_no_update;
1038
1039 ixgbe_for_each_ring(ring, q_vector->tx)
1040 ixgbe_update_tx_dca(adapter, ring, cpu);
1041
1042 ixgbe_for_each_ring(ring, q_vector->rx)
1043 ixgbe_update_rx_dca(adapter, ring, cpu);
1044
1045 q_vector->cpu = cpu;
1046 out_no_update:
1047 put_cpu();
1048 }
1049
1050 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1051 {
1052 int i;
1053
1054 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1055 return;
1056
1057 /* always use CB2 mode, difference is masked in the CB driver */
1058 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1059
1060 for (i = 0; i < adapter->num_q_vectors; i++) {
1061 adapter->q_vector[i]->cpu = -1;
1062 ixgbe_update_dca(adapter->q_vector[i]);
1063 }
1064 }
1065
1066 static int __ixgbe_notify_dca(struct device *dev, void *data)
1067 {
1068 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1069 unsigned long event = *(unsigned long *)data;
1070
1071 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1072 return 0;
1073
1074 switch (event) {
1075 case DCA_PROVIDER_ADD:
1076 /* if we're already enabled, don't do it again */
1077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1078 break;
1079 if (dca_add_requester(dev) == 0) {
1080 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1081 ixgbe_setup_dca(adapter);
1082 break;
1083 }
1084 /* Fall Through since DCA is disabled. */
1085 case DCA_PROVIDER_REMOVE:
1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1087 dca_remove_requester(dev);
1088 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1090 }
1091 break;
1092 }
1093
1094 return 0;
1095 }
1096
1097 #endif /* CONFIG_IXGBE_DCA */
1098 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1101 {
1102 if (ring->netdev->features & NETIF_F_RXHASH)
1103 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1104 }
1105
1106 #ifdef IXGBE_FCOE
1107 /**
1108 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1109 * @ring: structure containing ring specific data
1110 * @rx_desc: advanced rx descriptor
1111 *
1112 * Returns : true if it is FCoE pkt
1113 */
1114 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1115 union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1118
1119 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1120 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1121 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1122 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1123 }
1124
1125 #endif /* IXGBE_FCOE */
1126 /**
1127 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1128 * @ring: structure containing ring specific data
1129 * @rx_desc: current Rx descriptor being processed
1130 * @skb: skb currently being received and modified
1131 **/
1132 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1133 union ixgbe_adv_rx_desc *rx_desc,
1134 struct sk_buff *skb)
1135 {
1136 skb_checksum_none_assert(skb);
1137
1138 /* Rx csum disabled */
1139 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1140 return;
1141
1142 /* if IP and error */
1143 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1144 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1145 ring->rx_stats.csum_err++;
1146 return;
1147 }
1148
1149 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1150 return;
1151
1152 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1153 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1154
1155 /*
1156 * 82599 errata, UDP frames with a 0 checksum can be marked as
1157 * checksum errors.
1158 */
1159 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1160 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1161 return;
1162
1163 ring->rx_stats.csum_err++;
1164 return;
1165 }
1166
1167 /* It must be a TCP or UDP packet with a valid checksum */
1168 skb->ip_summed = CHECKSUM_UNNECESSARY;
1169 }
1170
1171 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1172 {
1173 rx_ring->next_to_use = val;
1174
1175 /* update next to alloc since we have filled the ring */
1176 rx_ring->next_to_alloc = val;
1177 /*
1178 * Force memory writes to complete before letting h/w
1179 * know there are new descriptors to fetch. (Only
1180 * applicable for weak-ordered memory model archs,
1181 * such as IA-64).
1182 */
1183 wmb();
1184 writel(val, rx_ring->tail);
1185 }
1186
1187 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1188 struct ixgbe_rx_buffer *bi)
1189 {
1190 struct page *page = bi->page;
1191 dma_addr_t dma = bi->dma;
1192
1193 /* since we are recycling buffers we should seldom need to alloc */
1194 if (likely(dma))
1195 return true;
1196
1197 /* alloc new page for storage */
1198 if (likely(!page)) {
1199 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1200 bi->skb, ixgbe_rx_pg_order(rx_ring));
1201 if (unlikely(!page)) {
1202 rx_ring->rx_stats.alloc_rx_page_failed++;
1203 return false;
1204 }
1205 bi->page = page;
1206 }
1207
1208 /* map page for use */
1209 dma = dma_map_page(rx_ring->dev, page, 0,
1210 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1211
1212 /*
1213 * if mapping failed free memory back to system since
1214 * there isn't much point in holding memory we can't use
1215 */
1216 if (dma_mapping_error(rx_ring->dev, dma)) {
1217 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1218 bi->page = NULL;
1219
1220 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 return false;
1222 }
1223
1224 bi->dma = dma;
1225 bi->page_offset = 0;
1226
1227 return true;
1228 }
1229
1230 /**
1231 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1232 * @rx_ring: ring to place buffers on
1233 * @cleaned_count: number of buffers to replace
1234 **/
1235 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1236 {
1237 union ixgbe_adv_rx_desc *rx_desc;
1238 struct ixgbe_rx_buffer *bi;
1239 u16 i = rx_ring->next_to_use;
1240
1241 /* nothing to do */
1242 if (!cleaned_count)
1243 return;
1244
1245 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1246 bi = &rx_ring->rx_buffer_info[i];
1247 i -= rx_ring->count;
1248
1249 do {
1250 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1251 break;
1252
1253 /*
1254 * Refresh the desc even if buffer_addrs didn't change
1255 * because each write-back erases this info.
1256 */
1257 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1258
1259 rx_desc++;
1260 bi++;
1261 i++;
1262 if (unlikely(!i)) {
1263 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1264 bi = rx_ring->rx_buffer_info;
1265 i -= rx_ring->count;
1266 }
1267
1268 /* clear the hdr_addr for the next_to_use descriptor */
1269 rx_desc->read.hdr_addr = 0;
1270
1271 cleaned_count--;
1272 } while (cleaned_count);
1273
1274 i += rx_ring->count;
1275
1276 if (rx_ring->next_to_use != i)
1277 ixgbe_release_rx_desc(rx_ring, i);
1278 }
1279
1280 /**
1281 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1282 * @data: pointer to the start of the headers
1283 * @max_len: total length of section to find headers in
1284 *
1285 * This function is meant to determine the length of headers that will
1286 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1287 * motivation of doing this is to only perform one pull for IPv4 TCP
1288 * packets so that we can do basic things like calculating the gso_size
1289 * based on the average data per packet.
1290 **/
1291 static unsigned int ixgbe_get_headlen(unsigned char *data,
1292 unsigned int max_len)
1293 {
1294 union {
1295 unsigned char *network;
1296 /* l2 headers */
1297 struct ethhdr *eth;
1298 struct vlan_hdr *vlan;
1299 /* l3 headers */
1300 struct iphdr *ipv4;
1301 struct ipv6hdr *ipv6;
1302 } hdr;
1303 __be16 protocol;
1304 u8 nexthdr = 0; /* default to not TCP */
1305 u8 hlen;
1306
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1309 return max_len;
1310
1311 /* initialize network frame pointer */
1312 hdr.network = data;
1313
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1317
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1321 return max_len;
1322
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1325 }
1326
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1330 return max_len;
1331
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1334
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1338
1339 /* record next protocol if header is present */
1340 if (!hdr.ipv4->frag_off)
1341 nexthdr = hdr.ipv4->protocol;
1342 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1343 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1344 return max_len;
1345
1346 /* record next protocol */
1347 nexthdr = hdr.ipv6->nexthdr;
1348 hlen = sizeof(struct ipv6hdr);
1349 #ifdef IXGBE_FCOE
1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1352 return max_len;
1353 hlen = FCOE_HEADER_LEN;
1354 #endif
1355 } else {
1356 return hdr.network - data;
1357 }
1358
1359 /* relocate pointer to start of L4 header */
1360 hdr.network += hlen;
1361
1362 /* finally sort out TCP/UDP */
1363 if (nexthdr == IPPROTO_TCP) {
1364 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1365 return max_len;
1366
1367 /* access doff as a u8 to avoid unaligned access on ia64 */
1368 hlen = (hdr.network[12] & 0xF0) >> 2;
1369
1370 /* verify hlen meets minimum size requirements */
1371 if (hlen < sizeof(struct tcphdr))
1372 return hdr.network - data;
1373
1374 hdr.network += hlen;
1375 } else if (nexthdr == IPPROTO_UDP) {
1376 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1377 return max_len;
1378
1379 hdr.network += sizeof(struct udphdr);
1380 }
1381
1382 /*
1383 * If everything has gone correctly hdr.network should be the
1384 * data section of the packet and will be the end of the header.
1385 * If not then it probably represents the end of the last recognized
1386 * header.
1387 */
1388 if ((hdr.network - data) < max_len)
1389 return hdr.network - data;
1390 else
1391 return max_len;
1392 }
1393
1394 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1395 struct sk_buff *skb)
1396 {
1397 u16 hdr_len = skb_headlen(skb);
1398
1399 /* set gso_size to avoid messing up TCP MSS */
1400 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1401 IXGBE_CB(skb)->append_cnt);
1402 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1403 }
1404
1405 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1406 struct sk_buff *skb)
1407 {
1408 /* if append_cnt is 0 then frame is not RSC */
1409 if (!IXGBE_CB(skb)->append_cnt)
1410 return;
1411
1412 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1413 rx_ring->rx_stats.rsc_flush++;
1414
1415 ixgbe_set_rsc_gso_size(rx_ring, skb);
1416
1417 /* gso_size is computed using append_cnt so always clear it last */
1418 IXGBE_CB(skb)->append_cnt = 0;
1419 }
1420
1421 /**
1422 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1423 * @rx_ring: rx descriptor ring packet is being transacted on
1424 * @rx_desc: pointer to the EOP Rx descriptor
1425 * @skb: pointer to current skb being populated
1426 *
1427 * This function checks the ring, descriptor, and packet information in
1428 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1429 * other fields within the skb.
1430 **/
1431 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1432 union ixgbe_adv_rx_desc *rx_desc,
1433 struct sk_buff *skb)
1434 {
1435 struct net_device *dev = rx_ring->netdev;
1436
1437 ixgbe_update_rsc_stats(rx_ring, skb);
1438
1439 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1440
1441 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1442
1443 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1444
1445 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1446 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1447 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1448 __vlan_hwaccel_put_tag(skb, vid);
1449 }
1450
1451 skb_record_rx_queue(skb, rx_ring->queue_index);
1452
1453 skb->protocol = eth_type_trans(skb, dev);
1454 }
1455
1456 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1457 struct sk_buff *skb)
1458 {
1459 struct ixgbe_adapter *adapter = q_vector->adapter;
1460
1461 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1462 napi_gro_receive(&q_vector->napi, skb);
1463 else
1464 netif_rx(skb);
1465 }
1466
1467 /**
1468 * ixgbe_is_non_eop - process handling of non-EOP buffers
1469 * @rx_ring: Rx ring being processed
1470 * @rx_desc: Rx descriptor for current buffer
1471 * @skb: Current socket buffer containing buffer in progress
1472 *
1473 * This function updates next to clean. If the buffer is an EOP buffer
1474 * this function exits returning false, otherwise it will place the
1475 * sk_buff in the next buffer to be chained and return true indicating
1476 * that this is in fact a non-EOP buffer.
1477 **/
1478 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1479 union ixgbe_adv_rx_desc *rx_desc,
1480 struct sk_buff *skb)
1481 {
1482 u32 ntc = rx_ring->next_to_clean + 1;
1483
1484 /* fetch, update, and store next to clean */
1485 ntc = (ntc < rx_ring->count) ? ntc : 0;
1486 rx_ring->next_to_clean = ntc;
1487
1488 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1489
1490 /* update RSC append count if present */
1491 if (ring_is_rsc_enabled(rx_ring)) {
1492 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1493 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1494
1495 if (unlikely(rsc_enabled)) {
1496 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1497
1498 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1499 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1500
1501 /* update ntc based on RSC value */
1502 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1503 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1504 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1505 }
1506 }
1507
1508 /* if we are the last buffer then there is nothing else to do */
1509 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1510 return false;
1511
1512 /* place skb in next buffer to be received */
1513 rx_ring->rx_buffer_info[ntc].skb = skb;
1514 rx_ring->rx_stats.non_eop_descs++;
1515
1516 return true;
1517 }
1518
1519 /**
1520 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1521 * @rx_ring: rx descriptor ring packet is being transacted on
1522 * @skb: pointer to current skb being adjusted
1523 *
1524 * This function is an ixgbe specific version of __pskb_pull_tail. The
1525 * main difference between this version and the original function is that
1526 * this function can make several assumptions about the state of things
1527 * that allow for significant optimizations versus the standard function.
1528 * As a result we can do things like drop a frag and maintain an accurate
1529 * truesize for the skb.
1530 */
1531 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1532 struct sk_buff *skb)
1533 {
1534 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1535 unsigned char *va;
1536 unsigned int pull_len;
1537
1538 /*
1539 * it is valid to use page_address instead of kmap since we are
1540 * working with pages allocated out of the lomem pool per
1541 * alloc_page(GFP_ATOMIC)
1542 */
1543 va = skb_frag_address(frag);
1544
1545 /*
1546 * we need the header to contain the greater of either ETH_HLEN or
1547 * 60 bytes if the skb->len is less than 60 for skb_pad.
1548 */
1549 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1550
1551 /* align pull length to size of long to optimize memcpy performance */
1552 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1553
1554 /* update all of the pointers */
1555 skb_frag_size_sub(frag, pull_len);
1556 frag->page_offset += pull_len;
1557 skb->data_len -= pull_len;
1558 skb->tail += pull_len;
1559 }
1560
1561 /**
1562 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1563 * @rx_ring: rx descriptor ring packet is being transacted on
1564 * @skb: pointer to current skb being updated
1565 *
1566 * This function provides a basic DMA sync up for the first fragment of an
1567 * skb. The reason for doing this is that the first fragment cannot be
1568 * unmapped until we have reached the end of packet descriptor for a buffer
1569 * chain.
1570 */
1571 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1572 struct sk_buff *skb)
1573 {
1574 /* if the page was released unmap it, else just sync our portion */
1575 if (unlikely(IXGBE_CB(skb)->page_released)) {
1576 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1577 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1578 IXGBE_CB(skb)->page_released = false;
1579 } else {
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1581
1582 dma_sync_single_range_for_cpu(rx_ring->dev,
1583 IXGBE_CB(skb)->dma,
1584 frag->page_offset,
1585 ixgbe_rx_bufsz(rx_ring),
1586 DMA_FROM_DEVICE);
1587 }
1588 IXGBE_CB(skb)->dma = 0;
1589 }
1590
1591 /**
1592 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1593 * @rx_ring: rx descriptor ring packet is being transacted on
1594 * @rx_desc: pointer to the EOP Rx descriptor
1595 * @skb: pointer to current skb being fixed
1596 *
1597 * Check for corrupted packet headers caused by senders on the local L2
1598 * embedded NIC switch not setting up their Tx Descriptors right. These
1599 * should be very rare.
1600 *
1601 * Also address the case where we are pulling data in on pages only
1602 * and as such no data is present in the skb header.
1603 *
1604 * In addition if skb is not at least 60 bytes we need to pad it so that
1605 * it is large enough to qualify as a valid Ethernet frame.
1606 *
1607 * Returns true if an error was encountered and skb was freed.
1608 **/
1609 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1610 union ixgbe_adv_rx_desc *rx_desc,
1611 struct sk_buff *skb)
1612 {
1613 struct net_device *netdev = rx_ring->netdev;
1614
1615 /* verify that the packet does not have any known errors */
1616 if (unlikely(ixgbe_test_staterr(rx_desc,
1617 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1618 !(netdev->features & NETIF_F_RXALL))) {
1619 dev_kfree_skb_any(skb);
1620 return true;
1621 }
1622
1623 /* place header in linear portion of buffer */
1624 if (skb_is_nonlinear(skb))
1625 ixgbe_pull_tail(rx_ring, skb);
1626
1627 #ifdef IXGBE_FCOE
1628 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1629 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1630 return false;
1631
1632 #endif
1633 /* if skb_pad returns an error the skb was freed */
1634 if (unlikely(skb->len < 60)) {
1635 int pad_len = 60 - skb->len;
1636
1637 if (skb_pad(skb, pad_len))
1638 return true;
1639 __skb_put(skb, pad_len);
1640 }
1641
1642 return false;
1643 }
1644
1645 /**
1646 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1647 * @rx_ring: rx descriptor ring to store buffers on
1648 * @old_buff: donor buffer to have page reused
1649 *
1650 * Synchronizes page for reuse by the adapter
1651 **/
1652 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1653 struct ixgbe_rx_buffer *old_buff)
1654 {
1655 struct ixgbe_rx_buffer *new_buff;
1656 u16 nta = rx_ring->next_to_alloc;
1657
1658 new_buff = &rx_ring->rx_buffer_info[nta];
1659
1660 /* update, and store next to alloc */
1661 nta++;
1662 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1663
1664 /* transfer page from old buffer to new buffer */
1665 new_buff->page = old_buff->page;
1666 new_buff->dma = old_buff->dma;
1667 new_buff->page_offset = old_buff->page_offset;
1668
1669 /* sync the buffer for use by the device */
1670 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1671 new_buff->page_offset,
1672 ixgbe_rx_bufsz(rx_ring),
1673 DMA_FROM_DEVICE);
1674 }
1675
1676 /**
1677 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1678 * @rx_ring: rx descriptor ring to transact packets on
1679 * @rx_buffer: buffer containing page to add
1680 * @rx_desc: descriptor containing length of buffer written by hardware
1681 * @skb: sk_buff to place the data into
1682 *
1683 * This function will add the data contained in rx_buffer->page to the skb.
1684 * This is done either through a direct copy if the data in the buffer is
1685 * less than the skb header size, otherwise it will just attach the page as
1686 * a frag to the skb.
1687 *
1688 * The function will then update the page offset if necessary and return
1689 * true if the buffer can be reused by the adapter.
1690 **/
1691 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1692 struct ixgbe_rx_buffer *rx_buffer,
1693 union ixgbe_adv_rx_desc *rx_desc,
1694 struct sk_buff *skb)
1695 {
1696 struct page *page = rx_buffer->page;
1697 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1698 #if (PAGE_SIZE < 8192)
1699 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1700 #else
1701 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1702 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1703 ixgbe_rx_bufsz(rx_ring);
1704 #endif
1705
1706 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1707 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1708
1709 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1710
1711 /* we can reuse buffer as-is, just make sure it is local */
1712 if (likely(page_to_nid(page) == numa_node_id()))
1713 return true;
1714
1715 /* this page cannot be reused so discard it */
1716 put_page(page);
1717 return false;
1718 }
1719
1720 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1721 rx_buffer->page_offset, size, truesize);
1722
1723 /* avoid re-using remote pages */
1724 if (unlikely(page_to_nid(page) != numa_node_id()))
1725 return false;
1726
1727 #if (PAGE_SIZE < 8192)
1728 /* if we are only owner of page we can reuse it */
1729 if (unlikely(page_count(page) != 1))
1730 return false;
1731
1732 /* flip page offset to other buffer */
1733 rx_buffer->page_offset ^= truesize;
1734
1735 /*
1736 * since we are the only owner of the page and we need to
1737 * increment it, just set the value to 2 in order to avoid
1738 * an unecessary locked operation
1739 */
1740 atomic_set(&page->_count, 2);
1741 #else
1742 /* move offset up to the next cache line */
1743 rx_buffer->page_offset += truesize;
1744
1745 if (rx_buffer->page_offset > last_offset)
1746 return false;
1747
1748 /* bump ref count on page before it is given to the stack */
1749 get_page(page);
1750 #endif
1751
1752 return true;
1753 }
1754
1755 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1756 union ixgbe_adv_rx_desc *rx_desc)
1757 {
1758 struct ixgbe_rx_buffer *rx_buffer;
1759 struct sk_buff *skb;
1760 struct page *page;
1761
1762 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1763 page = rx_buffer->page;
1764 prefetchw(page);
1765
1766 skb = rx_buffer->skb;
1767
1768 if (likely(!skb)) {
1769 void *page_addr = page_address(page) +
1770 rx_buffer->page_offset;
1771
1772 /* prefetch first cache line of first page */
1773 prefetch(page_addr);
1774 #if L1_CACHE_BYTES < 128
1775 prefetch(page_addr + L1_CACHE_BYTES);
1776 #endif
1777
1778 /* allocate a skb to store the frags */
1779 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1780 IXGBE_RX_HDR_SIZE);
1781 if (unlikely(!skb)) {
1782 rx_ring->rx_stats.alloc_rx_buff_failed++;
1783 return NULL;
1784 }
1785
1786 /*
1787 * we will be copying header into skb->data in
1788 * pskb_may_pull so it is in our interest to prefetch
1789 * it now to avoid a possible cache miss
1790 */
1791 prefetchw(skb->data);
1792
1793 /*
1794 * Delay unmapping of the first packet. It carries the
1795 * header information, HW may still access the header
1796 * after the writeback. Only unmap it when EOP is
1797 * reached
1798 */
1799 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1800 goto dma_sync;
1801
1802 IXGBE_CB(skb)->dma = rx_buffer->dma;
1803 } else {
1804 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1805 ixgbe_dma_sync_frag(rx_ring, skb);
1806
1807 dma_sync:
1808 /* we are reusing so sync this buffer for CPU use */
1809 dma_sync_single_range_for_cpu(rx_ring->dev,
1810 rx_buffer->dma,
1811 rx_buffer->page_offset,
1812 ixgbe_rx_bufsz(rx_ring),
1813 DMA_FROM_DEVICE);
1814 }
1815
1816 /* pull page into skb */
1817 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1818 /* hand second half of page back to the ring */
1819 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1820 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1821 /* the page has been released from the ring */
1822 IXGBE_CB(skb)->page_released = true;
1823 } else {
1824 /* we are not reusing the buffer so unmap it */
1825 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1826 ixgbe_rx_pg_size(rx_ring),
1827 DMA_FROM_DEVICE);
1828 }
1829
1830 /* clear contents of buffer_info */
1831 rx_buffer->skb = NULL;
1832 rx_buffer->dma = 0;
1833 rx_buffer->page = NULL;
1834
1835 return skb;
1836 }
1837
1838 /**
1839 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1840 * @q_vector: structure containing interrupt and ring information
1841 * @rx_ring: rx descriptor ring to transact packets on
1842 * @budget: Total limit on number of packets to process
1843 *
1844 * This function provides a "bounce buffer" approach to Rx interrupt
1845 * processing. The advantage to this is that on systems that have
1846 * expensive overhead for IOMMU access this provides a means of avoiding
1847 * it by maintaining the mapping of the page to the syste.
1848 *
1849 * Returns true if all work is completed without reaching budget
1850 **/
1851 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1852 struct ixgbe_ring *rx_ring,
1853 const int budget)
1854 {
1855 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1856 #ifdef IXGBE_FCOE
1857 struct ixgbe_adapter *adapter = q_vector->adapter;
1858 int ddp_bytes;
1859 unsigned int mss = 0;
1860 #endif /* IXGBE_FCOE */
1861 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1862
1863 do {
1864 union ixgbe_adv_rx_desc *rx_desc;
1865 struct sk_buff *skb;
1866
1867 /* return some buffers to hardware, one at a time is too slow */
1868 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1869 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1870 cleaned_count = 0;
1871 }
1872
1873 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1874
1875 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1876 break;
1877
1878 /*
1879 * This memory barrier is needed to keep us from reading
1880 * any other fields out of the rx_desc until we know the
1881 * RXD_STAT_DD bit is set
1882 */
1883 rmb();
1884
1885 /* retrieve a buffer from the ring */
1886 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1887
1888 /* exit if we failed to retrieve a buffer */
1889 if (!skb)
1890 break;
1891
1892 cleaned_count++;
1893
1894 /* place incomplete frames back on ring for completion */
1895 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1896 continue;
1897
1898 /* verify the packet layout is correct */
1899 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1900 continue;
1901
1902 /* probably a little skewed due to removing CRC */
1903 total_rx_bytes += skb->len;
1904
1905 /* populate checksum, timestamp, VLAN, and protocol */
1906 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1907
1908 #ifdef IXGBE_FCOE
1909 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1910 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1911 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1912 /* include DDPed FCoE data */
1913 if (ddp_bytes > 0) {
1914 if (!mss) {
1915 mss = rx_ring->netdev->mtu -
1916 sizeof(struct fcoe_hdr) -
1917 sizeof(struct fc_frame_header) -
1918 sizeof(struct fcoe_crc_eof);
1919 if (mss > 512)
1920 mss &= ~511;
1921 }
1922 total_rx_bytes += ddp_bytes;
1923 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1924 mss);
1925 }
1926 if (!ddp_bytes) {
1927 dev_kfree_skb_any(skb);
1928 continue;
1929 }
1930 }
1931
1932 #endif /* IXGBE_FCOE */
1933 ixgbe_rx_skb(q_vector, skb);
1934
1935 /* update budget accounting */
1936 total_rx_packets++;
1937 } while (likely(total_rx_packets < budget));
1938
1939 u64_stats_update_begin(&rx_ring->syncp);
1940 rx_ring->stats.packets += total_rx_packets;
1941 rx_ring->stats.bytes += total_rx_bytes;
1942 u64_stats_update_end(&rx_ring->syncp);
1943 q_vector->rx.total_packets += total_rx_packets;
1944 q_vector->rx.total_bytes += total_rx_bytes;
1945
1946 if (cleaned_count)
1947 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1948
1949 return (total_rx_packets < budget);
1950 }
1951
1952 /**
1953 * ixgbe_configure_msix - Configure MSI-X hardware
1954 * @adapter: board private structure
1955 *
1956 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1957 * interrupts.
1958 **/
1959 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1960 {
1961 struct ixgbe_q_vector *q_vector;
1962 int v_idx;
1963 u32 mask;
1964
1965 /* Populate MSIX to EITR Select */
1966 if (adapter->num_vfs > 32) {
1967 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1969 }
1970
1971 /*
1972 * Populate the IVAR table and set the ITR values to the
1973 * corresponding register.
1974 */
1975 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1976 struct ixgbe_ring *ring;
1977 q_vector = adapter->q_vector[v_idx];
1978
1979 ixgbe_for_each_ring(ring, q_vector->rx)
1980 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1981
1982 ixgbe_for_each_ring(ring, q_vector->tx)
1983 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1984
1985 ixgbe_write_eitr(q_vector);
1986 }
1987
1988 switch (adapter->hw.mac.type) {
1989 case ixgbe_mac_82598EB:
1990 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1991 v_idx);
1992 break;
1993 case ixgbe_mac_82599EB:
1994 case ixgbe_mac_X540:
1995 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1996 break;
1997 default:
1998 break;
1999 }
2000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2001
2002 /* set up to autoclear timer, and the vectors */
2003 mask = IXGBE_EIMS_ENABLE_MASK;
2004 mask &= ~(IXGBE_EIMS_OTHER |
2005 IXGBE_EIMS_MAILBOX |
2006 IXGBE_EIMS_LSC);
2007
2008 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2009 }
2010
2011 enum latency_range {
2012 lowest_latency = 0,
2013 low_latency = 1,
2014 bulk_latency = 2,
2015 latency_invalid = 255
2016 };
2017
2018 /**
2019 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2020 * @q_vector: structure containing interrupt and ring information
2021 * @ring_container: structure containing ring performance data
2022 *
2023 * Stores a new ITR value based on packets and byte
2024 * counts during the last interrupt. The advantage of per interrupt
2025 * computation is faster updates and more accurate ITR for the current
2026 * traffic pattern. Constants in this function were computed
2027 * based on theoretical maximum wire speed and thresholds were set based
2028 * on testing data as well as attempting to minimize response time
2029 * while increasing bulk throughput.
2030 * this functionality is controlled by the InterruptThrottleRate module
2031 * parameter (see ixgbe_param.c)
2032 **/
2033 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2034 struct ixgbe_ring_container *ring_container)
2035 {
2036 int bytes = ring_container->total_bytes;
2037 int packets = ring_container->total_packets;
2038 u32 timepassed_us;
2039 u64 bytes_perint;
2040 u8 itr_setting = ring_container->itr;
2041
2042 if (packets == 0)
2043 return;
2044
2045 /* simple throttlerate management
2046 * 0-10MB/s lowest (100000 ints/s)
2047 * 10-20MB/s low (20000 ints/s)
2048 * 20-1249MB/s bulk (8000 ints/s)
2049 */
2050 /* what was last interrupt timeslice? */
2051 timepassed_us = q_vector->itr >> 2;
2052 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2053
2054 switch (itr_setting) {
2055 case lowest_latency:
2056 if (bytes_perint > 10)
2057 itr_setting = low_latency;
2058 break;
2059 case low_latency:
2060 if (bytes_perint > 20)
2061 itr_setting = bulk_latency;
2062 else if (bytes_perint <= 10)
2063 itr_setting = lowest_latency;
2064 break;
2065 case bulk_latency:
2066 if (bytes_perint <= 20)
2067 itr_setting = low_latency;
2068 break;
2069 }
2070
2071 /* clear work counters since we have the values we need */
2072 ring_container->total_bytes = 0;
2073 ring_container->total_packets = 0;
2074
2075 /* write updated itr to ring container */
2076 ring_container->itr = itr_setting;
2077 }
2078
2079 /**
2080 * ixgbe_write_eitr - write EITR register in hardware specific way
2081 * @q_vector: structure containing interrupt and ring information
2082 *
2083 * This function is made to be called by ethtool and by the driver
2084 * when it needs to update EITR registers at runtime. Hardware
2085 * specific quirks/differences are taken care of here.
2086 */
2087 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2088 {
2089 struct ixgbe_adapter *adapter = q_vector->adapter;
2090 struct ixgbe_hw *hw = &adapter->hw;
2091 int v_idx = q_vector->v_idx;
2092 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2093
2094 switch (adapter->hw.mac.type) {
2095 case ixgbe_mac_82598EB:
2096 /* must write high and low 16 bits to reset counter */
2097 itr_reg |= (itr_reg << 16);
2098 break;
2099 case ixgbe_mac_82599EB:
2100 case ixgbe_mac_X540:
2101 /*
2102 * set the WDIS bit to not clear the timer bits and cause an
2103 * immediate assertion of the interrupt
2104 */
2105 itr_reg |= IXGBE_EITR_CNT_WDIS;
2106 break;
2107 default:
2108 break;
2109 }
2110 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2111 }
2112
2113 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2114 {
2115 u32 new_itr = q_vector->itr;
2116 u8 current_itr;
2117
2118 ixgbe_update_itr(q_vector, &q_vector->tx);
2119 ixgbe_update_itr(q_vector, &q_vector->rx);
2120
2121 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2122
2123 switch (current_itr) {
2124 /* counts and packets in update_itr are dependent on these numbers */
2125 case lowest_latency:
2126 new_itr = IXGBE_100K_ITR;
2127 break;
2128 case low_latency:
2129 new_itr = IXGBE_20K_ITR;
2130 break;
2131 case bulk_latency:
2132 new_itr = IXGBE_8K_ITR;
2133 break;
2134 default:
2135 break;
2136 }
2137
2138 if (new_itr != q_vector->itr) {
2139 /* do an exponential smoothing */
2140 new_itr = (10 * new_itr * q_vector->itr) /
2141 ((9 * new_itr) + q_vector->itr);
2142
2143 /* save the algorithm value here */
2144 q_vector->itr = new_itr;
2145
2146 ixgbe_write_eitr(q_vector);
2147 }
2148 }
2149
2150 /**
2151 * ixgbe_check_overtemp_subtask - check for over temperature
2152 * @adapter: pointer to adapter
2153 **/
2154 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2155 {
2156 struct ixgbe_hw *hw = &adapter->hw;
2157 u32 eicr = adapter->interrupt_event;
2158
2159 if (test_bit(__IXGBE_DOWN, &adapter->state))
2160 return;
2161
2162 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2163 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2164 return;
2165
2166 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2167
2168 switch (hw->device_id) {
2169 case IXGBE_DEV_ID_82599_T3_LOM:
2170 /*
2171 * Since the warning interrupt is for both ports
2172 * we don't have to check if:
2173 * - This interrupt wasn't for our port.
2174 * - We may have missed the interrupt so always have to
2175 * check if we got a LSC
2176 */
2177 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2178 !(eicr & IXGBE_EICR_LSC))
2179 return;
2180
2181 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2182 u32 speed;
2183 bool link_up = false;
2184
2185 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2186
2187 if (link_up)
2188 return;
2189 }
2190
2191 /* Check if this is not due to overtemp */
2192 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2193 return;
2194
2195 break;
2196 default:
2197 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2198 return;
2199 break;
2200 }
2201 e_crit(drv,
2202 "Network adapter has been stopped because it has over heated. "
2203 "Restart the computer. If the problem persists, "
2204 "power off the system and replace the adapter\n");
2205
2206 adapter->interrupt_event = 0;
2207 }
2208
2209 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2210 {
2211 struct ixgbe_hw *hw = &adapter->hw;
2212
2213 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2214 (eicr & IXGBE_EICR_GPI_SDP1)) {
2215 e_crit(probe, "Fan has stopped, replace the adapter\n");
2216 /* write to clear the interrupt */
2217 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2218 }
2219 }
2220
2221 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2222 {
2223 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2224 return;
2225
2226 switch (adapter->hw.mac.type) {
2227 case ixgbe_mac_82599EB:
2228 /*
2229 * Need to check link state so complete overtemp check
2230 * on service task
2231 */
2232 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2233 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2234 adapter->interrupt_event = eicr;
2235 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2236 ixgbe_service_event_schedule(adapter);
2237 return;
2238 }
2239 return;
2240 case ixgbe_mac_X540:
2241 if (!(eicr & IXGBE_EICR_TS))
2242 return;
2243 break;
2244 default:
2245 return;
2246 }
2247
2248 e_crit(drv,
2249 "Network adapter has been stopped because it has over heated. "
2250 "Restart the computer. If the problem persists, "
2251 "power off the system and replace the adapter\n");
2252 }
2253
2254 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2255 {
2256 struct ixgbe_hw *hw = &adapter->hw;
2257
2258 if (eicr & IXGBE_EICR_GPI_SDP2) {
2259 /* Clear the interrupt */
2260 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2261 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2262 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2263 ixgbe_service_event_schedule(adapter);
2264 }
2265 }
2266
2267 if (eicr & IXGBE_EICR_GPI_SDP1) {
2268 /* Clear the interrupt */
2269 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2270 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2271 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2272 ixgbe_service_event_schedule(adapter);
2273 }
2274 }
2275 }
2276
2277 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2278 {
2279 struct ixgbe_hw *hw = &adapter->hw;
2280
2281 adapter->lsc_int++;
2282 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2283 adapter->link_check_timeout = jiffies;
2284 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2285 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2286 IXGBE_WRITE_FLUSH(hw);
2287 ixgbe_service_event_schedule(adapter);
2288 }
2289 }
2290
2291 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2292 u64 qmask)
2293 {
2294 u32 mask;
2295 struct ixgbe_hw *hw = &adapter->hw;
2296
2297 switch (hw->mac.type) {
2298 case ixgbe_mac_82598EB:
2299 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2300 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2301 break;
2302 case ixgbe_mac_82599EB:
2303 case ixgbe_mac_X540:
2304 mask = (qmask & 0xFFFFFFFF);
2305 if (mask)
2306 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2307 mask = (qmask >> 32);
2308 if (mask)
2309 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2310 break;
2311 default:
2312 break;
2313 }
2314 /* skip the flush */
2315 }
2316
2317 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2318 u64 qmask)
2319 {
2320 u32 mask;
2321 struct ixgbe_hw *hw = &adapter->hw;
2322
2323 switch (hw->mac.type) {
2324 case ixgbe_mac_82598EB:
2325 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2326 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2327 break;
2328 case ixgbe_mac_82599EB:
2329 case ixgbe_mac_X540:
2330 mask = (qmask & 0xFFFFFFFF);
2331 if (mask)
2332 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2333 mask = (qmask >> 32);
2334 if (mask)
2335 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2336 break;
2337 default:
2338 break;
2339 }
2340 /* skip the flush */
2341 }
2342
2343 /**
2344 * ixgbe_irq_enable - Enable default interrupt generation settings
2345 * @adapter: board private structure
2346 **/
2347 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2348 bool flush)
2349 {
2350 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2351
2352 /* don't reenable LSC while waiting for link */
2353 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2354 mask &= ~IXGBE_EIMS_LSC;
2355
2356 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2357 switch (adapter->hw.mac.type) {
2358 case ixgbe_mac_82599EB:
2359 mask |= IXGBE_EIMS_GPI_SDP0;
2360 break;
2361 case ixgbe_mac_X540:
2362 mask |= IXGBE_EIMS_TS;
2363 break;
2364 default:
2365 break;
2366 }
2367 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2368 mask |= IXGBE_EIMS_GPI_SDP1;
2369 switch (adapter->hw.mac.type) {
2370 case ixgbe_mac_82599EB:
2371 mask |= IXGBE_EIMS_GPI_SDP1;
2372 mask |= IXGBE_EIMS_GPI_SDP2;
2373 case ixgbe_mac_X540:
2374 mask |= IXGBE_EIMS_ECC;
2375 mask |= IXGBE_EIMS_MAILBOX;
2376 break;
2377 default:
2378 break;
2379 }
2380
2381 if (adapter->hw.mac.type == ixgbe_mac_X540)
2382 mask |= IXGBE_EIMS_TIMESYNC;
2383
2384 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2385 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2386 mask |= IXGBE_EIMS_FLOW_DIR;
2387
2388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2389 if (queues)
2390 ixgbe_irq_enable_queues(adapter, ~0);
2391 if (flush)
2392 IXGBE_WRITE_FLUSH(&adapter->hw);
2393 }
2394
2395 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2396 {
2397 struct ixgbe_adapter *adapter = data;
2398 struct ixgbe_hw *hw = &adapter->hw;
2399 u32 eicr;
2400
2401 /*
2402 * Workaround for Silicon errata. Use clear-by-write instead
2403 * of clear-by-read. Reading with EICS will return the
2404 * interrupt causes without clearing, which later be done
2405 * with the write to EICR.
2406 */
2407 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2408 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2409
2410 if (eicr & IXGBE_EICR_LSC)
2411 ixgbe_check_lsc(adapter);
2412
2413 if (eicr & IXGBE_EICR_MAILBOX)
2414 ixgbe_msg_task(adapter);
2415
2416 switch (hw->mac.type) {
2417 case ixgbe_mac_82599EB:
2418 case ixgbe_mac_X540:
2419 if (eicr & IXGBE_EICR_ECC)
2420 e_info(link, "Received unrecoverable ECC Err, please "
2421 "reboot\n");
2422 /* Handle Flow Director Full threshold interrupt */
2423 if (eicr & IXGBE_EICR_FLOW_DIR) {
2424 int reinit_count = 0;
2425 int i;
2426 for (i = 0; i < adapter->num_tx_queues; i++) {
2427 struct ixgbe_ring *ring = adapter->tx_ring[i];
2428 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2429 &ring->state))
2430 reinit_count++;
2431 }
2432 if (reinit_count) {
2433 /* no more flow director interrupts until after init */
2434 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2435 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2436 ixgbe_service_event_schedule(adapter);
2437 }
2438 }
2439 ixgbe_check_sfp_event(adapter, eicr);
2440 ixgbe_check_overtemp_event(adapter, eicr);
2441 break;
2442 default:
2443 break;
2444 }
2445
2446 ixgbe_check_fan_failure(adapter, eicr);
2447
2448 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2449 ixgbe_ptp_check_pps_event(adapter, eicr);
2450
2451 /* re-enable the original interrupt state, no lsc, no queues */
2452 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2453 ixgbe_irq_enable(adapter, false, false);
2454
2455 return IRQ_HANDLED;
2456 }
2457
2458 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2459 {
2460 struct ixgbe_q_vector *q_vector = data;
2461
2462 /* EIAM disabled interrupts (on this vector) for us */
2463
2464 if (q_vector->rx.ring || q_vector->tx.ring)
2465 napi_schedule(&q_vector->napi);
2466
2467 return IRQ_HANDLED;
2468 }
2469
2470 /**
2471 * ixgbe_poll - NAPI Rx polling callback
2472 * @napi: structure for representing this polling device
2473 * @budget: how many packets driver is allowed to clean
2474 *
2475 * This function is used for legacy and MSI, NAPI mode
2476 **/
2477 int ixgbe_poll(struct napi_struct *napi, int budget)
2478 {
2479 struct ixgbe_q_vector *q_vector =
2480 container_of(napi, struct ixgbe_q_vector, napi);
2481 struct ixgbe_adapter *adapter = q_vector->adapter;
2482 struct ixgbe_ring *ring;
2483 int per_ring_budget;
2484 bool clean_complete = true;
2485
2486 #ifdef CONFIG_IXGBE_DCA
2487 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2488 ixgbe_update_dca(q_vector);
2489 #endif
2490
2491 ixgbe_for_each_ring(ring, q_vector->tx)
2492 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2493
2494 /* attempt to distribute budget to each queue fairly, but don't allow
2495 * the budget to go below 1 because we'll exit polling */
2496 if (q_vector->rx.count > 1)
2497 per_ring_budget = max(budget/q_vector->rx.count, 1);
2498 else
2499 per_ring_budget = budget;
2500
2501 ixgbe_for_each_ring(ring, q_vector->rx)
2502 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2503 per_ring_budget);
2504
2505 /* If all work not completed, return budget and keep polling */
2506 if (!clean_complete)
2507 return budget;
2508
2509 /* all work done, exit the polling mode */
2510 napi_complete(napi);
2511 if (adapter->rx_itr_setting & 1)
2512 ixgbe_set_itr(q_vector);
2513 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2514 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2515
2516 return 0;
2517 }
2518
2519 /**
2520 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2521 * @adapter: board private structure
2522 *
2523 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2524 * interrupts from the kernel.
2525 **/
2526 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2527 {
2528 struct net_device *netdev = adapter->netdev;
2529 int vector, err;
2530 int ri = 0, ti = 0;
2531
2532 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2533 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2534 struct msix_entry *entry = &adapter->msix_entries[vector];
2535
2536 if (q_vector->tx.ring && q_vector->rx.ring) {
2537 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2538 "%s-%s-%d", netdev->name, "TxRx", ri++);
2539 ti++;
2540 } else if (q_vector->rx.ring) {
2541 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2542 "%s-%s-%d", netdev->name, "rx", ri++);
2543 } else if (q_vector->tx.ring) {
2544 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2545 "%s-%s-%d", netdev->name, "tx", ti++);
2546 } else {
2547 /* skip this unused q_vector */
2548 continue;
2549 }
2550 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2551 q_vector->name, q_vector);
2552 if (err) {
2553 e_err(probe, "request_irq failed for MSIX interrupt "
2554 "Error: %d\n", err);
2555 goto free_queue_irqs;
2556 }
2557 /* If Flow Director is enabled, set interrupt affinity */
2558 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2559 /* assign the mask for this irq */
2560 irq_set_affinity_hint(entry->vector,
2561 &q_vector->affinity_mask);
2562 }
2563 }
2564
2565 err = request_irq(adapter->msix_entries[vector].vector,
2566 ixgbe_msix_other, 0, netdev->name, adapter);
2567 if (err) {
2568 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2569 goto free_queue_irqs;
2570 }
2571
2572 return 0;
2573
2574 free_queue_irqs:
2575 while (vector) {
2576 vector--;
2577 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2578 NULL);
2579 free_irq(adapter->msix_entries[vector].vector,
2580 adapter->q_vector[vector]);
2581 }
2582 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2583 pci_disable_msix(adapter->pdev);
2584 kfree(adapter->msix_entries);
2585 adapter->msix_entries = NULL;
2586 return err;
2587 }
2588
2589 /**
2590 * ixgbe_intr - legacy mode Interrupt Handler
2591 * @irq: interrupt number
2592 * @data: pointer to a network interface device structure
2593 **/
2594 static irqreturn_t ixgbe_intr(int irq, void *data)
2595 {
2596 struct ixgbe_adapter *adapter = data;
2597 struct ixgbe_hw *hw = &adapter->hw;
2598 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2599 u32 eicr;
2600
2601 /*
2602 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2603 * before the read of EICR.
2604 */
2605 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2606
2607 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2608 * therefore no explicit interrupt disable is necessary */
2609 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2610 if (!eicr) {
2611 /*
2612 * shared interrupt alert!
2613 * make sure interrupts are enabled because the read will
2614 * have disabled interrupts due to EIAM
2615 * finish the workaround of silicon errata on 82598. Unmask
2616 * the interrupt that we masked before the EICR read.
2617 */
2618 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2619 ixgbe_irq_enable(adapter, true, true);
2620 return IRQ_NONE; /* Not our interrupt */
2621 }
2622
2623 if (eicr & IXGBE_EICR_LSC)
2624 ixgbe_check_lsc(adapter);
2625
2626 switch (hw->mac.type) {
2627 case ixgbe_mac_82599EB:
2628 ixgbe_check_sfp_event(adapter, eicr);
2629 /* Fall through */
2630 case ixgbe_mac_X540:
2631 if (eicr & IXGBE_EICR_ECC)
2632 e_info(link, "Received unrecoverable ECC err, please "
2633 "reboot\n");
2634 ixgbe_check_overtemp_event(adapter, eicr);
2635 break;
2636 default:
2637 break;
2638 }
2639
2640 ixgbe_check_fan_failure(adapter, eicr);
2641 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2642 ixgbe_ptp_check_pps_event(adapter, eicr);
2643
2644 /* would disable interrupts here but EIAM disabled it */
2645 napi_schedule(&q_vector->napi);
2646
2647 /*
2648 * re-enable link(maybe) and non-queue interrupts, no flush.
2649 * ixgbe_poll will re-enable the queue interrupts
2650 */
2651 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2652 ixgbe_irq_enable(adapter, false, false);
2653
2654 return IRQ_HANDLED;
2655 }
2656
2657 /**
2658 * ixgbe_request_irq - initialize interrupts
2659 * @adapter: board private structure
2660 *
2661 * Attempts to configure interrupts using the best available
2662 * capabilities of the hardware and kernel.
2663 **/
2664 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2665 {
2666 struct net_device *netdev = adapter->netdev;
2667 int err;
2668
2669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2670 err = ixgbe_request_msix_irqs(adapter);
2671 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2672 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2673 netdev->name, adapter);
2674 else
2675 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2676 netdev->name, adapter);
2677
2678 if (err)
2679 e_err(probe, "request_irq failed, Error %d\n", err);
2680
2681 return err;
2682 }
2683
2684 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2685 {
2686 int vector;
2687
2688 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2689 free_irq(adapter->pdev->irq, adapter);
2690 return;
2691 }
2692
2693 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2694 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2695 struct msix_entry *entry = &adapter->msix_entries[vector];
2696
2697 /* free only the irqs that were actually requested */
2698 if (!q_vector->rx.ring && !q_vector->tx.ring)
2699 continue;
2700
2701 /* clear the affinity_mask in the IRQ descriptor */
2702 irq_set_affinity_hint(entry->vector, NULL);
2703
2704 free_irq(entry->vector, q_vector);
2705 }
2706
2707 free_irq(adapter->msix_entries[vector++].vector, adapter);
2708 }
2709
2710 /**
2711 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2712 * @adapter: board private structure
2713 **/
2714 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2715 {
2716 switch (adapter->hw.mac.type) {
2717 case ixgbe_mac_82598EB:
2718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2719 break;
2720 case ixgbe_mac_82599EB:
2721 case ixgbe_mac_X540:
2722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2725 break;
2726 default:
2727 break;
2728 }
2729 IXGBE_WRITE_FLUSH(&adapter->hw);
2730 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2731 int vector;
2732
2733 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2734 synchronize_irq(adapter->msix_entries[vector].vector);
2735
2736 synchronize_irq(adapter->msix_entries[vector++].vector);
2737 } else {
2738 synchronize_irq(adapter->pdev->irq);
2739 }
2740 }
2741
2742 /**
2743 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2744 *
2745 **/
2746 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2747 {
2748 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2749
2750 ixgbe_write_eitr(q_vector);
2751
2752 ixgbe_set_ivar(adapter, 0, 0, 0);
2753 ixgbe_set_ivar(adapter, 1, 0, 0);
2754
2755 e_info(hw, "Legacy interrupt IVAR setup done\n");
2756 }
2757
2758 /**
2759 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2760 * @adapter: board private structure
2761 * @ring: structure containing ring specific data
2762 *
2763 * Configure the Tx descriptor ring after a reset.
2764 **/
2765 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2766 struct ixgbe_ring *ring)
2767 {
2768 struct ixgbe_hw *hw = &adapter->hw;
2769 u64 tdba = ring->dma;
2770 int wait_loop = 10;
2771 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2772 u8 reg_idx = ring->reg_idx;
2773
2774 /* disable queue to avoid issues while updating state */
2775 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2776 IXGBE_WRITE_FLUSH(hw);
2777
2778 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2779 (tdba & DMA_BIT_MASK(32)));
2780 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2781 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2782 ring->count * sizeof(union ixgbe_adv_tx_desc));
2783 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2784 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2785 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2786
2787 /*
2788 * set WTHRESH to encourage burst writeback, it should not be set
2789 * higher than 1 when:
2790 * - ITR is 0 as it could cause false TX hangs
2791 * - ITR is set to > 100k int/sec and BQL is enabled
2792 *
2793 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2794 * to or less than the number of on chip descriptors, which is
2795 * currently 40.
2796 */
2797 #if IS_ENABLED(CONFIG_BQL)
2798 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2799 #else
2800 if (!ring->q_vector || (ring->q_vector->itr < 8))
2801 #endif
2802 txdctl |= (1 << 16); /* WTHRESH = 1 */
2803 else
2804 txdctl |= (8 << 16); /* WTHRESH = 8 */
2805
2806 /*
2807 * Setting PTHRESH to 32 both improves performance
2808 * and avoids a TX hang with DFP enabled
2809 */
2810 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2811 32; /* PTHRESH = 32 */
2812
2813 /* reinitialize flowdirector state */
2814 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2815 ring->atr_sample_rate = adapter->atr_sample_rate;
2816 ring->atr_count = 0;
2817 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2818 } else {
2819 ring->atr_sample_rate = 0;
2820 }
2821
2822 /* initialize XPS */
2823 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2824 struct ixgbe_q_vector *q_vector = ring->q_vector;
2825
2826 if (q_vector)
2827 netif_set_xps_queue(adapter->netdev,
2828 &q_vector->affinity_mask,
2829 ring->queue_index);
2830 }
2831
2832 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2833
2834 /* enable queue */
2835 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2836
2837 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2838 if (hw->mac.type == ixgbe_mac_82598EB &&
2839 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2840 return;
2841
2842 /* poll to verify queue is enabled */
2843 do {
2844 usleep_range(1000, 2000);
2845 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2846 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2847 if (!wait_loop)
2848 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2849 }
2850
2851 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2852 {
2853 struct ixgbe_hw *hw = &adapter->hw;
2854 u32 rttdcs, mtqc;
2855 u8 tcs = netdev_get_num_tc(adapter->netdev);
2856
2857 if (hw->mac.type == ixgbe_mac_82598EB)
2858 return;
2859
2860 /* disable the arbiter while setting MTQC */
2861 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2862 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2863 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2864
2865 /* set transmit pool layout */
2866 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2867 mtqc = IXGBE_MTQC_VT_ENA;
2868 if (tcs > 4)
2869 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2870 else if (tcs > 1)
2871 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2872 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2873 mtqc |= IXGBE_MTQC_32VF;
2874 else
2875 mtqc |= IXGBE_MTQC_64VF;
2876 } else {
2877 if (tcs > 4)
2878 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2879 else if (tcs > 1)
2880 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2881 else
2882 mtqc = IXGBE_MTQC_64Q_1PB;
2883 }
2884
2885 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2886
2887 /* Enable Security TX Buffer IFG for multiple pb */
2888 if (tcs) {
2889 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2890 sectx |= IXGBE_SECTX_DCB;
2891 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2892 }
2893
2894 /* re-enable the arbiter */
2895 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2896 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2897 }
2898
2899 /**
2900 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2901 * @adapter: board private structure
2902 *
2903 * Configure the Tx unit of the MAC after a reset.
2904 **/
2905 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2906 {
2907 struct ixgbe_hw *hw = &adapter->hw;
2908 u32 dmatxctl;
2909 u32 i;
2910
2911 ixgbe_setup_mtqc(adapter);
2912
2913 if (hw->mac.type != ixgbe_mac_82598EB) {
2914 /* DMATXCTL.EN must be before Tx queues are enabled */
2915 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2916 dmatxctl |= IXGBE_DMATXCTL_TE;
2917 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2918 }
2919
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2921 for (i = 0; i < adapter->num_tx_queues; i++)
2922 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2923 }
2924
2925 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2926 struct ixgbe_ring *ring)
2927 {
2928 struct ixgbe_hw *hw = &adapter->hw;
2929 u8 reg_idx = ring->reg_idx;
2930 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2931
2932 srrctl |= IXGBE_SRRCTL_DROP_EN;
2933
2934 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2935 }
2936
2937 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2938 struct ixgbe_ring *ring)
2939 {
2940 struct ixgbe_hw *hw = &adapter->hw;
2941 u8 reg_idx = ring->reg_idx;
2942 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2943
2944 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2945
2946 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2947 }
2948
2949 #ifdef CONFIG_IXGBE_DCB
2950 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2951 #else
2952 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2953 #endif
2954 {
2955 int i;
2956 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2957
2958 if (adapter->ixgbe_ieee_pfc)
2959 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2960
2961 /*
2962 * We should set the drop enable bit if:
2963 * SR-IOV is enabled
2964 * or
2965 * Number of Rx queues > 1 and flow control is disabled
2966 *
2967 * This allows us to avoid head of line blocking for security
2968 * and performance reasons.
2969 */
2970 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2971 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2972 for (i = 0; i < adapter->num_rx_queues; i++)
2973 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2974 } else {
2975 for (i = 0; i < adapter->num_rx_queues; i++)
2976 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2977 }
2978 }
2979
2980 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2981
2982 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2983 struct ixgbe_ring *rx_ring)
2984 {
2985 struct ixgbe_hw *hw = &adapter->hw;
2986 u32 srrctl;
2987 u8 reg_idx = rx_ring->reg_idx;
2988
2989 if (hw->mac.type == ixgbe_mac_82598EB) {
2990 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2991
2992 /*
2993 * if VMDq is not active we must program one srrctl register
2994 * per RSS queue since we have enabled RDRXCTL.MVMEN
2995 */
2996 reg_idx &= mask;
2997 }
2998
2999 /* configure header buffer length, needed for RSC */
3000 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3001
3002 /* configure the packet buffer length */
3003 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3004
3005 /* configure descriptor type */
3006 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3007
3008 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3009 }
3010
3011 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3012 {
3013 struct ixgbe_hw *hw = &adapter->hw;
3014 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3015 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3016 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3017 u32 mrqc = 0, reta = 0;
3018 u32 rxcsum;
3019 int i, j;
3020 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3021
3022 /*
3023 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3024 * make full use of any rings they may have. We will use the
3025 * PSRTYPE register to control how many rings we use within the PF.
3026 */
3027 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3028 rss_i = 2;
3029
3030 /* Fill out hash function seeds */
3031 for (i = 0; i < 10; i++)
3032 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3033
3034 /* Fill out redirection table */
3035 for (i = 0, j = 0; i < 128; i++, j++) {
3036 if (j == rss_i)
3037 j = 0;
3038 /* reta = 4-byte sliding window of
3039 * 0x00..(indices-1)(indices-1)00..etc. */
3040 reta = (reta << 8) | (j * 0x11);
3041 if ((i & 3) == 3)
3042 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3043 }
3044
3045 /* Disable indicating checksum in descriptor, enables RSS hash */
3046 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3047 rxcsum |= IXGBE_RXCSUM_PCSD;
3048 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3049
3050 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3051 if (adapter->ring_feature[RING_F_RSS].mask)
3052 mrqc = IXGBE_MRQC_RSSEN;
3053 } else {
3054 u8 tcs = netdev_get_num_tc(adapter->netdev);
3055
3056 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3057 if (tcs > 4)
3058 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3059 else if (tcs > 1)
3060 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3061 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3062 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3063 else
3064 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3065 } else {
3066 if (tcs > 4)
3067 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3068 else if (tcs > 1)
3069 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3070 else
3071 mrqc = IXGBE_MRQC_RSSEN;
3072 }
3073 }
3074
3075 /* Perform hash on these packet types */
3076 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3077 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3078 IXGBE_MRQC_RSS_FIELD_IPV6 |
3079 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3080
3081 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3082 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3083 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3084 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3085
3086 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3087 }
3088
3089 /**
3090 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3091 * @adapter: address of board private structure
3092 * @index: index of ring to set
3093 **/
3094 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3095 struct ixgbe_ring *ring)
3096 {
3097 struct ixgbe_hw *hw = &adapter->hw;
3098 u32 rscctrl;
3099 u8 reg_idx = ring->reg_idx;
3100
3101 if (!ring_is_rsc_enabled(ring))
3102 return;
3103
3104 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3105 rscctrl |= IXGBE_RSCCTL_RSCEN;
3106 /*
3107 * we must limit the number of descriptors so that the
3108 * total size of max desc * buf_len is not greater
3109 * than 65536
3110 */
3111 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3112 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3113 }
3114
3115 #define IXGBE_MAX_RX_DESC_POLL 10
3116 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3117 struct ixgbe_ring *ring)
3118 {
3119 struct ixgbe_hw *hw = &adapter->hw;
3120 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3121 u32 rxdctl;
3122 u8 reg_idx = ring->reg_idx;
3123
3124 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3125 if (hw->mac.type == ixgbe_mac_82598EB &&
3126 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3127 return;
3128
3129 do {
3130 usleep_range(1000, 2000);
3131 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3132 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3133
3134 if (!wait_loop) {
3135 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3136 "the polling period\n", reg_idx);
3137 }
3138 }
3139
3140 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3141 struct ixgbe_ring *ring)
3142 {
3143 struct ixgbe_hw *hw = &adapter->hw;
3144 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3145 u32 rxdctl;
3146 u8 reg_idx = ring->reg_idx;
3147
3148 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3149 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3150
3151 /* write value back with RXDCTL.ENABLE bit cleared */
3152 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3153
3154 if (hw->mac.type == ixgbe_mac_82598EB &&
3155 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3156 return;
3157
3158 /* the hardware may take up to 100us to really disable the rx queue */
3159 do {
3160 udelay(10);
3161 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3162 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3163
3164 if (!wait_loop) {
3165 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3166 "the polling period\n", reg_idx);
3167 }
3168 }
3169
3170 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3171 struct ixgbe_ring *ring)
3172 {
3173 struct ixgbe_hw *hw = &adapter->hw;
3174 u64 rdba = ring->dma;
3175 u32 rxdctl;
3176 u8 reg_idx = ring->reg_idx;
3177
3178 /* disable queue to avoid issues while updating state */
3179 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3180 ixgbe_disable_rx_queue(adapter, ring);
3181
3182 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3183 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3184 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3185 ring->count * sizeof(union ixgbe_adv_rx_desc));
3186 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3187 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3188 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3189
3190 ixgbe_configure_srrctl(adapter, ring);
3191 ixgbe_configure_rscctl(adapter, ring);
3192
3193 if (hw->mac.type == ixgbe_mac_82598EB) {
3194 /*
3195 * enable cache line friendly hardware writes:
3196 * PTHRESH=32 descriptors (half the internal cache),
3197 * this also removes ugly rx_no_buffer_count increment
3198 * HTHRESH=4 descriptors (to minimize latency on fetch)
3199 * WTHRESH=8 burst writeback up to two cache lines
3200 */
3201 rxdctl &= ~0x3FFFFF;
3202 rxdctl |= 0x080420;
3203 }
3204
3205 /* enable receive descriptor ring */
3206 rxdctl |= IXGBE_RXDCTL_ENABLE;
3207 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3208
3209 ixgbe_rx_desc_queue_enable(adapter, ring);
3210 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3211 }
3212
3213 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3214 {
3215 struct ixgbe_hw *hw = &adapter->hw;
3216 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3217 int p;
3218
3219 /* PSRTYPE must be initialized in non 82598 adapters */
3220 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3221 IXGBE_PSRTYPE_UDPHDR |
3222 IXGBE_PSRTYPE_IPV4HDR |
3223 IXGBE_PSRTYPE_L2HDR |
3224 IXGBE_PSRTYPE_IPV6HDR;
3225
3226 if (hw->mac.type == ixgbe_mac_82598EB)
3227 return;
3228
3229 if (rss_i > 3)
3230 psrtype |= 2 << 29;
3231 else if (rss_i > 1)
3232 psrtype |= 1 << 29;
3233
3234 for (p = 0; p < adapter->num_rx_pools; p++)
3235 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3236 psrtype);
3237 }
3238
3239 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3240 {
3241 struct ixgbe_hw *hw = &adapter->hw;
3242 u32 reg_offset, vf_shift;
3243 u32 gcr_ext, vmdctl;
3244 int i;
3245
3246 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3247 return;
3248
3249 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3250 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3251 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3252 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3253 vmdctl |= IXGBE_VT_CTL_REPLEN;
3254 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3255
3256 vf_shift = VMDQ_P(0) % 32;
3257 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3258
3259 /* Enable only the PF's pool for Tx/Rx */
3260 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3261 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3262 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3263 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3264 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3265 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3266
3267 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3268 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3269
3270 /*
3271 * Set up VF register offsets for selected VT Mode,
3272 * i.e. 32 or 64 VFs for SR-IOV
3273 */
3274 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3275 case IXGBE_82599_VMDQ_8Q_MASK:
3276 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3277 break;
3278 case IXGBE_82599_VMDQ_4Q_MASK:
3279 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3280 break;
3281 default:
3282 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3283 break;
3284 }
3285
3286 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3287
3288
3289 /* Enable MAC Anti-Spoofing */
3290 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3291 adapter->num_vfs);
3292 /* For VFs that have spoof checking turned off */
3293 for (i = 0; i < adapter->num_vfs; i++) {
3294 if (!adapter->vfinfo[i].spoofchk_enabled)
3295 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3296 }
3297 }
3298
3299 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3300 {
3301 struct ixgbe_hw *hw = &adapter->hw;
3302 struct net_device *netdev = adapter->netdev;
3303 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3304 struct ixgbe_ring *rx_ring;
3305 int i;
3306 u32 mhadd, hlreg0;
3307
3308 #ifdef IXGBE_FCOE
3309 /* adjust max frame to be able to do baby jumbo for FCoE */
3310 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3311 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3312 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3313
3314 #endif /* IXGBE_FCOE */
3315
3316 /* adjust max frame to be at least the size of a standard frame */
3317 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3318 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3319
3320 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3321 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3322 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3323 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3324
3325 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3326 }
3327
3328 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3329 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3330 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3331 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3332
3333 /*
3334 * Setup the HW Rx Head and Tail Descriptor Pointers and
3335 * the Base and Length of the Rx Descriptor Ring
3336 */
3337 for (i = 0; i < adapter->num_rx_queues; i++) {
3338 rx_ring = adapter->rx_ring[i];
3339 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3340 set_ring_rsc_enabled(rx_ring);
3341 else
3342 clear_ring_rsc_enabled(rx_ring);
3343 }
3344 }
3345
3346 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3347 {
3348 struct ixgbe_hw *hw = &adapter->hw;
3349 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3350
3351 switch (hw->mac.type) {
3352 case ixgbe_mac_82598EB:
3353 /*
3354 * For VMDq support of different descriptor types or
3355 * buffer sizes through the use of multiple SRRCTL
3356 * registers, RDRXCTL.MVMEN must be set to 1
3357 *
3358 * also, the manual doesn't mention it clearly but DCA hints
3359 * will only use queue 0's tags unless this bit is set. Side
3360 * effects of setting this bit are only that SRRCTL must be
3361 * fully programmed [0..15]
3362 */
3363 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3364 break;
3365 case ixgbe_mac_82599EB:
3366 case ixgbe_mac_X540:
3367 /* Disable RSC for ACK packets */
3368 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3369 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3370 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3371 /* hardware requires some bits to be set by default */
3372 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3373 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3374 break;
3375 default:
3376 /* We should do nothing since we don't know this hardware */
3377 return;
3378 }
3379
3380 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3381 }
3382
3383 /**
3384 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3385 * @adapter: board private structure
3386 *
3387 * Configure the Rx unit of the MAC after a reset.
3388 **/
3389 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3390 {
3391 struct ixgbe_hw *hw = &adapter->hw;
3392 int i;
3393 u32 rxctrl;
3394
3395 /* disable receives while setting up the descriptors */
3396 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3397 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3398
3399 ixgbe_setup_psrtype(adapter);
3400 ixgbe_setup_rdrxctl(adapter);
3401
3402 /* Program registers for the distribution of queues */
3403 ixgbe_setup_mrqc(adapter);
3404
3405 /* set_rx_buffer_len must be called before ring initialization */
3406 ixgbe_set_rx_buffer_len(adapter);
3407
3408 /*
3409 * Setup the HW Rx Head and Tail Descriptor Pointers and
3410 * the Base and Length of the Rx Descriptor Ring
3411 */
3412 for (i = 0; i < adapter->num_rx_queues; i++)
3413 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3414
3415 /* disable drop enable for 82598 parts */
3416 if (hw->mac.type == ixgbe_mac_82598EB)
3417 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3418
3419 /* enable all receives */
3420 rxctrl |= IXGBE_RXCTRL_RXEN;
3421 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3422 }
3423
3424 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3425 {
3426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3427 struct ixgbe_hw *hw = &adapter->hw;
3428
3429 /* add VID to filter table */
3430 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3431 set_bit(vid, adapter->active_vlans);
3432
3433 return 0;
3434 }
3435
3436 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3437 {
3438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3439 struct ixgbe_hw *hw = &adapter->hw;
3440
3441 /* remove VID from filter table */
3442 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3443 clear_bit(vid, adapter->active_vlans);
3444
3445 return 0;
3446 }
3447
3448 /**
3449 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3450 * @adapter: driver data
3451 */
3452 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3453 {
3454 struct ixgbe_hw *hw = &adapter->hw;
3455 u32 vlnctrl;
3456
3457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3458 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3459 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3460 }
3461
3462 /**
3463 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3464 * @adapter: driver data
3465 */
3466 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3467 {
3468 struct ixgbe_hw *hw = &adapter->hw;
3469 u32 vlnctrl;
3470
3471 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3472 vlnctrl |= IXGBE_VLNCTRL_VFE;
3473 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3474 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3475 }
3476
3477 /**
3478 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3479 * @adapter: driver data
3480 */
3481 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3482 {
3483 struct ixgbe_hw *hw = &adapter->hw;
3484 u32 vlnctrl;
3485 int i, j;
3486
3487 switch (hw->mac.type) {
3488 case ixgbe_mac_82598EB:
3489 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3490 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3491 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3492 break;
3493 case ixgbe_mac_82599EB:
3494 case ixgbe_mac_X540:
3495 for (i = 0; i < adapter->num_rx_queues; i++) {
3496 j = adapter->rx_ring[i]->reg_idx;
3497 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3498 vlnctrl &= ~IXGBE_RXDCTL_VME;
3499 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3500 }
3501 break;
3502 default:
3503 break;
3504 }
3505 }
3506
3507 /**
3508 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3509 * @adapter: driver data
3510 */
3511 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3512 {
3513 struct ixgbe_hw *hw = &adapter->hw;
3514 u32 vlnctrl;
3515 int i, j;
3516
3517 switch (hw->mac.type) {
3518 case ixgbe_mac_82598EB:
3519 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3520 vlnctrl |= IXGBE_VLNCTRL_VME;
3521 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3522 break;
3523 case ixgbe_mac_82599EB:
3524 case ixgbe_mac_X540:
3525 for (i = 0; i < adapter->num_rx_queues; i++) {
3526 j = adapter->rx_ring[i]->reg_idx;
3527 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3528 vlnctrl |= IXGBE_RXDCTL_VME;
3529 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3530 }
3531 break;
3532 default:
3533 break;
3534 }
3535 }
3536
3537 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3538 {
3539 u16 vid;
3540
3541 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3542
3543 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3544 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3545 }
3546
3547 /**
3548 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3549 * @netdev: network interface device structure
3550 *
3551 * Writes unicast address list to the RAR table.
3552 * Returns: -ENOMEM on failure/insufficient address space
3553 * 0 on no addresses written
3554 * X on writing X addresses to the RAR table
3555 **/
3556 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3557 {
3558 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3559 struct ixgbe_hw *hw = &adapter->hw;
3560 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3561 int count = 0;
3562
3563 /* In SR-IOV mode significantly less RAR entries are available */
3564 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3565 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3566
3567 /* return ENOMEM indicating insufficient memory for addresses */
3568 if (netdev_uc_count(netdev) > rar_entries)
3569 return -ENOMEM;
3570
3571 if (!netdev_uc_empty(netdev)) {
3572 struct netdev_hw_addr *ha;
3573 /* return error if we do not support writing to RAR table */
3574 if (!hw->mac.ops.set_rar)
3575 return -ENOMEM;
3576
3577 netdev_for_each_uc_addr(ha, netdev) {
3578 if (!rar_entries)
3579 break;
3580 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3581 VMDQ_P(0), IXGBE_RAH_AV);
3582 count++;
3583 }
3584 }
3585 /* write the addresses in reverse order to avoid write combining */
3586 for (; rar_entries > 0 ; rar_entries--)
3587 hw->mac.ops.clear_rar(hw, rar_entries);
3588
3589 return count;
3590 }
3591
3592 /**
3593 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3594 * @netdev: network interface device structure
3595 *
3596 * The set_rx_method entry point is called whenever the unicast/multicast
3597 * address list or the network interface flags are updated. This routine is
3598 * responsible for configuring the hardware for proper unicast, multicast and
3599 * promiscuous mode.
3600 **/
3601 void ixgbe_set_rx_mode(struct net_device *netdev)
3602 {
3603 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3604 struct ixgbe_hw *hw = &adapter->hw;
3605 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3606 int count;
3607
3608 /* Check for Promiscuous and All Multicast modes */
3609
3610 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611
3612 /* set all bits that we expect to always be set */
3613 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3614 fctrl |= IXGBE_FCTRL_BAM;
3615 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3616 fctrl |= IXGBE_FCTRL_PMCF;
3617
3618 /* clear the bits we are changing the status of */
3619 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3620
3621 if (netdev->flags & IFF_PROMISC) {
3622 hw->addr_ctrl.user_set_promisc = true;
3623 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3624 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3625 /* don't hardware filter vlans in promisc mode */
3626 ixgbe_vlan_filter_disable(adapter);
3627 } else {
3628 if (netdev->flags & IFF_ALLMULTI) {
3629 fctrl |= IXGBE_FCTRL_MPE;
3630 vmolr |= IXGBE_VMOLR_MPE;
3631 } else {
3632 /*
3633 * Write addresses to the MTA, if the attempt fails
3634 * then we should just turn on promiscuous mode so
3635 * that we can at least receive multicast traffic
3636 */
3637 hw->mac.ops.update_mc_addr_list(hw, netdev);
3638 vmolr |= IXGBE_VMOLR_ROMPE;
3639 }
3640 ixgbe_vlan_filter_enable(adapter);
3641 hw->addr_ctrl.user_set_promisc = false;
3642 }
3643
3644 /*
3645 * Write addresses to available RAR registers, if there is not
3646 * sufficient space to store all the addresses then enable
3647 * unicast promiscuous mode
3648 */
3649 count = ixgbe_write_uc_addr_list(netdev);
3650 if (count < 0) {
3651 fctrl |= IXGBE_FCTRL_UPE;
3652 vmolr |= IXGBE_VMOLR_ROPE;
3653 }
3654
3655 if (adapter->num_vfs)
3656 ixgbe_restore_vf_multicasts(adapter);
3657
3658 if (hw->mac.type != ixgbe_mac_82598EB) {
3659 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3660 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3661 IXGBE_VMOLR_ROPE);
3662 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3663 }
3664
3665 /* This is useful for sniffing bad packets. */
3666 if (adapter->netdev->features & NETIF_F_RXALL) {
3667 /* UPE and MPE will be handled by normal PROMISC logic
3668 * in e1000e_set_rx_mode */
3669 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3670 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3671 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3672
3673 fctrl &= ~(IXGBE_FCTRL_DPF);
3674 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3675 }
3676
3677 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3678
3679 if (netdev->features & NETIF_F_HW_VLAN_RX)
3680 ixgbe_vlan_strip_enable(adapter);
3681 else
3682 ixgbe_vlan_strip_disable(adapter);
3683 }
3684
3685 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3686 {
3687 int q_idx;
3688
3689 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3690 napi_enable(&adapter->q_vector[q_idx]->napi);
3691 }
3692
3693 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3694 {
3695 int q_idx;
3696
3697 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3698 napi_disable(&adapter->q_vector[q_idx]->napi);
3699 }
3700
3701 #ifdef CONFIG_IXGBE_DCB
3702 /**
3703 * ixgbe_configure_dcb - Configure DCB hardware
3704 * @adapter: ixgbe adapter struct
3705 *
3706 * This is called by the driver on open to configure the DCB hardware.
3707 * This is also called by the gennetlink interface when reconfiguring
3708 * the DCB state.
3709 */
3710 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3711 {
3712 struct ixgbe_hw *hw = &adapter->hw;
3713 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3714
3715 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3716 if (hw->mac.type == ixgbe_mac_82598EB)
3717 netif_set_gso_max_size(adapter->netdev, 65536);
3718 return;
3719 }
3720
3721 if (hw->mac.type == ixgbe_mac_82598EB)
3722 netif_set_gso_max_size(adapter->netdev, 32768);
3723
3724 #ifdef IXGBE_FCOE
3725 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3726 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3727 #endif
3728
3729 /* reconfigure the hardware */
3730 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3731 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3732 DCB_TX_CONFIG);
3733 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3734 DCB_RX_CONFIG);
3735 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3736 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3737 ixgbe_dcb_hw_ets(&adapter->hw,
3738 adapter->ixgbe_ieee_ets,
3739 max_frame);
3740 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3741 adapter->ixgbe_ieee_pfc->pfc_en,
3742 adapter->ixgbe_ieee_ets->prio_tc);
3743 }
3744
3745 /* Enable RSS Hash per TC */
3746 if (hw->mac.type != ixgbe_mac_82598EB) {
3747 u32 msb = 0;
3748 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3749
3750 while (rss_i) {
3751 msb++;
3752 rss_i >>= 1;
3753 }
3754
3755 /* write msb to all 8 TCs in one write */
3756 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3757 }
3758 }
3759 #endif
3760
3761 /* Additional bittime to account for IXGBE framing */
3762 #define IXGBE_ETH_FRAMING 20
3763
3764 /**
3765 * ixgbe_hpbthresh - calculate high water mark for flow control
3766 *
3767 * @adapter: board private structure to calculate for
3768 * @pb: packet buffer to calculate
3769 */
3770 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3771 {
3772 struct ixgbe_hw *hw = &adapter->hw;
3773 struct net_device *dev = adapter->netdev;
3774 int link, tc, kb, marker;
3775 u32 dv_id, rx_pba;
3776
3777 /* Calculate max LAN frame size */
3778 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3779
3780 #ifdef IXGBE_FCOE
3781 /* FCoE traffic class uses FCOE jumbo frames */
3782 if ((dev->features & NETIF_F_FCOE_MTU) &&
3783 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3784 (pb == ixgbe_fcoe_get_tc(adapter)))
3785 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3786
3787 #endif
3788 /* Calculate delay value for device */
3789 switch (hw->mac.type) {
3790 case ixgbe_mac_X540:
3791 dv_id = IXGBE_DV_X540(link, tc);
3792 break;
3793 default:
3794 dv_id = IXGBE_DV(link, tc);
3795 break;
3796 }
3797
3798 /* Loopback switch introduces additional latency */
3799 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3800 dv_id += IXGBE_B2BT(tc);
3801
3802 /* Delay value is calculated in bit times convert to KB */
3803 kb = IXGBE_BT2KB(dv_id);
3804 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3805
3806 marker = rx_pba - kb;
3807
3808 /* It is possible that the packet buffer is not large enough
3809 * to provide required headroom. In this case throw an error
3810 * to user and a do the best we can.
3811 */
3812 if (marker < 0) {
3813 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3814 "headroom to support flow control."
3815 "Decrease MTU or number of traffic classes\n", pb);
3816 marker = tc + 1;
3817 }
3818
3819 return marker;
3820 }
3821
3822 /**
3823 * ixgbe_lpbthresh - calculate low water mark for for flow control
3824 *
3825 * @adapter: board private structure to calculate for
3826 * @pb: packet buffer to calculate
3827 */
3828 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3829 {
3830 struct ixgbe_hw *hw = &adapter->hw;
3831 struct net_device *dev = adapter->netdev;
3832 int tc;
3833 u32 dv_id;
3834
3835 /* Calculate max LAN frame size */
3836 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3837
3838 /* Calculate delay value for device */
3839 switch (hw->mac.type) {
3840 case ixgbe_mac_X540:
3841 dv_id = IXGBE_LOW_DV_X540(tc);
3842 break;
3843 default:
3844 dv_id = IXGBE_LOW_DV(tc);
3845 break;
3846 }
3847
3848 /* Delay value is calculated in bit times convert to KB */
3849 return IXGBE_BT2KB(dv_id);
3850 }
3851
3852 /*
3853 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3854 */
3855 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3856 {
3857 struct ixgbe_hw *hw = &adapter->hw;
3858 int num_tc = netdev_get_num_tc(adapter->netdev);
3859 int i;
3860
3861 if (!num_tc)
3862 num_tc = 1;
3863
3864 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3865
3866 for (i = 0; i < num_tc; i++) {
3867 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3868
3869 /* Low water marks must not be larger than high water marks */
3870 if (hw->fc.low_water > hw->fc.high_water[i])
3871 hw->fc.low_water = 0;
3872 }
3873 }
3874
3875 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3876 {
3877 struct ixgbe_hw *hw = &adapter->hw;
3878 int hdrm;
3879 u8 tc = netdev_get_num_tc(adapter->netdev);
3880
3881 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3882 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3883 hdrm = 32 << adapter->fdir_pballoc;
3884 else
3885 hdrm = 0;
3886
3887 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3888 ixgbe_pbthresh_setup(adapter);
3889 }
3890
3891 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3892 {
3893 struct ixgbe_hw *hw = &adapter->hw;
3894 struct hlist_node *node2;
3895 struct ixgbe_fdir_filter *filter;
3896
3897 spin_lock(&adapter->fdir_perfect_lock);
3898
3899 if (!hlist_empty(&adapter->fdir_filter_list))
3900 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3901
3902 hlist_for_each_entry_safe(filter, node2,
3903 &adapter->fdir_filter_list, fdir_node) {
3904 ixgbe_fdir_write_perfect_filter_82599(hw,
3905 &filter->filter,
3906 filter->sw_idx,
3907 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3908 IXGBE_FDIR_DROP_QUEUE :
3909 adapter->rx_ring[filter->action]->reg_idx);
3910 }
3911
3912 spin_unlock(&adapter->fdir_perfect_lock);
3913 }
3914
3915 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3916 {
3917 struct ixgbe_hw *hw = &adapter->hw;
3918
3919 ixgbe_configure_pb(adapter);
3920 #ifdef CONFIG_IXGBE_DCB
3921 ixgbe_configure_dcb(adapter);
3922 #endif
3923 /*
3924 * We must restore virtualization before VLANs or else
3925 * the VLVF registers will not be populated
3926 */
3927 ixgbe_configure_virtualization(adapter);
3928
3929 ixgbe_set_rx_mode(adapter->netdev);
3930 ixgbe_restore_vlan(adapter);
3931
3932 switch (hw->mac.type) {
3933 case ixgbe_mac_82599EB:
3934 case ixgbe_mac_X540:
3935 hw->mac.ops.disable_rx_buff(hw);
3936 break;
3937 default:
3938 break;
3939 }
3940
3941 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3942 ixgbe_init_fdir_signature_82599(&adapter->hw,
3943 adapter->fdir_pballoc);
3944 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3945 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3946 adapter->fdir_pballoc);
3947 ixgbe_fdir_filter_restore(adapter);
3948 }
3949
3950 switch (hw->mac.type) {
3951 case ixgbe_mac_82599EB:
3952 case ixgbe_mac_X540:
3953 hw->mac.ops.enable_rx_buff(hw);
3954 break;
3955 default:
3956 break;
3957 }
3958
3959 #ifdef IXGBE_FCOE
3960 /* configure FCoE L2 filters, redirection table, and Rx control */
3961 ixgbe_configure_fcoe(adapter);
3962
3963 #endif /* IXGBE_FCOE */
3964 ixgbe_configure_tx(adapter);
3965 ixgbe_configure_rx(adapter);
3966 }
3967
3968 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3969 {
3970 switch (hw->phy.type) {
3971 case ixgbe_phy_sfp_avago:
3972 case ixgbe_phy_sfp_ftl:
3973 case ixgbe_phy_sfp_intel:
3974 case ixgbe_phy_sfp_unknown:
3975 case ixgbe_phy_sfp_passive_tyco:
3976 case ixgbe_phy_sfp_passive_unknown:
3977 case ixgbe_phy_sfp_active_unknown:
3978 case ixgbe_phy_sfp_ftl_active:
3979 return true;
3980 case ixgbe_phy_nl:
3981 if (hw->mac.type == ixgbe_mac_82598EB)
3982 return true;
3983 default:
3984 return false;
3985 }
3986 }
3987
3988 /**
3989 * ixgbe_sfp_link_config - set up SFP+ link
3990 * @adapter: pointer to private adapter struct
3991 **/
3992 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3993 {
3994 /*
3995 * We are assuming the worst case scenario here, and that
3996 * is that an SFP was inserted/removed after the reset
3997 * but before SFP detection was enabled. As such the best
3998 * solution is to just start searching as soon as we start
3999 */
4000 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4001 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4002
4003 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4004 }
4005
4006 /**
4007 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4008 * @hw: pointer to private hardware struct
4009 *
4010 * Returns 0 on success, negative on failure
4011 **/
4012 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4013 {
4014 u32 speed;
4015 bool autoneg, link_up = false;
4016 u32 ret = IXGBE_ERR_LINK_SETUP;
4017
4018 if (hw->mac.ops.check_link)
4019 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4020
4021 if (ret)
4022 goto link_cfg_out;
4023
4024 speed = hw->phy.autoneg_advertised;
4025 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4026 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4027 &autoneg);
4028 if (ret)
4029 goto link_cfg_out;
4030
4031 if (hw->mac.ops.setup_link)
4032 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4033 link_cfg_out:
4034 return ret;
4035 }
4036
4037 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4038 {
4039 struct ixgbe_hw *hw = &adapter->hw;
4040 u32 gpie = 0;
4041
4042 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4043 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4044 IXGBE_GPIE_OCD;
4045 gpie |= IXGBE_GPIE_EIAME;
4046 /*
4047 * use EIAM to auto-mask when MSI-X interrupt is asserted
4048 * this saves a register write for every interrupt
4049 */
4050 switch (hw->mac.type) {
4051 case ixgbe_mac_82598EB:
4052 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4053 break;
4054 case ixgbe_mac_82599EB:
4055 case ixgbe_mac_X540:
4056 default:
4057 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4058 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4059 break;
4060 }
4061 } else {
4062 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4063 * specifically only auto mask tx and rx interrupts */
4064 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4065 }
4066
4067 /* XXX: to interrupt immediately for EICS writes, enable this */
4068 /* gpie |= IXGBE_GPIE_EIMEN; */
4069
4070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4071 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4072
4073 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4074 case IXGBE_82599_VMDQ_8Q_MASK:
4075 gpie |= IXGBE_GPIE_VTMODE_16;
4076 break;
4077 case IXGBE_82599_VMDQ_4Q_MASK:
4078 gpie |= IXGBE_GPIE_VTMODE_32;
4079 break;
4080 default:
4081 gpie |= IXGBE_GPIE_VTMODE_64;
4082 break;
4083 }
4084 }
4085
4086 /* Enable Thermal over heat sensor interrupt */
4087 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4088 switch (adapter->hw.mac.type) {
4089 case ixgbe_mac_82599EB:
4090 gpie |= IXGBE_SDP0_GPIEN;
4091 break;
4092 case ixgbe_mac_X540:
4093 gpie |= IXGBE_EIMS_TS;
4094 break;
4095 default:
4096 break;
4097 }
4098 }
4099
4100 /* Enable fan failure interrupt */
4101 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4102 gpie |= IXGBE_SDP1_GPIEN;
4103
4104 if (hw->mac.type == ixgbe_mac_82599EB) {
4105 gpie |= IXGBE_SDP1_GPIEN;
4106 gpie |= IXGBE_SDP2_GPIEN;
4107 }
4108
4109 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4110 }
4111
4112 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4113 {
4114 struct ixgbe_hw *hw = &adapter->hw;
4115 int err;
4116 u32 ctrl_ext;
4117
4118 ixgbe_get_hw_control(adapter);
4119 ixgbe_setup_gpie(adapter);
4120
4121 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4122 ixgbe_configure_msix(adapter);
4123 else
4124 ixgbe_configure_msi_and_legacy(adapter);
4125
4126 /* enable the optics for 82599 SFP+ fiber */
4127 if (hw->mac.ops.enable_tx_laser)
4128 hw->mac.ops.enable_tx_laser(hw);
4129
4130 clear_bit(__IXGBE_DOWN, &adapter->state);
4131 ixgbe_napi_enable_all(adapter);
4132
4133 if (ixgbe_is_sfp(hw)) {
4134 ixgbe_sfp_link_config(adapter);
4135 } else {
4136 err = ixgbe_non_sfp_link_config(hw);
4137 if (err)
4138 e_err(probe, "link_config FAILED %d\n", err);
4139 }
4140
4141 /* clear any pending interrupts, may auto mask */
4142 IXGBE_READ_REG(hw, IXGBE_EICR);
4143 ixgbe_irq_enable(adapter, true, true);
4144
4145 /*
4146 * If this adapter has a fan, check to see if we had a failure
4147 * before we enabled the interrupt.
4148 */
4149 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4150 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4151 if (esdp & IXGBE_ESDP_SDP1)
4152 e_crit(drv, "Fan has stopped, replace the adapter\n");
4153 }
4154
4155 /* enable transmits */
4156 netif_tx_start_all_queues(adapter->netdev);
4157
4158 /* bring the link up in the watchdog, this could race with our first
4159 * link up interrupt but shouldn't be a problem */
4160 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4161 adapter->link_check_timeout = jiffies;
4162 mod_timer(&adapter->service_timer, jiffies);
4163
4164 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4165 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4166 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4167 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4168 }
4169
4170 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4171 {
4172 WARN_ON(in_interrupt());
4173 /* put off any impending NetWatchDogTimeout */
4174 adapter->netdev->trans_start = jiffies;
4175
4176 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4177 usleep_range(1000, 2000);
4178 ixgbe_down(adapter);
4179 /*
4180 * If SR-IOV enabled then wait a bit before bringing the adapter
4181 * back up to give the VFs time to respond to the reset. The
4182 * two second wait is based upon the watchdog timer cycle in
4183 * the VF driver.
4184 */
4185 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4186 msleep(2000);
4187 ixgbe_up(adapter);
4188 clear_bit(__IXGBE_RESETTING, &adapter->state);
4189 }
4190
4191 void ixgbe_up(struct ixgbe_adapter *adapter)
4192 {
4193 /* hardware has been reset, we need to reload some things */
4194 ixgbe_configure(adapter);
4195
4196 ixgbe_up_complete(adapter);
4197 }
4198
4199 void ixgbe_reset(struct ixgbe_adapter *adapter)
4200 {
4201 struct ixgbe_hw *hw = &adapter->hw;
4202 int err;
4203
4204 /* lock SFP init bit to prevent race conditions with the watchdog */
4205 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4206 usleep_range(1000, 2000);
4207
4208 /* clear all SFP and link config related flags while holding SFP_INIT */
4209 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4210 IXGBE_FLAG2_SFP_NEEDS_RESET);
4211 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4212
4213 err = hw->mac.ops.init_hw(hw);
4214 switch (err) {
4215 case 0:
4216 case IXGBE_ERR_SFP_NOT_PRESENT:
4217 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4218 break;
4219 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4220 e_dev_err("master disable timed out\n");
4221 break;
4222 case IXGBE_ERR_EEPROM_VERSION:
4223 /* We are running on a pre-production device, log a warning */
4224 e_dev_warn("This device is a pre-production adapter/LOM. "
4225 "Please be aware there may be issues associated with "
4226 "your hardware. If you are experiencing problems "
4227 "please contact your Intel or hardware "
4228 "representative who provided you with this "
4229 "hardware.\n");
4230 break;
4231 default:
4232 e_dev_err("Hardware Error: %d\n", err);
4233 }
4234
4235 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4236
4237 /* reprogram the RAR[0] in case user changed it. */
4238 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4239
4240 /* update SAN MAC vmdq pool selection */
4241 if (hw->mac.san_mac_rar_index)
4242 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4243
4244 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4245 ixgbe_ptp_reset(adapter);
4246 }
4247
4248 /**
4249 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4250 * @rx_ring: ring to free buffers from
4251 **/
4252 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4253 {
4254 struct device *dev = rx_ring->dev;
4255 unsigned long size;
4256 u16 i;
4257
4258 /* ring already cleared, nothing to do */
4259 if (!rx_ring->rx_buffer_info)
4260 return;
4261
4262 /* Free all the Rx ring sk_buffs */
4263 for (i = 0; i < rx_ring->count; i++) {
4264 struct ixgbe_rx_buffer *rx_buffer;
4265
4266 rx_buffer = &rx_ring->rx_buffer_info[i];
4267 if (rx_buffer->skb) {
4268 struct sk_buff *skb = rx_buffer->skb;
4269 if (IXGBE_CB(skb)->page_released) {
4270 dma_unmap_page(dev,
4271 IXGBE_CB(skb)->dma,
4272 ixgbe_rx_bufsz(rx_ring),
4273 DMA_FROM_DEVICE);
4274 IXGBE_CB(skb)->page_released = false;
4275 }
4276 dev_kfree_skb(skb);
4277 }
4278 rx_buffer->skb = NULL;
4279 if (rx_buffer->dma)
4280 dma_unmap_page(dev, rx_buffer->dma,
4281 ixgbe_rx_pg_size(rx_ring),
4282 DMA_FROM_DEVICE);
4283 rx_buffer->dma = 0;
4284 if (rx_buffer->page)
4285 __free_pages(rx_buffer->page,
4286 ixgbe_rx_pg_order(rx_ring));
4287 rx_buffer->page = NULL;
4288 }
4289
4290 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4291 memset(rx_ring->rx_buffer_info, 0, size);
4292
4293 /* Zero out the descriptor ring */
4294 memset(rx_ring->desc, 0, rx_ring->size);
4295
4296 rx_ring->next_to_alloc = 0;
4297 rx_ring->next_to_clean = 0;
4298 rx_ring->next_to_use = 0;
4299 }
4300
4301 /**
4302 * ixgbe_clean_tx_ring - Free Tx Buffers
4303 * @tx_ring: ring to be cleaned
4304 **/
4305 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4306 {
4307 struct ixgbe_tx_buffer *tx_buffer_info;
4308 unsigned long size;
4309 u16 i;
4310
4311 /* ring already cleared, nothing to do */
4312 if (!tx_ring->tx_buffer_info)
4313 return;
4314
4315 /* Free all the Tx ring sk_buffs */
4316 for (i = 0; i < tx_ring->count; i++) {
4317 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4318 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4319 }
4320
4321 netdev_tx_reset_queue(txring_txq(tx_ring));
4322
4323 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4324 memset(tx_ring->tx_buffer_info, 0, size);
4325
4326 /* Zero out the descriptor ring */
4327 memset(tx_ring->desc, 0, tx_ring->size);
4328
4329 tx_ring->next_to_use = 0;
4330 tx_ring->next_to_clean = 0;
4331 }
4332
4333 /**
4334 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4335 * @adapter: board private structure
4336 **/
4337 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4338 {
4339 int i;
4340
4341 for (i = 0; i < adapter->num_rx_queues; i++)
4342 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4343 }
4344
4345 /**
4346 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4347 * @adapter: board private structure
4348 **/
4349 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4350 {
4351 int i;
4352
4353 for (i = 0; i < adapter->num_tx_queues; i++)
4354 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4355 }
4356
4357 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4358 {
4359 struct hlist_node *node2;
4360 struct ixgbe_fdir_filter *filter;
4361
4362 spin_lock(&adapter->fdir_perfect_lock);
4363
4364 hlist_for_each_entry_safe(filter, node2,
4365 &adapter->fdir_filter_list, fdir_node) {
4366 hlist_del(&filter->fdir_node);
4367 kfree(filter);
4368 }
4369 adapter->fdir_filter_count = 0;
4370
4371 spin_unlock(&adapter->fdir_perfect_lock);
4372 }
4373
4374 void ixgbe_down(struct ixgbe_adapter *adapter)
4375 {
4376 struct net_device *netdev = adapter->netdev;
4377 struct ixgbe_hw *hw = &adapter->hw;
4378 u32 rxctrl;
4379 int i;
4380
4381 /* signal that we are down to the interrupt handler */
4382 set_bit(__IXGBE_DOWN, &adapter->state);
4383
4384 /* disable receives */
4385 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4386 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4387
4388 /* disable all enabled rx queues */
4389 for (i = 0; i < adapter->num_rx_queues; i++)
4390 /* this call also flushes the previous write */
4391 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4392
4393 usleep_range(10000, 20000);
4394
4395 netif_tx_stop_all_queues(netdev);
4396
4397 /* call carrier off first to avoid false dev_watchdog timeouts */
4398 netif_carrier_off(netdev);
4399 netif_tx_disable(netdev);
4400
4401 ixgbe_irq_disable(adapter);
4402
4403 ixgbe_napi_disable_all(adapter);
4404
4405 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4406 IXGBE_FLAG2_RESET_REQUESTED);
4407 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4408
4409 del_timer_sync(&adapter->service_timer);
4410
4411 if (adapter->num_vfs) {
4412 /* Clear EITR Select mapping */
4413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4414
4415 /* Mark all the VFs as inactive */
4416 for (i = 0 ; i < adapter->num_vfs; i++)
4417 adapter->vfinfo[i].clear_to_send = false;
4418
4419 /* ping all the active vfs to let them know we are going down */
4420 ixgbe_ping_all_vfs(adapter);
4421
4422 /* Disable all VFTE/VFRE TX/RX */
4423 ixgbe_disable_tx_rx(adapter);
4424 }
4425
4426 /* disable transmits in the hardware now that interrupts are off */
4427 for (i = 0; i < adapter->num_tx_queues; i++) {
4428 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4429 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4430 }
4431
4432 /* Disable the Tx DMA engine on 82599 and X540 */
4433 switch (hw->mac.type) {
4434 case ixgbe_mac_82599EB:
4435 case ixgbe_mac_X540:
4436 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4437 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4438 ~IXGBE_DMATXCTL_TE));
4439 break;
4440 default:
4441 break;
4442 }
4443
4444 if (!pci_channel_offline(adapter->pdev))
4445 ixgbe_reset(adapter);
4446
4447 /* power down the optics for 82599 SFP+ fiber */
4448 if (hw->mac.ops.disable_tx_laser)
4449 hw->mac.ops.disable_tx_laser(hw);
4450
4451 ixgbe_clean_all_tx_rings(adapter);
4452 ixgbe_clean_all_rx_rings(adapter);
4453
4454 #ifdef CONFIG_IXGBE_DCA
4455 /* since we reset the hardware DCA settings were cleared */
4456 ixgbe_setup_dca(adapter);
4457 #endif
4458 }
4459
4460 /**
4461 * ixgbe_tx_timeout - Respond to a Tx Hang
4462 * @netdev: network interface device structure
4463 **/
4464 static void ixgbe_tx_timeout(struct net_device *netdev)
4465 {
4466 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4467
4468 /* Do the reset outside of interrupt context */
4469 ixgbe_tx_timeout_reset(adapter);
4470 }
4471
4472 /**
4473 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4474 * @adapter: board private structure to initialize
4475 *
4476 * ixgbe_sw_init initializes the Adapter private data structure.
4477 * Fields are initialized based on PCI device information and
4478 * OS network device settings (MTU size).
4479 **/
4480 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4481 {
4482 struct ixgbe_hw *hw = &adapter->hw;
4483 struct pci_dev *pdev = adapter->pdev;
4484 unsigned int rss, fdir;
4485 u32 fwsm;
4486 #ifdef CONFIG_IXGBE_DCB
4487 int j;
4488 struct tc_configuration *tc;
4489 #endif
4490
4491 /* PCI config space info */
4492
4493 hw->vendor_id = pdev->vendor;
4494 hw->device_id = pdev->device;
4495 hw->revision_id = pdev->revision;
4496 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4497 hw->subsystem_device_id = pdev->subsystem_device;
4498
4499 /* Set common capability flags and settings */
4500 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4501 adapter->ring_feature[RING_F_RSS].limit = rss;
4502 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4503 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4504 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4505 adapter->atr_sample_rate = 20;
4506 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4507 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4508 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4509 #ifdef CONFIG_IXGBE_DCA
4510 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4511 #endif
4512 #ifdef IXGBE_FCOE
4513 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4514 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4515 #ifdef CONFIG_IXGBE_DCB
4516 /* Default traffic class to use for FCoE */
4517 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4518 #endif /* CONFIG_IXGBE_DCB */
4519 #endif /* IXGBE_FCOE */
4520
4521 /* Set MAC specific capability flags and exceptions */
4522 switch (hw->mac.type) {
4523 case ixgbe_mac_82598EB:
4524 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4525 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4526
4527 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4528 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4529
4530 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4531 adapter->ring_feature[RING_F_FDIR].limit = 0;
4532 adapter->atr_sample_rate = 0;
4533 adapter->fdir_pballoc = 0;
4534 #ifdef IXGBE_FCOE
4535 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4536 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4537 #ifdef CONFIG_IXGBE_DCB
4538 adapter->fcoe.up = 0;
4539 #endif /* IXGBE_DCB */
4540 #endif /* IXGBE_FCOE */
4541 break;
4542 case ixgbe_mac_82599EB:
4543 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4544 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4545 break;
4546 case ixgbe_mac_X540:
4547 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4548 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4549 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4550 break;
4551 default:
4552 break;
4553 }
4554
4555 #ifdef IXGBE_FCOE
4556 /* FCoE support exists, always init the FCoE lock */
4557 spin_lock_init(&adapter->fcoe.lock);
4558
4559 #endif
4560 /* n-tuple support exists, always init our spinlock */
4561 spin_lock_init(&adapter->fdir_perfect_lock);
4562
4563 #ifdef CONFIG_IXGBE_DCB
4564 switch (hw->mac.type) {
4565 case ixgbe_mac_X540:
4566 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4567 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4568 break;
4569 default:
4570 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4571 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4572 break;
4573 }
4574
4575 /* Configure DCB traffic classes */
4576 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4577 tc = &adapter->dcb_cfg.tc_config[j];
4578 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4579 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4580 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4581 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4582 tc->dcb_pfc = pfc_disabled;
4583 }
4584
4585 /* Initialize default user to priority mapping, UPx->TC0 */
4586 tc = &adapter->dcb_cfg.tc_config[0];
4587 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4588 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4589
4590 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4591 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4592 adapter->dcb_cfg.pfc_mode_enable = false;
4593 adapter->dcb_set_bitmap = 0x00;
4594 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4595 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4596 sizeof(adapter->temp_dcb_cfg));
4597
4598 #endif
4599
4600 /* default flow control settings */
4601 hw->fc.requested_mode = ixgbe_fc_full;
4602 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4603 ixgbe_pbthresh_setup(adapter);
4604 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4605 hw->fc.send_xon = true;
4606 hw->fc.disable_fc_autoneg =
4607 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4608
4609 #ifdef CONFIG_PCI_IOV
4610 /* assign number of SR-IOV VFs */
4611 if (hw->mac.type != ixgbe_mac_82598EB)
4612 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4613
4614 #endif
4615 /* enable itr by default in dynamic mode */
4616 adapter->rx_itr_setting = 1;
4617 adapter->tx_itr_setting = 1;
4618
4619 /* set default ring sizes */
4620 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4621 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4622
4623 /* set default work limits */
4624 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4625
4626 /* initialize eeprom parameters */
4627 if (ixgbe_init_eeprom_params_generic(hw)) {
4628 e_dev_err("EEPROM initialization failed\n");
4629 return -EIO;
4630 }
4631
4632 set_bit(__IXGBE_DOWN, &adapter->state);
4633
4634 return 0;
4635 }
4636
4637 /**
4638 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4639 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4640 *
4641 * Return 0 on success, negative on failure
4642 **/
4643 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4644 {
4645 struct device *dev = tx_ring->dev;
4646 int orig_node = dev_to_node(dev);
4647 int numa_node = -1;
4648 int size;
4649
4650 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4651
4652 if (tx_ring->q_vector)
4653 numa_node = tx_ring->q_vector->numa_node;
4654
4655 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4656 if (!tx_ring->tx_buffer_info)
4657 tx_ring->tx_buffer_info = vzalloc(size);
4658 if (!tx_ring->tx_buffer_info)
4659 goto err;
4660
4661 /* round up to nearest 4K */
4662 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4663 tx_ring->size = ALIGN(tx_ring->size, 4096);
4664
4665 set_dev_node(dev, numa_node);
4666 tx_ring->desc = dma_alloc_coherent(dev,
4667 tx_ring->size,
4668 &tx_ring->dma,
4669 GFP_KERNEL);
4670 set_dev_node(dev, orig_node);
4671 if (!tx_ring->desc)
4672 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4673 &tx_ring->dma, GFP_KERNEL);
4674 if (!tx_ring->desc)
4675 goto err;
4676
4677 tx_ring->next_to_use = 0;
4678 tx_ring->next_to_clean = 0;
4679 return 0;
4680
4681 err:
4682 vfree(tx_ring->tx_buffer_info);
4683 tx_ring->tx_buffer_info = NULL;
4684 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4685 return -ENOMEM;
4686 }
4687
4688 /**
4689 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4690 * @adapter: board private structure
4691 *
4692 * If this function returns with an error, then it's possible one or
4693 * more of the rings is populated (while the rest are not). It is the
4694 * callers duty to clean those orphaned rings.
4695 *
4696 * Return 0 on success, negative on failure
4697 **/
4698 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4699 {
4700 int i, err = 0;
4701
4702 for (i = 0; i < adapter->num_tx_queues; i++) {
4703 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4704 if (!err)
4705 continue;
4706
4707 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4708 goto err_setup_tx;
4709 }
4710
4711 return 0;
4712 err_setup_tx:
4713 /* rewind the index freeing the rings as we go */
4714 while (i--)
4715 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4716 return err;
4717 }
4718
4719 /**
4720 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4721 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4722 *
4723 * Returns 0 on success, negative on failure
4724 **/
4725 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4726 {
4727 struct device *dev = rx_ring->dev;
4728 int orig_node = dev_to_node(dev);
4729 int numa_node = -1;
4730 int size;
4731
4732 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4733
4734 if (rx_ring->q_vector)
4735 numa_node = rx_ring->q_vector->numa_node;
4736
4737 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4738 if (!rx_ring->rx_buffer_info)
4739 rx_ring->rx_buffer_info = vzalloc(size);
4740 if (!rx_ring->rx_buffer_info)
4741 goto err;
4742
4743 /* Round up to nearest 4K */
4744 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4745 rx_ring->size = ALIGN(rx_ring->size, 4096);
4746
4747 set_dev_node(dev, numa_node);
4748 rx_ring->desc = dma_alloc_coherent(dev,
4749 rx_ring->size,
4750 &rx_ring->dma,
4751 GFP_KERNEL);
4752 set_dev_node(dev, orig_node);
4753 if (!rx_ring->desc)
4754 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4755 &rx_ring->dma, GFP_KERNEL);
4756 if (!rx_ring->desc)
4757 goto err;
4758
4759 rx_ring->next_to_clean = 0;
4760 rx_ring->next_to_use = 0;
4761
4762 return 0;
4763 err:
4764 vfree(rx_ring->rx_buffer_info);
4765 rx_ring->rx_buffer_info = NULL;
4766 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4767 return -ENOMEM;
4768 }
4769
4770 /**
4771 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4772 * @adapter: board private structure
4773 *
4774 * If this function returns with an error, then it's possible one or
4775 * more of the rings is populated (while the rest are not). It is the
4776 * callers duty to clean those orphaned rings.
4777 *
4778 * Return 0 on success, negative on failure
4779 **/
4780 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4781 {
4782 int i, err = 0;
4783
4784 for (i = 0; i < adapter->num_rx_queues; i++) {
4785 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4786 if (!err)
4787 continue;
4788
4789 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4790 goto err_setup_rx;
4791 }
4792
4793 #ifdef IXGBE_FCOE
4794 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4795 if (!err)
4796 #endif
4797 return 0;
4798 err_setup_rx:
4799 /* rewind the index freeing the rings as we go */
4800 while (i--)
4801 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4802 return err;
4803 }
4804
4805 /**
4806 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4807 * @tx_ring: Tx descriptor ring for a specific queue
4808 *
4809 * Free all transmit software resources
4810 **/
4811 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4812 {
4813 ixgbe_clean_tx_ring(tx_ring);
4814
4815 vfree(tx_ring->tx_buffer_info);
4816 tx_ring->tx_buffer_info = NULL;
4817
4818 /* if not set, then don't free */
4819 if (!tx_ring->desc)
4820 return;
4821
4822 dma_free_coherent(tx_ring->dev, tx_ring->size,
4823 tx_ring->desc, tx_ring->dma);
4824
4825 tx_ring->desc = NULL;
4826 }
4827
4828 /**
4829 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4830 * @adapter: board private structure
4831 *
4832 * Free all transmit software resources
4833 **/
4834 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4835 {
4836 int i;
4837
4838 for (i = 0; i < adapter->num_tx_queues; i++)
4839 if (adapter->tx_ring[i]->desc)
4840 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4841 }
4842
4843 /**
4844 * ixgbe_free_rx_resources - Free Rx Resources
4845 * @rx_ring: ring to clean the resources from
4846 *
4847 * Free all receive software resources
4848 **/
4849 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4850 {
4851 ixgbe_clean_rx_ring(rx_ring);
4852
4853 vfree(rx_ring->rx_buffer_info);
4854 rx_ring->rx_buffer_info = NULL;
4855
4856 /* if not set, then don't free */
4857 if (!rx_ring->desc)
4858 return;
4859
4860 dma_free_coherent(rx_ring->dev, rx_ring->size,
4861 rx_ring->desc, rx_ring->dma);
4862
4863 rx_ring->desc = NULL;
4864 }
4865
4866 /**
4867 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4868 * @adapter: board private structure
4869 *
4870 * Free all receive software resources
4871 **/
4872 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4873 {
4874 int i;
4875
4876 #ifdef IXGBE_FCOE
4877 ixgbe_free_fcoe_ddp_resources(adapter);
4878
4879 #endif
4880 for (i = 0; i < adapter->num_rx_queues; i++)
4881 if (adapter->rx_ring[i]->desc)
4882 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4883 }
4884
4885 /**
4886 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4887 * @netdev: network interface device structure
4888 * @new_mtu: new value for maximum frame size
4889 *
4890 * Returns 0 on success, negative on failure
4891 **/
4892 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4893 {
4894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4895 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4896
4897 /* MTU < 68 is an error and causes problems on some kernels */
4898 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4899 return -EINVAL;
4900
4901 /*
4902 * For 82599EB we cannot allow legacy VFs to enable their receive
4903 * paths when MTU greater than 1500 is configured. So display a
4904 * warning that legacy VFs will be disabled.
4905 */
4906 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4907 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4908 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4909 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4910
4911 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4912
4913 /* must set new MTU before calling down or up */
4914 netdev->mtu = new_mtu;
4915
4916 if (netif_running(netdev))
4917 ixgbe_reinit_locked(adapter);
4918
4919 return 0;
4920 }
4921
4922 /**
4923 * ixgbe_open - Called when a network interface is made active
4924 * @netdev: network interface device structure
4925 *
4926 * Returns 0 on success, negative value on failure
4927 *
4928 * The open entry point is called when a network interface is made
4929 * active by the system (IFF_UP). At this point all resources needed
4930 * for transmit and receive operations are allocated, the interrupt
4931 * handler is registered with the OS, the watchdog timer is started,
4932 * and the stack is notified that the interface is ready.
4933 **/
4934 static int ixgbe_open(struct net_device *netdev)
4935 {
4936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4937 int err;
4938
4939 /* disallow open during test */
4940 if (test_bit(__IXGBE_TESTING, &adapter->state))
4941 return -EBUSY;
4942
4943 netif_carrier_off(netdev);
4944
4945 /* allocate transmit descriptors */
4946 err = ixgbe_setup_all_tx_resources(adapter);
4947 if (err)
4948 goto err_setup_tx;
4949
4950 /* allocate receive descriptors */
4951 err = ixgbe_setup_all_rx_resources(adapter);
4952 if (err)
4953 goto err_setup_rx;
4954
4955 ixgbe_configure(adapter);
4956
4957 err = ixgbe_request_irq(adapter);
4958 if (err)
4959 goto err_req_irq;
4960
4961 /* Notify the stack of the actual queue counts. */
4962 err = netif_set_real_num_tx_queues(netdev,
4963 adapter->num_rx_pools > 1 ? 1 :
4964 adapter->num_tx_queues);
4965 if (err)
4966 goto err_set_queues;
4967
4968
4969 err = netif_set_real_num_rx_queues(netdev,
4970 adapter->num_rx_pools > 1 ? 1 :
4971 adapter->num_rx_queues);
4972 if (err)
4973 goto err_set_queues;
4974
4975 ixgbe_ptp_init(adapter);
4976
4977 ixgbe_up_complete(adapter);
4978
4979 return 0;
4980
4981 err_set_queues:
4982 ixgbe_free_irq(adapter);
4983 err_req_irq:
4984 ixgbe_free_all_rx_resources(adapter);
4985 err_setup_rx:
4986 ixgbe_free_all_tx_resources(adapter);
4987 err_setup_tx:
4988 ixgbe_reset(adapter);
4989
4990 return err;
4991 }
4992
4993 /**
4994 * ixgbe_close - Disables a network interface
4995 * @netdev: network interface device structure
4996 *
4997 * Returns 0, this is not allowed to fail
4998 *
4999 * The close entry point is called when an interface is de-activated
5000 * by the OS. The hardware is still under the drivers control, but
5001 * needs to be disabled. A global MAC reset is issued to stop the
5002 * hardware, and all transmit and receive resources are freed.
5003 **/
5004 static int ixgbe_close(struct net_device *netdev)
5005 {
5006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5007
5008 ixgbe_ptp_stop(adapter);
5009
5010 ixgbe_down(adapter);
5011 ixgbe_free_irq(adapter);
5012
5013 ixgbe_fdir_filter_exit(adapter);
5014
5015 ixgbe_free_all_tx_resources(adapter);
5016 ixgbe_free_all_rx_resources(adapter);
5017
5018 ixgbe_release_hw_control(adapter);
5019
5020 return 0;
5021 }
5022
5023 #ifdef CONFIG_PM
5024 static int ixgbe_resume(struct pci_dev *pdev)
5025 {
5026 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5027 struct net_device *netdev = adapter->netdev;
5028 u32 err;
5029
5030 pci_set_power_state(pdev, PCI_D0);
5031 pci_restore_state(pdev);
5032 /*
5033 * pci_restore_state clears dev->state_saved so call
5034 * pci_save_state to restore it.
5035 */
5036 pci_save_state(pdev);
5037
5038 err = pci_enable_device_mem(pdev);
5039 if (err) {
5040 e_dev_err("Cannot enable PCI device from suspend\n");
5041 return err;
5042 }
5043 pci_set_master(pdev);
5044
5045 pci_wake_from_d3(pdev, false);
5046
5047 ixgbe_reset(adapter);
5048
5049 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5050
5051 rtnl_lock();
5052 err = ixgbe_init_interrupt_scheme(adapter);
5053 if (!err && netif_running(netdev))
5054 err = ixgbe_open(netdev);
5055
5056 rtnl_unlock();
5057
5058 if (err)
5059 return err;
5060
5061 netif_device_attach(netdev);
5062
5063 return 0;
5064 }
5065 #endif /* CONFIG_PM */
5066
5067 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5068 {
5069 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5070 struct net_device *netdev = adapter->netdev;
5071 struct ixgbe_hw *hw = &adapter->hw;
5072 u32 ctrl, fctrl;
5073 u32 wufc = adapter->wol;
5074 #ifdef CONFIG_PM
5075 int retval = 0;
5076 #endif
5077
5078 netif_device_detach(netdev);
5079
5080 if (netif_running(netdev)) {
5081 rtnl_lock();
5082 ixgbe_down(adapter);
5083 ixgbe_free_irq(adapter);
5084 ixgbe_free_all_tx_resources(adapter);
5085 ixgbe_free_all_rx_resources(adapter);
5086 rtnl_unlock();
5087 }
5088
5089 ixgbe_clear_interrupt_scheme(adapter);
5090
5091 #ifdef CONFIG_PM
5092 retval = pci_save_state(pdev);
5093 if (retval)
5094 return retval;
5095
5096 #endif
5097 if (wufc) {
5098 ixgbe_set_rx_mode(netdev);
5099
5100 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5101 if (hw->mac.ops.enable_tx_laser)
5102 hw->mac.ops.enable_tx_laser(hw);
5103
5104 /* turn on all-multi mode if wake on multicast is enabled */
5105 if (wufc & IXGBE_WUFC_MC) {
5106 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5107 fctrl |= IXGBE_FCTRL_MPE;
5108 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5109 }
5110
5111 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5112 ctrl |= IXGBE_CTRL_GIO_DIS;
5113 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5114
5115 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5116 } else {
5117 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5118 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5119 }
5120
5121 switch (hw->mac.type) {
5122 case ixgbe_mac_82598EB:
5123 pci_wake_from_d3(pdev, false);
5124 break;
5125 case ixgbe_mac_82599EB:
5126 case ixgbe_mac_X540:
5127 pci_wake_from_d3(pdev, !!wufc);
5128 break;
5129 default:
5130 break;
5131 }
5132
5133 *enable_wake = !!wufc;
5134
5135 ixgbe_release_hw_control(adapter);
5136
5137 pci_disable_device(pdev);
5138
5139 return 0;
5140 }
5141
5142 #ifdef CONFIG_PM
5143 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5144 {
5145 int retval;
5146 bool wake;
5147
5148 retval = __ixgbe_shutdown(pdev, &wake);
5149 if (retval)
5150 return retval;
5151
5152 if (wake) {
5153 pci_prepare_to_sleep(pdev);
5154 } else {
5155 pci_wake_from_d3(pdev, false);
5156 pci_set_power_state(pdev, PCI_D3hot);
5157 }
5158
5159 return 0;
5160 }
5161 #endif /* CONFIG_PM */
5162
5163 static void ixgbe_shutdown(struct pci_dev *pdev)
5164 {
5165 bool wake;
5166
5167 __ixgbe_shutdown(pdev, &wake);
5168
5169 if (system_state == SYSTEM_POWER_OFF) {
5170 pci_wake_from_d3(pdev, wake);
5171 pci_set_power_state(pdev, PCI_D3hot);
5172 }
5173 }
5174
5175 /**
5176 * ixgbe_update_stats - Update the board statistics counters.
5177 * @adapter: board private structure
5178 **/
5179 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5180 {
5181 struct net_device *netdev = adapter->netdev;
5182 struct ixgbe_hw *hw = &adapter->hw;
5183 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5184 u64 total_mpc = 0;
5185 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5186 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5187 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5188 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5189
5190 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5191 test_bit(__IXGBE_RESETTING, &adapter->state))
5192 return;
5193
5194 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5195 u64 rsc_count = 0;
5196 u64 rsc_flush = 0;
5197 for (i = 0; i < adapter->num_rx_queues; i++) {
5198 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5199 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5200 }
5201 adapter->rsc_total_count = rsc_count;
5202 adapter->rsc_total_flush = rsc_flush;
5203 }
5204
5205 for (i = 0; i < adapter->num_rx_queues; i++) {
5206 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5207 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5208 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5209 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5210 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5211 bytes += rx_ring->stats.bytes;
5212 packets += rx_ring->stats.packets;
5213 }
5214 adapter->non_eop_descs = non_eop_descs;
5215 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5216 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5217 adapter->hw_csum_rx_error = hw_csum_rx_error;
5218 netdev->stats.rx_bytes = bytes;
5219 netdev->stats.rx_packets = packets;
5220
5221 bytes = 0;
5222 packets = 0;
5223 /* gather some stats to the adapter struct that are per queue */
5224 for (i = 0; i < adapter->num_tx_queues; i++) {
5225 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5226 restart_queue += tx_ring->tx_stats.restart_queue;
5227 tx_busy += tx_ring->tx_stats.tx_busy;
5228 bytes += tx_ring->stats.bytes;
5229 packets += tx_ring->stats.packets;
5230 }
5231 adapter->restart_queue = restart_queue;
5232 adapter->tx_busy = tx_busy;
5233 netdev->stats.tx_bytes = bytes;
5234 netdev->stats.tx_packets = packets;
5235
5236 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5237
5238 /* 8 register reads */
5239 for (i = 0; i < 8; i++) {
5240 /* for packet buffers not used, the register should read 0 */
5241 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5242 missed_rx += mpc;
5243 hwstats->mpc[i] += mpc;
5244 total_mpc += hwstats->mpc[i];
5245 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5246 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5247 switch (hw->mac.type) {
5248 case ixgbe_mac_82598EB:
5249 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5250 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5251 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5252 hwstats->pxonrxc[i] +=
5253 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5254 break;
5255 case ixgbe_mac_82599EB:
5256 case ixgbe_mac_X540:
5257 hwstats->pxonrxc[i] +=
5258 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5259 break;
5260 default:
5261 break;
5262 }
5263 }
5264
5265 /*16 register reads */
5266 for (i = 0; i < 16; i++) {
5267 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5268 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5269 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5270 (hw->mac.type == ixgbe_mac_X540)) {
5271 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5272 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5273 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5274 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5275 }
5276 }
5277
5278 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5279 /* work around hardware counting issue */
5280 hwstats->gprc -= missed_rx;
5281
5282 ixgbe_update_xoff_received(adapter);
5283
5284 /* 82598 hardware only has a 32 bit counter in the high register */
5285 switch (hw->mac.type) {
5286 case ixgbe_mac_82598EB:
5287 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5288 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5289 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5290 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5291 break;
5292 case ixgbe_mac_X540:
5293 /* OS2BMC stats are X540 only*/
5294 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5295 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5296 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5297 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5298 case ixgbe_mac_82599EB:
5299 for (i = 0; i < 16; i++)
5300 adapter->hw_rx_no_dma_resources +=
5301 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5302 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5303 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5304 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5305 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5306 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5307 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5308 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5309 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5310 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5311 #ifdef IXGBE_FCOE
5312 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5313 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5314 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5315 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5316 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5317 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5318 /* Add up per cpu counters for total ddp aloc fail */
5319 if (adapter->fcoe.ddp_pool) {
5320 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5321 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5322 unsigned int cpu;
5323 u64 noddp = 0, noddp_ext_buff = 0;
5324 for_each_possible_cpu(cpu) {
5325 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5326 noddp += ddp_pool->noddp;
5327 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5328 }
5329 hwstats->fcoe_noddp = noddp;
5330 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5331 }
5332 #endif /* IXGBE_FCOE */
5333 break;
5334 default:
5335 break;
5336 }
5337 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5338 hwstats->bprc += bprc;
5339 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5340 if (hw->mac.type == ixgbe_mac_82598EB)
5341 hwstats->mprc -= bprc;
5342 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5343 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5344 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5345 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5346 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5347 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5348 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5349 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5350 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5351 hwstats->lxontxc += lxon;
5352 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5353 hwstats->lxofftxc += lxoff;
5354 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5355 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5356 /*
5357 * 82598 errata - tx of flow control packets is included in tx counters
5358 */
5359 xon_off_tot = lxon + lxoff;
5360 hwstats->gptc -= xon_off_tot;
5361 hwstats->mptc -= xon_off_tot;
5362 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5363 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5364 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5365 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5366 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5367 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5368 hwstats->ptc64 -= xon_off_tot;
5369 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5370 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5371 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5372 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5373 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5374 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5375
5376 /* Fill out the OS statistics structure */
5377 netdev->stats.multicast = hwstats->mprc;
5378
5379 /* Rx Errors */
5380 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5381 netdev->stats.rx_dropped = 0;
5382 netdev->stats.rx_length_errors = hwstats->rlec;
5383 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5384 netdev->stats.rx_missed_errors = total_mpc;
5385 }
5386
5387 /**
5388 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5389 * @adapter: pointer to the device adapter structure
5390 **/
5391 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5392 {
5393 struct ixgbe_hw *hw = &adapter->hw;
5394 int i;
5395
5396 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5397 return;
5398
5399 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5400
5401 /* if interface is down do nothing */
5402 if (test_bit(__IXGBE_DOWN, &adapter->state))
5403 return;
5404
5405 /* do nothing if we are not using signature filters */
5406 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5407 return;
5408
5409 adapter->fdir_overflow++;
5410
5411 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5412 for (i = 0; i < adapter->num_tx_queues; i++)
5413 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5414 &(adapter->tx_ring[i]->state));
5415 /* re-enable flow director interrupts */
5416 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5417 } else {
5418 e_err(probe, "failed to finish FDIR re-initialization, "
5419 "ignored adding FDIR ATR filters\n");
5420 }
5421 }
5422
5423 /**
5424 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5425 * @adapter: pointer to the device adapter structure
5426 *
5427 * This function serves two purposes. First it strobes the interrupt lines
5428 * in order to make certain interrupts are occurring. Secondly it sets the
5429 * bits needed to check for TX hangs. As a result we should immediately
5430 * determine if a hang has occurred.
5431 */
5432 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5433 {
5434 struct ixgbe_hw *hw = &adapter->hw;
5435 u64 eics = 0;
5436 int i;
5437
5438 /* If we're down or resetting, just bail */
5439 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5440 test_bit(__IXGBE_RESETTING, &adapter->state))
5441 return;
5442
5443 /* Force detection of hung controller */
5444 if (netif_carrier_ok(adapter->netdev)) {
5445 for (i = 0; i < adapter->num_tx_queues; i++)
5446 set_check_for_tx_hang(adapter->tx_ring[i]);
5447 }
5448
5449 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5450 /*
5451 * for legacy and MSI interrupts don't set any bits
5452 * that are enabled for EIAM, because this operation
5453 * would set *both* EIMS and EICS for any bit in EIAM
5454 */
5455 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5456 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5457 } else {
5458 /* get one bit for every active tx/rx interrupt vector */
5459 for (i = 0; i < adapter->num_q_vectors; i++) {
5460 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5461 if (qv->rx.ring || qv->tx.ring)
5462 eics |= ((u64)1 << i);
5463 }
5464 }
5465
5466 /* Cause software interrupt to ensure rings are cleaned */
5467 ixgbe_irq_rearm_queues(adapter, eics);
5468
5469 }
5470
5471 /**
5472 * ixgbe_watchdog_update_link - update the link status
5473 * @adapter: pointer to the device adapter structure
5474 * @link_speed: pointer to a u32 to store the link_speed
5475 **/
5476 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5477 {
5478 struct ixgbe_hw *hw = &adapter->hw;
5479 u32 link_speed = adapter->link_speed;
5480 bool link_up = adapter->link_up;
5481 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5482
5483 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5484 return;
5485
5486 if (hw->mac.ops.check_link) {
5487 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5488 } else {
5489 /* always assume link is up, if no check link function */
5490 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5491 link_up = true;
5492 }
5493
5494 if (adapter->ixgbe_ieee_pfc)
5495 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5496
5497 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5498 hw->mac.ops.fc_enable(hw);
5499 ixgbe_set_rx_drop_en(adapter);
5500 }
5501
5502 if (link_up ||
5503 time_after(jiffies, (adapter->link_check_timeout +
5504 IXGBE_TRY_LINK_TIMEOUT))) {
5505 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5506 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5507 IXGBE_WRITE_FLUSH(hw);
5508 }
5509
5510 adapter->link_up = link_up;
5511 adapter->link_speed = link_speed;
5512 }
5513
5514 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5515 {
5516 #ifdef CONFIG_IXGBE_DCB
5517 struct net_device *netdev = adapter->netdev;
5518 struct dcb_app app = {
5519 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5520 .protocol = 0,
5521 };
5522 u8 up = 0;
5523
5524 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5525 up = dcb_ieee_getapp_mask(netdev, &app);
5526
5527 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5528 #endif
5529 }
5530
5531 /**
5532 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5533 * print link up message
5534 * @adapter: pointer to the device adapter structure
5535 **/
5536 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5537 {
5538 struct net_device *netdev = adapter->netdev;
5539 struct ixgbe_hw *hw = &adapter->hw;
5540 u32 link_speed = adapter->link_speed;
5541 bool flow_rx, flow_tx;
5542
5543 /* only continue if link was previously down */
5544 if (netif_carrier_ok(netdev))
5545 return;
5546
5547 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5548
5549 switch (hw->mac.type) {
5550 case ixgbe_mac_82598EB: {
5551 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5552 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5553 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5554 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5555 }
5556 break;
5557 case ixgbe_mac_X540:
5558 case ixgbe_mac_82599EB: {
5559 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5560 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5561 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5562 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5563 }
5564 break;
5565 default:
5566 flow_tx = false;
5567 flow_rx = false;
5568 break;
5569 }
5570
5571 adapter->last_rx_ptp_check = jiffies;
5572
5573 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5574 ixgbe_ptp_start_cyclecounter(adapter);
5575
5576 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5577 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5578 "10 Gbps" :
5579 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5580 "1 Gbps" :
5581 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5582 "100 Mbps" :
5583 "unknown speed"))),
5584 ((flow_rx && flow_tx) ? "RX/TX" :
5585 (flow_rx ? "RX" :
5586 (flow_tx ? "TX" : "None"))));
5587
5588 netif_carrier_on(netdev);
5589 ixgbe_check_vf_rate_limit(adapter);
5590
5591 /* update the default user priority for VFs */
5592 ixgbe_update_default_up(adapter);
5593
5594 /* ping all the active vfs to let them know link has changed */
5595 ixgbe_ping_all_vfs(adapter);
5596 }
5597
5598 /**
5599 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5600 * print link down message
5601 * @adapter: pointer to the adapter structure
5602 **/
5603 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5604 {
5605 struct net_device *netdev = adapter->netdev;
5606 struct ixgbe_hw *hw = &adapter->hw;
5607
5608 adapter->link_up = false;
5609 adapter->link_speed = 0;
5610
5611 /* only continue if link was up previously */
5612 if (!netif_carrier_ok(netdev))
5613 return;
5614
5615 /* poll for SFP+ cable when link is down */
5616 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5617 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5618
5619 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5620 ixgbe_ptp_start_cyclecounter(adapter);
5621
5622 e_info(drv, "NIC Link is Down\n");
5623 netif_carrier_off(netdev);
5624
5625 /* ping all the active vfs to let them know link has changed */
5626 ixgbe_ping_all_vfs(adapter);
5627 }
5628
5629 /**
5630 * ixgbe_watchdog_flush_tx - flush queues on link down
5631 * @adapter: pointer to the device adapter structure
5632 **/
5633 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5634 {
5635 int i;
5636 int some_tx_pending = 0;
5637
5638 if (!netif_carrier_ok(adapter->netdev)) {
5639 for (i = 0; i < adapter->num_tx_queues; i++) {
5640 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5641 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5642 some_tx_pending = 1;
5643 break;
5644 }
5645 }
5646
5647 if (some_tx_pending) {
5648 /* We've lost link, so the controller stops DMA,
5649 * but we've got queued Tx work that's never going
5650 * to get done, so reset controller to flush Tx.
5651 * (Do the reset outside of interrupt context).
5652 */
5653 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5654 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5655 }
5656 }
5657 }
5658
5659 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5660 {
5661 u32 ssvpc;
5662
5663 /* Do not perform spoof check for 82598 or if not in IOV mode */
5664 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5665 adapter->num_vfs == 0)
5666 return;
5667
5668 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5669
5670 /*
5671 * ssvpc register is cleared on read, if zero then no
5672 * spoofed packets in the last interval.
5673 */
5674 if (!ssvpc)
5675 return;
5676
5677 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5678 }
5679
5680 /**
5681 * ixgbe_watchdog_subtask - check and bring link up
5682 * @adapter: pointer to the device adapter structure
5683 **/
5684 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5685 {
5686 /* if interface is down do nothing */
5687 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5688 test_bit(__IXGBE_RESETTING, &adapter->state))
5689 return;
5690
5691 ixgbe_watchdog_update_link(adapter);
5692
5693 if (adapter->link_up)
5694 ixgbe_watchdog_link_is_up(adapter);
5695 else
5696 ixgbe_watchdog_link_is_down(adapter);
5697
5698 ixgbe_spoof_check(adapter);
5699 ixgbe_update_stats(adapter);
5700
5701 ixgbe_watchdog_flush_tx(adapter);
5702 }
5703
5704 /**
5705 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5706 * @adapter: the ixgbe adapter structure
5707 **/
5708 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5709 {
5710 struct ixgbe_hw *hw = &adapter->hw;
5711 s32 err;
5712
5713 /* not searching for SFP so there is nothing to do here */
5714 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5715 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5716 return;
5717
5718 /* concurent i2c reads are not supported */
5719 if (test_bit(__IXGBE_READ_I2C, &adapter->state))
5720 return;
5721
5722 /* someone else is in init, wait until next service event */
5723 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5724 return;
5725
5726 err = hw->phy.ops.identify_sfp(hw);
5727 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5728 goto sfp_out;
5729
5730 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5731 /* If no cable is present, then we need to reset
5732 * the next time we find a good cable. */
5733 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5734 }
5735
5736 /* exit on error */
5737 if (err)
5738 goto sfp_out;
5739
5740 /* exit if reset not needed */
5741 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5742 goto sfp_out;
5743
5744 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5745
5746 /*
5747 * A module may be identified correctly, but the EEPROM may not have
5748 * support for that module. setup_sfp() will fail in that case, so
5749 * we should not allow that module to load.
5750 */
5751 if (hw->mac.type == ixgbe_mac_82598EB)
5752 err = hw->phy.ops.reset(hw);
5753 else
5754 err = hw->mac.ops.setup_sfp(hw);
5755
5756 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5757 goto sfp_out;
5758
5759 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5760 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5761
5762 sfp_out:
5763 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5764
5765 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5766 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5767 e_dev_err("failed to initialize because an unsupported "
5768 "SFP+ module type was detected.\n");
5769 e_dev_err("Reload the driver after installing a "
5770 "supported module.\n");
5771 unregister_netdev(adapter->netdev);
5772 }
5773 }
5774
5775 /**
5776 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5777 * @adapter: the ixgbe adapter structure
5778 **/
5779 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5780 {
5781 struct ixgbe_hw *hw = &adapter->hw;
5782 u32 speed;
5783 bool autoneg = false;
5784
5785 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5786 return;
5787
5788 /* someone else is in init, wait until next service event */
5789 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5790 return;
5791
5792 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5793
5794 speed = hw->phy.autoneg_advertised;
5795 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5796 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
5797 if (hw->mac.ops.setup_link)
5798 hw->mac.ops.setup_link(hw, speed, true);
5799
5800 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5801 adapter->link_check_timeout = jiffies;
5802 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5803 }
5804
5805 #ifdef CONFIG_PCI_IOV
5806 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5807 {
5808 int vf;
5809 struct ixgbe_hw *hw = &adapter->hw;
5810 struct net_device *netdev = adapter->netdev;
5811 u32 gpc;
5812 u32 ciaa, ciad;
5813
5814 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5815 if (gpc) /* If incrementing then no need for the check below */
5816 return;
5817 /*
5818 * Check to see if a bad DMA write target from an errant or
5819 * malicious VF has caused a PCIe error. If so then we can
5820 * issue a VFLR to the offending VF(s) and then resume without
5821 * requesting a full slot reset.
5822 */
5823
5824 for (vf = 0; vf < adapter->num_vfs; vf++) {
5825 ciaa = (vf << 16) | 0x80000000;
5826 /* 32 bit read so align, we really want status at offset 6 */
5827 ciaa |= PCI_COMMAND;
5828 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5829 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5830 ciaa &= 0x7FFFFFFF;
5831 /* disable debug mode asap after reading data */
5832 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5833 /* Get the upper 16 bits which will be the PCI status reg */
5834 ciad >>= 16;
5835 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5836 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5837 /* Issue VFLR */
5838 ciaa = (vf << 16) | 0x80000000;
5839 ciaa |= 0xA8;
5840 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5841 ciad = 0x00008000; /* VFLR */
5842 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5843 ciaa &= 0x7FFFFFFF;
5844 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5845 }
5846 }
5847 }
5848
5849 #endif
5850 /**
5851 * ixgbe_service_timer - Timer Call-back
5852 * @data: pointer to adapter cast into an unsigned long
5853 **/
5854 static void ixgbe_service_timer(unsigned long data)
5855 {
5856 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5857 unsigned long next_event_offset;
5858 bool ready = true;
5859
5860 /* poll faster when waiting for link */
5861 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5862 next_event_offset = HZ / 10;
5863 else
5864 next_event_offset = HZ * 2;
5865
5866 #ifdef CONFIG_PCI_IOV
5867 /*
5868 * don't bother with SR-IOV VF DMA hang check if there are
5869 * no VFs or the link is down
5870 */
5871 if (!adapter->num_vfs ||
5872 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5873 goto normal_timer_service;
5874
5875 /* If we have VFs allocated then we must check for DMA hangs */
5876 ixgbe_check_for_bad_vf(adapter);
5877 next_event_offset = HZ / 50;
5878 adapter->timer_event_accumulator++;
5879
5880 if (adapter->timer_event_accumulator >= 100)
5881 adapter->timer_event_accumulator = 0;
5882 else
5883 ready = false;
5884
5885 normal_timer_service:
5886 #endif
5887 /* Reset the timer */
5888 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5889
5890 if (ready)
5891 ixgbe_service_event_schedule(adapter);
5892 }
5893
5894 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5895 {
5896 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5897 return;
5898
5899 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5900
5901 /* If we're already down or resetting, just bail */
5902 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5903 test_bit(__IXGBE_RESETTING, &adapter->state))
5904 return;
5905
5906 ixgbe_dump(adapter);
5907 netdev_err(adapter->netdev, "Reset adapter\n");
5908 adapter->tx_timeout_count++;
5909
5910 ixgbe_reinit_locked(adapter);
5911 }
5912
5913 /**
5914 * ixgbe_service_task - manages and runs subtasks
5915 * @work: pointer to work_struct containing our data
5916 **/
5917 static void ixgbe_service_task(struct work_struct *work)
5918 {
5919 struct ixgbe_adapter *adapter = container_of(work,
5920 struct ixgbe_adapter,
5921 service_task);
5922 ixgbe_reset_subtask(adapter);
5923 ixgbe_sfp_detection_subtask(adapter);
5924 ixgbe_sfp_link_config_subtask(adapter);
5925 ixgbe_check_overtemp_subtask(adapter);
5926 ixgbe_watchdog_subtask(adapter);
5927 ixgbe_fdir_reinit_subtask(adapter);
5928 ixgbe_check_hang_subtask(adapter);
5929
5930 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5931 ixgbe_ptp_overflow_check(adapter);
5932 ixgbe_ptp_rx_hang(adapter);
5933 }
5934
5935 ixgbe_service_event_complete(adapter);
5936 }
5937
5938 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5939 struct ixgbe_tx_buffer *first,
5940 u8 *hdr_len)
5941 {
5942 struct sk_buff *skb = first->skb;
5943 u32 vlan_macip_lens, type_tucmd;
5944 u32 mss_l4len_idx, l4len;
5945
5946 if (skb->ip_summed != CHECKSUM_PARTIAL)
5947 return 0;
5948
5949 if (!skb_is_gso(skb))
5950 return 0;
5951
5952 if (skb_header_cloned(skb)) {
5953 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5954 if (err)
5955 return err;
5956 }
5957
5958 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5959 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5960
5961 if (first->protocol == __constant_htons(ETH_P_IP)) {
5962 struct iphdr *iph = ip_hdr(skb);
5963 iph->tot_len = 0;
5964 iph->check = 0;
5965 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5966 iph->daddr, 0,
5967 IPPROTO_TCP,
5968 0);
5969 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5970 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5971 IXGBE_TX_FLAGS_CSUM |
5972 IXGBE_TX_FLAGS_IPV4;
5973 } else if (skb_is_gso_v6(skb)) {
5974 ipv6_hdr(skb)->payload_len = 0;
5975 tcp_hdr(skb)->check =
5976 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5977 &ipv6_hdr(skb)->daddr,
5978 0, IPPROTO_TCP, 0);
5979 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5980 IXGBE_TX_FLAGS_CSUM;
5981 }
5982
5983 /* compute header lengths */
5984 l4len = tcp_hdrlen(skb);
5985 *hdr_len = skb_transport_offset(skb) + l4len;
5986
5987 /* update gso size and bytecount with header size */
5988 first->gso_segs = skb_shinfo(skb)->gso_segs;
5989 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5990
5991 /* mss_l4len_id: use 0 as index for TSO */
5992 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5993 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5994
5995 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5996 vlan_macip_lens = skb_network_header_len(skb);
5997 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5998 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5999
6000 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6001 mss_l4len_idx);
6002
6003 return 1;
6004 }
6005
6006 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6007 struct ixgbe_tx_buffer *first)
6008 {
6009 struct sk_buff *skb = first->skb;
6010 u32 vlan_macip_lens = 0;
6011 u32 mss_l4len_idx = 0;
6012 u32 type_tucmd = 0;
6013
6014 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6015 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6016 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6017 return;
6018 } else {
6019 u8 l4_hdr = 0;
6020 switch (first->protocol) {
6021 case __constant_htons(ETH_P_IP):
6022 vlan_macip_lens |= skb_network_header_len(skb);
6023 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6024 l4_hdr = ip_hdr(skb)->protocol;
6025 break;
6026 case __constant_htons(ETH_P_IPV6):
6027 vlan_macip_lens |= skb_network_header_len(skb);
6028 l4_hdr = ipv6_hdr(skb)->nexthdr;
6029 break;
6030 default:
6031 if (unlikely(net_ratelimit())) {
6032 dev_warn(tx_ring->dev,
6033 "partial checksum but proto=%x!\n",
6034 first->protocol);
6035 }
6036 break;
6037 }
6038
6039 switch (l4_hdr) {
6040 case IPPROTO_TCP:
6041 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6042 mss_l4len_idx = tcp_hdrlen(skb) <<
6043 IXGBE_ADVTXD_L4LEN_SHIFT;
6044 break;
6045 case IPPROTO_SCTP:
6046 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6047 mss_l4len_idx = sizeof(struct sctphdr) <<
6048 IXGBE_ADVTXD_L4LEN_SHIFT;
6049 break;
6050 case IPPROTO_UDP:
6051 mss_l4len_idx = sizeof(struct udphdr) <<
6052 IXGBE_ADVTXD_L4LEN_SHIFT;
6053 break;
6054 default:
6055 if (unlikely(net_ratelimit())) {
6056 dev_warn(tx_ring->dev,
6057 "partial checksum but l4 proto=%x!\n",
6058 l4_hdr);
6059 }
6060 break;
6061 }
6062
6063 /* update TX checksum flag */
6064 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6065 }
6066
6067 /* vlan_macip_lens: MACLEN, VLAN tag */
6068 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6069 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6070
6071 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6072 type_tucmd, mss_l4len_idx);
6073 }
6074
6075 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6076 ((_flag <= _result) ? \
6077 ((u32)(_input & _flag) * (_result / _flag)) : \
6078 ((u32)(_input & _flag) / (_flag / _result)))
6079
6080 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6081 {
6082 /* set type for advanced descriptor with frame checksum insertion */
6083 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6084 IXGBE_ADVTXD_DCMD_DEXT |
6085 IXGBE_ADVTXD_DCMD_IFCS;
6086
6087 /* set HW vlan bit if vlan is present */
6088 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6089 IXGBE_ADVTXD_DCMD_VLE);
6090
6091 /* set segmentation enable bits for TSO/FSO */
6092 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6093 IXGBE_ADVTXD_DCMD_TSE);
6094
6095 /* set timestamp bit if present */
6096 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6097 IXGBE_ADVTXD_MAC_TSTAMP);
6098
6099 /* insert frame checksum */
6100 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6101
6102 return cmd_type;
6103 }
6104
6105 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6106 u32 tx_flags, unsigned int paylen)
6107 {
6108 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6109
6110 /* enable L4 checksum for TSO and TX checksum offload */
6111 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6112 IXGBE_TX_FLAGS_CSUM,
6113 IXGBE_ADVTXD_POPTS_TXSM);
6114
6115 /* enble IPv4 checksum for TSO */
6116 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6117 IXGBE_TX_FLAGS_IPV4,
6118 IXGBE_ADVTXD_POPTS_IXSM);
6119
6120 /*
6121 * Check Context must be set if Tx switch is enabled, which it
6122 * always is for case where virtual functions are running
6123 */
6124 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6125 IXGBE_TX_FLAGS_CC,
6126 IXGBE_ADVTXD_CC);
6127
6128 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6129 }
6130
6131 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6132 IXGBE_TXD_CMD_RS)
6133
6134 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6135 struct ixgbe_tx_buffer *first,
6136 const u8 hdr_len)
6137 {
6138 struct sk_buff *skb = first->skb;
6139 struct ixgbe_tx_buffer *tx_buffer;
6140 union ixgbe_adv_tx_desc *tx_desc;
6141 struct skb_frag_struct *frag;
6142 dma_addr_t dma;
6143 unsigned int data_len, size;
6144 u32 tx_flags = first->tx_flags;
6145 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6146 u16 i = tx_ring->next_to_use;
6147
6148 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6149
6150 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6151
6152 size = skb_headlen(skb);
6153 data_len = skb->data_len;
6154
6155 #ifdef IXGBE_FCOE
6156 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6157 if (data_len < sizeof(struct fcoe_crc_eof)) {
6158 size -= sizeof(struct fcoe_crc_eof) - data_len;
6159 data_len = 0;
6160 } else {
6161 data_len -= sizeof(struct fcoe_crc_eof);
6162 }
6163 }
6164
6165 #endif
6166 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6167
6168 tx_buffer = first;
6169
6170 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6171 if (dma_mapping_error(tx_ring->dev, dma))
6172 goto dma_error;
6173
6174 /* record length, and DMA address */
6175 dma_unmap_len_set(tx_buffer, len, size);
6176 dma_unmap_addr_set(tx_buffer, dma, dma);
6177
6178 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6179
6180 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6181 tx_desc->read.cmd_type_len =
6182 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6183
6184 i++;
6185 tx_desc++;
6186 if (i == tx_ring->count) {
6187 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6188 i = 0;
6189 }
6190 tx_desc->read.olinfo_status = 0;
6191
6192 dma += IXGBE_MAX_DATA_PER_TXD;
6193 size -= IXGBE_MAX_DATA_PER_TXD;
6194
6195 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6196 }
6197
6198 if (likely(!data_len))
6199 break;
6200
6201 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6202
6203 i++;
6204 tx_desc++;
6205 if (i == tx_ring->count) {
6206 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6207 i = 0;
6208 }
6209 tx_desc->read.olinfo_status = 0;
6210
6211 #ifdef IXGBE_FCOE
6212 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6213 #else
6214 size = skb_frag_size(frag);
6215 #endif
6216 data_len -= size;
6217
6218 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6219 DMA_TO_DEVICE);
6220
6221 tx_buffer = &tx_ring->tx_buffer_info[i];
6222 }
6223
6224 /* write last descriptor with RS and EOP bits */
6225 cmd_type |= size | IXGBE_TXD_CMD;
6226 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6227
6228 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6229
6230 /* set the timestamp */
6231 first->time_stamp = jiffies;
6232
6233 /*
6234 * Force memory writes to complete before letting h/w know there
6235 * are new descriptors to fetch. (Only applicable for weak-ordered
6236 * memory model archs, such as IA-64).
6237 *
6238 * We also need this memory barrier to make certain all of the
6239 * status bits have been updated before next_to_watch is written.
6240 */
6241 wmb();
6242
6243 /* set next_to_watch value indicating a packet is present */
6244 first->next_to_watch = tx_desc;
6245
6246 i++;
6247 if (i == tx_ring->count)
6248 i = 0;
6249
6250 tx_ring->next_to_use = i;
6251
6252 /* notify HW of packet */
6253 writel(i, tx_ring->tail);
6254
6255 return;
6256 dma_error:
6257 dev_err(tx_ring->dev, "TX DMA map failed\n");
6258
6259 /* clear dma mappings for failed tx_buffer_info map */
6260 for (;;) {
6261 tx_buffer = &tx_ring->tx_buffer_info[i];
6262 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6263 if (tx_buffer == first)
6264 break;
6265 if (i == 0)
6266 i = tx_ring->count;
6267 i--;
6268 }
6269
6270 tx_ring->next_to_use = i;
6271 }
6272
6273 static void ixgbe_atr(struct ixgbe_ring *ring,
6274 struct ixgbe_tx_buffer *first)
6275 {
6276 struct ixgbe_q_vector *q_vector = ring->q_vector;
6277 union ixgbe_atr_hash_dword input = { .dword = 0 };
6278 union ixgbe_atr_hash_dword common = { .dword = 0 };
6279 union {
6280 unsigned char *network;
6281 struct iphdr *ipv4;
6282 struct ipv6hdr *ipv6;
6283 } hdr;
6284 struct tcphdr *th;
6285 __be16 vlan_id;
6286
6287 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6288 if (!q_vector)
6289 return;
6290
6291 /* do nothing if sampling is disabled */
6292 if (!ring->atr_sample_rate)
6293 return;
6294
6295 ring->atr_count++;
6296
6297 /* snag network header to get L4 type and address */
6298 hdr.network = skb_network_header(first->skb);
6299
6300 /* Currently only IPv4/IPv6 with TCP is supported */
6301 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6302 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6303 (first->protocol != __constant_htons(ETH_P_IP) ||
6304 hdr.ipv4->protocol != IPPROTO_TCP))
6305 return;
6306
6307 th = tcp_hdr(first->skb);
6308
6309 /* skip this packet since it is invalid or the socket is closing */
6310 if (!th || th->fin)
6311 return;
6312
6313 /* sample on all syn packets or once every atr sample count */
6314 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6315 return;
6316
6317 /* reset sample count */
6318 ring->atr_count = 0;
6319
6320 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6321
6322 /*
6323 * src and dst are inverted, think how the receiver sees them
6324 *
6325 * The input is broken into two sections, a non-compressed section
6326 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6327 * is XORed together and stored in the compressed dword.
6328 */
6329 input.formatted.vlan_id = vlan_id;
6330
6331 /*
6332 * since src port and flex bytes occupy the same word XOR them together
6333 * and write the value to source port portion of compressed dword
6334 */
6335 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6336 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6337 else
6338 common.port.src ^= th->dest ^ first->protocol;
6339 common.port.dst ^= th->source;
6340
6341 if (first->protocol == __constant_htons(ETH_P_IP)) {
6342 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6343 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6344 } else {
6345 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6346 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6347 hdr.ipv6->saddr.s6_addr32[1] ^
6348 hdr.ipv6->saddr.s6_addr32[2] ^
6349 hdr.ipv6->saddr.s6_addr32[3] ^
6350 hdr.ipv6->daddr.s6_addr32[0] ^
6351 hdr.ipv6->daddr.s6_addr32[1] ^
6352 hdr.ipv6->daddr.s6_addr32[2] ^
6353 hdr.ipv6->daddr.s6_addr32[3];
6354 }
6355
6356 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6357 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6358 input, common, ring->queue_index);
6359 }
6360
6361 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6362 {
6363 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6364 /* Herbert's original patch had:
6365 * smp_mb__after_netif_stop_queue();
6366 * but since that doesn't exist yet, just open code it. */
6367 smp_mb();
6368
6369 /* We need to check again in a case another CPU has just
6370 * made room available. */
6371 if (likely(ixgbe_desc_unused(tx_ring) < size))
6372 return -EBUSY;
6373
6374 /* A reprieve! - use start_queue because it doesn't call schedule */
6375 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6376 ++tx_ring->tx_stats.restart_queue;
6377 return 0;
6378 }
6379
6380 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6381 {
6382 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6383 return 0;
6384 return __ixgbe_maybe_stop_tx(tx_ring, size);
6385 }
6386
6387 #ifdef IXGBE_FCOE
6388 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6389 {
6390 struct ixgbe_adapter *adapter;
6391 struct ixgbe_ring_feature *f;
6392 int txq;
6393
6394 /*
6395 * only execute the code below if protocol is FCoE
6396 * or FIP and we have FCoE enabled on the adapter
6397 */
6398 switch (vlan_get_protocol(skb)) {
6399 case __constant_htons(ETH_P_FCOE):
6400 case __constant_htons(ETH_P_FIP):
6401 adapter = netdev_priv(dev);
6402
6403 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6404 break;
6405 default:
6406 return __netdev_pick_tx(dev, skb);
6407 }
6408
6409 f = &adapter->ring_feature[RING_F_FCOE];
6410
6411 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6412 smp_processor_id();
6413
6414 while (txq >= f->indices)
6415 txq -= f->indices;
6416
6417 return txq + f->offset;
6418 }
6419
6420 #endif
6421 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6422 struct ixgbe_adapter *adapter,
6423 struct ixgbe_ring *tx_ring)
6424 {
6425 struct ixgbe_tx_buffer *first;
6426 int tso;
6427 u32 tx_flags = 0;
6428 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6429 unsigned short f;
6430 #endif
6431 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6432 __be16 protocol = skb->protocol;
6433 u8 hdr_len = 0;
6434
6435 /*
6436 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6437 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6438 * + 2 desc gap to keep tail from touching head,
6439 * + 1 desc for context descriptor,
6440 * otherwise try next time
6441 */
6442 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6443 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6444 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6445 #else
6446 count += skb_shinfo(skb)->nr_frags;
6447 #endif
6448 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6449 tx_ring->tx_stats.tx_busy++;
6450 return NETDEV_TX_BUSY;
6451 }
6452
6453 /* record the location of the first descriptor for this packet */
6454 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6455 first->skb = skb;
6456 first->bytecount = skb->len;
6457 first->gso_segs = 1;
6458
6459 /* if we have a HW VLAN tag being added default to the HW one */
6460 if (vlan_tx_tag_present(skb)) {
6461 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6462 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6463 /* else if it is a SW VLAN check the next protocol and store the tag */
6464 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6465 struct vlan_hdr *vhdr, _vhdr;
6466 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6467 if (!vhdr)
6468 goto out_drop;
6469
6470 protocol = vhdr->h_vlan_encapsulated_proto;
6471 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6472 IXGBE_TX_FLAGS_VLAN_SHIFT;
6473 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6474 }
6475
6476 skb_tx_timestamp(skb);
6477
6478 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6479 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6480 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6481
6482 /* schedule check for Tx timestamp */
6483 adapter->ptp_tx_skb = skb_get(skb);
6484 adapter->ptp_tx_start = jiffies;
6485 schedule_work(&adapter->ptp_tx_work);
6486 }
6487
6488 #ifdef CONFIG_PCI_IOV
6489 /*
6490 * Use the l2switch_enable flag - would be false if the DMA
6491 * Tx switch had been disabled.
6492 */
6493 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6494 tx_flags |= IXGBE_TX_FLAGS_CC;
6495
6496 #endif
6497 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6498 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6499 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6500 (skb->priority != TC_PRIO_CONTROL))) {
6501 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6502 tx_flags |= (skb->priority & 0x7) <<
6503 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6504 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6505 struct vlan_ethhdr *vhdr;
6506 if (skb_header_cloned(skb) &&
6507 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6508 goto out_drop;
6509 vhdr = (struct vlan_ethhdr *)skb->data;
6510 vhdr->h_vlan_TCI = htons(tx_flags >>
6511 IXGBE_TX_FLAGS_VLAN_SHIFT);
6512 } else {
6513 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6514 }
6515 }
6516
6517 /* record initial flags and protocol */
6518 first->tx_flags = tx_flags;
6519 first->protocol = protocol;
6520
6521 #ifdef IXGBE_FCOE
6522 /* setup tx offload for FCoE */
6523 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6524 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6525 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6526 if (tso < 0)
6527 goto out_drop;
6528
6529 goto xmit_fcoe;
6530 }
6531
6532 #endif /* IXGBE_FCOE */
6533 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6534 if (tso < 0)
6535 goto out_drop;
6536 else if (!tso)
6537 ixgbe_tx_csum(tx_ring, first);
6538
6539 /* add the ATR filter if ATR is on */
6540 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6541 ixgbe_atr(tx_ring, first);
6542
6543 #ifdef IXGBE_FCOE
6544 xmit_fcoe:
6545 #endif /* IXGBE_FCOE */
6546 ixgbe_tx_map(tx_ring, first, hdr_len);
6547
6548 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6549
6550 return NETDEV_TX_OK;
6551
6552 out_drop:
6553 dev_kfree_skb_any(first->skb);
6554 first->skb = NULL;
6555
6556 return NETDEV_TX_OK;
6557 }
6558
6559 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6560 struct net_device *netdev)
6561 {
6562 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6563 struct ixgbe_ring *tx_ring;
6564
6565 /*
6566 * The minimum packet size for olinfo paylen is 17 so pad the skb
6567 * in order to meet this minimum size requirement.
6568 */
6569 if (unlikely(skb->len < 17)) {
6570 if (skb_pad(skb, 17 - skb->len))
6571 return NETDEV_TX_OK;
6572 skb->len = 17;
6573 skb_set_tail_pointer(skb, 17);
6574 }
6575
6576 tx_ring = adapter->tx_ring[skb->queue_mapping];
6577 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6578 }
6579
6580 /**
6581 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6582 * @netdev: network interface device structure
6583 * @p: pointer to an address structure
6584 *
6585 * Returns 0 on success, negative on failure
6586 **/
6587 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6588 {
6589 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6590 struct ixgbe_hw *hw = &adapter->hw;
6591 struct sockaddr *addr = p;
6592
6593 if (!is_valid_ether_addr(addr->sa_data))
6594 return -EADDRNOTAVAIL;
6595
6596 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6597 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6598
6599 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6600
6601 return 0;
6602 }
6603
6604 static int
6605 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6606 {
6607 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6608 struct ixgbe_hw *hw = &adapter->hw;
6609 u16 value;
6610 int rc;
6611
6612 if (prtad != hw->phy.mdio.prtad)
6613 return -EINVAL;
6614 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6615 if (!rc)
6616 rc = value;
6617 return rc;
6618 }
6619
6620 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6621 u16 addr, u16 value)
6622 {
6623 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6624 struct ixgbe_hw *hw = &adapter->hw;
6625
6626 if (prtad != hw->phy.mdio.prtad)
6627 return -EINVAL;
6628 return hw->phy.ops.write_reg(hw, addr, devad, value);
6629 }
6630
6631 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6632 {
6633 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6634
6635 switch (cmd) {
6636 case SIOCSHWTSTAMP:
6637 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6638 default:
6639 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6640 }
6641 }
6642
6643 /**
6644 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6645 * netdev->dev_addrs
6646 * @netdev: network interface device structure
6647 *
6648 * Returns non-zero on failure
6649 **/
6650 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6651 {
6652 int err = 0;
6653 struct ixgbe_adapter *adapter = netdev_priv(dev);
6654 struct ixgbe_hw *hw = &adapter->hw;
6655
6656 if (is_valid_ether_addr(hw->mac.san_addr)) {
6657 rtnl_lock();
6658 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6659 rtnl_unlock();
6660
6661 /* update SAN MAC vmdq pool selection */
6662 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6663 }
6664 return err;
6665 }
6666
6667 /**
6668 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6669 * netdev->dev_addrs
6670 * @netdev: network interface device structure
6671 *
6672 * Returns non-zero on failure
6673 **/
6674 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6675 {
6676 int err = 0;
6677 struct ixgbe_adapter *adapter = netdev_priv(dev);
6678 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6679
6680 if (is_valid_ether_addr(mac->san_addr)) {
6681 rtnl_lock();
6682 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6683 rtnl_unlock();
6684 }
6685 return err;
6686 }
6687
6688 #ifdef CONFIG_NET_POLL_CONTROLLER
6689 /*
6690 * Polling 'interrupt' - used by things like netconsole to send skbs
6691 * without having to re-enable interrupts. It's not called while
6692 * the interrupt routine is executing.
6693 */
6694 static void ixgbe_netpoll(struct net_device *netdev)
6695 {
6696 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6697 int i;
6698
6699 /* if interface is down do nothing */
6700 if (test_bit(__IXGBE_DOWN, &adapter->state))
6701 return;
6702
6703 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6704 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6705 for (i = 0; i < adapter->num_q_vectors; i++)
6706 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6707 } else {
6708 ixgbe_intr(adapter->pdev->irq, netdev);
6709 }
6710 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6711 }
6712
6713 #endif
6714 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6715 struct rtnl_link_stats64 *stats)
6716 {
6717 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6718 int i;
6719
6720 rcu_read_lock();
6721 for (i = 0; i < adapter->num_rx_queues; i++) {
6722 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6723 u64 bytes, packets;
6724 unsigned int start;
6725
6726 if (ring) {
6727 do {
6728 start = u64_stats_fetch_begin_bh(&ring->syncp);
6729 packets = ring->stats.packets;
6730 bytes = ring->stats.bytes;
6731 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6732 stats->rx_packets += packets;
6733 stats->rx_bytes += bytes;
6734 }
6735 }
6736
6737 for (i = 0; i < adapter->num_tx_queues; i++) {
6738 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6739 u64 bytes, packets;
6740 unsigned int start;
6741
6742 if (ring) {
6743 do {
6744 start = u64_stats_fetch_begin_bh(&ring->syncp);
6745 packets = ring->stats.packets;
6746 bytes = ring->stats.bytes;
6747 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6748 stats->tx_packets += packets;
6749 stats->tx_bytes += bytes;
6750 }
6751 }
6752 rcu_read_unlock();
6753 /* following stats updated by ixgbe_watchdog_task() */
6754 stats->multicast = netdev->stats.multicast;
6755 stats->rx_errors = netdev->stats.rx_errors;
6756 stats->rx_length_errors = netdev->stats.rx_length_errors;
6757 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6758 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6759 return stats;
6760 }
6761
6762 #ifdef CONFIG_IXGBE_DCB
6763 /**
6764 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6765 * @adapter: pointer to ixgbe_adapter
6766 * @tc: number of traffic classes currently enabled
6767 *
6768 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6769 * 802.1Q priority maps to a packet buffer that exists.
6770 */
6771 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6772 {
6773 struct ixgbe_hw *hw = &adapter->hw;
6774 u32 reg, rsave;
6775 int i;
6776
6777 /* 82598 have a static priority to TC mapping that can not
6778 * be changed so no validation is needed.
6779 */
6780 if (hw->mac.type == ixgbe_mac_82598EB)
6781 return;
6782
6783 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6784 rsave = reg;
6785
6786 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6787 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6788
6789 /* If up2tc is out of bounds default to zero */
6790 if (up2tc > tc)
6791 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6792 }
6793
6794 if (reg != rsave)
6795 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6796
6797 return;
6798 }
6799
6800 /**
6801 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6802 * @adapter: Pointer to adapter struct
6803 *
6804 * Populate the netdev user priority to tc map
6805 */
6806 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6807 {
6808 struct net_device *dev = adapter->netdev;
6809 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6810 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6811 u8 prio;
6812
6813 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6814 u8 tc = 0;
6815
6816 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6817 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6818 else if (ets)
6819 tc = ets->prio_tc[prio];
6820
6821 netdev_set_prio_tc_map(dev, prio, tc);
6822 }
6823 }
6824
6825 #endif /* CONFIG_IXGBE_DCB */
6826 /**
6827 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6828 *
6829 * @netdev: net device to configure
6830 * @tc: number of traffic classes to enable
6831 */
6832 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6833 {
6834 struct ixgbe_adapter *adapter = netdev_priv(dev);
6835 struct ixgbe_hw *hw = &adapter->hw;
6836
6837 /* Hardware supports up to 8 traffic classes */
6838 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6839 (hw->mac.type == ixgbe_mac_82598EB &&
6840 tc < MAX_TRAFFIC_CLASS))
6841 return -EINVAL;
6842
6843 /* Hardware has to reinitialize queues and interrupts to
6844 * match packet buffer alignment. Unfortunately, the
6845 * hardware is not flexible enough to do this dynamically.
6846 */
6847 if (netif_running(dev))
6848 ixgbe_close(dev);
6849 ixgbe_clear_interrupt_scheme(adapter);
6850
6851 #ifdef CONFIG_IXGBE_DCB
6852 if (tc) {
6853 netdev_set_num_tc(dev, tc);
6854 ixgbe_set_prio_tc_map(adapter);
6855
6856 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6857
6858 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6859 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6860 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6861 }
6862 } else {
6863 netdev_reset_tc(dev);
6864
6865 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6866 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6867
6868 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6869
6870 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6871 adapter->dcb_cfg.pfc_mode_enable = false;
6872 }
6873
6874 ixgbe_validate_rtr(adapter, tc);
6875
6876 #endif /* CONFIG_IXGBE_DCB */
6877 ixgbe_init_interrupt_scheme(adapter);
6878
6879 if (netif_running(dev))
6880 return ixgbe_open(dev);
6881
6882 return 0;
6883 }
6884
6885 #ifdef CONFIG_PCI_IOV
6886 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6887 {
6888 struct net_device *netdev = adapter->netdev;
6889
6890 rtnl_lock();
6891 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6892 rtnl_unlock();
6893 }
6894
6895 #endif
6896 void ixgbe_do_reset(struct net_device *netdev)
6897 {
6898 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6899
6900 if (netif_running(netdev))
6901 ixgbe_reinit_locked(adapter);
6902 else
6903 ixgbe_reset(adapter);
6904 }
6905
6906 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6907 netdev_features_t features)
6908 {
6909 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6910
6911 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6912 if (!(features & NETIF_F_RXCSUM))
6913 features &= ~NETIF_F_LRO;
6914
6915 /* Turn off LRO if not RSC capable */
6916 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6917 features &= ~NETIF_F_LRO;
6918
6919 return features;
6920 }
6921
6922 static int ixgbe_set_features(struct net_device *netdev,
6923 netdev_features_t features)
6924 {
6925 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926 netdev_features_t changed = netdev->features ^ features;
6927 bool need_reset = false;
6928
6929 /* Make sure RSC matches LRO, reset if change */
6930 if (!(features & NETIF_F_LRO)) {
6931 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6932 need_reset = true;
6933 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6934 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6935 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6936 if (adapter->rx_itr_setting == 1 ||
6937 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6938 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6939 need_reset = true;
6940 } else if ((changed ^ features) & NETIF_F_LRO) {
6941 e_info(probe, "rx-usecs set too low, "
6942 "disabling RSC\n");
6943 }
6944 }
6945
6946 /*
6947 * Check if Flow Director n-tuple support was enabled or disabled. If
6948 * the state changed, we need to reset.
6949 */
6950 switch (features & NETIF_F_NTUPLE) {
6951 case NETIF_F_NTUPLE:
6952 /* turn off ATR, enable perfect filters and reset */
6953 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6954 need_reset = true;
6955
6956 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6957 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6958 break;
6959 default:
6960 /* turn off perfect filters, enable ATR and reset */
6961 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6962 need_reset = true;
6963
6964 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6965
6966 /* We cannot enable ATR if SR-IOV is enabled */
6967 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6968 break;
6969
6970 /* We cannot enable ATR if we have 2 or more traffic classes */
6971 if (netdev_get_num_tc(netdev) > 1)
6972 break;
6973
6974 /* We cannot enable ATR if RSS is disabled */
6975 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6976 break;
6977
6978 /* A sample rate of 0 indicates ATR disabled */
6979 if (!adapter->atr_sample_rate)
6980 break;
6981
6982 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6983 break;
6984 }
6985
6986 if (features & NETIF_F_HW_VLAN_RX)
6987 ixgbe_vlan_strip_enable(adapter);
6988 else
6989 ixgbe_vlan_strip_disable(adapter);
6990
6991 if (changed & NETIF_F_RXALL)
6992 need_reset = true;
6993
6994 netdev->features = features;
6995 if (need_reset)
6996 ixgbe_do_reset(netdev);
6997
6998 return 0;
6999 }
7000
7001 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7002 struct net_device *dev,
7003 const unsigned char *addr,
7004 u16 flags)
7005 {
7006 struct ixgbe_adapter *adapter = netdev_priv(dev);
7007 int err;
7008
7009 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7010 return -EOPNOTSUPP;
7011
7012 /* Hardware does not support aging addresses so if a
7013 * ndm_state is given only allow permanent addresses
7014 */
7015 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7016 pr_info("%s: FDB only supports static addresses\n",
7017 ixgbe_driver_name);
7018 return -EINVAL;
7019 }
7020
7021 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7022 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7023
7024 if (netdev_uc_count(dev) < rar_uc_entries)
7025 err = dev_uc_add_excl(dev, addr);
7026 else
7027 err = -ENOMEM;
7028 } else if (is_multicast_ether_addr(addr)) {
7029 err = dev_mc_add_excl(dev, addr);
7030 } else {
7031 err = -EINVAL;
7032 }
7033
7034 /* Only return duplicate errors if NLM_F_EXCL is set */
7035 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7036 err = 0;
7037
7038 return err;
7039 }
7040
7041 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
7042 struct net_device *dev,
7043 const unsigned char *addr)
7044 {
7045 struct ixgbe_adapter *adapter = netdev_priv(dev);
7046 int err = -EOPNOTSUPP;
7047
7048 if (ndm->ndm_state & NUD_PERMANENT) {
7049 pr_info("%s: FDB only supports static addresses\n",
7050 ixgbe_driver_name);
7051 return -EINVAL;
7052 }
7053
7054 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7055 if (is_unicast_ether_addr(addr))
7056 err = dev_uc_del(dev, addr);
7057 else if (is_multicast_ether_addr(addr))
7058 err = dev_mc_del(dev, addr);
7059 else
7060 err = -EINVAL;
7061 }
7062
7063 return err;
7064 }
7065
7066 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7067 struct netlink_callback *cb,
7068 struct net_device *dev,
7069 int idx)
7070 {
7071 struct ixgbe_adapter *adapter = netdev_priv(dev);
7072
7073 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7074 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7075
7076 return idx;
7077 }
7078
7079 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7080 struct nlmsghdr *nlh)
7081 {
7082 struct ixgbe_adapter *adapter = netdev_priv(dev);
7083 struct nlattr *attr, *br_spec;
7084 int rem;
7085
7086 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7087 return -EOPNOTSUPP;
7088
7089 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7090
7091 nla_for_each_nested(attr, br_spec, rem) {
7092 __u16 mode;
7093 u32 reg = 0;
7094
7095 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7096 continue;
7097
7098 mode = nla_get_u16(attr);
7099 if (mode == BRIDGE_MODE_VEPA) {
7100 reg = 0;
7101 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7102 } else if (mode == BRIDGE_MODE_VEB) {
7103 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7104 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7105 } else
7106 return -EINVAL;
7107
7108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7109
7110 e_info(drv, "enabling bridge mode: %s\n",
7111 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7112 }
7113
7114 return 0;
7115 }
7116
7117 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7118 struct net_device *dev,
7119 u32 filter_mask)
7120 {
7121 struct ixgbe_adapter *adapter = netdev_priv(dev);
7122 u16 mode;
7123
7124 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7125 return 0;
7126
7127 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7128 mode = BRIDGE_MODE_VEB;
7129 else
7130 mode = BRIDGE_MODE_VEPA;
7131
7132 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7133 }
7134
7135 static const struct net_device_ops ixgbe_netdev_ops = {
7136 .ndo_open = ixgbe_open,
7137 .ndo_stop = ixgbe_close,
7138 .ndo_start_xmit = ixgbe_xmit_frame,
7139 #ifdef IXGBE_FCOE
7140 .ndo_select_queue = ixgbe_select_queue,
7141 #endif
7142 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7143 .ndo_validate_addr = eth_validate_addr,
7144 .ndo_set_mac_address = ixgbe_set_mac,
7145 .ndo_change_mtu = ixgbe_change_mtu,
7146 .ndo_tx_timeout = ixgbe_tx_timeout,
7147 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7148 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7149 .ndo_do_ioctl = ixgbe_ioctl,
7150 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7151 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7152 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7153 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7154 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7155 .ndo_get_stats64 = ixgbe_get_stats64,
7156 #ifdef CONFIG_IXGBE_DCB
7157 .ndo_setup_tc = ixgbe_setup_tc,
7158 #endif
7159 #ifdef CONFIG_NET_POLL_CONTROLLER
7160 .ndo_poll_controller = ixgbe_netpoll,
7161 #endif
7162 #ifdef IXGBE_FCOE
7163 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7164 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7165 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7166 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7167 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7168 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7169 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7170 #endif /* IXGBE_FCOE */
7171 .ndo_set_features = ixgbe_set_features,
7172 .ndo_fix_features = ixgbe_fix_features,
7173 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7174 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7175 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7176 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7177 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7178 };
7179
7180 /**
7181 * ixgbe_wol_supported - Check whether device supports WoL
7182 * @hw: hw specific details
7183 * @device_id: the device ID
7184 * @subdev_id: the subsystem device ID
7185 *
7186 * This function is used by probe and ethtool to determine
7187 * which devices have WoL support
7188 *
7189 **/
7190 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7191 u16 subdevice_id)
7192 {
7193 struct ixgbe_hw *hw = &adapter->hw;
7194 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7195 int is_wol_supported = 0;
7196
7197 switch (device_id) {
7198 case IXGBE_DEV_ID_82599_SFP:
7199 /* Only these subdevices could supports WOL */
7200 switch (subdevice_id) {
7201 case IXGBE_SUBDEV_ID_82599_560FLR:
7202 /* only support first port */
7203 if (hw->bus.func != 0)
7204 break;
7205 case IXGBE_SUBDEV_ID_82599_SFP:
7206 case IXGBE_SUBDEV_ID_82599_RNDC:
7207 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7208 is_wol_supported = 1;
7209 break;
7210 }
7211 break;
7212 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7213 /* All except this subdevice support WOL */
7214 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7215 is_wol_supported = 1;
7216 break;
7217 case IXGBE_DEV_ID_82599_KX4:
7218 is_wol_supported = 1;
7219 break;
7220 case IXGBE_DEV_ID_X540T:
7221 case IXGBE_DEV_ID_X540T1:
7222 /* check eeprom to see if enabled wol */
7223 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7224 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7225 (hw->bus.func == 0))) {
7226 is_wol_supported = 1;
7227 }
7228 break;
7229 }
7230
7231 return is_wol_supported;
7232 }
7233
7234 /**
7235 * ixgbe_probe - Device Initialization Routine
7236 * @pdev: PCI device information struct
7237 * @ent: entry in ixgbe_pci_tbl
7238 *
7239 * Returns 0 on success, negative on failure
7240 *
7241 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7242 * The OS initialization, configuring of the adapter private structure,
7243 * and a hardware reset occur.
7244 **/
7245 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7246 {
7247 struct net_device *netdev;
7248 struct ixgbe_adapter *adapter = NULL;
7249 struct ixgbe_hw *hw;
7250 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7251 static int cards_found;
7252 int i, err, pci_using_dac;
7253 unsigned int indices = MAX_TX_QUEUES;
7254 u8 part_str[IXGBE_PBANUM_LENGTH];
7255 #ifdef IXGBE_FCOE
7256 u16 device_caps;
7257 #endif
7258 u32 eec;
7259
7260 /* Catch broken hardware that put the wrong VF device ID in
7261 * the PCIe SR-IOV capability.
7262 */
7263 if (pdev->is_virtfn) {
7264 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7265 pci_name(pdev), pdev->vendor, pdev->device);
7266 return -EINVAL;
7267 }
7268
7269 err = pci_enable_device_mem(pdev);
7270 if (err)
7271 return err;
7272
7273 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7274 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7275 pci_using_dac = 1;
7276 } else {
7277 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7278 if (err) {
7279 err = dma_set_coherent_mask(&pdev->dev,
7280 DMA_BIT_MASK(32));
7281 if (err) {
7282 dev_err(&pdev->dev,
7283 "No usable DMA configuration, aborting\n");
7284 goto err_dma;
7285 }
7286 }
7287 pci_using_dac = 0;
7288 }
7289
7290 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7291 IORESOURCE_MEM), ixgbe_driver_name);
7292 if (err) {
7293 dev_err(&pdev->dev,
7294 "pci_request_selected_regions failed 0x%x\n", err);
7295 goto err_pci_reg;
7296 }
7297
7298 pci_enable_pcie_error_reporting(pdev);
7299
7300 pci_set_master(pdev);
7301 pci_save_state(pdev);
7302
7303 if (ii->mac == ixgbe_mac_82598EB) {
7304 #ifdef CONFIG_IXGBE_DCB
7305 /* 8 TC w/ 4 queues per TC */
7306 indices = 4 * MAX_TRAFFIC_CLASS;
7307 #else
7308 indices = IXGBE_MAX_RSS_INDICES;
7309 #endif
7310 }
7311
7312 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7313 if (!netdev) {
7314 err = -ENOMEM;
7315 goto err_alloc_etherdev;
7316 }
7317
7318 SET_NETDEV_DEV(netdev, &pdev->dev);
7319
7320 adapter = netdev_priv(netdev);
7321 pci_set_drvdata(pdev, adapter);
7322
7323 adapter->netdev = netdev;
7324 adapter->pdev = pdev;
7325 hw = &adapter->hw;
7326 hw->back = adapter;
7327 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7328
7329 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7330 pci_resource_len(pdev, 0));
7331 if (!hw->hw_addr) {
7332 err = -EIO;
7333 goto err_ioremap;
7334 }
7335
7336 netdev->netdev_ops = &ixgbe_netdev_ops;
7337 ixgbe_set_ethtool_ops(netdev);
7338 netdev->watchdog_timeo = 5 * HZ;
7339 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7340
7341 adapter->bd_number = cards_found;
7342
7343 /* Setup hw api */
7344 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7345 hw->mac.type = ii->mac;
7346
7347 /* EEPROM */
7348 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7349 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7350 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7351 if (!(eec & (1 << 8)))
7352 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7353
7354 /* PHY */
7355 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7356 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7357 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7358 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7359 hw->phy.mdio.mmds = 0;
7360 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7361 hw->phy.mdio.dev = netdev;
7362 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7363 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7364
7365 ii->get_invariants(hw);
7366
7367 /* setup the private structure */
7368 err = ixgbe_sw_init(adapter);
7369 if (err)
7370 goto err_sw_init;
7371
7372 /* Make it possible the adapter to be woken up via WOL */
7373 switch (adapter->hw.mac.type) {
7374 case ixgbe_mac_82599EB:
7375 case ixgbe_mac_X540:
7376 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7377 break;
7378 default:
7379 break;
7380 }
7381
7382 /*
7383 * If there is a fan on this device and it has failed log the
7384 * failure.
7385 */
7386 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7387 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7388 if (esdp & IXGBE_ESDP_SDP1)
7389 e_crit(probe, "Fan has stopped, replace the adapter\n");
7390 }
7391
7392 if (allow_unsupported_sfp)
7393 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7394
7395 /* reset_hw fills in the perm_addr as well */
7396 hw->phy.reset_if_overtemp = true;
7397 err = hw->mac.ops.reset_hw(hw);
7398 hw->phy.reset_if_overtemp = false;
7399 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7400 hw->mac.type == ixgbe_mac_82598EB) {
7401 err = 0;
7402 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7403 e_dev_err("failed to load because an unsupported SFP+ "
7404 "module type was detected.\n");
7405 e_dev_err("Reload the driver after installing a supported "
7406 "module.\n");
7407 goto err_sw_init;
7408 } else if (err) {
7409 e_dev_err("HW Init failed: %d\n", err);
7410 goto err_sw_init;
7411 }
7412
7413 #ifdef CONFIG_PCI_IOV
7414 /* SR-IOV not supported on the 82598 */
7415 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7416 goto skip_sriov;
7417 /* Mailbox */
7418 ixgbe_init_mbx_params_pf(hw);
7419 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7420 ixgbe_enable_sriov(adapter);
7421 pci_sriov_set_totalvfs(pdev, 63);
7422 skip_sriov:
7423
7424 #endif
7425 netdev->features = NETIF_F_SG |
7426 NETIF_F_IP_CSUM |
7427 NETIF_F_IPV6_CSUM |
7428 NETIF_F_HW_VLAN_TX |
7429 NETIF_F_HW_VLAN_RX |
7430 NETIF_F_HW_VLAN_FILTER |
7431 NETIF_F_TSO |
7432 NETIF_F_TSO6 |
7433 NETIF_F_RXHASH |
7434 NETIF_F_RXCSUM;
7435
7436 netdev->hw_features = netdev->features;
7437
7438 switch (adapter->hw.mac.type) {
7439 case ixgbe_mac_82599EB:
7440 case ixgbe_mac_X540:
7441 netdev->features |= NETIF_F_SCTP_CSUM;
7442 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7443 NETIF_F_NTUPLE;
7444 break;
7445 default:
7446 break;
7447 }
7448
7449 netdev->hw_features |= NETIF_F_RXALL;
7450
7451 netdev->vlan_features |= NETIF_F_TSO;
7452 netdev->vlan_features |= NETIF_F_TSO6;
7453 netdev->vlan_features |= NETIF_F_IP_CSUM;
7454 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7455 netdev->vlan_features |= NETIF_F_SG;
7456
7457 netdev->priv_flags |= IFF_UNICAST_FLT;
7458 netdev->priv_flags |= IFF_SUPP_NOFCS;
7459
7460 #ifdef CONFIG_IXGBE_DCB
7461 netdev->dcbnl_ops = &dcbnl_ops;
7462 #endif
7463
7464 #ifdef IXGBE_FCOE
7465 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7466 unsigned int fcoe_l;
7467
7468 if (hw->mac.ops.get_device_caps) {
7469 hw->mac.ops.get_device_caps(hw, &device_caps);
7470 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7471 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7472 }
7473
7474
7475 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7476 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7477
7478 netdev->features |= NETIF_F_FSO |
7479 NETIF_F_FCOE_CRC;
7480
7481 netdev->vlan_features |= NETIF_F_FSO |
7482 NETIF_F_FCOE_CRC |
7483 NETIF_F_FCOE_MTU;
7484 }
7485 #endif /* IXGBE_FCOE */
7486 if (pci_using_dac) {
7487 netdev->features |= NETIF_F_HIGHDMA;
7488 netdev->vlan_features |= NETIF_F_HIGHDMA;
7489 }
7490
7491 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7492 netdev->hw_features |= NETIF_F_LRO;
7493 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7494 netdev->features |= NETIF_F_LRO;
7495
7496 /* make sure the EEPROM is good */
7497 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7498 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7499 err = -EIO;
7500 goto err_sw_init;
7501 }
7502
7503 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7504
7505 if (!is_valid_ether_addr(netdev->dev_addr)) {
7506 e_dev_err("invalid MAC address\n");
7507 err = -EIO;
7508 goto err_sw_init;
7509 }
7510
7511 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7512 (unsigned long) adapter);
7513
7514 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7515 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7516
7517 err = ixgbe_init_interrupt_scheme(adapter);
7518 if (err)
7519 goto err_sw_init;
7520
7521 /* WOL not supported for all devices */
7522 adapter->wol = 0;
7523 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7524 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7525 adapter->wol = IXGBE_WUFC_MAG;
7526
7527 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7528
7529 /* save off EEPROM version number */
7530 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7531 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7532
7533 /* pick up the PCI bus settings for reporting later */
7534 hw->mac.ops.get_bus_info(hw);
7535
7536 /* print bus type/speed/width info */
7537 e_dev_info("(PCI Express:%s:%s) %pM\n",
7538 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7539 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7540 "Unknown"),
7541 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7542 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7543 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7544 "Unknown"),
7545 netdev->dev_addr);
7546
7547 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7548 if (err)
7549 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7550 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7551 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7552 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7553 part_str);
7554 else
7555 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7556 hw->mac.type, hw->phy.type, part_str);
7557
7558 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7559 e_dev_warn("PCI-Express bandwidth available for this card is "
7560 "not sufficient for optimal performance.\n");
7561 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7562 "is required.\n");
7563 }
7564
7565 /* reset the hardware with the new settings */
7566 err = hw->mac.ops.start_hw(hw);
7567 if (err == IXGBE_ERR_EEPROM_VERSION) {
7568 /* We are running on a pre-production device, log a warning */
7569 e_dev_warn("This device is a pre-production adapter/LOM. "
7570 "Please be aware there may be issues associated "
7571 "with your hardware. If you are experiencing "
7572 "problems please contact your Intel or hardware "
7573 "representative who provided you with this "
7574 "hardware.\n");
7575 }
7576 strcpy(netdev->name, "eth%d");
7577 err = register_netdev(netdev);
7578 if (err)
7579 goto err_register;
7580
7581 /* power down the optics for 82599 SFP+ fiber */
7582 if (hw->mac.ops.disable_tx_laser)
7583 hw->mac.ops.disable_tx_laser(hw);
7584
7585 /* carrier off reporting is important to ethtool even BEFORE open */
7586 netif_carrier_off(netdev);
7587
7588 #ifdef CONFIG_IXGBE_DCA
7589 if (dca_add_requester(&pdev->dev) == 0) {
7590 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7591 ixgbe_setup_dca(adapter);
7592 }
7593 #endif
7594 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7595 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7596 for (i = 0; i < adapter->num_vfs; i++)
7597 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7598 }
7599
7600 /* firmware requires driver version to be 0xFFFFFFFF
7601 * since os does not support feature
7602 */
7603 if (hw->mac.ops.set_fw_drv_ver)
7604 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7605 0xFF);
7606
7607 /* add san mac addr to netdev */
7608 ixgbe_add_sanmac_netdev(netdev);
7609
7610 e_dev_info("%s\n", ixgbe_default_device_descr);
7611 cards_found++;
7612
7613 #ifdef CONFIG_IXGBE_HWMON
7614 if (ixgbe_sysfs_init(adapter))
7615 e_err(probe, "failed to allocate sysfs resources\n");
7616 #endif /* CONFIG_IXGBE_HWMON */
7617
7618 #ifdef CONFIG_DEBUG_FS
7619 ixgbe_dbg_adapter_init(adapter);
7620 #endif /* CONFIG_DEBUG_FS */
7621
7622 return 0;
7623
7624 err_register:
7625 ixgbe_release_hw_control(adapter);
7626 ixgbe_clear_interrupt_scheme(adapter);
7627 err_sw_init:
7628 ixgbe_disable_sriov(adapter);
7629 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7630 iounmap(hw->hw_addr);
7631 err_ioremap:
7632 free_netdev(netdev);
7633 err_alloc_etherdev:
7634 pci_release_selected_regions(pdev,
7635 pci_select_bars(pdev, IORESOURCE_MEM));
7636 err_pci_reg:
7637 err_dma:
7638 pci_disable_device(pdev);
7639 return err;
7640 }
7641
7642 /**
7643 * ixgbe_remove - Device Removal Routine
7644 * @pdev: PCI device information struct
7645 *
7646 * ixgbe_remove is called by the PCI subsystem to alert the driver
7647 * that it should release a PCI device. The could be caused by a
7648 * Hot-Plug event, or because the driver is going to be removed from
7649 * memory.
7650 **/
7651 static void ixgbe_remove(struct pci_dev *pdev)
7652 {
7653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7654 struct net_device *netdev = adapter->netdev;
7655
7656 #ifdef CONFIG_DEBUG_FS
7657 ixgbe_dbg_adapter_exit(adapter);
7658 #endif /*CONFIG_DEBUG_FS */
7659
7660 set_bit(__IXGBE_DOWN, &adapter->state);
7661 cancel_work_sync(&adapter->service_task);
7662
7663
7664 #ifdef CONFIG_IXGBE_DCA
7665 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7666 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7667 dca_remove_requester(&pdev->dev);
7668 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7669 }
7670
7671 #endif
7672 #ifdef CONFIG_IXGBE_HWMON
7673 ixgbe_sysfs_exit(adapter);
7674 #endif /* CONFIG_IXGBE_HWMON */
7675
7676 /* remove the added san mac */
7677 ixgbe_del_sanmac_netdev(netdev);
7678
7679 if (netdev->reg_state == NETREG_REGISTERED)
7680 unregister_netdev(netdev);
7681
7682 #ifdef CONFIG_PCI_IOV
7683 /*
7684 * Only disable SR-IOV on unload if the user specified the now
7685 * deprecated max_vfs module parameter.
7686 */
7687 if (max_vfs)
7688 ixgbe_disable_sriov(adapter);
7689 #endif
7690 ixgbe_clear_interrupt_scheme(adapter);
7691
7692 ixgbe_release_hw_control(adapter);
7693
7694 #ifdef CONFIG_DCB
7695 kfree(adapter->ixgbe_ieee_pfc);
7696 kfree(adapter->ixgbe_ieee_ets);
7697
7698 #endif
7699 iounmap(adapter->hw.hw_addr);
7700 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7701 IORESOURCE_MEM));
7702
7703 e_dev_info("complete\n");
7704
7705 free_netdev(netdev);
7706
7707 pci_disable_pcie_error_reporting(pdev);
7708
7709 pci_disable_device(pdev);
7710 }
7711
7712 /**
7713 * ixgbe_io_error_detected - called when PCI error is detected
7714 * @pdev: Pointer to PCI device
7715 * @state: The current pci connection state
7716 *
7717 * This function is called after a PCI bus error affecting
7718 * this device has been detected.
7719 */
7720 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7721 pci_channel_state_t state)
7722 {
7723 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7724 struct net_device *netdev = adapter->netdev;
7725
7726 #ifdef CONFIG_PCI_IOV
7727 struct pci_dev *bdev, *vfdev;
7728 u32 dw0, dw1, dw2, dw3;
7729 int vf, pos;
7730 u16 req_id, pf_func;
7731
7732 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7733 adapter->num_vfs == 0)
7734 goto skip_bad_vf_detection;
7735
7736 bdev = pdev->bus->self;
7737 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7738 bdev = bdev->bus->self;
7739
7740 if (!bdev)
7741 goto skip_bad_vf_detection;
7742
7743 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7744 if (!pos)
7745 goto skip_bad_vf_detection;
7746
7747 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7748 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7749 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7750 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7751
7752 req_id = dw1 >> 16;
7753 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7754 if (!(req_id & 0x0080))
7755 goto skip_bad_vf_detection;
7756
7757 pf_func = req_id & 0x01;
7758 if ((pf_func & 1) == (pdev->devfn & 1)) {
7759 unsigned int device_id;
7760
7761 vf = (req_id & 0x7F) >> 1;
7762 e_dev_err("VF %d has caused a PCIe error\n", vf);
7763 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7764 "%8.8x\tdw3: %8.8x\n",
7765 dw0, dw1, dw2, dw3);
7766 switch (adapter->hw.mac.type) {
7767 case ixgbe_mac_82599EB:
7768 device_id = IXGBE_82599_VF_DEVICE_ID;
7769 break;
7770 case ixgbe_mac_X540:
7771 device_id = IXGBE_X540_VF_DEVICE_ID;
7772 break;
7773 default:
7774 device_id = 0;
7775 break;
7776 }
7777
7778 /* Find the pci device of the offending VF */
7779 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7780 while (vfdev) {
7781 if (vfdev->devfn == (req_id & 0xFF))
7782 break;
7783 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7784 device_id, vfdev);
7785 }
7786 /*
7787 * There's a slim chance the VF could have been hot plugged,
7788 * so if it is no longer present we don't need to issue the
7789 * VFLR. Just clean up the AER in that case.
7790 */
7791 if (vfdev) {
7792 e_dev_err("Issuing VFLR to VF %d\n", vf);
7793 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7794 /* Free device reference count */
7795 pci_dev_put(vfdev);
7796 }
7797
7798 pci_cleanup_aer_uncorrect_error_status(pdev);
7799 }
7800
7801 /*
7802 * Even though the error may have occurred on the other port
7803 * we still need to increment the vf error reference count for
7804 * both ports because the I/O resume function will be called
7805 * for both of them.
7806 */
7807 adapter->vferr_refcount++;
7808
7809 return PCI_ERS_RESULT_RECOVERED;
7810
7811 skip_bad_vf_detection:
7812 #endif /* CONFIG_PCI_IOV */
7813 netif_device_detach(netdev);
7814
7815 if (state == pci_channel_io_perm_failure)
7816 return PCI_ERS_RESULT_DISCONNECT;
7817
7818 if (netif_running(netdev))
7819 ixgbe_down(adapter);
7820 pci_disable_device(pdev);
7821
7822 /* Request a slot reset. */
7823 return PCI_ERS_RESULT_NEED_RESET;
7824 }
7825
7826 /**
7827 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7828 * @pdev: Pointer to PCI device
7829 *
7830 * Restart the card from scratch, as if from a cold-boot.
7831 */
7832 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7833 {
7834 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7835 pci_ers_result_t result;
7836 int err;
7837
7838 if (pci_enable_device_mem(pdev)) {
7839 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7840 result = PCI_ERS_RESULT_DISCONNECT;
7841 } else {
7842 pci_set_master(pdev);
7843 pci_restore_state(pdev);
7844 pci_save_state(pdev);
7845
7846 pci_wake_from_d3(pdev, false);
7847
7848 ixgbe_reset(adapter);
7849 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7850 result = PCI_ERS_RESULT_RECOVERED;
7851 }
7852
7853 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7854 if (err) {
7855 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7856 "failed 0x%0x\n", err);
7857 /* non-fatal, continue */
7858 }
7859
7860 return result;
7861 }
7862
7863 /**
7864 * ixgbe_io_resume - called when traffic can start flowing again.
7865 * @pdev: Pointer to PCI device
7866 *
7867 * This callback is called when the error recovery driver tells us that
7868 * its OK to resume normal operation.
7869 */
7870 static void ixgbe_io_resume(struct pci_dev *pdev)
7871 {
7872 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7873 struct net_device *netdev = adapter->netdev;
7874
7875 #ifdef CONFIG_PCI_IOV
7876 if (adapter->vferr_refcount) {
7877 e_info(drv, "Resuming after VF err\n");
7878 adapter->vferr_refcount--;
7879 return;
7880 }
7881
7882 #endif
7883 if (netif_running(netdev))
7884 ixgbe_up(adapter);
7885
7886 netif_device_attach(netdev);
7887 }
7888
7889 static const struct pci_error_handlers ixgbe_err_handler = {
7890 .error_detected = ixgbe_io_error_detected,
7891 .slot_reset = ixgbe_io_slot_reset,
7892 .resume = ixgbe_io_resume,
7893 };
7894
7895 static struct pci_driver ixgbe_driver = {
7896 .name = ixgbe_driver_name,
7897 .id_table = ixgbe_pci_tbl,
7898 .probe = ixgbe_probe,
7899 .remove = ixgbe_remove,
7900 #ifdef CONFIG_PM
7901 .suspend = ixgbe_suspend,
7902 .resume = ixgbe_resume,
7903 #endif
7904 .shutdown = ixgbe_shutdown,
7905 .sriov_configure = ixgbe_pci_sriov_configure,
7906 .err_handler = &ixgbe_err_handler
7907 };
7908
7909 /**
7910 * ixgbe_init_module - Driver Registration Routine
7911 *
7912 * ixgbe_init_module is the first routine called when the driver is
7913 * loaded. All it does is register with the PCI subsystem.
7914 **/
7915 static int __init ixgbe_init_module(void)
7916 {
7917 int ret;
7918 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7919 pr_info("%s\n", ixgbe_copyright);
7920
7921 #ifdef CONFIG_DEBUG_FS
7922 ixgbe_dbg_init();
7923 #endif /* CONFIG_DEBUG_FS */
7924
7925 ret = pci_register_driver(&ixgbe_driver);
7926 if (ret) {
7927 #ifdef CONFIG_DEBUG_FS
7928 ixgbe_dbg_exit();
7929 #endif /* CONFIG_DEBUG_FS */
7930 return ret;
7931 }
7932
7933 #ifdef CONFIG_IXGBE_DCA
7934 dca_register_notify(&dca_notifier);
7935 #endif
7936
7937 return 0;
7938 }
7939
7940 module_init(ixgbe_init_module);
7941
7942 /**
7943 * ixgbe_exit_module - Driver Exit Cleanup Routine
7944 *
7945 * ixgbe_exit_module is called just before the driver is removed
7946 * from memory.
7947 **/
7948 static void __exit ixgbe_exit_module(void)
7949 {
7950 #ifdef CONFIG_IXGBE_DCA
7951 dca_unregister_notify(&dca_notifier);
7952 #endif
7953 pci_unregister_driver(&ixgbe_driver);
7954
7955 #ifdef CONFIG_DEBUG_FS
7956 ixgbe_dbg_exit();
7957 #endif /* CONFIG_DEBUG_FS */
7958
7959 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7960 }
7961
7962 #ifdef CONFIG_IXGBE_DCA
7963 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7964 void *p)
7965 {
7966 int ret_val;
7967
7968 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7969 __ixgbe_notify_dca);
7970
7971 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7972 }
7973
7974 #endif /* CONFIG_IXGBE_DCA */
7975
7976 module_exit(ixgbe_exit_module);
7977
7978 /* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)