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net: remove use of ndo_set_multicast_list in drivers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / dec / tulip / dmfe.c
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@lxorguk.ukuu.org.uk>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
66 #define DRV_NAME "dmfe"
67 #define DRV_VERSION "1.36.4"
68 #define DRV_RELDATE "2002-01-17"
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/ptrace.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/ethtool.h>
84 #include <linux/skbuff.h>
85 #include <linux/delay.h>
86 #include <linux/spinlock.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89
90 #include <asm/processor.h>
91 #include <asm/io.h>
92 #include <asm/dma.h>
93 #include <asm/uaccess.h>
94 #include <asm/irq.h>
95
96 #ifdef CONFIG_TULIP_DM910X
97 #include <linux/of.h>
98 #endif
99
100
101 /* Board/System/Debug information/definition ---------------- */
102 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107 #define DM9102_IO_SIZE 0x80
108 #define DM9102A_IO_SIZE 0x100
109 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115 #define TX_BUF_ALLOC 0x600
116 #define RX_ALLOC_SIZE 0x620
117 #define DM910X_RESET 1
118 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119 #define CR6_DEFAULT 0x00080000 /* HD */
120 #define CR7_DEFAULT 0x180c1
121 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123 #define MAX_PACKET_SIZE 1514
124 #define DMFE_MAX_MULTICAST 14
125 #define RX_COPY_SIZE 100
126 #define MAX_CHECK_PACKET 0x8000
127 #define DM9801_NOISE_FLOOR 8
128 #define DM9802_NOISE_FLOOR 5
129
130 #define DMFE_WOL_LINKCHANGE 0x20000000
131 #define DMFE_WOL_SAMPLEPACKET 0x10000000
132 #define DMFE_WOL_MAGICPACKET 0x08000000
133
134
135 #define DMFE_10MHF 0
136 #define DMFE_100MHF 1
137 #define DMFE_10MFD 4
138 #define DMFE_100MFD 5
139 #define DMFE_AUTO 8
140 #define DMFE_1M_HPNA 0x10
141
142 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
153 #define DMFE_DBUG(dbug_now, msg, value) \
154 do { \
155 if (dmfe_debug || (dbug_now)) \
156 pr_err("%s %lx\n", \
157 (msg), (long) (value)); \
158 } while (0)
159
160 #define SHOW_MEDIA_TYPE(mode) \
161 pr_info("Change Speed to %sMhz %s duplex\n" , \
162 (mode & 1) ? "100":"10", \
163 (mode & 4) ? "full":"half");
164
165
166 /* CR9 definition: SROM/MII */
167 #define CR9_SROM_READ 0x4800
168 #define CR9_SRCS 0x1
169 #define CR9_SRCLK 0x2
170 #define CR9_CRDOUT 0x8
171 #define SROM_DATA_0 0x0
172 #define SROM_DATA_1 0x4
173 #define PHY_DATA_1 0x20000
174 #define PHY_DATA_0 0x00000
175 #define MDCLKH 0x10000
176
177 #define PHY_POWER_DOWN 0x800
178
179 #define SROM_V41_CODE 0x14
180
181 #define SROM_CLK_WRITE(data, ioaddr) \
182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
185 udelay(5); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
187 udelay(5);
188
189 #define __CHK_IO_SIZE(pci_id, dev_rev) \
190 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
191 DM9102A_IO_SIZE: DM9102_IO_SIZE)
192
193 #define CHK_IO_SIZE(pci_dev) \
194 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
195 (pci_dev)->revision))
196
197 /* Sten Check */
198 #define DEVICE net_device
199
200 /* Structure/enum declaration ------------------------------- */
201 struct tx_desc {
202 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
203 char *tx_buf_ptr; /* Data for us */
204 struct tx_desc *next_tx_desc;
205 } __attribute__(( aligned(32) ));
206
207 struct rx_desc {
208 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
209 struct sk_buff *rx_skb_ptr; /* Data for us */
210 struct rx_desc *next_rx_desc;
211 } __attribute__(( aligned(32) ));
212
213 struct dmfe_board_info {
214 u32 chip_id; /* Chip vendor/Device ID */
215 u8 chip_revision; /* Chip revision */
216 struct DEVICE *next_dev; /* next device */
217 struct pci_dev *pdev; /* PCI device */
218 spinlock_t lock;
219
220 long ioaddr; /* I/O base address */
221 u32 cr0_data;
222 u32 cr5_data;
223 u32 cr6_data;
224 u32 cr7_data;
225 u32 cr15_data;
226
227 /* pointer for memory physical address */
228 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
229 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
230 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
231 dma_addr_t first_tx_desc_dma;
232 dma_addr_t first_rx_desc_dma;
233
234 /* descriptor pointer */
235 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
236 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
237 unsigned char *desc_pool_ptr; /* descriptor pool memory */
238 struct tx_desc *first_tx_desc;
239 struct tx_desc *tx_insert_ptr;
240 struct tx_desc *tx_remove_ptr;
241 struct rx_desc *first_rx_desc;
242 struct rx_desc *rx_insert_ptr;
243 struct rx_desc *rx_ready_ptr; /* packet come pointer */
244 unsigned long tx_packet_cnt; /* transmitted packet count */
245 unsigned long tx_queue_cnt; /* wait to send packet count */
246 unsigned long rx_avail_cnt; /* available rx descriptor count */
247 unsigned long interval_rx_cnt; /* rx packet count a callback time */
248
249 u16 HPNA_command; /* For HPNA register 16 */
250 u16 HPNA_timer; /* For HPNA remote device check */
251 u16 dbug_cnt;
252 u16 NIC_capability; /* NIC media capability */
253 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
254
255 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
256 u8 chip_type; /* Keep DM9102A chip type */
257 u8 media_mode; /* user specify media mode */
258 u8 op_mode; /* real work media mode */
259 u8 phy_addr;
260 u8 wait_reset; /* Hardware failed, need to reset */
261 u8 dm910x_chk_mode; /* Operating mode check */
262 u8 first_in_callback; /* Flag to record state */
263 u8 wol_mode; /* user WOL settings */
264 struct timer_list timer;
265
266 /* Driver defined statistic counter */
267 unsigned long tx_fifo_underrun;
268 unsigned long tx_loss_carrier;
269 unsigned long tx_no_carrier;
270 unsigned long tx_late_collision;
271 unsigned long tx_excessive_collision;
272 unsigned long tx_jabber_timeout;
273 unsigned long reset_count;
274 unsigned long reset_cr8;
275 unsigned long reset_fatal;
276 unsigned long reset_TXtimeout;
277
278 /* NIC SROM data */
279 unsigned char srom[128];
280 };
281
282 enum dmfe_offsets {
283 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
284 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
285 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
286 DCR15 = 0x78
287 };
288
289 enum dmfe_CR6_bits {
290 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
291 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
292 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
293 };
294
295 /* Global variable declaration ----------------------------- */
296 static int __devinitdata printed_version;
297 static const char version[] __devinitconst =
298 "Davicom DM9xxx net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
299
300 static int dmfe_debug;
301 static unsigned char dmfe_media_mode = DMFE_AUTO;
302 static u32 dmfe_cr6_user_set;
303
304 /* For module input parameter */
305 static int debug;
306 static u32 cr6set;
307 static unsigned char mode = 8;
308 static u8 chkmode = 1;
309 static u8 HPNA_mode; /* Default: Low Power/High Speed */
310 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
311 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
312 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
313 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
314 4: TX pause packet */
315
316
317 /* function declaration ------------------------------------- */
318 static int dmfe_open(struct DEVICE *);
319 static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
320 static int dmfe_stop(struct DEVICE *);
321 static void dmfe_set_filter_mode(struct DEVICE *);
322 static const struct ethtool_ops netdev_ethtool_ops;
323 static u16 read_srom_word(long ,int);
324 static irqreturn_t dmfe_interrupt(int , void *);
325 #ifdef CONFIG_NET_POLL_CONTROLLER
326 static void poll_dmfe (struct net_device *dev);
327 #endif
328 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
329 static void allocate_rx_buffer(struct dmfe_board_info *);
330 static void update_cr6(u32, unsigned long);
331 static void send_filter_frame(struct DEVICE *);
332 static void dm9132_id_table(struct DEVICE *);
333 static u16 phy_read(unsigned long, u8, u8, u32);
334 static void phy_write(unsigned long, u8, u8, u16, u32);
335 static void phy_write_1bit(unsigned long, u32);
336 static u16 phy_read_1bit(unsigned long);
337 static u8 dmfe_sense_speed(struct dmfe_board_info *);
338 static void dmfe_process_mode(struct dmfe_board_info *);
339 static void dmfe_timer(unsigned long);
340 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
341 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
342 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
343 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
344 static void dmfe_dynamic_reset(struct DEVICE *);
345 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
346 static void dmfe_init_dm910x(struct DEVICE *);
347 static void dmfe_parse_srom(struct dmfe_board_info *);
348 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
349 static void dmfe_program_DM9802(struct dmfe_board_info *);
350 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
351 static void dmfe_set_phyxcer(struct dmfe_board_info *);
352
353 /* DM910X network board routine ---------------------------- */
354
355 static const struct net_device_ops netdev_ops = {
356 .ndo_open = dmfe_open,
357 .ndo_stop = dmfe_stop,
358 .ndo_start_xmit = dmfe_start_xmit,
359 .ndo_set_rx_mode = dmfe_set_filter_mode,
360 .ndo_change_mtu = eth_change_mtu,
361 .ndo_set_mac_address = eth_mac_addr,
362 .ndo_validate_addr = eth_validate_addr,
363 #ifdef CONFIG_NET_POLL_CONTROLLER
364 .ndo_poll_controller = poll_dmfe,
365 #endif
366 };
367
368 /*
369 * Search DM910X board ,allocate space and register it
370 */
371
372 static int __devinit dmfe_init_one (struct pci_dev *pdev,
373 const struct pci_device_id *ent)
374 {
375 struct dmfe_board_info *db; /* board information structure */
376 struct net_device *dev;
377 u32 pci_pmr;
378 int i, err;
379
380 DMFE_DBUG(0, "dmfe_init_one()", 0);
381
382 if (!printed_version++)
383 pr_info("%s\n", version);
384
385 /*
386 * SPARC on-board DM910x chips should be handled by the main
387 * tulip driver, except for early DM9100s.
388 */
389 #ifdef CONFIG_TULIP_DM910X
390 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
391 ent->driver_data == PCI_DM9102_ID) {
392 struct device_node *dp = pci_device_to_OF_node(pdev);
393
394 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
395 pr_info("skipping on-board DM910x (use tulip)\n");
396 return -ENODEV;
397 }
398 }
399 #endif
400
401 /* Init network device */
402 dev = alloc_etherdev(sizeof(*db));
403 if (dev == NULL)
404 return -ENOMEM;
405 SET_NETDEV_DEV(dev, &pdev->dev);
406
407 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
408 pr_warn("32-bit PCI DMA not available\n");
409 err = -ENODEV;
410 goto err_out_free;
411 }
412
413 /* Enable Master/IO access, Disable memory access */
414 err = pci_enable_device(pdev);
415 if (err)
416 goto err_out_free;
417
418 if (!pci_resource_start(pdev, 0)) {
419 pr_err("I/O base is zero\n");
420 err = -ENODEV;
421 goto err_out_disable;
422 }
423
424 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
425 pr_err("Allocated I/O size too small\n");
426 err = -ENODEV;
427 goto err_out_disable;
428 }
429
430 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
431
432 /* Set Latency Timer 80h */
433 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
434 Need a PCI quirk.. */
435
436 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
437 #endif
438
439 if (pci_request_regions(pdev, DRV_NAME)) {
440 pr_err("Failed to request PCI regions\n");
441 err = -ENODEV;
442 goto err_out_disable;
443 }
444
445 /* Init system & device */
446 db = netdev_priv(dev);
447
448 /* Allocate Tx/Rx descriptor memory */
449 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
450 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
451 if (!db->desc_pool_ptr)
452 goto err_out_res;
453
454 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
455 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
456 if (!db->buf_pool_ptr)
457 goto err_out_free_desc;
458
459 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
460 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
461 db->buf_pool_start = db->buf_pool_ptr;
462 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
463
464 db->chip_id = ent->driver_data;
465 db->ioaddr = pci_resource_start(pdev, 0);
466 db->chip_revision = pdev->revision;
467 db->wol_mode = 0;
468
469 db->pdev = pdev;
470
471 dev->base_addr = db->ioaddr;
472 dev->irq = pdev->irq;
473 pci_set_drvdata(pdev, dev);
474 dev->netdev_ops = &netdev_ops;
475 dev->ethtool_ops = &netdev_ethtool_ops;
476 netif_carrier_off(dev);
477 spin_lock_init(&db->lock);
478
479 pci_read_config_dword(pdev, 0x50, &pci_pmr);
480 pci_pmr &= 0x70000;
481 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
482 db->chip_type = 1; /* DM9102A E3 */
483 else
484 db->chip_type = 0;
485
486 /* read 64 word srom data */
487 for (i = 0; i < 64; i++)
488 ((__le16 *) db->srom)[i] =
489 cpu_to_le16(read_srom_word(db->ioaddr, i));
490
491 /* Set Node address */
492 for (i = 0; i < 6; i++)
493 dev->dev_addr[i] = db->srom[20 + i];
494
495 err = register_netdev (dev);
496 if (err)
497 goto err_out_free_buf;
498
499 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
500 ent->driver_data >> 16,
501 pci_name(pdev), dev->dev_addr, dev->irq);
502
503 pci_set_master(pdev);
504
505 return 0;
506
507 err_out_free_buf:
508 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
509 db->buf_pool_ptr, db->buf_pool_dma_ptr);
510 err_out_free_desc:
511 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
512 db->desc_pool_ptr, db->desc_pool_dma_ptr);
513 err_out_res:
514 pci_release_regions(pdev);
515 err_out_disable:
516 pci_disable_device(pdev);
517 err_out_free:
518 pci_set_drvdata(pdev, NULL);
519 free_netdev(dev);
520
521 return err;
522 }
523
524
525 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
526 {
527 struct net_device *dev = pci_get_drvdata(pdev);
528 struct dmfe_board_info *db = netdev_priv(dev);
529
530 DMFE_DBUG(0, "dmfe_remove_one()", 0);
531
532 if (dev) {
533
534 unregister_netdev(dev);
535
536 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
537 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
538 db->desc_pool_dma_ptr);
539 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
540 db->buf_pool_ptr, db->buf_pool_dma_ptr);
541 pci_release_regions(pdev);
542 free_netdev(dev); /* free board information */
543
544 pci_set_drvdata(pdev, NULL);
545 }
546
547 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
548 }
549
550
551 /*
552 * Open the interface.
553 * The interface is opened whenever "ifconfig" actives it.
554 */
555
556 static int dmfe_open(struct DEVICE *dev)
557 {
558 int ret;
559 struct dmfe_board_info *db = netdev_priv(dev);
560
561 DMFE_DBUG(0, "dmfe_open", 0);
562
563 ret = request_irq(dev->irq, dmfe_interrupt,
564 IRQF_SHARED, dev->name, dev);
565 if (ret)
566 return ret;
567
568 /* system variable init */
569 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
570 db->tx_packet_cnt = 0;
571 db->tx_queue_cnt = 0;
572 db->rx_avail_cnt = 0;
573 db->wait_reset = 0;
574
575 db->first_in_callback = 0;
576 db->NIC_capability = 0xf; /* All capability*/
577 db->PHY_reg4 = 0x1e0;
578
579 /* CR6 operation mode decision */
580 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
581 (db->chip_revision >= 0x30) ) {
582 db->cr6_data |= DMFE_TXTH_256;
583 db->cr0_data = CR0_DEFAULT;
584 db->dm910x_chk_mode=4; /* Enter the normal mode */
585 } else {
586 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
587 db->cr0_data = 0;
588 db->dm910x_chk_mode = 1; /* Enter the check mode */
589 }
590
591 /* Initialize DM910X board */
592 dmfe_init_dm910x(dev);
593
594 /* Active System Interface */
595 netif_wake_queue(dev);
596
597 /* set and active a timer process */
598 init_timer(&db->timer);
599 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
600 db->timer.data = (unsigned long)dev;
601 db->timer.function = dmfe_timer;
602 add_timer(&db->timer);
603
604 return 0;
605 }
606
607
608 /* Initialize DM910X board
609 * Reset DM910X board
610 * Initialize TX/Rx descriptor chain structure
611 * Send the set-up frame
612 * Enable Tx/Rx machine
613 */
614
615 static void dmfe_init_dm910x(struct DEVICE *dev)
616 {
617 struct dmfe_board_info *db = netdev_priv(dev);
618 unsigned long ioaddr = db->ioaddr;
619
620 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
621
622 /* Reset DM910x MAC controller */
623 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
624 udelay(100);
625 outl(db->cr0_data, ioaddr + DCR0);
626 udelay(5);
627
628 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
629 db->phy_addr = 1;
630
631 /* Parser SROM and media mode */
632 dmfe_parse_srom(db);
633 db->media_mode = dmfe_media_mode;
634
635 /* RESET Phyxcer Chip by GPR port bit 7 */
636 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
637 if (db->chip_id == PCI_DM9009_ID) {
638 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
639 mdelay(300); /* Delay 300 ms */
640 }
641 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
642
643 /* Process Phyxcer Media Mode */
644 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
645 dmfe_set_phyxcer(db);
646
647 /* Media Mode Process */
648 if ( !(db->media_mode & DMFE_AUTO) )
649 db->op_mode = db->media_mode; /* Force Mode */
650
651 /* Initialize Transmit/Receive decriptor and CR3/4 */
652 dmfe_descriptor_init(db, ioaddr);
653
654 /* Init CR6 to program DM910x operation */
655 update_cr6(db->cr6_data, ioaddr);
656
657 /* Send setup frame */
658 if (db->chip_id == PCI_DM9132_ID)
659 dm9132_id_table(dev); /* DM9132 */
660 else
661 send_filter_frame(dev); /* DM9102/DM9102A */
662
663 /* Init CR7, interrupt active bit */
664 db->cr7_data = CR7_DEFAULT;
665 outl(db->cr7_data, ioaddr + DCR7);
666
667 /* Init CR15, Tx jabber and Rx watchdog timer */
668 outl(db->cr15_data, ioaddr + DCR15);
669
670 /* Enable DM910X Tx/Rx function */
671 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
672 update_cr6(db->cr6_data, ioaddr);
673 }
674
675
676 /*
677 * Hardware start transmission.
678 * Send a packet to media from the upper layer.
679 */
680
681 static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
682 struct DEVICE *dev)
683 {
684 struct dmfe_board_info *db = netdev_priv(dev);
685 struct tx_desc *txptr;
686 unsigned long flags;
687
688 DMFE_DBUG(0, "dmfe_start_xmit", 0);
689
690 /* Too large packet check */
691 if (skb->len > MAX_PACKET_SIZE) {
692 pr_err("big packet = %d\n", (u16)skb->len);
693 dev_kfree_skb(skb);
694 return NETDEV_TX_OK;
695 }
696
697 /* Resource flag check */
698 netif_stop_queue(dev);
699
700 spin_lock_irqsave(&db->lock, flags);
701
702 /* No Tx resource check, it never happen nromally */
703 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
704 spin_unlock_irqrestore(&db->lock, flags);
705 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
706 return NETDEV_TX_BUSY;
707 }
708
709 /* Disable NIC interrupt */
710 outl(0, dev->base_addr + DCR7);
711
712 /* transmit this packet */
713 txptr = db->tx_insert_ptr;
714 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
715 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
716
717 /* Point to next transmit free descriptor */
718 db->tx_insert_ptr = txptr->next_tx_desc;
719
720 /* Transmit Packet Process */
721 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
722 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
723 db->tx_packet_cnt++; /* Ready to send */
724 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
725 dev->trans_start = jiffies; /* saved time stamp */
726 } else {
727 db->tx_queue_cnt++; /* queue TX packet */
728 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
729 }
730
731 /* Tx resource check */
732 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
733 netif_wake_queue(dev);
734
735 /* Restore CR7 to enable interrupt */
736 spin_unlock_irqrestore(&db->lock, flags);
737 outl(db->cr7_data, dev->base_addr + DCR7);
738
739 /* free this SKB */
740 dev_kfree_skb(skb);
741
742 return NETDEV_TX_OK;
743 }
744
745
746 /*
747 * Stop the interface.
748 * The interface is stopped when it is brought.
749 */
750
751 static int dmfe_stop(struct DEVICE *dev)
752 {
753 struct dmfe_board_info *db = netdev_priv(dev);
754 unsigned long ioaddr = dev->base_addr;
755
756 DMFE_DBUG(0, "dmfe_stop", 0);
757
758 /* disable system */
759 netif_stop_queue(dev);
760
761 /* deleted timer */
762 del_timer_sync(&db->timer);
763
764 /* Reset & stop DM910X board */
765 outl(DM910X_RESET, ioaddr + DCR0);
766 udelay(5);
767 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
768
769 /* free interrupt */
770 free_irq(dev->irq, dev);
771
772 /* free allocated rx buffer */
773 dmfe_free_rxbuffer(db);
774
775 #if 0
776 /* show statistic counter */
777 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
778 db->tx_fifo_underrun, db->tx_excessive_collision,
779 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
780 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
781 db->reset_fatal, db->reset_TXtimeout);
782 #endif
783
784 return 0;
785 }
786
787
788 /*
789 * DM9102 insterrupt handler
790 * receive the packet to upper layer, free the transmitted packet
791 */
792
793 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
794 {
795 struct DEVICE *dev = dev_id;
796 struct dmfe_board_info *db = netdev_priv(dev);
797 unsigned long ioaddr = dev->base_addr;
798 unsigned long flags;
799
800 DMFE_DBUG(0, "dmfe_interrupt()", 0);
801
802 spin_lock_irqsave(&db->lock, flags);
803
804 /* Got DM910X status */
805 db->cr5_data = inl(ioaddr + DCR5);
806 outl(db->cr5_data, ioaddr + DCR5);
807 if ( !(db->cr5_data & 0xc1) ) {
808 spin_unlock_irqrestore(&db->lock, flags);
809 return IRQ_HANDLED;
810 }
811
812 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
813 outl(0, ioaddr + DCR7);
814
815 /* Check system status */
816 if (db->cr5_data & 0x2000) {
817 /* system bus error happen */
818 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
819 db->reset_fatal++;
820 db->wait_reset = 1; /* Need to RESET */
821 spin_unlock_irqrestore(&db->lock, flags);
822 return IRQ_HANDLED;
823 }
824
825 /* Received the coming packet */
826 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
827 dmfe_rx_packet(dev, db);
828
829 /* reallocate rx descriptor buffer */
830 if (db->rx_avail_cnt<RX_DESC_CNT)
831 allocate_rx_buffer(db);
832
833 /* Free the transmitted descriptor */
834 if ( db->cr5_data & 0x01)
835 dmfe_free_tx_pkt(dev, db);
836
837 /* Mode Check */
838 if (db->dm910x_chk_mode & 0x2) {
839 db->dm910x_chk_mode = 0x4;
840 db->cr6_data |= 0x100;
841 update_cr6(db->cr6_data, db->ioaddr);
842 }
843
844 /* Restore CR7 to enable interrupt mask */
845 outl(db->cr7_data, ioaddr + DCR7);
846
847 spin_unlock_irqrestore(&db->lock, flags);
848 return IRQ_HANDLED;
849 }
850
851
852 #ifdef CONFIG_NET_POLL_CONTROLLER
853 /*
854 * Polling 'interrupt' - used by things like netconsole to send skbs
855 * without having to re-enable interrupts. It's not called while
856 * the interrupt routine is executing.
857 */
858
859 static void poll_dmfe (struct net_device *dev)
860 {
861 /* disable_irq here is not very nice, but with the lockless
862 interrupt handler we have no other choice. */
863 disable_irq(dev->irq);
864 dmfe_interrupt (dev->irq, dev);
865 enable_irq(dev->irq);
866 }
867 #endif
868
869 /*
870 * Free TX resource after TX complete
871 */
872
873 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
874 {
875 struct tx_desc *txptr;
876 unsigned long ioaddr = dev->base_addr;
877 u32 tdes0;
878
879 txptr = db->tx_remove_ptr;
880 while(db->tx_packet_cnt) {
881 tdes0 = le32_to_cpu(txptr->tdes0);
882 if (tdes0 & 0x80000000)
883 break;
884
885 /* A packet sent completed */
886 db->tx_packet_cnt--;
887 dev->stats.tx_packets++;
888
889 /* Transmit statistic counter */
890 if ( tdes0 != 0x7fffffff ) {
891 dev->stats.collisions += (tdes0 >> 3) & 0xf;
892 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
893 if (tdes0 & TDES0_ERR_MASK) {
894 dev->stats.tx_errors++;
895
896 if (tdes0 & 0x0002) { /* UnderRun */
897 db->tx_fifo_underrun++;
898 if ( !(db->cr6_data & CR6_SFT) ) {
899 db->cr6_data = db->cr6_data | CR6_SFT;
900 update_cr6(db->cr6_data, db->ioaddr);
901 }
902 }
903 if (tdes0 & 0x0100)
904 db->tx_excessive_collision++;
905 if (tdes0 & 0x0200)
906 db->tx_late_collision++;
907 if (tdes0 & 0x0400)
908 db->tx_no_carrier++;
909 if (tdes0 & 0x0800)
910 db->tx_loss_carrier++;
911 if (tdes0 & 0x4000)
912 db->tx_jabber_timeout++;
913 }
914 }
915
916 txptr = txptr->next_tx_desc;
917 }/* End of while */
918
919 /* Update TX remove pointer to next */
920 db->tx_remove_ptr = txptr;
921
922 /* Send the Tx packet in queue */
923 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
924 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
925 db->tx_packet_cnt++; /* Ready to send */
926 db->tx_queue_cnt--;
927 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
928 dev->trans_start = jiffies; /* saved time stamp */
929 }
930
931 /* Resource available check */
932 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
933 netif_wake_queue(dev); /* Active upper layer, send again */
934 }
935
936
937 /*
938 * Calculate the CRC valude of the Rx packet
939 * flag = 1 : return the reverse CRC (for the received packet CRC)
940 * 0 : return the normal CRC (for Hash Table index)
941 */
942
943 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
944 {
945 u32 crc = crc32(~0, Data, Len);
946 if (flag) crc = ~crc;
947 return crc;
948 }
949
950
951 /*
952 * Receive the come packet and pass to upper layer
953 */
954
955 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
956 {
957 struct rx_desc *rxptr;
958 struct sk_buff *skb, *newskb;
959 int rxlen;
960 u32 rdes0;
961
962 rxptr = db->rx_ready_ptr;
963
964 while(db->rx_avail_cnt) {
965 rdes0 = le32_to_cpu(rxptr->rdes0);
966 if (rdes0 & 0x80000000) /* packet owner check */
967 break;
968
969 db->rx_avail_cnt--;
970 db->interval_rx_cnt++;
971
972 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
973 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
974
975 if ( (rdes0 & 0x300) != 0x300) {
976 /* A packet without First/Last flag */
977 /* reuse this SKB */
978 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
979 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
980 } else {
981 /* A packet with First/Last flag */
982 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
983
984 /* error summary bit check */
985 if (rdes0 & 0x8000) {
986 /* This is a error packet */
987 dev->stats.rx_errors++;
988 if (rdes0 & 1)
989 dev->stats.rx_fifo_errors++;
990 if (rdes0 & 2)
991 dev->stats.rx_crc_errors++;
992 if (rdes0 & 0x80)
993 dev->stats.rx_length_errors++;
994 }
995
996 if ( !(rdes0 & 0x8000) ||
997 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
998 skb = rxptr->rx_skb_ptr;
999
1000 /* Received Packet CRC check need or not */
1001 if ( (db->dm910x_chk_mode & 1) &&
1002 (cal_CRC(skb->data, rxlen, 1) !=
1003 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1004 /* Found a error received packet */
1005 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1006 db->dm910x_chk_mode = 3;
1007 } else {
1008 /* Good packet, send to upper layer */
1009 /* Shorst packet used new SKB */
1010 if ((rxlen < RX_COPY_SIZE) &&
1011 ((newskb = dev_alloc_skb(rxlen + 2))
1012 != NULL)) {
1013
1014 skb = newskb;
1015 /* size less than COPY_SIZE, allocate a rxlen SKB */
1016 skb_reserve(skb, 2); /* 16byte align */
1017 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1018 skb_put(skb, rxlen),
1019 rxlen);
1020 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1021 } else
1022 skb_put(skb, rxlen);
1023
1024 skb->protocol = eth_type_trans(skb, dev);
1025 netif_rx(skb);
1026 dev->stats.rx_packets++;
1027 dev->stats.rx_bytes += rxlen;
1028 }
1029 } else {
1030 /* Reuse SKB buffer when the packet is error */
1031 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1032 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1033 }
1034 }
1035
1036 rxptr = rxptr->next_rx_desc;
1037 }
1038
1039 db->rx_ready_ptr = rxptr;
1040 }
1041
1042 /*
1043 * Set DM910X multicast address
1044 */
1045
1046 static void dmfe_set_filter_mode(struct DEVICE * dev)
1047 {
1048 struct dmfe_board_info *db = netdev_priv(dev);
1049 unsigned long flags;
1050 int mc_count = netdev_mc_count(dev);
1051
1052 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1053 spin_lock_irqsave(&db->lock, flags);
1054
1055 if (dev->flags & IFF_PROMISC) {
1056 DMFE_DBUG(0, "Enable PROM Mode", 0);
1057 db->cr6_data |= CR6_PM | CR6_PBF;
1058 update_cr6(db->cr6_data, db->ioaddr);
1059 spin_unlock_irqrestore(&db->lock, flags);
1060 return;
1061 }
1062
1063 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1064 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1065 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1066 db->cr6_data |= CR6_PAM;
1067 spin_unlock_irqrestore(&db->lock, flags);
1068 return;
1069 }
1070
1071 DMFE_DBUG(0, "Set multicast address", mc_count);
1072 if (db->chip_id == PCI_DM9132_ID)
1073 dm9132_id_table(dev); /* DM9132 */
1074 else
1075 send_filter_frame(dev); /* DM9102/DM9102A */
1076 spin_unlock_irqrestore(&db->lock, flags);
1077 }
1078
1079 /*
1080 * Ethtool interace
1081 */
1082
1083 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1084 struct ethtool_drvinfo *info)
1085 {
1086 struct dmfe_board_info *np = netdev_priv(dev);
1087
1088 strcpy(info->driver, DRV_NAME);
1089 strcpy(info->version, DRV_VERSION);
1090 if (np->pdev)
1091 strcpy(info->bus_info, pci_name(np->pdev));
1092 else
1093 sprintf(info->bus_info, "EISA 0x%lx %d",
1094 dev->base_addr, dev->irq);
1095 }
1096
1097 static int dmfe_ethtool_set_wol(struct net_device *dev,
1098 struct ethtool_wolinfo *wolinfo)
1099 {
1100 struct dmfe_board_info *db = netdev_priv(dev);
1101
1102 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1103 WAKE_ARP | WAKE_MAGICSECURE))
1104 return -EOPNOTSUPP;
1105
1106 db->wol_mode = wolinfo->wolopts;
1107 return 0;
1108 }
1109
1110 static void dmfe_ethtool_get_wol(struct net_device *dev,
1111 struct ethtool_wolinfo *wolinfo)
1112 {
1113 struct dmfe_board_info *db = netdev_priv(dev);
1114
1115 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1116 wolinfo->wolopts = db->wol_mode;
1117 }
1118
1119
1120 static const struct ethtool_ops netdev_ethtool_ops = {
1121 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1122 .get_link = ethtool_op_get_link,
1123 .set_wol = dmfe_ethtool_set_wol,
1124 .get_wol = dmfe_ethtool_get_wol,
1125 };
1126
1127 /*
1128 * A periodic timer routine
1129 * Dynamic media sense, allocate Rx buffer...
1130 */
1131
1132 static void dmfe_timer(unsigned long data)
1133 {
1134 u32 tmp_cr8;
1135 unsigned char tmp_cr12;
1136 struct DEVICE *dev = (struct DEVICE *) data;
1137 struct dmfe_board_info *db = netdev_priv(dev);
1138 unsigned long flags;
1139
1140 int link_ok, link_ok_phy;
1141
1142 DMFE_DBUG(0, "dmfe_timer()", 0);
1143 spin_lock_irqsave(&db->lock, flags);
1144
1145 /* Media mode process when Link OK before enter this route */
1146 if (db->first_in_callback == 0) {
1147 db->first_in_callback = 1;
1148 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1149 db->cr6_data &= ~0x40000;
1150 update_cr6(db->cr6_data, db->ioaddr);
1151 phy_write(db->ioaddr,
1152 db->phy_addr, 0, 0x1000, db->chip_id);
1153 db->cr6_data |= 0x40000;
1154 update_cr6(db->cr6_data, db->ioaddr);
1155 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1156 add_timer(&db->timer);
1157 spin_unlock_irqrestore(&db->lock, flags);
1158 return;
1159 }
1160 }
1161
1162
1163 /* Operating Mode Check */
1164 if ( (db->dm910x_chk_mode & 0x1) &&
1165 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1166 db->dm910x_chk_mode = 0x4;
1167
1168 /* Dynamic reset DM910X : system error or transmit time-out */
1169 tmp_cr8 = inl(db->ioaddr + DCR8);
1170 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1171 db->reset_cr8++;
1172 db->wait_reset = 1;
1173 }
1174 db->interval_rx_cnt = 0;
1175
1176 /* TX polling kick monitor */
1177 if ( db->tx_packet_cnt &&
1178 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1179 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1180
1181 /* TX Timeout */
1182 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
1183 db->reset_TXtimeout++;
1184 db->wait_reset = 1;
1185 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1186 }
1187 }
1188
1189 if (db->wait_reset) {
1190 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1191 db->reset_count++;
1192 dmfe_dynamic_reset(dev);
1193 db->first_in_callback = 0;
1194 db->timer.expires = DMFE_TIMER_WUT;
1195 add_timer(&db->timer);
1196 spin_unlock_irqrestore(&db->lock, flags);
1197 return;
1198 }
1199
1200 /* Link status check, Dynamic media type change */
1201 if (db->chip_id == PCI_DM9132_ID)
1202 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1203 else
1204 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1205
1206 if ( ((db->chip_id == PCI_DM9102_ID) &&
1207 (db->chip_revision == 0x30)) ||
1208 ((db->chip_id == PCI_DM9132_ID) &&
1209 (db->chip_revision == 0x10)) ) {
1210 /* DM9102A Chip */
1211 if (tmp_cr12 & 2)
1212 link_ok = 0;
1213 else
1214 link_ok = 1;
1215 }
1216 else
1217 /*0x43 is used instead of 0x3 because bit 6 should represent
1218 link status of external PHY */
1219 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1220
1221
1222 /* If chip reports that link is failed it could be because external
1223 PHY link status pin is not connected correctly to chip
1224 To be sure ask PHY too.
1225 */
1226
1227 /* need a dummy read because of PHY's register latch*/
1228 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1229 link_ok_phy = (phy_read (db->ioaddr,
1230 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1231
1232 if (link_ok_phy != link_ok) {
1233 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1234 link_ok = link_ok | link_ok_phy;
1235 }
1236
1237 if ( !link_ok && netif_carrier_ok(dev)) {
1238 /* Link Failed */
1239 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1240 netif_carrier_off(dev);
1241
1242 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1243 /* AUTO or force 1M Homerun/Longrun don't need */
1244 if ( !(db->media_mode & 0x38) )
1245 phy_write(db->ioaddr, db->phy_addr,
1246 0, 0x1000, db->chip_id);
1247
1248 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1249 if (db->media_mode & DMFE_AUTO) {
1250 /* 10/100M link failed, used 1M Home-Net */
1251 db->cr6_data|=0x00040000; /* bit18=1, MII */
1252 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1253 update_cr6(db->cr6_data, db->ioaddr);
1254 }
1255 } else if (!netif_carrier_ok(dev)) {
1256
1257 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1258
1259 /* Auto Sense Speed */
1260 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1261 netif_carrier_on(dev);
1262 SHOW_MEDIA_TYPE(db->op_mode);
1263 }
1264
1265 dmfe_process_mode(db);
1266 }
1267
1268 /* HPNA remote command check */
1269 if (db->HPNA_command & 0xf00) {
1270 db->HPNA_timer--;
1271 if (!db->HPNA_timer)
1272 dmfe_HPNA_remote_cmd_chk(db);
1273 }
1274
1275 /* Timer active again */
1276 db->timer.expires = DMFE_TIMER_WUT;
1277 add_timer(&db->timer);
1278 spin_unlock_irqrestore(&db->lock, flags);
1279 }
1280
1281
1282 /*
1283 * Dynamic reset the DM910X board
1284 * Stop DM910X board
1285 * Free Tx/Rx allocated memory
1286 * Reset DM910X board
1287 * Re-initialize DM910X board
1288 */
1289
1290 static void dmfe_dynamic_reset(struct DEVICE *dev)
1291 {
1292 struct dmfe_board_info *db = netdev_priv(dev);
1293
1294 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1295
1296 /* Sopt MAC controller */
1297 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1298 update_cr6(db->cr6_data, dev->base_addr);
1299 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1300 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1301
1302 /* Disable upper layer interface */
1303 netif_stop_queue(dev);
1304
1305 /* Free Rx Allocate buffer */
1306 dmfe_free_rxbuffer(db);
1307
1308 /* system variable init */
1309 db->tx_packet_cnt = 0;
1310 db->tx_queue_cnt = 0;
1311 db->rx_avail_cnt = 0;
1312 netif_carrier_off(dev);
1313 db->wait_reset = 0;
1314
1315 /* Re-initialize DM910X board */
1316 dmfe_init_dm910x(dev);
1317
1318 /* Restart upper layer interface */
1319 netif_wake_queue(dev);
1320 }
1321
1322
1323 /*
1324 * free all allocated rx buffer
1325 */
1326
1327 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1328 {
1329 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1330
1331 /* free allocated rx buffer */
1332 while (db->rx_avail_cnt) {
1333 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1334 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1335 db->rx_avail_cnt--;
1336 }
1337 }
1338
1339
1340 /*
1341 * Reuse the SK buffer
1342 */
1343
1344 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1345 {
1346 struct rx_desc *rxptr = db->rx_insert_ptr;
1347
1348 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1349 rxptr->rx_skb_ptr = skb;
1350 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1351 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1352 wmb();
1353 rxptr->rdes0 = cpu_to_le32(0x80000000);
1354 db->rx_avail_cnt++;
1355 db->rx_insert_ptr = rxptr->next_rx_desc;
1356 } else
1357 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1358 }
1359
1360
1361 /*
1362 * Initialize transmit/Receive descriptor
1363 * Using Chain structure, and allocate Tx/Rx buffer
1364 */
1365
1366 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1367 {
1368 struct tx_desc *tmp_tx;
1369 struct rx_desc *tmp_rx;
1370 unsigned char *tmp_buf;
1371 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1372 dma_addr_t tmp_buf_dma;
1373 int i;
1374
1375 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1376
1377 /* tx descriptor start pointer */
1378 db->tx_insert_ptr = db->first_tx_desc;
1379 db->tx_remove_ptr = db->first_tx_desc;
1380 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1381
1382 /* rx descriptor start pointer */
1383 db->first_rx_desc = (void *)db->first_tx_desc +
1384 sizeof(struct tx_desc) * TX_DESC_CNT;
1385
1386 db->first_rx_desc_dma = db->first_tx_desc_dma +
1387 sizeof(struct tx_desc) * TX_DESC_CNT;
1388 db->rx_insert_ptr = db->first_rx_desc;
1389 db->rx_ready_ptr = db->first_rx_desc;
1390 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1391
1392 /* Init Transmit chain */
1393 tmp_buf = db->buf_pool_start;
1394 tmp_buf_dma = db->buf_pool_dma_start;
1395 tmp_tx_dma = db->first_tx_desc_dma;
1396 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1397 tmp_tx->tx_buf_ptr = tmp_buf;
1398 tmp_tx->tdes0 = cpu_to_le32(0);
1399 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1400 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1401 tmp_tx_dma += sizeof(struct tx_desc);
1402 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1403 tmp_tx->next_tx_desc = tmp_tx + 1;
1404 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1405 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1406 }
1407 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1408 tmp_tx->next_tx_desc = db->first_tx_desc;
1409
1410 /* Init Receive descriptor chain */
1411 tmp_rx_dma=db->first_rx_desc_dma;
1412 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1413 tmp_rx->rdes0 = cpu_to_le32(0);
1414 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1415 tmp_rx_dma += sizeof(struct rx_desc);
1416 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1417 tmp_rx->next_rx_desc = tmp_rx + 1;
1418 }
1419 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1420 tmp_rx->next_rx_desc = db->first_rx_desc;
1421
1422 /* pre-allocate Rx buffer */
1423 allocate_rx_buffer(db);
1424 }
1425
1426
1427 /*
1428 * Update CR6 value
1429 * Firstly stop DM910X , then written value and start
1430 */
1431
1432 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1433 {
1434 u32 cr6_tmp;
1435
1436 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1437 outl(cr6_tmp, ioaddr + DCR6);
1438 udelay(5);
1439 outl(cr6_data, ioaddr + DCR6);
1440 udelay(5);
1441 }
1442
1443
1444 /*
1445 * Send a setup frame for DM9132
1446 * This setup frame initialize DM910X address filter mode
1447 */
1448
1449 static void dm9132_id_table(struct DEVICE *dev)
1450 {
1451 struct netdev_hw_addr *ha;
1452 u16 * addrptr;
1453 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1454 u32 hash_val;
1455 u16 i, hash_table[4];
1456
1457 DMFE_DBUG(0, "dm9132_id_table()", 0);
1458
1459 /* Node address */
1460 addrptr = (u16 *) dev->dev_addr;
1461 outw(addrptr[0], ioaddr);
1462 ioaddr += 4;
1463 outw(addrptr[1], ioaddr);
1464 ioaddr += 4;
1465 outw(addrptr[2], ioaddr);
1466 ioaddr += 4;
1467
1468 /* Clear Hash Table */
1469 memset(hash_table, 0, sizeof(hash_table));
1470
1471 /* broadcast address */
1472 hash_table[3] = 0x8000;
1473
1474 /* the multicast address in Hash Table : 64 bits */
1475 netdev_for_each_mc_addr(ha, dev) {
1476 hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f;
1477 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1478 }
1479
1480 /* Write the hash table to MAC MD table */
1481 for (i = 0; i < 4; i++, ioaddr += 4)
1482 outw(hash_table[i], ioaddr);
1483 }
1484
1485
1486 /*
1487 * Send a setup frame for DM9102/DM9102A
1488 * This setup frame initialize DM910X address filter mode
1489 */
1490
1491 static void send_filter_frame(struct DEVICE *dev)
1492 {
1493 struct dmfe_board_info *db = netdev_priv(dev);
1494 struct netdev_hw_addr *ha;
1495 struct tx_desc *txptr;
1496 u16 * addrptr;
1497 u32 * suptr;
1498 int i;
1499
1500 DMFE_DBUG(0, "send_filter_frame()", 0);
1501
1502 txptr = db->tx_insert_ptr;
1503 suptr = (u32 *) txptr->tx_buf_ptr;
1504
1505 /* Node address */
1506 addrptr = (u16 *) dev->dev_addr;
1507 *suptr++ = addrptr[0];
1508 *suptr++ = addrptr[1];
1509 *suptr++ = addrptr[2];
1510
1511 /* broadcast address */
1512 *suptr++ = 0xffff;
1513 *suptr++ = 0xffff;
1514 *suptr++ = 0xffff;
1515
1516 /* fit the multicast address */
1517 netdev_for_each_mc_addr(ha, dev) {
1518 addrptr = (u16 *) ha->addr;
1519 *suptr++ = addrptr[0];
1520 *suptr++ = addrptr[1];
1521 *suptr++ = addrptr[2];
1522 }
1523
1524 for (i = netdev_mc_count(dev); i < 14; i++) {
1525 *suptr++ = 0xffff;
1526 *suptr++ = 0xffff;
1527 *suptr++ = 0xffff;
1528 }
1529
1530 /* prepare the setup frame */
1531 db->tx_insert_ptr = txptr->next_tx_desc;
1532 txptr->tdes1 = cpu_to_le32(0x890000c0);
1533
1534 /* Resource Check and Send the setup packet */
1535 if (!db->tx_packet_cnt) {
1536 /* Resource Empty */
1537 db->tx_packet_cnt++;
1538 txptr->tdes0 = cpu_to_le32(0x80000000);
1539 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1540 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1541 update_cr6(db->cr6_data, dev->base_addr);
1542 dev->trans_start = jiffies;
1543 } else
1544 db->tx_queue_cnt++; /* Put in TX queue */
1545 }
1546
1547
1548 /*
1549 * Allocate rx buffer,
1550 * As possible as allocate maxiumn Rx buffer
1551 */
1552
1553 static void allocate_rx_buffer(struct dmfe_board_info *db)
1554 {
1555 struct rx_desc *rxptr;
1556 struct sk_buff *skb;
1557
1558 rxptr = db->rx_insert_ptr;
1559
1560 while(db->rx_avail_cnt < RX_DESC_CNT) {
1561 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1562 break;
1563 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1564 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1565 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1566 wmb();
1567 rxptr->rdes0 = cpu_to_le32(0x80000000);
1568 rxptr = rxptr->next_rx_desc;
1569 db->rx_avail_cnt++;
1570 }
1571
1572 db->rx_insert_ptr = rxptr;
1573 }
1574
1575
1576 /*
1577 * Read one word data from the serial ROM
1578 */
1579
1580 static u16 read_srom_word(long ioaddr, int offset)
1581 {
1582 int i;
1583 u16 srom_data = 0;
1584 long cr9_ioaddr = ioaddr + DCR9;
1585
1586 outl(CR9_SROM_READ, cr9_ioaddr);
1587 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1588
1589 /* Send the Read Command 110b */
1590 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1591 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1592 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1593
1594 /* Send the offset */
1595 for (i = 5; i >= 0; i--) {
1596 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1597 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1598 }
1599
1600 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1601
1602 for (i = 16; i > 0; i--) {
1603 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1604 udelay(5);
1605 srom_data = (srom_data << 1) |
1606 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1607 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1608 udelay(5);
1609 }
1610
1611 outl(CR9_SROM_READ, cr9_ioaddr);
1612 return srom_data;
1613 }
1614
1615
1616 /*
1617 * Auto sense the media mode
1618 */
1619
1620 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1621 {
1622 u8 ErrFlag = 0;
1623 u16 phy_mode;
1624
1625 /* CR6 bit18=0, select 10/100M */
1626 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1627
1628 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1629 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1630
1631 if ( (phy_mode & 0x24) == 0x24 ) {
1632 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1633 phy_mode = phy_read(db->ioaddr,
1634 db->phy_addr, 7, db->chip_id) & 0xf000;
1635 else /* DM9102/DM9102A */
1636 phy_mode = phy_read(db->ioaddr,
1637 db->phy_addr, 17, db->chip_id) & 0xf000;
1638 switch (phy_mode) {
1639 case 0x1000: db->op_mode = DMFE_10MHF; break;
1640 case 0x2000: db->op_mode = DMFE_10MFD; break;
1641 case 0x4000: db->op_mode = DMFE_100MHF; break;
1642 case 0x8000: db->op_mode = DMFE_100MFD; break;
1643 default: db->op_mode = DMFE_10MHF;
1644 ErrFlag = 1;
1645 break;
1646 }
1647 } else {
1648 db->op_mode = DMFE_10MHF;
1649 DMFE_DBUG(0, "Link Failed :", phy_mode);
1650 ErrFlag = 1;
1651 }
1652
1653 return ErrFlag;
1654 }
1655
1656
1657 /*
1658 * Set 10/100 phyxcer capability
1659 * AUTO mode : phyxcer register4 is NIC capability
1660 * Force mode: phyxcer register4 is the force media
1661 */
1662
1663 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1664 {
1665 u16 phy_reg;
1666
1667 /* Select 10/100M phyxcer */
1668 db->cr6_data &= ~0x40000;
1669 update_cr6(db->cr6_data, db->ioaddr);
1670
1671 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1672 if (db->chip_id == PCI_DM9009_ID) {
1673 phy_reg = phy_read(db->ioaddr,
1674 db->phy_addr, 18, db->chip_id) & ~0x1000;
1675
1676 phy_write(db->ioaddr,
1677 db->phy_addr, 18, phy_reg, db->chip_id);
1678 }
1679
1680 /* Phyxcer capability setting */
1681 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1682
1683 if (db->media_mode & DMFE_AUTO) {
1684 /* AUTO Mode */
1685 phy_reg |= db->PHY_reg4;
1686 } else {
1687 /* Force Mode */
1688 switch(db->media_mode) {
1689 case DMFE_10MHF: phy_reg |= 0x20; break;
1690 case DMFE_10MFD: phy_reg |= 0x40; break;
1691 case DMFE_100MHF: phy_reg |= 0x80; break;
1692 case DMFE_100MFD: phy_reg |= 0x100; break;
1693 }
1694 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1695 }
1696
1697 /* Write new capability to Phyxcer Reg4 */
1698 if ( !(phy_reg & 0x01e0)) {
1699 phy_reg|=db->PHY_reg4;
1700 db->media_mode|=DMFE_AUTO;
1701 }
1702 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1703
1704 /* Restart Auto-Negotiation */
1705 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1706 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1707 if ( !db->chip_type )
1708 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1709 }
1710
1711
1712 /*
1713 * Process op-mode
1714 * AUTO mode : PHY controller in Auto-negotiation Mode
1715 * Force mode: PHY controller in force mode with HUB
1716 * N-way force capability with SWITCH
1717 */
1718
1719 static void dmfe_process_mode(struct dmfe_board_info *db)
1720 {
1721 u16 phy_reg;
1722
1723 /* Full Duplex Mode Check */
1724 if (db->op_mode & 0x4)
1725 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1726 else
1727 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1728
1729 /* Transciver Selection */
1730 if (db->op_mode & 0x10) /* 1M HomePNA */
1731 db->cr6_data |= 0x40000;/* External MII select */
1732 else
1733 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1734
1735 update_cr6(db->cr6_data, db->ioaddr);
1736
1737 /* 10/100M phyxcer force mode need */
1738 if ( !(db->media_mode & 0x18)) {
1739 /* Forece Mode */
1740 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1741 if ( !(phy_reg & 0x1) ) {
1742 /* parter without N-Way capability */
1743 phy_reg = 0x0;
1744 switch(db->op_mode) {
1745 case DMFE_10MHF: phy_reg = 0x0; break;
1746 case DMFE_10MFD: phy_reg = 0x100; break;
1747 case DMFE_100MHF: phy_reg = 0x2000; break;
1748 case DMFE_100MFD: phy_reg = 0x2100; break;
1749 }
1750 phy_write(db->ioaddr,
1751 db->phy_addr, 0, phy_reg, db->chip_id);
1752 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1753 mdelay(20);
1754 phy_write(db->ioaddr,
1755 db->phy_addr, 0, phy_reg, db->chip_id);
1756 }
1757 }
1758 }
1759
1760
1761 /*
1762 * Write a word to Phy register
1763 */
1764
1765 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1766 u16 phy_data, u32 chip_id)
1767 {
1768 u16 i;
1769 unsigned long ioaddr;
1770
1771 if (chip_id == PCI_DM9132_ID) {
1772 ioaddr = iobase + 0x80 + offset * 4;
1773 outw(phy_data, ioaddr);
1774 } else {
1775 /* DM9102/DM9102A Chip */
1776 ioaddr = iobase + DCR9;
1777
1778 /* Send 33 synchronization clock to Phy controller */
1779 for (i = 0; i < 35; i++)
1780 phy_write_1bit(ioaddr, PHY_DATA_1);
1781
1782 /* Send start command(01) to Phy */
1783 phy_write_1bit(ioaddr, PHY_DATA_0);
1784 phy_write_1bit(ioaddr, PHY_DATA_1);
1785
1786 /* Send write command(01) to Phy */
1787 phy_write_1bit(ioaddr, PHY_DATA_0);
1788 phy_write_1bit(ioaddr, PHY_DATA_1);
1789
1790 /* Send Phy address */
1791 for (i = 0x10; i > 0; i = i >> 1)
1792 phy_write_1bit(ioaddr,
1793 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1794
1795 /* Send register address */
1796 for (i = 0x10; i > 0; i = i >> 1)
1797 phy_write_1bit(ioaddr,
1798 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1799
1800 /* written trasnition */
1801 phy_write_1bit(ioaddr, PHY_DATA_1);
1802 phy_write_1bit(ioaddr, PHY_DATA_0);
1803
1804 /* Write a word data to PHY controller */
1805 for ( i = 0x8000; i > 0; i >>= 1)
1806 phy_write_1bit(ioaddr,
1807 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1808 }
1809 }
1810
1811
1812 /*
1813 * Read a word data from phy register
1814 */
1815
1816 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1817 {
1818 int i;
1819 u16 phy_data;
1820 unsigned long ioaddr;
1821
1822 if (chip_id == PCI_DM9132_ID) {
1823 /* DM9132 Chip */
1824 ioaddr = iobase + 0x80 + offset * 4;
1825 phy_data = inw(ioaddr);
1826 } else {
1827 /* DM9102/DM9102A Chip */
1828 ioaddr = iobase + DCR9;
1829
1830 /* Send 33 synchronization clock to Phy controller */
1831 for (i = 0; i < 35; i++)
1832 phy_write_1bit(ioaddr, PHY_DATA_1);
1833
1834 /* Send start command(01) to Phy */
1835 phy_write_1bit(ioaddr, PHY_DATA_0);
1836 phy_write_1bit(ioaddr, PHY_DATA_1);
1837
1838 /* Send read command(10) to Phy */
1839 phy_write_1bit(ioaddr, PHY_DATA_1);
1840 phy_write_1bit(ioaddr, PHY_DATA_0);
1841
1842 /* Send Phy address */
1843 for (i = 0x10; i > 0; i = i >> 1)
1844 phy_write_1bit(ioaddr,
1845 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1846
1847 /* Send register address */
1848 for (i = 0x10; i > 0; i = i >> 1)
1849 phy_write_1bit(ioaddr,
1850 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1851
1852 /* Skip transition state */
1853 phy_read_1bit(ioaddr);
1854
1855 /* read 16bit data */
1856 for (phy_data = 0, i = 0; i < 16; i++) {
1857 phy_data <<= 1;
1858 phy_data |= phy_read_1bit(ioaddr);
1859 }
1860 }
1861
1862 return phy_data;
1863 }
1864
1865
1866 /*
1867 * Write one bit data to Phy Controller
1868 */
1869
1870 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1871 {
1872 outl(phy_data, ioaddr); /* MII Clock Low */
1873 udelay(1);
1874 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1875 udelay(1);
1876 outl(phy_data, ioaddr); /* MII Clock Low */
1877 udelay(1);
1878 }
1879
1880
1881 /*
1882 * Read one bit phy data from PHY controller
1883 */
1884
1885 static u16 phy_read_1bit(unsigned long ioaddr)
1886 {
1887 u16 phy_data;
1888
1889 outl(0x50000, ioaddr);
1890 udelay(1);
1891 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1892 outl(0x40000, ioaddr);
1893 udelay(1);
1894
1895 return phy_data;
1896 }
1897
1898
1899 /*
1900 * Parser SROM and media mode
1901 */
1902
1903 static void dmfe_parse_srom(struct dmfe_board_info * db)
1904 {
1905 char * srom = db->srom;
1906 int dmfe_mode, tmp_reg;
1907
1908 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1909
1910 /* Init CR15 */
1911 db->cr15_data = CR15_DEFAULT;
1912
1913 /* Check SROM Version */
1914 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1915 /* SROM V4.01 */
1916 /* Get NIC support media mode */
1917 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1918 db->PHY_reg4 = 0;
1919 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1920 switch( db->NIC_capability & tmp_reg ) {
1921 case 0x1: db->PHY_reg4 |= 0x0020; break;
1922 case 0x2: db->PHY_reg4 |= 0x0040; break;
1923 case 0x4: db->PHY_reg4 |= 0x0080; break;
1924 case 0x8: db->PHY_reg4 |= 0x0100; break;
1925 }
1926 }
1927
1928 /* Media Mode Force or not check */
1929 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1930 le32_to_cpup((__le32 *) (srom + 36)));
1931 switch(dmfe_mode) {
1932 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1933 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1934 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1935 case 0x100:
1936 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1937 }
1938
1939 /* Special Function setting */
1940 /* VLAN function */
1941 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1942 db->cr15_data |= 0x40;
1943
1944 /* Flow Control */
1945 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1946 db->cr15_data |= 0x400;
1947
1948 /* TX pause packet */
1949 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1950 db->cr15_data |= 0x9800;
1951 }
1952
1953 /* Parse HPNA parameter */
1954 db->HPNA_command = 1;
1955
1956 /* Accept remote command or not */
1957 if (HPNA_rx_cmd == 0)
1958 db->HPNA_command |= 0x8000;
1959
1960 /* Issue remote command & operation mode */
1961 if (HPNA_tx_cmd == 1)
1962 switch(HPNA_mode) { /* Issue Remote Command */
1963 case 0: db->HPNA_command |= 0x0904; break;
1964 case 1: db->HPNA_command |= 0x0a00; break;
1965 case 2: db->HPNA_command |= 0x0506; break;
1966 case 3: db->HPNA_command |= 0x0602; break;
1967 }
1968 else
1969 switch(HPNA_mode) { /* Don't Issue */
1970 case 0: db->HPNA_command |= 0x0004; break;
1971 case 1: db->HPNA_command |= 0x0000; break;
1972 case 2: db->HPNA_command |= 0x0006; break;
1973 case 3: db->HPNA_command |= 0x0002; break;
1974 }
1975
1976 /* Check DM9801 or DM9802 present or not */
1977 db->HPNA_present = 0;
1978 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1979 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1980 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1981 /* DM9801 or DM9802 present */
1982 db->HPNA_timer = 8;
1983 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1984 /* DM9801 HomeRun */
1985 db->HPNA_present = 1;
1986 dmfe_program_DM9801(db, tmp_reg);
1987 } else {
1988 /* DM9802 LongRun */
1989 db->HPNA_present = 2;
1990 dmfe_program_DM9802(db);
1991 }
1992 }
1993
1994 }
1995
1996
1997 /*
1998 * Init HomeRun DM9801
1999 */
2000
2001 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2002 {
2003 uint reg17, reg25;
2004
2005 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2006 switch(HPNA_rev) {
2007 case 0xb900: /* DM9801 E3 */
2008 db->HPNA_command |= 0x1000;
2009 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2010 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2011 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2012 break;
2013 case 0xb901: /* DM9801 E4 */
2014 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2015 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2016 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2017 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2018 break;
2019 case 0xb902: /* DM9801 E5 */
2020 case 0xb903: /* DM9801 E6 */
2021 default:
2022 db->HPNA_command |= 0x1000;
2023 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2024 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2025 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2026 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2027 break;
2028 }
2029 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2030 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2031 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2032 }
2033
2034
2035 /*
2036 * Init HomeRun DM9802
2037 */
2038
2039 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2040 {
2041 uint phy_reg;
2042
2043 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2044 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2045 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2046 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2047 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2048 }
2049
2050
2051 /*
2052 * Check remote HPNA power and speed status. If not correct,
2053 * issue command again.
2054 */
2055
2056 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2057 {
2058 uint phy_reg;
2059
2060 /* Got remote device status */
2061 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2062 switch(phy_reg) {
2063 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2064 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2065 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2066 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2067 }
2068
2069 /* Check remote device status match our setting ot not */
2070 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2071 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2072 db->chip_id);
2073 db->HPNA_timer=8;
2074 } else
2075 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2076 }
2077
2078
2079
2080 static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
2081 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2082 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2083 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2084 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2085 { 0, }
2086 };
2087 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2088
2089
2090 #ifdef CONFIG_PM
2091 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2092 {
2093 struct net_device *dev = pci_get_drvdata(pci_dev);
2094 struct dmfe_board_info *db = netdev_priv(dev);
2095 u32 tmp;
2096
2097 /* Disable upper layer interface */
2098 netif_device_detach(dev);
2099
2100 /* Disable Tx/Rx */
2101 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2102 update_cr6(db->cr6_data, dev->base_addr);
2103
2104 /* Disable Interrupt */
2105 outl(0, dev->base_addr + DCR7);
2106 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2107
2108 /* Fre RX buffers */
2109 dmfe_free_rxbuffer(db);
2110
2111 /* Enable WOL */
2112 pci_read_config_dword(pci_dev, 0x40, &tmp);
2113 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2114
2115 if (db->wol_mode & WAKE_PHY)
2116 tmp |= DMFE_WOL_LINKCHANGE;
2117 if (db->wol_mode & WAKE_MAGIC)
2118 tmp |= DMFE_WOL_MAGICPACKET;
2119
2120 pci_write_config_dword(pci_dev, 0x40, tmp);
2121
2122 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2123 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2124
2125 /* Power down device*/
2126 pci_save_state(pci_dev);
2127 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2128
2129 return 0;
2130 }
2131
2132 static int dmfe_resume(struct pci_dev *pci_dev)
2133 {
2134 struct net_device *dev = pci_get_drvdata(pci_dev);
2135 u32 tmp;
2136
2137 pci_set_power_state(pci_dev, PCI_D0);
2138 pci_restore_state(pci_dev);
2139
2140 /* Re-initialize DM910X board */
2141 dmfe_init_dm910x(dev);
2142
2143 /* Disable WOL */
2144 pci_read_config_dword(pci_dev, 0x40, &tmp);
2145
2146 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2147 pci_write_config_dword(pci_dev, 0x40, tmp);
2148
2149 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2150 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2151
2152 /* Restart upper layer interface */
2153 netif_device_attach(dev);
2154
2155 return 0;
2156 }
2157 #else
2158 #define dmfe_suspend NULL
2159 #define dmfe_resume NULL
2160 #endif
2161
2162 static struct pci_driver dmfe_driver = {
2163 .name = "dmfe",
2164 .id_table = dmfe_pci_tbl,
2165 .probe = dmfe_init_one,
2166 .remove = __devexit_p(dmfe_remove_one),
2167 .suspend = dmfe_suspend,
2168 .resume = dmfe_resume
2169 };
2170
2171 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2172 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2173 MODULE_LICENSE("GPL");
2174 MODULE_VERSION(DRV_VERSION);
2175
2176 module_param(debug, int, 0);
2177 module_param(mode, byte, 0);
2178 module_param(cr6set, int, 0);
2179 module_param(chkmode, byte, 0);
2180 module_param(HPNA_mode, byte, 0);
2181 module_param(HPNA_rx_cmd, byte, 0);
2182 module_param(HPNA_tx_cmd, byte, 0);
2183 module_param(HPNA_NoiseFloor, byte, 0);
2184 module_param(SF_mode, byte, 0);
2185 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2186 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2187 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2188
2189 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2190 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2191
2192 /* Description:
2193 * when user used insmod to add module, system invoked init_module()
2194 * to initialize and register.
2195 */
2196
2197 static int __init dmfe_init_module(void)
2198 {
2199 int rc;
2200
2201 pr_info("%s\n", version);
2202 printed_version = 1;
2203
2204 DMFE_DBUG(0, "init_module() ", debug);
2205
2206 if (debug)
2207 dmfe_debug = debug; /* set debug flag */
2208 if (cr6set)
2209 dmfe_cr6_user_set = cr6set;
2210
2211 switch(mode) {
2212 case DMFE_10MHF:
2213 case DMFE_100MHF:
2214 case DMFE_10MFD:
2215 case DMFE_100MFD:
2216 case DMFE_1M_HPNA:
2217 dmfe_media_mode = mode;
2218 break;
2219 default:dmfe_media_mode = DMFE_AUTO;
2220 break;
2221 }
2222
2223 if (HPNA_mode > 4)
2224 HPNA_mode = 0; /* Default: LP/HS */
2225 if (HPNA_rx_cmd > 1)
2226 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2227 if (HPNA_tx_cmd > 1)
2228 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2229 if (HPNA_NoiseFloor > 15)
2230 HPNA_NoiseFloor = 0;
2231
2232 rc = pci_register_driver(&dmfe_driver);
2233 if (rc < 0)
2234 return rc;
2235
2236 return 0;
2237 }
2238
2239
2240 /*
2241 * Description:
2242 * when user used rmmod to delete module, system invoked clean_module()
2243 * to un-register all registered services.
2244 */
2245
2246 static void __exit dmfe_cleanup_module(void)
2247 {
2248 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2249 pci_unregister_driver(&dmfe_driver);
2250 }
2251
2252 module_init(dmfe_init_module);
2253 module_exit(dmfe_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)