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ARM: mxs: icoll: Fix interrupts gpio bank 0
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / cadence / macb.c
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_data/macb.h>
26 #include <linux/platform_device.h>
27 #include <linux/phy.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30 #include <linux/of_net.h>
31 #include <linux/pinctrl/consumer.h>
32
33 #include "macb.h"
34
35 #define RX_BUFFER_SIZE 128
36 #define RX_RING_SIZE 512 /* must be power of 2 */
37 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
38
39 #define TX_RING_SIZE 128 /* must be power of 2 */
40 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
41
42 /* level of occupied TX descriptors under which we wake up TX process */
43 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
44
45 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
46 | MACB_BIT(ISR_ROVR))
47 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
48 | MACB_BIT(ISR_RLE) \
49 | MACB_BIT(TXERR))
50 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
51
52 /*
53 * Graceful stop timeouts in us. We should allow up to
54 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
55 */
56 #define MACB_HALT_TIMEOUT 1230
57
58 /* Ring buffer accessors */
59 static unsigned int macb_tx_ring_wrap(unsigned int index)
60 {
61 return index & (TX_RING_SIZE - 1);
62 }
63
64 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
65 {
66 return &bp->tx_ring[macb_tx_ring_wrap(index)];
67 }
68
69 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
70 {
71 return &bp->tx_skb[macb_tx_ring_wrap(index)];
72 }
73
74 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
75 {
76 dma_addr_t offset;
77
78 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
79
80 return bp->tx_ring_dma + offset;
81 }
82
83 static unsigned int macb_rx_ring_wrap(unsigned int index)
84 {
85 return index & (RX_RING_SIZE - 1);
86 }
87
88 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
89 {
90 return &bp->rx_ring[macb_rx_ring_wrap(index)];
91 }
92
93 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
94 {
95 return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index);
96 }
97
98 void macb_set_hwaddr(struct macb *bp)
99 {
100 u32 bottom;
101 u16 top;
102
103 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
104 macb_or_gem_writel(bp, SA1B, bottom);
105 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
106 macb_or_gem_writel(bp, SA1T, top);
107
108 /* Clear unused address register sets */
109 macb_or_gem_writel(bp, SA2B, 0);
110 macb_or_gem_writel(bp, SA2T, 0);
111 macb_or_gem_writel(bp, SA3B, 0);
112 macb_or_gem_writel(bp, SA3T, 0);
113 macb_or_gem_writel(bp, SA4B, 0);
114 macb_or_gem_writel(bp, SA4T, 0);
115 }
116 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
117
118 void macb_get_hwaddr(struct macb *bp)
119 {
120 struct macb_platform_data *pdata;
121 u32 bottom;
122 u16 top;
123 u8 addr[6];
124 int i;
125
126 pdata = bp->pdev->dev.platform_data;
127
128 /* Check all 4 address register for vaild address */
129 for (i = 0; i < 4; i++) {
130 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
131 top = macb_or_gem_readl(bp, SA1T + i * 8);
132
133 if (pdata && pdata->rev_eth_addr) {
134 addr[5] = bottom & 0xff;
135 addr[4] = (bottom >> 8) & 0xff;
136 addr[3] = (bottom >> 16) & 0xff;
137 addr[2] = (bottom >> 24) & 0xff;
138 addr[1] = top & 0xff;
139 addr[0] = (top & 0xff00) >> 8;
140 } else {
141 addr[0] = bottom & 0xff;
142 addr[1] = (bottom >> 8) & 0xff;
143 addr[2] = (bottom >> 16) & 0xff;
144 addr[3] = (bottom >> 24) & 0xff;
145 addr[4] = top & 0xff;
146 addr[5] = (top >> 8) & 0xff;
147 }
148
149 if (is_valid_ether_addr(addr)) {
150 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
151 return;
152 }
153 }
154
155 netdev_info(bp->dev, "invalid hw address, using random\n");
156 eth_hw_addr_random(bp->dev);
157 }
158 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
159
160 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
161 {
162 struct macb *bp = bus->priv;
163 int value;
164
165 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
166 | MACB_BF(RW, MACB_MAN_READ)
167 | MACB_BF(PHYA, mii_id)
168 | MACB_BF(REGA, regnum)
169 | MACB_BF(CODE, MACB_MAN_CODE)));
170
171 /* wait for end of transfer */
172 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
173 cpu_relax();
174
175 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
176
177 return value;
178 }
179
180 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
181 u16 value)
182 {
183 struct macb *bp = bus->priv;
184
185 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
186 | MACB_BF(RW, MACB_MAN_WRITE)
187 | MACB_BF(PHYA, mii_id)
188 | MACB_BF(REGA, regnum)
189 | MACB_BF(CODE, MACB_MAN_CODE)
190 | MACB_BF(DATA, value)));
191
192 /* wait for end of transfer */
193 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
194 cpu_relax();
195
196 return 0;
197 }
198
199 static int macb_mdio_reset(struct mii_bus *bus)
200 {
201 return 0;
202 }
203
204 static void macb_handle_link_change(struct net_device *dev)
205 {
206 struct macb *bp = netdev_priv(dev);
207 struct phy_device *phydev = bp->phy_dev;
208 unsigned long flags;
209
210 int status_change = 0;
211
212 spin_lock_irqsave(&bp->lock, flags);
213
214 if (phydev->link) {
215 if ((bp->speed != phydev->speed) ||
216 (bp->duplex != phydev->duplex)) {
217 u32 reg;
218
219 reg = macb_readl(bp, NCFGR);
220 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
221 if (macb_is_gem(bp))
222 reg &= ~GEM_BIT(GBE);
223
224 if (phydev->duplex)
225 reg |= MACB_BIT(FD);
226 if (phydev->speed == SPEED_100)
227 reg |= MACB_BIT(SPD);
228 if (phydev->speed == SPEED_1000)
229 reg |= GEM_BIT(GBE);
230
231 macb_or_gem_writel(bp, NCFGR, reg);
232
233 bp->speed = phydev->speed;
234 bp->duplex = phydev->duplex;
235 status_change = 1;
236 }
237 }
238
239 if (phydev->link != bp->link) {
240 if (!phydev->link) {
241 bp->speed = 0;
242 bp->duplex = -1;
243 }
244 bp->link = phydev->link;
245
246 status_change = 1;
247 }
248
249 spin_unlock_irqrestore(&bp->lock, flags);
250
251 if (status_change) {
252 if (phydev->link) {
253 netif_carrier_on(dev);
254 netdev_info(dev, "link up (%d/%s)\n",
255 phydev->speed,
256 phydev->duplex == DUPLEX_FULL ?
257 "Full" : "Half");
258 } else {
259 netif_carrier_off(dev);
260 netdev_info(dev, "link down\n");
261 }
262 }
263 }
264
265 /* based on au1000_eth. c*/
266 static int macb_mii_probe(struct net_device *dev)
267 {
268 struct macb *bp = netdev_priv(dev);
269 struct macb_platform_data *pdata;
270 struct phy_device *phydev;
271 int phy_irq;
272 int ret;
273
274 phydev = phy_find_first(bp->mii_bus);
275 if (!phydev) {
276 netdev_err(dev, "no PHY found\n");
277 return -1;
278 }
279
280 pdata = dev_get_platdata(&bp->pdev->dev);
281 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
282 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
283 if (!ret) {
284 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
285 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
286 }
287 }
288
289 /* attach the mac to the phy */
290 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
291 bp->phy_interface);
292 if (ret) {
293 netdev_err(dev, "Could not attach to PHY\n");
294 return ret;
295 }
296
297 /* mask with MAC supported features */
298 if (macb_is_gem(bp))
299 phydev->supported &= PHY_GBIT_FEATURES;
300 else
301 phydev->supported &= PHY_BASIC_FEATURES;
302
303 phydev->advertising = phydev->supported;
304
305 bp->link = 0;
306 bp->speed = 0;
307 bp->duplex = -1;
308 bp->phy_dev = phydev;
309
310 return 0;
311 }
312
313 int macb_mii_init(struct macb *bp)
314 {
315 struct macb_platform_data *pdata;
316 int err = -ENXIO, i;
317
318 /* Enable management port */
319 macb_writel(bp, NCR, MACB_BIT(MPE));
320
321 bp->mii_bus = mdiobus_alloc();
322 if (bp->mii_bus == NULL) {
323 err = -ENOMEM;
324 goto err_out;
325 }
326
327 bp->mii_bus->name = "MACB_mii_bus";
328 bp->mii_bus->read = &macb_mdio_read;
329 bp->mii_bus->write = &macb_mdio_write;
330 bp->mii_bus->reset = &macb_mdio_reset;
331 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
332 bp->pdev->name, bp->pdev->id);
333 bp->mii_bus->priv = bp;
334 bp->mii_bus->parent = &bp->dev->dev;
335 pdata = bp->pdev->dev.platform_data;
336
337 if (pdata)
338 bp->mii_bus->phy_mask = pdata->phy_mask;
339
340 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
341 if (!bp->mii_bus->irq) {
342 err = -ENOMEM;
343 goto err_out_free_mdiobus;
344 }
345
346 for (i = 0; i < PHY_MAX_ADDR; i++)
347 bp->mii_bus->irq[i] = PHY_POLL;
348
349 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
350
351 if (mdiobus_register(bp->mii_bus))
352 goto err_out_free_mdio_irq;
353
354 if (macb_mii_probe(bp->dev) != 0) {
355 goto err_out_unregister_bus;
356 }
357
358 return 0;
359
360 err_out_unregister_bus:
361 mdiobus_unregister(bp->mii_bus);
362 err_out_free_mdio_irq:
363 kfree(bp->mii_bus->irq);
364 err_out_free_mdiobus:
365 mdiobus_free(bp->mii_bus);
366 err_out:
367 return err;
368 }
369 EXPORT_SYMBOL_GPL(macb_mii_init);
370
371 static void macb_update_stats(struct macb *bp)
372 {
373 u32 __iomem *reg = bp->regs + MACB_PFR;
374 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
375 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
376
377 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
378
379 for(; p < end; p++, reg++)
380 *p += __raw_readl(reg);
381 }
382
383 static int macb_halt_tx(struct macb *bp)
384 {
385 unsigned long halt_time, timeout;
386 u32 status;
387
388 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
389
390 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
391 do {
392 halt_time = jiffies;
393 status = macb_readl(bp, TSR);
394 if (!(status & MACB_BIT(TGO)))
395 return 0;
396
397 usleep_range(10, 250);
398 } while (time_before(halt_time, timeout));
399
400 return -ETIMEDOUT;
401 }
402
403 static void macb_tx_error_task(struct work_struct *work)
404 {
405 struct macb *bp = container_of(work, struct macb, tx_error_task);
406 struct macb_tx_skb *tx_skb;
407 struct sk_buff *skb;
408 unsigned int tail;
409
410 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
411 bp->tx_tail, bp->tx_head);
412
413 /* Make sure nobody is trying to queue up new packets */
414 netif_stop_queue(bp->dev);
415
416 /*
417 * Stop transmission now
418 * (in case we have just queued new packets)
419 */
420 if (macb_halt_tx(bp))
421 /* Just complain for now, reinitializing TX path can be good */
422 netdev_err(bp->dev, "BUG: halt tx timed out\n");
423
424 /* No need for the lock here as nobody will interrupt us anymore */
425
426 /*
427 * Treat frames in TX queue including the ones that caused the error.
428 * Free transmit buffers in upper layer.
429 */
430 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
431 struct macb_dma_desc *desc;
432 u32 ctrl;
433
434 desc = macb_tx_desc(bp, tail);
435 ctrl = desc->ctrl;
436 tx_skb = macb_tx_skb(bp, tail);
437 skb = tx_skb->skb;
438
439 if (ctrl & MACB_BIT(TX_USED)) {
440 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
441 macb_tx_ring_wrap(tail), skb->data);
442 bp->stats.tx_packets++;
443 bp->stats.tx_bytes += skb->len;
444 } else {
445 /*
446 * "Buffers exhausted mid-frame" errors may only happen
447 * if the driver is buggy, so complain loudly about those.
448 * Statistics are updated by hardware.
449 */
450 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
451 netdev_err(bp->dev,
452 "BUG: TX buffers exhausted mid-frame\n");
453
454 desc->ctrl = ctrl | MACB_BIT(TX_USED);
455 }
456
457 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
458 DMA_TO_DEVICE);
459 tx_skb->skb = NULL;
460 dev_kfree_skb(skb);
461 }
462
463 /* Make descriptor updates visible to hardware */
464 wmb();
465
466 /* Reinitialize the TX desc queue */
467 macb_writel(bp, TBQP, bp->tx_ring_dma);
468 /* Make TX ring reflect state of hardware */
469 bp->tx_head = bp->tx_tail = 0;
470
471 /* Now we are ready to start transmission again */
472 netif_wake_queue(bp->dev);
473
474 /* Housework before enabling TX IRQ */
475 macb_writel(bp, TSR, macb_readl(bp, TSR));
476 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
477 }
478
479 static void macb_tx_interrupt(struct macb *bp)
480 {
481 unsigned int tail;
482 unsigned int head;
483 u32 status;
484
485 status = macb_readl(bp, TSR);
486 macb_writel(bp, TSR, status);
487
488 macb_writel(bp, ISR, MACB_BIT(TCOMP));
489
490 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
491 (unsigned long)status);
492
493 head = bp->tx_head;
494 for (tail = bp->tx_tail; tail != head; tail++) {
495 struct macb_tx_skb *tx_skb;
496 struct sk_buff *skb;
497 struct macb_dma_desc *desc;
498 u32 ctrl;
499
500 desc = macb_tx_desc(bp, tail);
501
502 /* Make hw descriptor updates visible to CPU */
503 rmb();
504
505 ctrl = desc->ctrl;
506
507 if (!(ctrl & MACB_BIT(TX_USED)))
508 break;
509
510 tx_skb = macb_tx_skb(bp, tail);
511 skb = tx_skb->skb;
512
513 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
514 macb_tx_ring_wrap(tail), skb->data);
515 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
516 DMA_TO_DEVICE);
517 bp->stats.tx_packets++;
518 bp->stats.tx_bytes += skb->len;
519 tx_skb->skb = NULL;
520 dev_kfree_skb_irq(skb);
521 }
522
523 bp->tx_tail = tail;
524 if (netif_queue_stopped(bp->dev)
525 && CIRC_CNT(bp->tx_head, bp->tx_tail,
526 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
527 netif_wake_queue(bp->dev);
528 }
529
530 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
531 unsigned int last_frag)
532 {
533 unsigned int len;
534 unsigned int frag;
535 unsigned int offset;
536 struct sk_buff *skb;
537 struct macb_dma_desc *desc;
538
539 desc = macb_rx_desc(bp, last_frag);
540 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
541
542 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
543 macb_rx_ring_wrap(first_frag),
544 macb_rx_ring_wrap(last_frag), len);
545
546 /*
547 * The ethernet header starts NET_IP_ALIGN bytes into the
548 * first buffer. Since the header is 14 bytes, this makes the
549 * payload word-aligned.
550 *
551 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
552 * the two padding bytes into the skb so that we avoid hitting
553 * the slowpath in memcpy(), and pull them off afterwards.
554 */
555 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
556 if (!skb) {
557 bp->stats.rx_dropped++;
558 for (frag = first_frag; ; frag++) {
559 desc = macb_rx_desc(bp, frag);
560 desc->addr &= ~MACB_BIT(RX_USED);
561 if (frag == last_frag)
562 break;
563 }
564
565 /* Make descriptor updates visible to hardware */
566 wmb();
567
568 return 1;
569 }
570
571 offset = 0;
572 len += NET_IP_ALIGN;
573 skb_checksum_none_assert(skb);
574 skb_put(skb, len);
575
576 for (frag = first_frag; ; frag++) {
577 unsigned int frag_len = RX_BUFFER_SIZE;
578
579 if (offset + frag_len > len) {
580 BUG_ON(frag != last_frag);
581 frag_len = len - offset;
582 }
583 skb_copy_to_linear_data_offset(skb, offset,
584 macb_rx_buffer(bp, frag), frag_len);
585 offset += RX_BUFFER_SIZE;
586 desc = macb_rx_desc(bp, frag);
587 desc->addr &= ~MACB_BIT(RX_USED);
588
589 if (frag == last_frag)
590 break;
591 }
592
593 /* Make descriptor updates visible to hardware */
594 wmb();
595
596 __skb_pull(skb, NET_IP_ALIGN);
597 skb->protocol = eth_type_trans(skb, bp->dev);
598
599 bp->stats.rx_packets++;
600 bp->stats.rx_bytes += skb->len;
601 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
602 skb->len, skb->csum);
603 netif_receive_skb(skb);
604
605 return 0;
606 }
607
608 /* Mark DMA descriptors from begin up to and not including end as unused */
609 static void discard_partial_frame(struct macb *bp, unsigned int begin,
610 unsigned int end)
611 {
612 unsigned int frag;
613
614 for (frag = begin; frag != end; frag++) {
615 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
616 desc->addr &= ~MACB_BIT(RX_USED);
617 }
618
619 /* Make descriptor updates visible to hardware */
620 wmb();
621
622 /*
623 * When this happens, the hardware stats registers for
624 * whatever caused this is updated, so we don't have to record
625 * anything.
626 */
627 }
628
629 static int macb_rx(struct macb *bp, int budget)
630 {
631 int received = 0;
632 unsigned int tail;
633 int first_frag = -1;
634
635 for (tail = bp->rx_tail; budget > 0; tail++) {
636 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
637 u32 addr, ctrl;
638
639 /* Make hw descriptor updates visible to CPU */
640 rmb();
641
642 addr = desc->addr;
643 ctrl = desc->ctrl;
644
645 if (!(addr & MACB_BIT(RX_USED)))
646 break;
647
648 if (ctrl & MACB_BIT(RX_SOF)) {
649 if (first_frag != -1)
650 discard_partial_frame(bp, first_frag, tail);
651 first_frag = tail;
652 }
653
654 if (ctrl & MACB_BIT(RX_EOF)) {
655 int dropped;
656 BUG_ON(first_frag == -1);
657
658 dropped = macb_rx_frame(bp, first_frag, tail);
659 first_frag = -1;
660 if (!dropped) {
661 received++;
662 budget--;
663 }
664 }
665 }
666
667 if (first_frag != -1)
668 bp->rx_tail = first_frag;
669 else
670 bp->rx_tail = tail;
671
672 return received;
673 }
674
675 static int macb_poll(struct napi_struct *napi, int budget)
676 {
677 struct macb *bp = container_of(napi, struct macb, napi);
678 int work_done;
679 u32 status;
680
681 status = macb_readl(bp, RSR);
682 macb_writel(bp, RSR, status);
683
684 work_done = 0;
685
686 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
687 (unsigned long)status, budget);
688
689 work_done = macb_rx(bp, budget);
690 if (work_done < budget) {
691 napi_complete(napi);
692
693 /*
694 * We've done what we can to clean the buffers. Make sure we
695 * get notified when new packets arrive.
696 */
697 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
698
699 /* Packets received while interrupts were disabled */
700 status = macb_readl(bp, RSR);
701 if (unlikely(status))
702 napi_reschedule(napi);
703 }
704
705 /* TODO: Handle errors */
706
707 return work_done;
708 }
709
710 static irqreturn_t macb_interrupt(int irq, void *dev_id)
711 {
712 struct net_device *dev = dev_id;
713 struct macb *bp = netdev_priv(dev);
714 u32 status;
715
716 status = macb_readl(bp, ISR);
717
718 if (unlikely(!status))
719 return IRQ_NONE;
720
721 spin_lock(&bp->lock);
722
723 while (status) {
724 /* close possible race with dev_close */
725 if (unlikely(!netif_running(dev))) {
726 macb_writel(bp, IDR, -1);
727 break;
728 }
729
730 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
731
732 if (status & MACB_RX_INT_FLAGS) {
733 /*
734 * There's no point taking any more interrupts
735 * until we have processed the buffers. The
736 * scheduling call may fail if the poll routine
737 * is already scheduled, so disable interrupts
738 * now.
739 */
740 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
741 macb_writel(bp, ISR, MACB_BIT(RCOMP));
742
743 if (napi_schedule_prep(&bp->napi)) {
744 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
745 __napi_schedule(&bp->napi);
746 }
747 }
748
749 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
750 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
751 schedule_work(&bp->tx_error_task);
752 break;
753 }
754
755 if (status & MACB_BIT(TCOMP))
756 macb_tx_interrupt(bp);
757
758 /*
759 * Link change detection isn't possible with RMII, so we'll
760 * add that if/when we get our hands on a full-blown MII PHY.
761 */
762
763 if (status & MACB_BIT(ISR_ROVR)) {
764 /* We missed at least one packet */
765 if (macb_is_gem(bp))
766 bp->hw_stats.gem.rx_overruns++;
767 else
768 bp->hw_stats.macb.rx_overruns++;
769 }
770
771 if (status & MACB_BIT(HRESP)) {
772 /*
773 * TODO: Reset the hardware, and maybe move the
774 * netdev_err to a lower-priority context as well
775 * (work queue?)
776 */
777 netdev_err(dev, "DMA bus error: HRESP not OK\n");
778 }
779
780 status = macb_readl(bp, ISR);
781 }
782
783 spin_unlock(&bp->lock);
784
785 return IRQ_HANDLED;
786 }
787
788 #ifdef CONFIG_NET_POLL_CONTROLLER
789 /*
790 * Polling receive - used by netconsole and other diagnostic tools
791 * to allow network i/o with interrupts disabled.
792 */
793 static void macb_poll_controller(struct net_device *dev)
794 {
795 unsigned long flags;
796
797 local_irq_save(flags);
798 macb_interrupt(dev->irq, dev);
799 local_irq_restore(flags);
800 }
801 #endif
802
803 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
804 {
805 struct macb *bp = netdev_priv(dev);
806 dma_addr_t mapping;
807 unsigned int len, entry;
808 struct macb_dma_desc *desc;
809 struct macb_tx_skb *tx_skb;
810 u32 ctrl;
811 unsigned long flags;
812
813 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
814 netdev_vdbg(bp->dev,
815 "start_xmit: len %u head %p data %p tail %p end %p\n",
816 skb->len, skb->head, skb->data,
817 skb_tail_pointer(skb), skb_end_pointer(skb));
818 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
819 skb->data, 16, true);
820 #endif
821
822 len = skb->len;
823 spin_lock_irqsave(&bp->lock, flags);
824
825 /* This is a hard error, log it. */
826 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
827 netif_stop_queue(dev);
828 spin_unlock_irqrestore(&bp->lock, flags);
829 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
830 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
831 bp->tx_head, bp->tx_tail);
832 return NETDEV_TX_BUSY;
833 }
834
835 entry = macb_tx_ring_wrap(bp->tx_head);
836 bp->tx_head++;
837 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
838 mapping = dma_map_single(&bp->pdev->dev, skb->data,
839 len, DMA_TO_DEVICE);
840
841 tx_skb = &bp->tx_skb[entry];
842 tx_skb->skb = skb;
843 tx_skb->mapping = mapping;
844 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
845 skb->data, (unsigned long)mapping);
846
847 ctrl = MACB_BF(TX_FRMLEN, len);
848 ctrl |= MACB_BIT(TX_LAST);
849 if (entry == (TX_RING_SIZE - 1))
850 ctrl |= MACB_BIT(TX_WRAP);
851
852 desc = &bp->tx_ring[entry];
853 desc->addr = mapping;
854 desc->ctrl = ctrl;
855
856 /* Make newly initialized descriptor visible to hardware */
857 wmb();
858
859 skb_tx_timestamp(skb);
860
861 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
862
863 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
864 netif_stop_queue(dev);
865
866 spin_unlock_irqrestore(&bp->lock, flags);
867
868 return NETDEV_TX_OK;
869 }
870
871 static void macb_free_consistent(struct macb *bp)
872 {
873 if (bp->tx_skb) {
874 kfree(bp->tx_skb);
875 bp->tx_skb = NULL;
876 }
877 if (bp->rx_ring) {
878 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
879 bp->rx_ring, bp->rx_ring_dma);
880 bp->rx_ring = NULL;
881 }
882 if (bp->tx_ring) {
883 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
884 bp->tx_ring, bp->tx_ring_dma);
885 bp->tx_ring = NULL;
886 }
887 if (bp->rx_buffers) {
888 dma_free_coherent(&bp->pdev->dev,
889 RX_RING_SIZE * RX_BUFFER_SIZE,
890 bp->rx_buffers, bp->rx_buffers_dma);
891 bp->rx_buffers = NULL;
892 }
893 }
894
895 static int macb_alloc_consistent(struct macb *bp)
896 {
897 int size;
898
899 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
900 bp->tx_skb = kmalloc(size, GFP_KERNEL);
901 if (!bp->tx_skb)
902 goto out_err;
903
904 size = RX_RING_BYTES;
905 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
906 &bp->rx_ring_dma, GFP_KERNEL);
907 if (!bp->rx_ring)
908 goto out_err;
909 netdev_dbg(bp->dev,
910 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
911 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
912
913 size = TX_RING_BYTES;
914 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
915 &bp->tx_ring_dma, GFP_KERNEL);
916 if (!bp->tx_ring)
917 goto out_err;
918 netdev_dbg(bp->dev,
919 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
920 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
921
922 size = RX_RING_SIZE * RX_BUFFER_SIZE;
923 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
924 &bp->rx_buffers_dma, GFP_KERNEL);
925 if (!bp->rx_buffers)
926 goto out_err;
927 netdev_dbg(bp->dev,
928 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
929 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
930
931 return 0;
932
933 out_err:
934 macb_free_consistent(bp);
935 return -ENOMEM;
936 }
937
938 static void macb_init_rings(struct macb *bp)
939 {
940 int i;
941 dma_addr_t addr;
942
943 addr = bp->rx_buffers_dma;
944 for (i = 0; i < RX_RING_SIZE; i++) {
945 bp->rx_ring[i].addr = addr;
946 bp->rx_ring[i].ctrl = 0;
947 addr += RX_BUFFER_SIZE;
948 }
949 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
950
951 for (i = 0; i < TX_RING_SIZE; i++) {
952 bp->tx_ring[i].addr = 0;
953 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
954 }
955 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
956
957 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
958 }
959
960 static void macb_reset_hw(struct macb *bp)
961 {
962 /*
963 * Disable RX and TX (XXX: Should we halt the transmission
964 * more gracefully?)
965 */
966 macb_writel(bp, NCR, 0);
967
968 /* Clear the stats registers (XXX: Update stats first?) */
969 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
970
971 /* Clear all status flags */
972 macb_writel(bp, TSR, -1);
973 macb_writel(bp, RSR, -1);
974
975 /* Disable all interrupts */
976 macb_writel(bp, IDR, -1);
977 macb_readl(bp, ISR);
978 }
979
980 static u32 gem_mdc_clk_div(struct macb *bp)
981 {
982 u32 config;
983 unsigned long pclk_hz = clk_get_rate(bp->pclk);
984
985 if (pclk_hz <= 20000000)
986 config = GEM_BF(CLK, GEM_CLK_DIV8);
987 else if (pclk_hz <= 40000000)
988 config = GEM_BF(CLK, GEM_CLK_DIV16);
989 else if (pclk_hz <= 80000000)
990 config = GEM_BF(CLK, GEM_CLK_DIV32);
991 else if (pclk_hz <= 120000000)
992 config = GEM_BF(CLK, GEM_CLK_DIV48);
993 else if (pclk_hz <= 160000000)
994 config = GEM_BF(CLK, GEM_CLK_DIV64);
995 else
996 config = GEM_BF(CLK, GEM_CLK_DIV96);
997
998 return config;
999 }
1000
1001 static u32 macb_mdc_clk_div(struct macb *bp)
1002 {
1003 u32 config;
1004 unsigned long pclk_hz;
1005
1006 if (macb_is_gem(bp))
1007 return gem_mdc_clk_div(bp);
1008
1009 pclk_hz = clk_get_rate(bp->pclk);
1010 if (pclk_hz <= 20000000)
1011 config = MACB_BF(CLK, MACB_CLK_DIV8);
1012 else if (pclk_hz <= 40000000)
1013 config = MACB_BF(CLK, MACB_CLK_DIV16);
1014 else if (pclk_hz <= 80000000)
1015 config = MACB_BF(CLK, MACB_CLK_DIV32);
1016 else
1017 config = MACB_BF(CLK, MACB_CLK_DIV64);
1018
1019 return config;
1020 }
1021
1022 /*
1023 * Get the DMA bus width field of the network configuration register that we
1024 * should program. We find the width from decoding the design configuration
1025 * register to find the maximum supported data bus width.
1026 */
1027 static u32 macb_dbw(struct macb *bp)
1028 {
1029 if (!macb_is_gem(bp))
1030 return 0;
1031
1032 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1033 case 4:
1034 return GEM_BF(DBW, GEM_DBW128);
1035 case 2:
1036 return GEM_BF(DBW, GEM_DBW64);
1037 case 1:
1038 default:
1039 return GEM_BF(DBW, GEM_DBW32);
1040 }
1041 }
1042
1043 /*
1044 * Configure the receive DMA engine
1045 * - use the correct receive buffer size
1046 * - set the possibility to use INCR16 bursts
1047 * (if not supported by FIFO, it will fallback to default)
1048 * - set both rx/tx packet buffers to full memory size
1049 * These are configurable parameters for GEM.
1050 */
1051 static void macb_configure_dma(struct macb *bp)
1052 {
1053 u32 dmacfg;
1054
1055 if (macb_is_gem(bp)) {
1056 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1057 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
1058 dmacfg |= GEM_BF(FBLDO, 16);
1059 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1060 dmacfg &= ~GEM_BIT(ENDIA);
1061 gem_writel(bp, DMACFG, dmacfg);
1062 }
1063 }
1064
1065 static void macb_init_hw(struct macb *bp)
1066 {
1067 u32 config;
1068
1069 macb_reset_hw(bp);
1070 macb_set_hwaddr(bp);
1071
1072 config = macb_mdc_clk_div(bp);
1073 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1074 config |= MACB_BIT(PAE); /* PAuse Enable */
1075 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1076 config |= MACB_BIT(BIG); /* Receive oversized frames */
1077 if (bp->dev->flags & IFF_PROMISC)
1078 config |= MACB_BIT(CAF); /* Copy All Frames */
1079 if (!(bp->dev->flags & IFF_BROADCAST))
1080 config |= MACB_BIT(NBC); /* No BroadCast */
1081 config |= macb_dbw(bp);
1082 macb_writel(bp, NCFGR, config);
1083 bp->speed = SPEED_10;
1084 bp->duplex = DUPLEX_HALF;
1085
1086 macb_configure_dma(bp);
1087
1088 /* Initialize TX and RX buffers */
1089 macb_writel(bp, RBQP, bp->rx_ring_dma);
1090 macb_writel(bp, TBQP, bp->tx_ring_dma);
1091
1092 /* Enable TX and RX */
1093 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1094
1095 /* Enable interrupts */
1096 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1097 | MACB_TX_INT_FLAGS
1098 | MACB_BIT(HRESP)));
1099
1100 }
1101
1102 /*
1103 * The hash address register is 64 bits long and takes up two
1104 * locations in the memory map. The least significant bits are stored
1105 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1106 *
1107 * The unicast hash enable and the multicast hash enable bits in the
1108 * network configuration register enable the reception of hash matched
1109 * frames. The destination address is reduced to a 6 bit index into
1110 * the 64 bit hash register using the following hash function. The
1111 * hash function is an exclusive or of every sixth bit of the
1112 * destination address.
1113 *
1114 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1115 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1116 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1117 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1118 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1119 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1120 *
1121 * da[0] represents the least significant bit of the first byte
1122 * received, that is, the multicast/unicast indicator, and da[47]
1123 * represents the most significant bit of the last byte received. If
1124 * the hash index, hi[n], points to a bit that is set in the hash
1125 * register then the frame will be matched according to whether the
1126 * frame is multicast or unicast. A multicast match will be signalled
1127 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1128 * index points to a bit set in the hash register. A unicast match
1129 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1130 * and the hash index points to a bit set in the hash register. To
1131 * receive all multicast frames, the hash register should be set with
1132 * all ones and the multicast hash enable bit should be set in the
1133 * network configuration register.
1134 */
1135
1136 static inline int hash_bit_value(int bitnr, __u8 *addr)
1137 {
1138 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1139 return 1;
1140 return 0;
1141 }
1142
1143 /*
1144 * Return the hash index value for the specified address.
1145 */
1146 static int hash_get_index(__u8 *addr)
1147 {
1148 int i, j, bitval;
1149 int hash_index = 0;
1150
1151 for (j = 0; j < 6; j++) {
1152 for (i = 0, bitval = 0; i < 8; i++)
1153 bitval ^= hash_bit_value(i*6 + j, addr);
1154
1155 hash_index |= (bitval << j);
1156 }
1157
1158 return hash_index;
1159 }
1160
1161 /*
1162 * Add multicast addresses to the internal multicast-hash table.
1163 */
1164 static void macb_sethashtable(struct net_device *dev)
1165 {
1166 struct netdev_hw_addr *ha;
1167 unsigned long mc_filter[2];
1168 unsigned int bitnr;
1169 struct macb *bp = netdev_priv(dev);
1170
1171 mc_filter[0] = mc_filter[1] = 0;
1172
1173 netdev_for_each_mc_addr(ha, dev) {
1174 bitnr = hash_get_index(ha->addr);
1175 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1176 }
1177
1178 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1179 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1180 }
1181
1182 /*
1183 * Enable/Disable promiscuous and multicast modes.
1184 */
1185 void macb_set_rx_mode(struct net_device *dev)
1186 {
1187 unsigned long cfg;
1188 struct macb *bp = netdev_priv(dev);
1189
1190 cfg = macb_readl(bp, NCFGR);
1191
1192 if (dev->flags & IFF_PROMISC)
1193 /* Enable promiscuous mode */
1194 cfg |= MACB_BIT(CAF);
1195 else if (dev->flags & (~IFF_PROMISC))
1196 /* Disable promiscuous mode */
1197 cfg &= ~MACB_BIT(CAF);
1198
1199 if (dev->flags & IFF_ALLMULTI) {
1200 /* Enable all multicast mode */
1201 macb_or_gem_writel(bp, HRB, -1);
1202 macb_or_gem_writel(bp, HRT, -1);
1203 cfg |= MACB_BIT(NCFGR_MTI);
1204 } else if (!netdev_mc_empty(dev)) {
1205 /* Enable specific multicasts */
1206 macb_sethashtable(dev);
1207 cfg |= MACB_BIT(NCFGR_MTI);
1208 } else if (dev->flags & (~IFF_ALLMULTI)) {
1209 /* Disable all multicast mode */
1210 macb_or_gem_writel(bp, HRB, 0);
1211 macb_or_gem_writel(bp, HRT, 0);
1212 cfg &= ~MACB_BIT(NCFGR_MTI);
1213 }
1214
1215 macb_writel(bp, NCFGR, cfg);
1216 }
1217 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1218
1219 static int macb_open(struct net_device *dev)
1220 {
1221 struct macb *bp = netdev_priv(dev);
1222 int err;
1223
1224 netdev_dbg(bp->dev, "open\n");
1225
1226 /* carrier starts down */
1227 netif_carrier_off(dev);
1228
1229 /* if the phy is not yet register, retry later*/
1230 if (!bp->phy_dev)
1231 return -EAGAIN;
1232
1233 err = macb_alloc_consistent(bp);
1234 if (err) {
1235 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1236 err);
1237 return err;
1238 }
1239
1240 napi_enable(&bp->napi);
1241
1242 macb_init_rings(bp);
1243 macb_init_hw(bp);
1244
1245 /* schedule a link state check */
1246 phy_start(bp->phy_dev);
1247
1248 netif_start_queue(dev);
1249
1250 return 0;
1251 }
1252
1253 static int macb_close(struct net_device *dev)
1254 {
1255 struct macb *bp = netdev_priv(dev);
1256 unsigned long flags;
1257
1258 netif_stop_queue(dev);
1259 napi_disable(&bp->napi);
1260
1261 if (bp->phy_dev)
1262 phy_stop(bp->phy_dev);
1263
1264 spin_lock_irqsave(&bp->lock, flags);
1265 macb_reset_hw(bp);
1266 netif_carrier_off(dev);
1267 spin_unlock_irqrestore(&bp->lock, flags);
1268
1269 macb_free_consistent(bp);
1270
1271 return 0;
1272 }
1273
1274 static void gem_update_stats(struct macb *bp)
1275 {
1276 u32 __iomem *reg = bp->regs + GEM_OTX;
1277 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1278 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1279
1280 for (; p < end; p++, reg++)
1281 *p += __raw_readl(reg);
1282 }
1283
1284 static struct net_device_stats *gem_get_stats(struct macb *bp)
1285 {
1286 struct gem_stats *hwstat = &bp->hw_stats.gem;
1287 struct net_device_stats *nstat = &bp->stats;
1288
1289 gem_update_stats(bp);
1290
1291 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1292 hwstat->rx_alignment_errors +
1293 hwstat->rx_resource_errors +
1294 hwstat->rx_overruns +
1295 hwstat->rx_oversize_frames +
1296 hwstat->rx_jabbers +
1297 hwstat->rx_undersized_frames +
1298 hwstat->rx_length_field_frame_errors);
1299 nstat->tx_errors = (hwstat->tx_late_collisions +
1300 hwstat->tx_excessive_collisions +
1301 hwstat->tx_underrun +
1302 hwstat->tx_carrier_sense_errors);
1303 nstat->multicast = hwstat->rx_multicast_frames;
1304 nstat->collisions = (hwstat->tx_single_collision_frames +
1305 hwstat->tx_multiple_collision_frames +
1306 hwstat->tx_excessive_collisions);
1307 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1308 hwstat->rx_jabbers +
1309 hwstat->rx_undersized_frames +
1310 hwstat->rx_length_field_frame_errors);
1311 nstat->rx_over_errors = hwstat->rx_resource_errors;
1312 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1313 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1314 nstat->rx_fifo_errors = hwstat->rx_overruns;
1315 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1316 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1317 nstat->tx_fifo_errors = hwstat->tx_underrun;
1318
1319 return nstat;
1320 }
1321
1322 struct net_device_stats *macb_get_stats(struct net_device *dev)
1323 {
1324 struct macb *bp = netdev_priv(dev);
1325 struct net_device_stats *nstat = &bp->stats;
1326 struct macb_stats *hwstat = &bp->hw_stats.macb;
1327
1328 if (macb_is_gem(bp))
1329 return gem_get_stats(bp);
1330
1331 /* read stats from hardware */
1332 macb_update_stats(bp);
1333
1334 /* Convert HW stats into netdevice stats */
1335 nstat->rx_errors = (hwstat->rx_fcs_errors +
1336 hwstat->rx_align_errors +
1337 hwstat->rx_resource_errors +
1338 hwstat->rx_overruns +
1339 hwstat->rx_oversize_pkts +
1340 hwstat->rx_jabbers +
1341 hwstat->rx_undersize_pkts +
1342 hwstat->sqe_test_errors +
1343 hwstat->rx_length_mismatch);
1344 nstat->tx_errors = (hwstat->tx_late_cols +
1345 hwstat->tx_excessive_cols +
1346 hwstat->tx_underruns +
1347 hwstat->tx_carrier_errors);
1348 nstat->collisions = (hwstat->tx_single_cols +
1349 hwstat->tx_multiple_cols +
1350 hwstat->tx_excessive_cols);
1351 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1352 hwstat->rx_jabbers +
1353 hwstat->rx_undersize_pkts +
1354 hwstat->rx_length_mismatch);
1355 nstat->rx_over_errors = hwstat->rx_resource_errors +
1356 hwstat->rx_overruns;
1357 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1358 nstat->rx_frame_errors = hwstat->rx_align_errors;
1359 nstat->rx_fifo_errors = hwstat->rx_overruns;
1360 /* XXX: What does "missed" mean? */
1361 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1362 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1363 nstat->tx_fifo_errors = hwstat->tx_underruns;
1364 /* Don't know about heartbeat or window errors... */
1365
1366 return nstat;
1367 }
1368 EXPORT_SYMBOL_GPL(macb_get_stats);
1369
1370 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1371 {
1372 struct macb *bp = netdev_priv(dev);
1373 struct phy_device *phydev = bp->phy_dev;
1374
1375 if (!phydev)
1376 return -ENODEV;
1377
1378 return phy_ethtool_gset(phydev, cmd);
1379 }
1380
1381 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1382 {
1383 struct macb *bp = netdev_priv(dev);
1384 struct phy_device *phydev = bp->phy_dev;
1385
1386 if (!phydev)
1387 return -ENODEV;
1388
1389 return phy_ethtool_sset(phydev, cmd);
1390 }
1391
1392 static int macb_get_regs_len(struct net_device *netdev)
1393 {
1394 return MACB_GREGS_NBR * sizeof(u32);
1395 }
1396
1397 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1398 void *p)
1399 {
1400 struct macb *bp = netdev_priv(dev);
1401 unsigned int tail, head;
1402 u32 *regs_buff = p;
1403
1404 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1405 | MACB_GREGS_VERSION;
1406
1407 tail = macb_tx_ring_wrap(bp->tx_tail);
1408 head = macb_tx_ring_wrap(bp->tx_head);
1409
1410 regs_buff[0] = macb_readl(bp, NCR);
1411 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1412 regs_buff[2] = macb_readl(bp, NSR);
1413 regs_buff[3] = macb_readl(bp, TSR);
1414 regs_buff[4] = macb_readl(bp, RBQP);
1415 regs_buff[5] = macb_readl(bp, TBQP);
1416 regs_buff[6] = macb_readl(bp, RSR);
1417 regs_buff[7] = macb_readl(bp, IMR);
1418
1419 regs_buff[8] = tail;
1420 regs_buff[9] = head;
1421 regs_buff[10] = macb_tx_dma(bp, tail);
1422 regs_buff[11] = macb_tx_dma(bp, head);
1423
1424 if (macb_is_gem(bp)) {
1425 regs_buff[12] = gem_readl(bp, USRIO);
1426 regs_buff[13] = gem_readl(bp, DMACFG);
1427 }
1428 }
1429
1430 const struct ethtool_ops macb_ethtool_ops = {
1431 .get_settings = macb_get_settings,
1432 .set_settings = macb_set_settings,
1433 .get_regs_len = macb_get_regs_len,
1434 .get_regs = macb_get_regs,
1435 .get_link = ethtool_op_get_link,
1436 .get_ts_info = ethtool_op_get_ts_info,
1437 };
1438 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1439
1440 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1441 {
1442 struct macb *bp = netdev_priv(dev);
1443 struct phy_device *phydev = bp->phy_dev;
1444
1445 if (!netif_running(dev))
1446 return -EINVAL;
1447
1448 if (!phydev)
1449 return -ENODEV;
1450
1451 return phy_mii_ioctl(phydev, rq, cmd);
1452 }
1453 EXPORT_SYMBOL_GPL(macb_ioctl);
1454
1455 static const struct net_device_ops macb_netdev_ops = {
1456 .ndo_open = macb_open,
1457 .ndo_stop = macb_close,
1458 .ndo_start_xmit = macb_start_xmit,
1459 .ndo_set_rx_mode = macb_set_rx_mode,
1460 .ndo_get_stats = macb_get_stats,
1461 .ndo_do_ioctl = macb_ioctl,
1462 .ndo_validate_addr = eth_validate_addr,
1463 .ndo_change_mtu = eth_change_mtu,
1464 .ndo_set_mac_address = eth_mac_addr,
1465 #ifdef CONFIG_NET_POLL_CONTROLLER
1466 .ndo_poll_controller = macb_poll_controller,
1467 #endif
1468 };
1469
1470 #if defined(CONFIG_OF)
1471 static const struct of_device_id macb_dt_ids[] = {
1472 { .compatible = "cdns,at32ap7000-macb" },
1473 { .compatible = "cdns,at91sam9260-macb" },
1474 { .compatible = "cdns,macb" },
1475 { .compatible = "cdns,pc302-gem" },
1476 { .compatible = "cdns,gem" },
1477 { /* sentinel */ }
1478 };
1479 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1480 #endif
1481
1482 static int __init macb_probe(struct platform_device *pdev)
1483 {
1484 struct macb_platform_data *pdata;
1485 struct resource *regs;
1486 struct net_device *dev;
1487 struct macb *bp;
1488 struct phy_device *phydev;
1489 u32 config;
1490 int err = -ENXIO;
1491 struct pinctrl *pinctrl;
1492 const char *mac;
1493
1494 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495 if (!regs) {
1496 dev_err(&pdev->dev, "no mmio resource defined\n");
1497 goto err_out;
1498 }
1499
1500 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1501 if (IS_ERR(pinctrl)) {
1502 err = PTR_ERR(pinctrl);
1503 if (err == -EPROBE_DEFER)
1504 goto err_out;
1505
1506 dev_warn(&pdev->dev, "No pinctrl provided\n");
1507 }
1508
1509 err = -ENOMEM;
1510 dev = alloc_etherdev(sizeof(*bp));
1511 if (!dev)
1512 goto err_out;
1513
1514 SET_NETDEV_DEV(dev, &pdev->dev);
1515
1516 /* TODO: Actually, we have some interesting features... */
1517 dev->features |= 0;
1518
1519 bp = netdev_priv(dev);
1520 bp->pdev = pdev;
1521 bp->dev = dev;
1522
1523 spin_lock_init(&bp->lock);
1524 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1525
1526 bp->pclk = clk_get(&pdev->dev, "pclk");
1527 if (IS_ERR(bp->pclk)) {
1528 dev_err(&pdev->dev, "failed to get macb_clk\n");
1529 goto err_out_free_dev;
1530 }
1531 clk_prepare_enable(bp->pclk);
1532
1533 bp->hclk = clk_get(&pdev->dev, "hclk");
1534 if (IS_ERR(bp->hclk)) {
1535 dev_err(&pdev->dev, "failed to get hclk\n");
1536 goto err_out_put_pclk;
1537 }
1538 clk_prepare_enable(bp->hclk);
1539
1540 bp->regs = ioremap(regs->start, resource_size(regs));
1541 if (!bp->regs) {
1542 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1543 err = -ENOMEM;
1544 goto err_out_disable_clocks;
1545 }
1546
1547 dev->irq = platform_get_irq(pdev, 0);
1548 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1549 if (err) {
1550 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1551 dev->irq, err);
1552 goto err_out_iounmap;
1553 }
1554
1555 dev->netdev_ops = &macb_netdev_ops;
1556 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1557 dev->ethtool_ops = &macb_ethtool_ops;
1558
1559 dev->base_addr = regs->start;
1560
1561 /* Set MII management clock divider */
1562 config = macb_mdc_clk_div(bp);
1563 config |= macb_dbw(bp);
1564 macb_writel(bp, NCFGR, config);
1565
1566 mac = of_get_mac_address(pdev->dev.of_node);
1567 if (mac)
1568 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1569 else
1570 macb_get_hwaddr(bp);
1571
1572 err = of_get_phy_mode(pdev->dev.of_node);
1573 if (err < 0) {
1574 pdata = pdev->dev.platform_data;
1575 if (pdata && pdata->is_rmii)
1576 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1577 else
1578 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1579 } else {
1580 bp->phy_interface = err;
1581 }
1582
1583 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1584 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1585 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1586 #if defined(CONFIG_ARCH_AT91)
1587 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1588 MACB_BIT(CLKEN)));
1589 #else
1590 macb_or_gem_writel(bp, USRIO, 0);
1591 #endif
1592 else
1593 #if defined(CONFIG_ARCH_AT91)
1594 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1595 #else
1596 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1597 #endif
1598
1599 err = register_netdev(dev);
1600 if (err) {
1601 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1602 goto err_out_free_irq;
1603 }
1604
1605 err = macb_mii_init(bp);
1606 if (err)
1607 goto err_out_unregister_netdev;
1608
1609 platform_set_drvdata(pdev, dev);
1610
1611 netif_carrier_off(dev);
1612
1613 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1614 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1615 dev->irq, dev->dev_addr);
1616
1617 phydev = bp->phy_dev;
1618 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1619 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1620
1621 return 0;
1622
1623 err_out_unregister_netdev:
1624 unregister_netdev(dev);
1625 err_out_free_irq:
1626 free_irq(dev->irq, dev);
1627 err_out_iounmap:
1628 iounmap(bp->regs);
1629 err_out_disable_clocks:
1630 clk_disable_unprepare(bp->hclk);
1631 clk_put(bp->hclk);
1632 clk_disable_unprepare(bp->pclk);
1633 err_out_put_pclk:
1634 clk_put(bp->pclk);
1635 err_out_free_dev:
1636 free_netdev(dev);
1637 err_out:
1638 platform_set_drvdata(pdev, NULL);
1639 return err;
1640 }
1641
1642 static int __exit macb_remove(struct platform_device *pdev)
1643 {
1644 struct net_device *dev;
1645 struct macb *bp;
1646
1647 dev = platform_get_drvdata(pdev);
1648
1649 if (dev) {
1650 bp = netdev_priv(dev);
1651 if (bp->phy_dev)
1652 phy_disconnect(bp->phy_dev);
1653 mdiobus_unregister(bp->mii_bus);
1654 kfree(bp->mii_bus->irq);
1655 mdiobus_free(bp->mii_bus);
1656 unregister_netdev(dev);
1657 free_irq(dev->irq, dev);
1658 iounmap(bp->regs);
1659 clk_disable_unprepare(bp->hclk);
1660 clk_put(bp->hclk);
1661 clk_disable_unprepare(bp->pclk);
1662 clk_put(bp->pclk);
1663 free_netdev(dev);
1664 platform_set_drvdata(pdev, NULL);
1665 }
1666
1667 return 0;
1668 }
1669
1670 #ifdef CONFIG_PM
1671 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1672 {
1673 struct net_device *netdev = platform_get_drvdata(pdev);
1674 struct macb *bp = netdev_priv(netdev);
1675
1676 netif_carrier_off(netdev);
1677 netif_device_detach(netdev);
1678
1679 clk_disable_unprepare(bp->hclk);
1680 clk_disable_unprepare(bp->pclk);
1681
1682 return 0;
1683 }
1684
1685 static int macb_resume(struct platform_device *pdev)
1686 {
1687 struct net_device *netdev = platform_get_drvdata(pdev);
1688 struct macb *bp = netdev_priv(netdev);
1689
1690 clk_prepare_enable(bp->pclk);
1691 clk_prepare_enable(bp->hclk);
1692
1693 netif_device_attach(netdev);
1694
1695 return 0;
1696 }
1697 #else
1698 #define macb_suspend NULL
1699 #define macb_resume NULL
1700 #endif
1701
1702 static struct platform_driver macb_driver = {
1703 .remove = __exit_p(macb_remove),
1704 .suspend = macb_suspend,
1705 .resume = macb_resume,
1706 .driver = {
1707 .name = "macb",
1708 .owner = THIS_MODULE,
1709 .of_match_table = of_match_ptr(macb_dt_ids),
1710 },
1711 };
1712
1713 module_platform_driver_probe(macb_driver, macb_probe);
1714
1715 MODULE_LICENSE("GPL");
1716 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1717 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1718 MODULE_ALIAS("platform:macb");
kernel source for telekom puls (alcatel/mediatek)