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bnx2x: add afex support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
19
20 /* compilation time flags */
21
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
25
26 #define DRV_MODULE_VERSION "1.72.17-0"
27 #define DRV_MODULE_RELDATE "2012/04/02"
28 #define BNX2X_BC_VER 0x040200
29
30 #if defined(CONFIG_DCB)
31 #define BCM_DCBNL
32 #endif
33
34
35 #include "bnx2x_hsi.h"
36
37 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
38 #define BCM_CNIC 1
39 #include "../cnic_if.h"
40 #endif
41
42 #ifdef BCM_CNIC
43 #define BNX2X_MIN_MSIX_VEC_CNT 3
44 #define BNX2X_MSIX_VEC_FP_START 2
45 #else
46 #define BNX2X_MIN_MSIX_VEC_CNT 2
47 #define BNX2X_MSIX_VEC_FP_START 1
48 #endif
49
50 #include <linux/mdio.h>
51
52 #include "bnx2x_reg.h"
53 #include "bnx2x_fw_defs.h"
54 #include "bnx2x_hsi.h"
55 #include "bnx2x_link.h"
56 #include "bnx2x_sp.h"
57 #include "bnx2x_dcb.h"
58 #include "bnx2x_stats.h"
59
60 /* error/debug prints */
61
62 #define DRV_MODULE_NAME "bnx2x"
63
64 /* for messages that are currently off */
65 #define BNX2X_MSG_OFF 0x0
66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
72 #define BNX2X_MSG_IOV 0x0800000
73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
74 #define BNX2X_MSG_ETHTOOL 0x4000000
75 #define BNX2X_MSG_DCB 0x8000000
76
77 /* regular debug print */
78 #define DP(__mask, fmt, ...) \
79 do { \
80 if (unlikely(bp->msg_enable & (__mask))) \
81 pr_notice("[%s:%d(%s)]" fmt, \
82 __func__, __LINE__, \
83 bp->dev ? (bp->dev->name) : "?", \
84 ##__VA_ARGS__); \
85 } while (0)
86
87 #define DP_CONT(__mask, fmt, ...) \
88 do { \
89 if (unlikely(bp->msg_enable & (__mask))) \
90 pr_cont(fmt, ##__VA_ARGS__); \
91 } while (0)
92
93 /* errors debug print */
94 #define BNX2X_DBG_ERR(fmt, ...) \
95 do { \
96 if (unlikely(netif_msg_probe(bp))) \
97 pr_err("[%s:%d(%s)]" fmt, \
98 __func__, __LINE__, \
99 bp->dev ? (bp->dev->name) : "?", \
100 ##__VA_ARGS__); \
101 } while (0)
102
103 /* for errors (never masked) */
104 #define BNX2X_ERR(fmt, ...) \
105 do { \
106 pr_err("[%s:%d(%s)]" fmt, \
107 __func__, __LINE__, \
108 bp->dev ? (bp->dev->name) : "?", \
109 ##__VA_ARGS__); \
110 } while (0)
111
112 #define BNX2X_ERROR(fmt, ...) \
113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
114
115
116 /* before we have a dev->name use dev_info() */
117 #define BNX2X_DEV_INFO(fmt, ...) \
118 do { \
119 if (unlikely(netif_msg_probe(bp))) \
120 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
121 } while (0)
122
123 #ifdef BNX2X_STOP_ON_ERROR
124 void bnx2x_int_disable(struct bnx2x *bp);
125 #define bnx2x_panic() \
126 do { \
127 bp->panic = 1; \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_int_disable(bp); \
130 bnx2x_panic_dump(bp); \
131 } while (0)
132 #else
133 #define bnx2x_panic() \
134 do { \
135 bp->panic = 1; \
136 BNX2X_ERR("driver assert\n"); \
137 bnx2x_panic_dump(bp); \
138 } while (0)
139 #endif
140
141 #define bnx2x_mc_addr(ha) ((ha)->addr)
142 #define bnx2x_uc_addr(ha) ((ha)->addr)
143
144 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
145 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
146 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
147
148
149 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
150
151 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
152 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
153 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
154
155 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
156 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
157 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
158
159 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
160 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
161
162 #define REG_RD_DMAE(bp, offset, valp, len32) \
163 do { \
164 bnx2x_read_dmae(bp, offset, len32);\
165 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
166 } while (0)
167
168 #define REG_WR_DMAE(bp, offset, valp, len32) \
169 do { \
170 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
171 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
172 offset, len32); \
173 } while (0)
174
175 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
176 REG_WR_DMAE(bp, offset, valp, len32)
177
178 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
179 do { \
180 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
181 bnx2x_write_big_buf_wb(bp, addr, len32); \
182 } while (0)
183
184 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
185 offsetof(struct shmem_region, field))
186 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
187 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
188
189 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
190 offsetof(struct shmem2_region, field))
191 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
192 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
193 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
194 offsetof(struct mf_cfg, field))
195 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
196 offsetof(struct mf2_cfg, field))
197
198 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
199 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
200 MF_CFG_ADDR(bp, field), (val))
201 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
202
203 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
204 (SHMEM2_RD((bp), size) > \
205 offsetof(struct shmem2_region, field)))
206
207 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
208 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
209
210 /* SP SB indices */
211
212 /* General SP events - stats query, cfc delete, etc */
213 #define HC_SP_INDEX_ETH_DEF_CONS 3
214
215 /* EQ completions */
216 #define HC_SP_INDEX_EQ_CONS 7
217
218 /* FCoE L2 connection completions */
219 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
220 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
221 /* iSCSI L2 */
222 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
223 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
224
225 /* Special clients parameters */
226
227 /* SB indices */
228 /* FCoE L2 */
229 #define BNX2X_FCOE_L2_RX_INDEX \
230 (&bp->def_status_blk->sp_sb.\
231 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
232
233 #define BNX2X_FCOE_L2_TX_INDEX \
234 (&bp->def_status_blk->sp_sb.\
235 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
236
237 /**
238 * CIDs and CLIDs:
239 * CLIDs below is a CLID for func 0, then the CLID for other
240 * functions will be calculated by the formula:
241 *
242 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
243 *
244 */
245 enum {
246 BNX2X_ISCSI_ETH_CL_ID_IDX,
247 BNX2X_FCOE_ETH_CL_ID_IDX,
248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
249 };
250
251 #define BNX2X_CNIC_START_ETH_CID 48
252 enum {
253 /* iSCSI L2 */
254 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID,
255 /* FCoE L2 */
256 BNX2X_FCOE_ETH_CID,
257 };
258
259 /** Additional rings budgeting */
260 #ifdef BCM_CNIC
261 #define CNIC_PRESENT 1
262 #define FCOE_PRESENT 1
263 #else
264 #define CNIC_PRESENT 0
265 #define FCOE_PRESENT 0
266 #endif /* BCM_CNIC */
267 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
268
269 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
270 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
271
272 #define SM_RX_ID 0
273 #define SM_TX_ID 1
274
275 /* defines for multiple tx priority indices */
276 #define FIRST_TX_ONLY_COS_INDEX 1
277 #define FIRST_TX_COS_INDEX 0
278
279 /* defines for decodeing the fastpath index and the cos index out of the
280 * transmission queue index
281 */
282 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x
283
284 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
285 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
286
287 /* rules for calculating the cids of tx-only connections */
288 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
289 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
290
291 /* fp index inside class of service range */
292 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
293
294 /*
295 * 0..15 eth cos0
296 * 16..31 eth cos1 if applicable
297 * 32..47 eth cos2 If applicable
298 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
299 */
300 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
301 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
302
303 /* fast path */
304 /*
305 * This driver uses new build_skb() API :
306 * RX ring buffer contains pointer to kmalloc() data only,
307 * skb are built only after Hardware filled the frame.
308 */
309 struct sw_rx_bd {
310 u8 *data;
311 DEFINE_DMA_UNMAP_ADDR(mapping);
312 };
313
314 struct sw_tx_bd {
315 struct sk_buff *skb;
316 u16 first_bd;
317 u8 flags;
318 /* Set on the first BD descriptor when there is a split BD */
319 #define BNX2X_TSO_SPLIT_BD (1<<0)
320 };
321
322 struct sw_rx_page {
323 struct page *page;
324 DEFINE_DMA_UNMAP_ADDR(mapping);
325 };
326
327 union db_prod {
328 struct doorbell_set_prod data;
329 u32 raw;
330 };
331
332 /* dropless fc FW/HW related params */
333 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
334 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
335 ETH_MAX_AGGREGATION_QUEUES_E1 :\
336 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
337 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
338 #define FW_PREFETCH_CNT 16
339 #define DROPLESS_FC_HEADROOM 100
340
341 /* MC hsi */
342 #define BCM_PAGE_SHIFT 12
343 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
344 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
345 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
346
347 #define PAGES_PER_SGE_SHIFT 0
348 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
349 #define SGE_PAGE_SIZE PAGE_SIZE
350 #define SGE_PAGE_SHIFT PAGE_SHIFT
351 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
352 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
353
354 /* SGE ring related macros */
355 #define NUM_RX_SGE_PAGES 2
356 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
357 #define NEXT_PAGE_SGE_DESC_CNT 2
358 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
359 /* RX_SGE_CNT is promised to be a power of 2 */
360 #define RX_SGE_MASK (RX_SGE_CNT - 1)
361 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
362 #define MAX_RX_SGE (NUM_RX_SGE - 1)
363 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
364 (MAX_RX_SGE_CNT - 1)) ? \
365 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
366 (x) + 1)
367 #define RX_SGE(x) ((x) & MAX_RX_SGE)
368
369 /*
370 * Number of required SGEs is the sum of two:
371 * 1. Number of possible opened aggregations (next packet for
372 * these aggregations will probably consume SGE immidiatelly)
373 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
374 * after placement on BD for new TPA aggregation)
375 *
376 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
377 */
378 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
379 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
380 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
381 MAX_RX_SGE_CNT)
382 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
383 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
384 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
385
386 /* Manipulate a bit vector defined as an array of u64 */
387
388 /* Number of bits in one sge_mask array element */
389 #define BIT_VEC64_ELEM_SZ 64
390 #define BIT_VEC64_ELEM_SHIFT 6
391 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
392
393
394 #define __BIT_VEC64_SET_BIT(el, bit) \
395 do { \
396 el = ((el) | ((u64)0x1 << (bit))); \
397 } while (0)
398
399 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
400 do { \
401 el = ((el) & (~((u64)0x1 << (bit)))); \
402 } while (0)
403
404
405 #define BIT_VEC64_SET_BIT(vec64, idx) \
406 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
407 (idx) & BIT_VEC64_ELEM_MASK)
408
409 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
410 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
411 (idx) & BIT_VEC64_ELEM_MASK)
412
413 #define BIT_VEC64_TEST_BIT(vec64, idx) \
414 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
415 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
416
417 /* Creates a bitmask of all ones in less significant bits.
418 idx - index of the most significant bit in the created mask */
419 #define BIT_VEC64_ONES_MASK(idx) \
420 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
421 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
422
423 /*******************************************************/
424
425
426
427 /* Number of u64 elements in SGE mask array */
428 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
429 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
430 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
431
432 union host_hc_status_block {
433 /* pointer to fp status block e1x */
434 struct host_hc_status_block_e1x *e1x_sb;
435 /* pointer to fp status block e2 */
436 struct host_hc_status_block_e2 *e2_sb;
437 };
438
439 struct bnx2x_agg_info {
440 /*
441 * First aggregation buffer is a data buffer, the following - are pages.
442 * We will preallocate the data buffer for each aggregation when
443 * we open the interface and will replace the BD at the consumer
444 * with this one when we receive the TPA_START CQE in order to
445 * keep the Rx BD ring consistent.
446 */
447 struct sw_rx_bd first_buf;
448 u8 tpa_state;
449 #define BNX2X_TPA_START 1
450 #define BNX2X_TPA_STOP 2
451 #define BNX2X_TPA_ERROR 3
452 u8 placement_offset;
453 u16 parsing_flags;
454 u16 vlan_tag;
455 u16 len_on_bd;
456 u32 rxhash;
457 u16 gro_size;
458 u16 full_page;
459 };
460
461 #define Q_STATS_OFFSET32(stat_name) \
462 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
463
464 struct bnx2x_fp_txdata {
465
466 struct sw_tx_bd *tx_buf_ring;
467
468 union eth_tx_bd_types *tx_desc_ring;
469 dma_addr_t tx_desc_mapping;
470
471 u32 cid;
472
473 union db_prod tx_db;
474
475 u16 tx_pkt_prod;
476 u16 tx_pkt_cons;
477 u16 tx_bd_prod;
478 u16 tx_bd_cons;
479
480 unsigned long tx_pkt;
481
482 __le16 *tx_cons_sb;
483
484 int txq_index;
485 };
486
487 enum bnx2x_tpa_mode_t {
488 TPA_MODE_LRO,
489 TPA_MODE_GRO
490 };
491
492 struct bnx2x_fastpath {
493 struct bnx2x *bp; /* parent */
494
495 #define BNX2X_NAPI_WEIGHT 128
496 struct napi_struct napi;
497 union host_hc_status_block status_blk;
498 /* chip independed shortcuts into sb structure */
499 __le16 *sb_index_values;
500 __le16 *sb_running_index;
501 /* chip independed shortcut into rx_prods_offset memory */
502 u32 ustorm_rx_prods_offset;
503
504 u32 rx_buf_size;
505
506 dma_addr_t status_blk_mapping;
507
508 enum bnx2x_tpa_mode_t mode;
509
510 u8 max_cos; /* actual number of active tx coses */
511 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
512
513 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
514 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
515
516 struct eth_rx_bd *rx_desc_ring;
517 dma_addr_t rx_desc_mapping;
518
519 union eth_rx_cqe *rx_comp_ring;
520 dma_addr_t rx_comp_mapping;
521
522 /* SGE ring */
523 struct eth_rx_sge *rx_sge_ring;
524 dma_addr_t rx_sge_mapping;
525
526 u64 sge_mask[RX_SGE_MASK_LEN];
527
528 u32 cid;
529
530 __le16 fp_hc_idx;
531
532 u8 index; /* number in fp array */
533 u8 rx_queue; /* index for skb_record */
534 u8 cl_id; /* eth client id */
535 u8 cl_qzone_id;
536 u8 fw_sb_id; /* status block number in FW */
537 u8 igu_sb_id; /* status block number in HW */
538
539 u16 rx_bd_prod;
540 u16 rx_bd_cons;
541 u16 rx_comp_prod;
542 u16 rx_comp_cons;
543 u16 rx_sge_prod;
544 /* The last maximal completed SGE */
545 u16 last_max_sge;
546 __le16 *rx_cons_sb;
547 unsigned long rx_pkt,
548 rx_calls;
549
550 /* TPA related */
551 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
552 u8 disable_tpa;
553 #ifdef BNX2X_STOP_ON_ERROR
554 u64 tpa_queue_used;
555 #endif
556
557 struct tstorm_per_queue_stats old_tclient;
558 struct ustorm_per_queue_stats old_uclient;
559 struct xstorm_per_queue_stats old_xclient;
560 struct bnx2x_eth_q_stats eth_q_stats;
561 struct bnx2x_eth_q_stats_old eth_q_stats_old;
562
563 /* The size is calculated using the following:
564 sizeof name field from netdev structure +
565 4 ('-Xx-' string) +
566 4 (for the digits and to make it DWORD aligned) */
567 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
568 char name[FP_NAME_SIZE];
569
570 /* MACs object */
571 struct bnx2x_vlan_mac_obj mac_obj;
572
573 /* Queue State object */
574 struct bnx2x_queue_sp_obj q_obj;
575
576 };
577
578 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
579
580 /* Use 2500 as a mini-jumbo MTU for FCoE */
581 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
582
583 /* FCoE L2 `fastpath' entry is right after the eth entries */
584 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
585 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
586 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
587 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
588 txdata[FIRST_TX_COS_INDEX].var)
589
590
591 #define IS_ETH_FP(fp) (fp->index < \
592 BNX2X_NUM_ETH_QUEUES(fp->bp))
593 #ifdef BCM_CNIC
594 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
595 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
596 #else
597 #define IS_FCOE_FP(fp) false
598 #define IS_FCOE_IDX(idx) false
599 #endif
600
601
602 /* MC hsi */
603 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
604 #define RX_COPY_THRESH 92
605
606 #define NUM_TX_RINGS 16
607 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
608 #define NEXT_PAGE_TX_DESC_CNT 1
609 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
610 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
611 #define MAX_TX_BD (NUM_TX_BD - 1)
612 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
613 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
614 (MAX_TX_DESC_CNT - 1)) ? \
615 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
616 (x) + 1)
617 #define TX_BD(x) ((x) & MAX_TX_BD)
618 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
619
620 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
621 #define NUM_RX_RINGS 8
622 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
623 #define NEXT_PAGE_RX_DESC_CNT 2
624 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
625 #define RX_DESC_MASK (RX_DESC_CNT - 1)
626 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
627 #define MAX_RX_BD (NUM_RX_BD - 1)
628 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
629
630 /* dropless fc calculations for BDs
631 *
632 * Number of BDs should as number of buffers in BRB:
633 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
634 * "next" elements on each page
635 */
636 #define NUM_BD_REQ BRB_SIZE(bp)
637 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
638 MAX_RX_DESC_CNT)
639 #define BD_TH_LO(bp) (NUM_BD_REQ + \
640 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
641 FW_DROP_LEVEL(bp))
642 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
643
644 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
645
646 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
647 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
648 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
649 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
650 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
651 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
652 MIN_RX_AVAIL))
653
654 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
655 (MAX_RX_DESC_CNT - 1)) ? \
656 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
657 (x) + 1)
658 #define RX_BD(x) ((x) & MAX_RX_BD)
659
660 /*
661 * As long as CQE is X times bigger than BD entry we have to allocate X times
662 * more pages for CQ ring in order to keep it balanced with BD ring
663 */
664 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
665 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
666 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
667 #define NEXT_PAGE_RCQ_DESC_CNT 1
668 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
669 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
670 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
671 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
672 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
673 (MAX_RCQ_DESC_CNT - 1)) ? \
674 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
675 (x) + 1)
676 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
677
678 /* dropless fc calculations for RCQs
679 *
680 * Number of RCQs should be as number of buffers in BRB:
681 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
682 * "next" elements on each page
683 */
684 #define NUM_RCQ_REQ BRB_SIZE(bp)
685 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
686 MAX_RCQ_DESC_CNT)
687 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
688 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
689 FW_DROP_LEVEL(bp))
690 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
691
692
693 /* This is needed for determining of last_max */
694 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
695 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
696
697
698 #define BNX2X_SWCID_SHIFT 17
699 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
700
701 /* used on a CID received from the HW */
702 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
703 #define CQE_CMD(x) (le32_to_cpu(x) >> \
704 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
705
706 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
707 le32_to_cpu((bd)->addr_lo))
708 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
709
710 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
711 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
712 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
713 #error "Min DB doorbell stride is 8"
714 #endif
715 #define DPM_TRIGER_TYPE 0x40
716 #define DOORBELL(bp, cid, val) \
717 do { \
718 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
719 DPM_TRIGER_TYPE); \
720 } while (0)
721
722
723 /* TX CSUM helpers */
724 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
725 skb->csum_offset)
726 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
727 skb->csum_offset))
728
729 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
730
731 #define XMIT_PLAIN 0
732 #define XMIT_CSUM_V4 0x1
733 #define XMIT_CSUM_V6 0x2
734 #define XMIT_CSUM_TCP 0x4
735 #define XMIT_GSO_V4 0x8
736 #define XMIT_GSO_V6 0x10
737
738 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
739 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
740
741
742 /* stuff added to make the code fit 80Col */
743 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
744 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
745 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
746 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
747 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
748
749 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
750
751 #define BNX2X_IP_CSUM_ERR(cqe) \
752 (!((cqe)->fast_path_cqe.status_flags & \
753 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
754 ((cqe)->fast_path_cqe.type_error_flags & \
755 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
756
757 #define BNX2X_L4_CSUM_ERR(cqe) \
758 (!((cqe)->fast_path_cqe.status_flags & \
759 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
760 ((cqe)->fast_path_cqe.type_error_flags & \
761 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
762
763 #define BNX2X_RX_CSUM_OK(cqe) \
764 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
765
766 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
767 (((le16_to_cpu(flags) & \
768 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
769 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
770 == PRS_FLAG_OVERETH_IPV4)
771 #define BNX2X_RX_SUM_FIX(cqe) \
772 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
773
774
775 #define FP_USB_FUNC_OFF \
776 offsetof(struct cstorm_status_block_u, func)
777 #define FP_CSB_FUNC_OFF \
778 offsetof(struct cstorm_status_block_c, func)
779
780 #define HC_INDEX_ETH_RX_CQ_CONS 1
781
782 #define HC_INDEX_OOO_TX_CQ_CONS 4
783
784 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
785
786 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
787
788 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
789
790 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
791
792 #define BNX2X_RX_SB_INDEX \
793 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
794
795 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
796
797 #define BNX2X_TX_SB_INDEX_COS0 \
798 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
799
800 /* end of fast path */
801
802 /* common */
803
804 struct bnx2x_common {
805
806 u32 chip_id;
807 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
808 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
809
810 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
811 #define CHIP_NUM_57710 0x164e
812 #define CHIP_NUM_57711 0x164f
813 #define CHIP_NUM_57711E 0x1650
814 #define CHIP_NUM_57712 0x1662
815 #define CHIP_NUM_57712_MF 0x1663
816 #define CHIP_NUM_57713 0x1651
817 #define CHIP_NUM_57713E 0x1652
818 #define CHIP_NUM_57800 0x168a
819 #define CHIP_NUM_57800_MF 0x16a5
820 #define CHIP_NUM_57810 0x168e
821 #define CHIP_NUM_57810_MF 0x16ae
822 #define CHIP_NUM_57811 0x163d
823 #define CHIP_NUM_57811_MF 0x163e
824 #define CHIP_NUM_57840 0x168d
825 #define CHIP_NUM_57840_MF 0x16ab
826 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
827 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
828 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
829 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
830 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
831 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
832 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
833 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
834 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
835 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
836 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
837 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
838 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
839 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
840 CHIP_IS_57711E(bp))
841 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
842 CHIP_IS_57712_MF(bp))
843 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
844 CHIP_IS_57800_MF(bp) || \
845 CHIP_IS_57810(bp) || \
846 CHIP_IS_57810_MF(bp) || \
847 CHIP_IS_57811(bp) || \
848 CHIP_IS_57811_MF(bp) || \
849 CHIP_IS_57840(bp) || \
850 CHIP_IS_57840_MF(bp))
851 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
852 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
853 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
854
855 #define CHIP_REV_SHIFT 12
856 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
857 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
858 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
859 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
860 /* assume maximum 5 revisions */
861 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
862 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
863 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
864 !(CHIP_REV_VAL(bp) & 0x00001000))
865 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
866 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
867 (CHIP_REV_VAL(bp) & 0x00001000))
868
869 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
870 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
871
872 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
873 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
874 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
875 (CHIP_REV_SHIFT + 1)) \
876 << CHIP_REV_SHIFT)
877 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
878 CHIP_REV_SIM(bp) :\
879 CHIP_REV_VAL(bp))
880 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
881 (CHIP_REV(bp) == CHIP_REV_Bx))
882 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
883 (CHIP_REV(bp) == CHIP_REV_Ax))
884
885 int flash_size;
886 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
887 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
888 #define BNX2X_NVRAM_PAGE_SIZE 256
889
890 u32 shmem_base;
891 u32 shmem2_base;
892 u32 mf_cfg_base;
893 u32 mf2_cfg_base;
894
895 u32 hw_config;
896
897 u32 bc_ver;
898
899 u8 int_block;
900 #define INT_BLOCK_HC 0
901 #define INT_BLOCK_IGU 1
902 #define INT_BLOCK_MODE_NORMAL 0
903 #define INT_BLOCK_MODE_BW_COMP 2
904 #define CHIP_INT_MODE_IS_NBC(bp) \
905 (!CHIP_IS_E1x(bp) && \
906 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
907 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
908
909 u8 chip_port_mode;
910 #define CHIP_4_PORT_MODE 0x0
911 #define CHIP_2_PORT_MODE 0x1
912 #define CHIP_PORT_MODE_NONE 0x2
913 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
914 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
915
916 u32 boot_mode;
917 };
918
919 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
920 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
921 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
922
923 /* end of common */
924
925 /* port */
926
927 struct bnx2x_port {
928 u32 pmf;
929
930 u32 link_config[LINK_CONFIG_SIZE];
931
932 u32 supported[LINK_CONFIG_SIZE];
933 /* link settings - missing defines */
934 #define SUPPORTED_2500baseX_Full (1 << 15)
935
936 u32 advertising[LINK_CONFIG_SIZE];
937 /* link settings - missing defines */
938 #define ADVERTISED_2500baseX_Full (1 << 15)
939
940 u32 phy_addr;
941
942 /* used to synchronize phy accesses */
943 struct mutex phy_mutex;
944 int need_hw_lock;
945
946 u32 port_stx;
947
948 struct nig_stats old_nig_stats;
949 };
950
951 /* end of port */
952
953 #define STATS_OFFSET32(stat_name) \
954 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
955
956 /* slow path */
957
958 /* slow path work-queue */
959 extern struct workqueue_struct *bnx2x_wq;
960
961 #define BNX2X_MAX_NUM_OF_VFS 64
962 #define BNX2X_VF_ID_INVALID 0xFF
963
964 /*
965 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
966 * control by the number of fast-path status blocks supported by the
967 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
968 * status block represents an independent interrupts context that can
969 * serve a regular L2 networking queue. However special L2 queues such
970 * as the FCoE queue do not require a FP-SB and other components like
971 * the CNIC may consume FP-SB reducing the number of possible L2 queues
972 *
973 * If the maximum number of FP-SB available is X then:
974 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
975 * regular L2 queues is Y=X-1
976 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
977 * c. If the FCoE L2 queue is supported the actual number of L2 queues
978 * is Y+1
979 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
980 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
981 * FP interrupt context for the CNIC).
982 * e. The number of HW context (CID count) is always X or X+1 if FCoE
983 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
984 */
985
986 /* fast-path interrupt contexts E1x */
987 #define FP_SB_MAX_E1x 16
988 /* fast-path interrupt contexts E2 */
989 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
990
991 union cdu_context {
992 struct eth_context eth;
993 char pad[1024];
994 };
995
996 /* CDU host DB constants */
997 #define CDU_ILT_PAGE_SZ_HW 3
998 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
999 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1000
1001 #ifdef BCM_CNIC
1002 #define CNIC_ISCSI_CID_MAX 256
1003 #define CNIC_FCOE_CID_MAX 2048
1004 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1005 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1006 #endif
1007
1008 #define QM_ILT_PAGE_SZ_HW 0
1009 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1010 #define QM_CID_ROUND 1024
1011
1012 #ifdef BCM_CNIC
1013 /* TM (timers) host DB constants */
1014 #define TM_ILT_PAGE_SZ_HW 0
1015 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1016 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1017 #define TM_CONN_NUM 1024
1018 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1019 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1020
1021 /* SRC (Searcher) host DB constants */
1022 #define SRC_ILT_PAGE_SZ_HW 0
1023 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1024 #define SRC_HASH_BITS 10
1025 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1026 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1027 #define SRC_T2_SZ SRC_ILT_SZ
1028 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1029
1030 #endif
1031
1032 #define MAX_DMAE_C 8
1033
1034 /* DMA memory not used in fastpath */
1035 struct bnx2x_slowpath {
1036 union {
1037 struct mac_configuration_cmd e1x;
1038 struct eth_classify_rules_ramrod_data e2;
1039 } mac_rdata;
1040
1041
1042 union {
1043 struct tstorm_eth_mac_filter_config e1x;
1044 struct eth_filter_rules_ramrod_data e2;
1045 } rx_mode_rdata;
1046
1047 union {
1048 struct mac_configuration_cmd e1;
1049 struct eth_multicast_rules_ramrod_data e2;
1050 } mcast_rdata;
1051
1052 struct eth_rss_update_ramrod_data rss_rdata;
1053
1054 /* Queue State related ramrods are always sent under rtnl_lock */
1055 union {
1056 struct client_init_ramrod_data init_data;
1057 struct client_update_ramrod_data update_data;
1058 } q_rdata;
1059
1060 union {
1061 struct function_start_data func_start;
1062 /* pfc configuration for DCBX ramrod */
1063 struct flow_control_configuration pfc_config;
1064 } func_rdata;
1065
1066 /* afex ramrod can not be a part of func_rdata union because these
1067 * events might arrive in parallel to other events from func_rdata.
1068 * Therefore, if they would have been defined in the same union,
1069 * data can get corrupted.
1070 */
1071 struct afex_vif_list_ramrod_data func_afex_rdata;
1072
1073 /* used by dmae command executer */
1074 struct dmae_command dmae[MAX_DMAE_C];
1075
1076 u32 stats_comp;
1077 union mac_stats mac_stats;
1078 struct nig_stats nig_stats;
1079 struct host_port_stats port_stats;
1080 struct host_func_stats func_stats;
1081
1082 u32 wb_comp;
1083 u32 wb_data[4];
1084
1085 union drv_info_to_mcp drv_info_to_mcp;
1086 };
1087
1088 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1089 #define bnx2x_sp_mapping(bp, var) \
1090 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1091
1092
1093 /* attn group wiring */
1094 #define MAX_DYNAMIC_ATTN_GRPS 8
1095
1096 struct attn_route {
1097 u32 sig[5];
1098 };
1099
1100 struct iro {
1101 u32 base;
1102 u16 m1;
1103 u16 m2;
1104 u16 m3;
1105 u16 size;
1106 };
1107
1108 struct hw_context {
1109 union cdu_context *vcxt;
1110 dma_addr_t cxt_mapping;
1111 size_t size;
1112 };
1113
1114 /* forward */
1115 struct bnx2x_ilt;
1116
1117
1118 enum bnx2x_recovery_state {
1119 BNX2X_RECOVERY_DONE,
1120 BNX2X_RECOVERY_INIT,
1121 BNX2X_RECOVERY_WAIT,
1122 BNX2X_RECOVERY_FAILED,
1123 BNX2X_RECOVERY_NIC_LOADING
1124 };
1125
1126 /*
1127 * Event queue (EQ or event ring) MC hsi
1128 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1129 */
1130 #define NUM_EQ_PAGES 1
1131 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1132 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1133 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1134 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1135 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1136
1137 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1138 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1139 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1140
1141 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1142 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1143
1144 #define BNX2X_EQ_INDEX \
1145 (&bp->def_status_blk->sp_sb.\
1146 index_values[HC_SP_INDEX_EQ_CONS])
1147
1148 /* This is a data that will be used to create a link report message.
1149 * We will keep the data used for the last link report in order
1150 * to prevent reporting the same link parameters twice.
1151 */
1152 struct bnx2x_link_report_data {
1153 u16 line_speed; /* Effective line speed */
1154 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1155 };
1156
1157 enum {
1158 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1159 BNX2X_LINK_REPORT_LINK_DOWN,
1160 BNX2X_LINK_REPORT_RX_FC_ON,
1161 BNX2X_LINK_REPORT_TX_FC_ON,
1162 };
1163
1164 enum {
1165 BNX2X_PORT_QUERY_IDX,
1166 BNX2X_PF_QUERY_IDX,
1167 BNX2X_FCOE_QUERY_IDX,
1168 BNX2X_FIRST_QUEUE_QUERY_IDX,
1169 };
1170
1171 struct bnx2x_fw_stats_req {
1172 struct stats_query_header hdr;
1173 struct stats_query_entry query[FP_SB_MAX_E1x+
1174 BNX2X_FIRST_QUEUE_QUERY_IDX];
1175 };
1176
1177 struct bnx2x_fw_stats_data {
1178 struct stats_counter storm_counters;
1179 struct per_port_stats port;
1180 struct per_pf_stats pf;
1181 struct fcoe_statistics_params fcoe;
1182 struct per_queue_stats queue_stats[1];
1183 };
1184
1185 /* Public slow path states */
1186 enum {
1187 BNX2X_SP_RTNL_SETUP_TC,
1188 BNX2X_SP_RTNL_TX_TIMEOUT,
1189 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1190 BNX2X_SP_RTNL_FAN_FAILURE,
1191 };
1192
1193
1194 struct bnx2x_prev_path_list {
1195 u8 bus;
1196 u8 slot;
1197 u8 path;
1198 struct list_head list;
1199 };
1200
1201 struct bnx2x {
1202 /* Fields used in the tx and intr/napi performance paths
1203 * are grouped together in the beginning of the structure
1204 */
1205 struct bnx2x_fastpath *fp;
1206 void __iomem *regview;
1207 void __iomem *doorbells;
1208 u16 db_size;
1209
1210 u8 pf_num; /* absolute PF number */
1211 u8 pfid; /* per-path PF number */
1212 int base_fw_ndsb; /**/
1213 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1214 #define BP_PORT(bp) (bp->pfid & 1)
1215 #define BP_FUNC(bp) (bp->pfid)
1216 #define BP_ABS_FUNC(bp) (bp->pf_num)
1217 #define BP_VN(bp) ((bp)->pfid >> 1)
1218 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1219 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1220 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1221 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1222 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1223
1224 struct net_device *dev;
1225 struct pci_dev *pdev;
1226
1227 const struct iro *iro_arr;
1228 #define IRO (bp->iro_arr)
1229
1230 enum bnx2x_recovery_state recovery_state;
1231 int is_leader;
1232 struct msix_entry *msix_table;
1233
1234 int tx_ring_size;
1235
1236 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1237 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1238 #define ETH_MIN_PACKET_SIZE 60
1239 #define ETH_MAX_PACKET_SIZE 1500
1240 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1241 /* TCP with Timestamp Option (32) + IPv6 (40) */
1242 #define ETH_MAX_TPA_HEADER_SIZE 72
1243 #define ETH_MIN_TPA_HEADER_SIZE 40
1244
1245 /* Max supported alignment is 256 (8 shift) */
1246 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1247
1248 /* FW uses 2 Cache lines Alignment for start packet and size
1249 *
1250 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1251 * at the end of skb->data, to avoid wasting a full cache line.
1252 * This reduces memory use (skb->truesize).
1253 */
1254 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1255
1256 #define BNX2X_FW_RX_ALIGN_END \
1257 max(1UL << BNX2X_RX_ALIGN_SHIFT, \
1258 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1259
1260 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1261
1262 struct host_sp_status_block *def_status_blk;
1263 #define DEF_SB_IGU_ID 16
1264 #define DEF_SB_ID HC_SP_SB_ID
1265 __le16 def_idx;
1266 __le16 def_att_idx;
1267 u32 attn_state;
1268 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1269
1270 /* slow path ring */
1271 struct eth_spe *spq;
1272 dma_addr_t spq_mapping;
1273 u16 spq_prod_idx;
1274 struct eth_spe *spq_prod_bd;
1275 struct eth_spe *spq_last_bd;
1276 __le16 *dsb_sp_prod;
1277 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1278 /* used to synchronize spq accesses */
1279 spinlock_t spq_lock;
1280
1281 /* event queue */
1282 union event_ring_elem *eq_ring;
1283 dma_addr_t eq_mapping;
1284 u16 eq_prod;
1285 u16 eq_cons;
1286 __le16 *eq_cons_sb;
1287 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1288
1289
1290
1291 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1292 u16 stats_pending;
1293 /* Counter for completed statistics ramrods */
1294 u16 stats_comp;
1295
1296 /* End of fields used in the performance code paths */
1297
1298 int panic;
1299 int msg_enable;
1300
1301 u32 flags;
1302 #define PCIX_FLAG (1 << 0)
1303 #define PCI_32BIT_FLAG (1 << 1)
1304 #define ONE_PORT_FLAG (1 << 2)
1305 #define NO_WOL_FLAG (1 << 3)
1306 #define USING_DAC_FLAG (1 << 4)
1307 #define USING_MSIX_FLAG (1 << 5)
1308 #define USING_MSI_FLAG (1 << 6)
1309 #define DISABLE_MSI_FLAG (1 << 7)
1310 #define TPA_ENABLE_FLAG (1 << 8)
1311 #define NO_MCP_FLAG (1 << 9)
1312
1313 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1314 #define GRO_ENABLE_FLAG (1 << 10)
1315 #define MF_FUNC_DIS (1 << 11)
1316 #define OWN_CNIC_IRQ (1 << 12)
1317 #define NO_ISCSI_OOO_FLAG (1 << 13)
1318 #define NO_ISCSI_FLAG (1 << 14)
1319 #define NO_FCOE_FLAG (1 << 15)
1320 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1321 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1322
1323 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1324 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1325 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1326
1327 int pm_cap;
1328 int mrrs;
1329
1330 struct delayed_work sp_task;
1331 struct delayed_work sp_rtnl_task;
1332
1333 struct delayed_work period_task;
1334 struct timer_list timer;
1335 int current_interval;
1336
1337 u16 fw_seq;
1338 u16 fw_drv_pulse_wr_seq;
1339 u32 func_stx;
1340
1341 struct link_params link_params;
1342 struct link_vars link_vars;
1343 u32 link_cnt;
1344 struct bnx2x_link_report_data last_reported_link;
1345
1346 struct mdio_if_info mdio;
1347
1348 struct bnx2x_common common;
1349 struct bnx2x_port port;
1350
1351 struct cmng_init cmng;
1352
1353 u32 mf_config[E1HVN_MAX];
1354 u32 mf_ext_config;
1355 u32 path_has_ovlan; /* E3 */
1356 u16 mf_ov;
1357 u8 mf_mode;
1358 #define IS_MF(bp) (bp->mf_mode != 0)
1359 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1360 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1361 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1362
1363 u8 wol;
1364
1365 bool gro_check;
1366
1367 int rx_ring_size;
1368
1369 u16 tx_quick_cons_trip_int;
1370 u16 tx_quick_cons_trip;
1371 u16 tx_ticks_int;
1372 u16 tx_ticks;
1373
1374 u16 rx_quick_cons_trip_int;
1375 u16 rx_quick_cons_trip;
1376 u16 rx_ticks_int;
1377 u16 rx_ticks;
1378 /* Maximal coalescing timeout in us */
1379 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1380
1381 u32 lin_cnt;
1382
1383 u16 state;
1384 #define BNX2X_STATE_CLOSED 0
1385 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1386 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1387 #define BNX2X_STATE_OPEN 0x3000
1388 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1389 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1390
1391 #define BNX2X_STATE_DIAG 0xe000
1392 #define BNX2X_STATE_ERROR 0xf000
1393
1394 #define BNX2X_MAX_PRIORITY 8
1395 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1396 #define BNX2X_MAX_COS 3
1397 #define BNX2X_MAX_TX_COS 2
1398 int num_queues;
1399 int disable_tpa;
1400
1401 u32 rx_mode;
1402 #define BNX2X_RX_MODE_NONE 0
1403 #define BNX2X_RX_MODE_NORMAL 1
1404 #define BNX2X_RX_MODE_ALLMULTI 2
1405 #define BNX2X_RX_MODE_PROMISC 3
1406 #define BNX2X_MAX_MULTICAST 64
1407
1408 u8 igu_dsb_id;
1409 u8 igu_base_sb;
1410 u8 igu_sb_cnt;
1411 dma_addr_t def_status_blk_mapping;
1412
1413 struct bnx2x_slowpath *slowpath;
1414 dma_addr_t slowpath_mapping;
1415
1416 /* Total number of FW statistics requests */
1417 u8 fw_stats_num;
1418
1419 /*
1420 * This is a memory buffer that will contain both statistics
1421 * ramrod request and data.
1422 */
1423 void *fw_stats;
1424 dma_addr_t fw_stats_mapping;
1425
1426 /*
1427 * FW statistics request shortcut (points at the
1428 * beginning of fw_stats buffer).
1429 */
1430 struct bnx2x_fw_stats_req *fw_stats_req;
1431 dma_addr_t fw_stats_req_mapping;
1432 int fw_stats_req_sz;
1433
1434 /*
1435 * FW statistics data shortcut (points at the begining of
1436 * fw_stats buffer + fw_stats_req_sz).
1437 */
1438 struct bnx2x_fw_stats_data *fw_stats_data;
1439 dma_addr_t fw_stats_data_mapping;
1440 int fw_stats_data_sz;
1441
1442 struct hw_context context;
1443
1444 struct bnx2x_ilt *ilt;
1445 #define BP_ILT(bp) ((bp)->ilt)
1446 #define ILT_MAX_LINES 256
1447 /*
1448 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1449 * to CNIC.
1450 */
1451 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1452
1453 /*
1454 * Maximum CID count that might be required by the bnx2x:
1455 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1456 */
1457 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1458 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1459 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1460 ILT_PAGE_CIDS))
1461 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1462
1463 int qm_cid_count;
1464
1465 int dropless_fc;
1466
1467 #ifdef BCM_CNIC
1468 u32 cnic_flags;
1469 #define BNX2X_CNIC_FLAG_MAC_SET 1
1470 void *t2;
1471 dma_addr_t t2_mapping;
1472 struct cnic_ops __rcu *cnic_ops;
1473 void *cnic_data;
1474 u32 cnic_tag;
1475 struct cnic_eth_dev cnic_eth_dev;
1476 union host_hc_status_block cnic_sb;
1477 dma_addr_t cnic_sb_mapping;
1478 struct eth_spe *cnic_kwq;
1479 struct eth_spe *cnic_kwq_prod;
1480 struct eth_spe *cnic_kwq_cons;
1481 struct eth_spe *cnic_kwq_last;
1482 u16 cnic_kwq_pending;
1483 u16 cnic_spq_pending;
1484 u8 fip_mac[ETH_ALEN];
1485 struct mutex cnic_mutex;
1486 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1487
1488 /* Start index of the "special" (CNIC related) L2 cleints */
1489 u8 cnic_base_cl_id;
1490 #endif
1491
1492 int dmae_ready;
1493 /* used to synchronize dmae accesses */
1494 spinlock_t dmae_lock;
1495
1496 /* used to protect the FW mail box */
1497 struct mutex fw_mb_mutex;
1498
1499 /* used to synchronize stats collecting */
1500 int stats_state;
1501
1502 /* used for synchronization of concurrent threads statistics handling */
1503 spinlock_t stats_lock;
1504
1505 /* used by dmae command loader */
1506 struct dmae_command stats_dmae;
1507 int executer_idx;
1508
1509 u16 stats_counter;
1510 struct bnx2x_eth_stats eth_stats;
1511 struct host_func_stats func_stats;
1512 struct bnx2x_eth_stats_old eth_stats_old;
1513 struct bnx2x_net_stats_old net_stats_old;
1514 struct bnx2x_fw_port_stats_old fw_stats_old;
1515 bool stats_init;
1516
1517 struct z_stream_s *strm;
1518 void *gunzip_buf;
1519 dma_addr_t gunzip_mapping;
1520 int gunzip_outlen;
1521 #define FW_BUF_SIZE 0x8000
1522 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1523 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1524 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1525
1526 struct raw_op *init_ops;
1527 /* Init blocks offsets inside init_ops */
1528 u16 *init_ops_offsets;
1529 /* Data blob - has 32 bit granularity */
1530 u32 *init_data;
1531 u32 init_mode_flags;
1532 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1533 /* Zipped PRAM blobs - raw data */
1534 const u8 *tsem_int_table_data;
1535 const u8 *tsem_pram_data;
1536 const u8 *usem_int_table_data;
1537 const u8 *usem_pram_data;
1538 const u8 *xsem_int_table_data;
1539 const u8 *xsem_pram_data;
1540 const u8 *csem_int_table_data;
1541 const u8 *csem_pram_data;
1542 #define INIT_OPS(bp) (bp->init_ops)
1543 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1544 #define INIT_DATA(bp) (bp->init_data)
1545 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1546 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1547 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1548 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1549 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1550 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1551 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1552 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1553
1554 #define PHY_FW_VER_LEN 20
1555 char fw_ver[32];
1556 const struct firmware *firmware;
1557
1558 /* DCB support on/off */
1559 u16 dcb_state;
1560 #define BNX2X_DCB_STATE_OFF 0
1561 #define BNX2X_DCB_STATE_ON 1
1562
1563 /* DCBX engine mode */
1564 int dcbx_enabled;
1565 #define BNX2X_DCBX_ENABLED_OFF 0
1566 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1567 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1568 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1569
1570 bool dcbx_mode_uset;
1571
1572 struct bnx2x_config_dcbx_params dcbx_config_params;
1573 struct bnx2x_dcbx_port_params dcbx_port_params;
1574 int dcb_version;
1575
1576 /* CAM credit pools */
1577 struct bnx2x_credit_pool_obj macs_pool;
1578
1579 /* RX_MODE object */
1580 struct bnx2x_rx_mode_obj rx_mode_obj;
1581
1582 /* MCAST object */
1583 struct bnx2x_mcast_obj mcast_obj;
1584
1585 /* RSS configuration object */
1586 struct bnx2x_rss_config_obj rss_conf_obj;
1587
1588 /* Function State controlling object */
1589 struct bnx2x_func_sp_obj func_obj;
1590
1591 unsigned long sp_state;
1592
1593 /* operation indication for the sp_rtnl task */
1594 unsigned long sp_rtnl_state;
1595
1596 /* DCBX Negotation results */
1597 struct dcbx_features dcbx_local_feat;
1598 u32 dcbx_error;
1599
1600 #ifdef BCM_DCBNL
1601 struct dcbx_features dcbx_remote_feat;
1602 u32 dcbx_remote_flags;
1603 #endif
1604 /* AFEX: store default vlan used */
1605 int afex_def_vlan_tag;
1606 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1607 u32 pending_max;
1608
1609 /* multiple tx classes of service */
1610 u8 max_cos;
1611
1612 /* priority to cos mapping */
1613 u8 prio_to_cos[8];
1614 };
1615
1616 /* Tx queues may be less or equal to Rx queues */
1617 extern int num_queues;
1618 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1619 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1620 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1621
1622 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1623
1624 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1625 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1626
1627 #define RSS_IPV4_CAP_MASK \
1628 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1629
1630 #define RSS_IPV4_TCP_CAP_MASK \
1631 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1632
1633 #define RSS_IPV6_CAP_MASK \
1634 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1635
1636 #define RSS_IPV6_TCP_CAP_MASK \
1637 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1638
1639 /* func init flags */
1640 #define FUNC_FLG_RSS 0x0001
1641 #define FUNC_FLG_STATS 0x0002
1642 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1643 #define FUNC_FLG_TPA 0x0008
1644 #define FUNC_FLG_SPQ 0x0010
1645 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1646
1647
1648 struct bnx2x_func_init_params {
1649 /* dma */
1650 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1651 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1652
1653 u16 func_flgs;
1654 u16 func_id; /* abs fid */
1655 u16 pf_id;
1656 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1657 };
1658
1659 #define for_each_eth_queue(bp, var) \
1660 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1661
1662 #define for_each_nondefault_eth_queue(bp, var) \
1663 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1664
1665 #define for_each_queue(bp, var) \
1666 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1667 if (skip_queue(bp, var)) \
1668 continue; \
1669 else
1670
1671 /* Skip forwarding FP */
1672 #define for_each_rx_queue(bp, var) \
1673 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1674 if (skip_rx_queue(bp, var)) \
1675 continue; \
1676 else
1677
1678 /* Skip OOO FP */
1679 #define for_each_tx_queue(bp, var) \
1680 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1681 if (skip_tx_queue(bp, var)) \
1682 continue; \
1683 else
1684
1685 #define for_each_nondefault_queue(bp, var) \
1686 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1687 if (skip_queue(bp, var)) \
1688 continue; \
1689 else
1690
1691 #define for_each_cos_in_tx_queue(fp, var) \
1692 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1693
1694 /* skip rx queue
1695 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1696 */
1697 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1698
1699 /* skip tx queue
1700 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1701 */
1702 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1703
1704 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1705
1706
1707
1708
1709 /**
1710 * bnx2x_set_mac_one - configure a single MAC address
1711 *
1712 * @bp: driver handle
1713 * @mac: MAC to configure
1714 * @obj: MAC object handle
1715 * @set: if 'true' add a new MAC, otherwise - delete
1716 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1717 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1718 *
1719 * Configures one MAC according to provided parameters or continues the
1720 * execution of previously scheduled commands if RAMROD_CONT is set in
1721 * ramrod_flags.
1722 *
1723 * Returns zero if operation has successfully completed, a positive value if the
1724 * operation has been successfully scheduled and a negative - if a requested
1725 * operations has failed.
1726 */
1727 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1728 struct bnx2x_vlan_mac_obj *obj, bool set,
1729 int mac_type, unsigned long *ramrod_flags);
1730 /**
1731 * Deletes all MACs configured for the specific MAC object.
1732 *
1733 * @param bp Function driver instance
1734 * @param mac_obj MAC object to cleanup
1735 *
1736 * @return zero if all MACs were cleaned
1737 */
1738
1739 /**
1740 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1741 *
1742 * @bp: driver handle
1743 * @mac_obj: MAC object handle
1744 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1745 * @wait_for_comp: if 'true' block until completion
1746 *
1747 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1748 *
1749 * Returns zero if operation has successfully completed, a positive value if the
1750 * operation has been successfully scheduled and a negative - if a requested
1751 * operations has failed.
1752 */
1753 int bnx2x_del_all_macs(struct bnx2x *bp,
1754 struct bnx2x_vlan_mac_obj *mac_obj,
1755 int mac_type, bool wait_for_comp);
1756
1757 /* Init Function API */
1758 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1759 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1760 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1761 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1762 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1763 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1764
1765
1766 /* dmae */
1767 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1768 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1769 u32 len32);
1770 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1771 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1772 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1773 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1774 bool with_comp, u8 comp_type);
1775
1776
1777 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1778 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1779 u32 data_hi, u32 data_lo, int cmd_type);
1780 void bnx2x_update_coalesce(struct bnx2x *bp);
1781 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1782
1783 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1784 int wait)
1785 {
1786 u32 val;
1787
1788 do {
1789 val = REG_RD(bp, reg);
1790 if (val == expected)
1791 break;
1792 ms -= wait;
1793 msleep(wait);
1794
1795 } while (ms > 0);
1796
1797 return val;
1798 }
1799
1800 #define BNX2X_ILT_ZALLOC(x, y, size) \
1801 do { \
1802 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1803 if (x) \
1804 memset(x, 0, size); \
1805 } while (0)
1806
1807 #define BNX2X_ILT_FREE(x, y, size) \
1808 do { \
1809 if (x) { \
1810 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1811 x = NULL; \
1812 y = 0; \
1813 } \
1814 } while (0)
1815
1816 #define ILOG2(x) (ilog2((x)))
1817
1818 #define ILT_NUM_PAGE_ENTRIES (3072)
1819 /* In 57710/11 we use whole table since we have 8 func
1820 * In 57712 we have only 4 func, but use same size per func, then only half of
1821 * the table in use
1822 */
1823 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1824
1825 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1826 /*
1827 * the phys address is shifted right 12 bits and has an added
1828 * 1=valid bit added to the 53rd bit
1829 * then since this is a wide register(TM)
1830 * we split it into two 32 bit writes
1831 */
1832 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1833 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1834
1835 /* load/unload mode */
1836 #define LOAD_NORMAL 0
1837 #define LOAD_OPEN 1
1838 #define LOAD_DIAG 2
1839 #define UNLOAD_NORMAL 0
1840 #define UNLOAD_CLOSE 1
1841 #define UNLOAD_RECOVERY 2
1842
1843
1844 /* DMAE command defines */
1845 #define DMAE_TIMEOUT -1
1846 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1847 #define DMAE_NOT_RDY -3
1848 #define DMAE_PCI_ERR_FLAG 0x80000000
1849
1850 #define DMAE_SRC_PCI 0
1851 #define DMAE_SRC_GRC 1
1852
1853 #define DMAE_DST_NONE 0
1854 #define DMAE_DST_PCI 1
1855 #define DMAE_DST_GRC 2
1856
1857 #define DMAE_COMP_PCI 0
1858 #define DMAE_COMP_GRC 1
1859
1860 /* E2 and onward - PCI error handling in the completion */
1861
1862 #define DMAE_COMP_REGULAR 0
1863 #define DMAE_COM_SET_ERR 1
1864
1865 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1866 DMAE_COMMAND_SRC_SHIFT)
1867 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1868 DMAE_COMMAND_SRC_SHIFT)
1869
1870 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1871 DMAE_COMMAND_DST_SHIFT)
1872 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1873 DMAE_COMMAND_DST_SHIFT)
1874
1875 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1876 DMAE_COMMAND_C_DST_SHIFT)
1877 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1878 DMAE_COMMAND_C_DST_SHIFT)
1879
1880 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1881
1882 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1883 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1884 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1885 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1886
1887 #define DMAE_CMD_PORT_0 0
1888 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1889
1890 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1891 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1892 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1893
1894 #define DMAE_SRC_PF 0
1895 #define DMAE_SRC_VF 1
1896
1897 #define DMAE_DST_PF 0
1898 #define DMAE_DST_VF 1
1899
1900 #define DMAE_C_SRC 0
1901 #define DMAE_C_DST 1
1902
1903 #define DMAE_LEN32_RD_MAX 0x80
1904 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1905
1906 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1907 indicates eror */
1908
1909 #define MAX_DMAE_C_PER_PORT 8
1910 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1911 BP_VN(bp))
1912 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1913 E1HVN_MAX)
1914
1915 /* PCIE link and speed */
1916 #define PCICFG_LINK_WIDTH 0x1f00000
1917 #define PCICFG_LINK_WIDTH_SHIFT 20
1918 #define PCICFG_LINK_SPEED 0xf0000
1919 #define PCICFG_LINK_SPEED_SHIFT 16
1920
1921
1922 #define BNX2X_NUM_TESTS 7
1923
1924 #define BNX2X_PHY_LOOPBACK 0
1925 #define BNX2X_MAC_LOOPBACK 1
1926 #define BNX2X_PHY_LOOPBACK_FAILED 1
1927 #define BNX2X_MAC_LOOPBACK_FAILED 2
1928 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1929 BNX2X_PHY_LOOPBACK_FAILED)
1930
1931
1932 #define STROM_ASSERT_ARRAY_SIZE 50
1933
1934
1935 /* must be used on a CID before placing it on a HW ring */
1936 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1937 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1938 (x))
1939
1940 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1941 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1942
1943
1944 #define BNX2X_BTR 4
1945 #define MAX_SPQ_PENDING 8
1946
1947 /* CMNG constants, as derived from system spec calculations */
1948 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1949 #define DEF_MIN_RATE 100
1950 /* resolution of the rate shaping timer - 400 usec */
1951 #define RS_PERIODIC_TIMEOUT_USEC 400
1952 /* number of bytes in single QM arbitration cycle -
1953 * coefficient for calculating the fairness timer */
1954 #define QM_ARB_BYTES 160000
1955 /* resolution of Min algorithm 1:100 */
1956 #define MIN_RES 100
1957 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1958 #define MIN_ABOVE_THRESH 32768
1959 /* Fairness algorithm integration time coefficient -
1960 * for calculating the actual Tfair */
1961 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1962 /* Memory of fairness algorithm . 2 cycles */
1963 #define FAIR_MEM 2
1964
1965
1966 #define ATTN_NIG_FOR_FUNC (1L << 8)
1967 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1968 #define GPIO_2_FUNC (1L << 10)
1969 #define GPIO_3_FUNC (1L << 11)
1970 #define GPIO_4_FUNC (1L << 12)
1971 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1972 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1973 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1974 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1975 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1976 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1977
1978 #define ATTN_HARD_WIRED_MASK 0xff00
1979 #define ATTENTION_ID 4
1980
1981
1982 /* stuff added to make the code fit 80Col */
1983
1984 #define BNX2X_PMF_LINK_ASSERT \
1985 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1986
1987 #define BNX2X_MC_ASSERT_BITS \
1988 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1989 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1990 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1991 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1992
1993 #define BNX2X_MCP_ASSERT \
1994 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1995
1996 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1997 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1998 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1999 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2000 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2001 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2002 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2003
2004 #define HW_INTERRUT_ASSERT_SET_0 \
2005 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2006 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2007 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2008 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2009 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2010 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2011 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2012 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2013 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2014 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2015 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2016 #define HW_INTERRUT_ASSERT_SET_1 \
2017 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2018 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2019 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2020 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2021 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2022 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2023 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2024 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2025 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2026 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2027 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2028 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2029 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2030 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2031 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2032 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2033 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2034 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2035 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2036 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2037 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2038 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2039 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2040 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2041 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2042 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2043 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2044 #define HW_INTERRUT_ASSERT_SET_2 \
2045 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2046 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2047 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2048 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2049 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2050 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2051 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2052 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2053 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2054 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2055 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2056 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2057 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2058
2059 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2060 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2061 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2062 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2063
2064 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2065 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2066
2067 #define MULTI_MASK 0x7f
2068
2069
2070 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2071 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2072 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2073 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2074
2075 #define DEF_USB_IGU_INDEX_OFF \
2076 offsetof(struct cstorm_def_status_block_u, igu_index)
2077 #define DEF_CSB_IGU_INDEX_OFF \
2078 offsetof(struct cstorm_def_status_block_c, igu_index)
2079 #define DEF_XSB_IGU_INDEX_OFF \
2080 offsetof(struct xstorm_def_status_block, igu_index)
2081 #define DEF_TSB_IGU_INDEX_OFF \
2082 offsetof(struct tstorm_def_status_block, igu_index)
2083
2084 #define DEF_USB_SEGMENT_OFF \
2085 offsetof(struct cstorm_def_status_block_u, segment)
2086 #define DEF_CSB_SEGMENT_OFF \
2087 offsetof(struct cstorm_def_status_block_c, segment)
2088 #define DEF_XSB_SEGMENT_OFF \
2089 offsetof(struct xstorm_def_status_block, segment)
2090 #define DEF_TSB_SEGMENT_OFF \
2091 offsetof(struct tstorm_def_status_block, segment)
2092
2093 #define BNX2X_SP_DSB_INDEX \
2094 (&bp->def_status_blk->sp_sb.\
2095 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2096
2097 #define SET_FLAG(value, mask, flag) \
2098 do {\
2099 (value) &= ~(mask);\
2100 (value) |= ((flag) << (mask##_SHIFT));\
2101 } while (0)
2102
2103 #define GET_FLAG(value, mask) \
2104 (((value) & (mask)) >> (mask##_SHIFT))
2105
2106 #define GET_FIELD(value, fname) \
2107 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2108
2109 #define CAM_IS_INVALID(x) \
2110 (GET_FLAG(x.flags, \
2111 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2112 (T_ETH_MAC_COMMAND_INVALIDATE))
2113
2114 /* Number of u32 elements in MC hash array */
2115 #define MC_HASH_SIZE 8
2116 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2117 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2118
2119
2120 #ifndef PXP2_REG_PXP2_INT_STS
2121 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2122 #endif
2123
2124 #ifndef ETH_MAX_RX_CLIENTS_E2
2125 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2126 #endif
2127
2128 #define BNX2X_VPD_LEN 128
2129 #define VENDOR_ID_LEN 4
2130
2131 /* Congestion management fairness mode */
2132 #define CMNG_FNS_NONE 0
2133 #define CMNG_FNS_MINMAX 1
2134
2135 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2136 #define HC_SEG_ACCESS_ATTN 4
2137 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2138
2139 static const u32 dmae_reg_go_c[] = {
2140 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2141 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2142 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2143 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2144 };
2145
2146 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2147 void bnx2x_notify_link_changed(struct bnx2x *bp);
2148
2149
2150 #define BNX2X_MF_SD_PROTOCOL(bp) \
2151 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2152
2153 #ifdef BCM_CNIC
2154 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2155 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2156
2157 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2158 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2159
2160 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2161 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2162
2163 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2164 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2165
2166 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2167 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2168 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2169 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2170 #else
2171 #define IS_MF_FCOE_AFEX(bp) false
2172 #endif
2173
2174
2175 #endif /* bnx2x.h */
kernel source for telekom puls (alcatel/mediatek)