projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / dl2k.c
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12 /*
13 Rev Date Description
14 ==========================================================================
15 0.01 2001/05/03 Created DL2000-based linux driver
16 0.02 2001/05/21 Added VLAN and hardware checksum support.
17 1.00 2001/06/26 Added jumbo frame support.
18 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
19 1.02 2001/10/08 Supported fiber media.
20 Added flow control parameters.
21 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
22 the fiber devices.
23 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
24 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
25 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
26 Fixed tx_full flag incorrect.
27 Added tx_coalesce paramter.
28 1.07 2002/01/03 Fixed miscount of RX frame error.
29 1.08 2002/01/17 Fixed the multicast bug.
30 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
31 Added rio_timer() to watch rx buffers.
32 1.10 2002/04/16 Fixed miscount of carrier error.
33 1.11 2002/05/23 Added ISR schedule scheme
34 Fixed miscount of rx frame error for DGE-550SX.
35 Fixed VLAN bug.
36 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
37 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
38 errs) with some mainboards.
39 2. Use definition "DRV_NAME" "DRV_VERSION"
40 "DRV_RELDATE" for flexibility.
41 1.14 2002/08/14 Support ethtool.
42 1.15 2002/08/27 Changed the default media to Auto-Negotiation
43 for the fiber devices.
44 1.16 2002/09/04 More power down time for fiber devices auto-
45 negotiation.
46 Fix disconnect bug after ifup and ifdown.
47 1.17 2002/10/03 Fix RMON statistics overflow.
48 Always use I/O mapping to access eeprom,
49 avoid system freezing with some chipsets.
50
51 */
52 #define DRV_NAME "D-Link DL2000-based linux driver"
53 #define DRV_VERSION "v1.17a"
54 #define DRV_RELDATE "2002/10/04"
55 #include "dl2k.h"
56
57 static char version[] __devinitdata =
58 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
59 #define MAX_UNITS 8
60 static int mtu[MAX_UNITS];
61 static int vlan[MAX_UNITS];
62 static int jumbo[MAX_UNITS];
63 static char *media[MAX_UNITS];
64 static int tx_flow=-1;
65 static int rx_flow=-1;
66 static int copy_thresh;
67 static int rx_coalesce=10; /* Rx frame count each interrupt */
68 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
69 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
70
71
72 MODULE_AUTHOR ("Edward Peng");
73 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
74 MODULE_LICENSE("GPL");
75 module_param_array(mtu, int, NULL, 0);
76 module_param_array(media, charp, NULL, 0);
77 module_param_array(vlan, int, NULL, 0);
78 module_param_array(jumbo, int, NULL, 0);
79 module_param(tx_flow, int, 0);
80 module_param(rx_flow, int, 0);
81 module_param(copy_thresh, int, 0);
82 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
83 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
84 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
85
86
87 /* Enable the default interrupts */
88 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
89 UpdateStats | LinkEvent)
90 #define EnableInt() \
91 writew(DEFAULT_INTR, ioaddr + IntEnable)
92
93 static int max_intrloop = 50;
94 static int multicast_filter_limit = 0x40;
95
96 static int rio_open (struct net_device *dev);
97 static void rio_timer (unsigned long data);
98 static void rio_tx_timeout (struct net_device *dev);
99 static void alloc_list (struct net_device *dev);
100 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
101 static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
102 static void rio_free_tx (struct net_device *dev, int irq);
103 static void tx_error (struct net_device *dev, int tx_status);
104 static int receive_packet (struct net_device *dev);
105 static void rio_error (struct net_device *dev, int int_status);
106 static int change_mtu (struct net_device *dev, int new_mtu);
107 static void set_multicast (struct net_device *dev);
108 static struct net_device_stats *get_stats (struct net_device *dev);
109 static int clear_stats (struct net_device *dev);
110 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
111 static int rio_close (struct net_device *dev);
112 static int find_miiphy (struct net_device *dev);
113 static int parse_eeprom (struct net_device *dev);
114 static int read_eeprom (long ioaddr, int eep_addr);
115 static int mii_wait_link (struct net_device *dev, int wait);
116 static int mii_set_media (struct net_device *dev);
117 static int mii_get_media (struct net_device *dev);
118 static int mii_set_media_pcs (struct net_device *dev);
119 static int mii_get_media_pcs (struct net_device *dev);
120 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
121 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
122 u16 data);
123
124 static struct ethtool_ops ethtool_ops;
125
126 static int __devinit
127 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
128 {
129 struct net_device *dev;
130 struct netdev_private *np;
131 static int card_idx;
132 int chip_idx = ent->driver_data;
133 int err, irq;
134 long ioaddr;
135 static int version_printed;
136 void *ring_space;
137 dma_addr_t ring_dma;
138
139 if (!version_printed++)
140 printk ("%s", version);
141
142 err = pci_enable_device (pdev);
143 if (err)
144 return err;
145
146 irq = pdev->irq;
147 err = pci_request_regions (pdev, "dl2k");
148 if (err)
149 goto err_out_disable;
150
151 pci_set_master (pdev);
152 dev = alloc_etherdev (sizeof (*np));
153 if (!dev) {
154 err = -ENOMEM;
155 goto err_out_res;
156 }
157 SET_MODULE_OWNER (dev);
158 SET_NETDEV_DEV(dev, &pdev->dev);
159
160 #ifdef MEM_MAPPING
161 ioaddr = pci_resource_start (pdev, 1);
162 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
163 if (!ioaddr) {
164 err = -ENOMEM;
165 goto err_out_dev;
166 }
167 #else
168 ioaddr = pci_resource_start (pdev, 0);
169 #endif
170 dev->base_addr = ioaddr;
171 dev->irq = irq;
172 np = netdev_priv(dev);
173 np->chip_id = chip_idx;
174 np->pdev = pdev;
175 spin_lock_init (&np->tx_lock);
176 spin_lock_init (&np->rx_lock);
177
178 /* Parse manual configuration */
179 np->an_enable = 1;
180 np->tx_coalesce = 1;
181 if (card_idx < MAX_UNITS) {
182 if (media[card_idx] != NULL) {
183 np->an_enable = 0;
184 if (strcmp (media[card_idx], "auto") == 0 ||
185 strcmp (media[card_idx], "autosense") == 0 ||
186 strcmp (media[card_idx], "0") == 0 ) {
187 np->an_enable = 2;
188 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
189 strcmp (media[card_idx], "4") == 0) {
190 np->speed = 100;
191 np->full_duplex = 1;
192 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
193 || strcmp (media[card_idx], "3") == 0) {
194 np->speed = 100;
195 np->full_duplex = 0;
196 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
197 strcmp (media[card_idx], "2") == 0) {
198 np->speed = 10;
199 np->full_duplex = 1;
200 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
201 strcmp (media[card_idx], "1") == 0) {
202 np->speed = 10;
203 np->full_duplex = 0;
204 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
205 strcmp (media[card_idx], "6") == 0) {
206 np->speed=1000;
207 np->full_duplex=1;
208 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
209 strcmp (media[card_idx], "5") == 0) {
210 np->speed = 1000;
211 np->full_duplex = 0;
212 } else {
213 np->an_enable = 1;
214 }
215 }
216 if (jumbo[card_idx] != 0) {
217 np->jumbo = 1;
218 dev->mtu = MAX_JUMBO;
219 } else {
220 np->jumbo = 0;
221 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
222 dev->mtu = mtu[card_idx];
223 }
224 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
225 vlan[card_idx] : 0;
226 if (rx_coalesce > 0 && rx_timeout > 0) {
227 np->rx_coalesce = rx_coalesce;
228 np->rx_timeout = rx_timeout;
229 np->coalesce = 1;
230 }
231 np->tx_flow = (tx_flow == 0) ? 0 : 1;
232 np->rx_flow = (rx_flow == 0) ? 0 : 1;
233
234 if (tx_coalesce < 1)
235 tx_coalesce = 1;
236 else if (tx_coalesce > TX_RING_SIZE-1)
237 tx_coalesce = TX_RING_SIZE - 1;
238 }
239 dev->open = &rio_open;
240 dev->hard_start_xmit = &start_xmit;
241 dev->stop = &rio_close;
242 dev->get_stats = &get_stats;
243 dev->set_multicast_list = &set_multicast;
244 dev->do_ioctl = &rio_ioctl;
245 dev->tx_timeout = &rio_tx_timeout;
246 dev->watchdog_timeo = TX_TIMEOUT;
247 dev->change_mtu = &change_mtu;
248 SET_ETHTOOL_OPS(dev, &ethtool_ops);
249 #if 0
250 dev->features = NETIF_F_IP_CSUM;
251 #endif
252 pci_set_drvdata (pdev, dev);
253
254 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
255 if (!ring_space)
256 goto err_out_iounmap;
257 np->tx_ring = (struct netdev_desc *) ring_space;
258 np->tx_ring_dma = ring_dma;
259
260 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
261 if (!ring_space)
262 goto err_out_unmap_tx;
263 np->rx_ring = (struct netdev_desc *) ring_space;
264 np->rx_ring_dma = ring_dma;
265
266 /* Parse eeprom data */
267 parse_eeprom (dev);
268
269 /* Find PHY address */
270 err = find_miiphy (dev);
271 if (err)
272 goto err_out_unmap_rx;
273
274 /* Fiber device? */
275 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
276 np->link_status = 0;
277 /* Set media and reset PHY */
278 if (np->phy_media) {
279 /* default Auto-Negotiation for fiber deivices */
280 if (np->an_enable == 2) {
281 np->an_enable = 1;
282 }
283 mii_set_media_pcs (dev);
284 } else {
285 /* Auto-Negotiation is mandatory for 1000BASE-T,
286 IEEE 802.3ab Annex 28D page 14 */
287 if (np->speed == 1000)
288 np->an_enable = 1;
289 mii_set_media (dev);
290 }
291 pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
292
293 err = register_netdev (dev);
294 if (err)
295 goto err_out_unmap_rx;
296
297 card_idx++;
298
299 printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
300 dev->name, np->name,
301 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
302 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
303 if (tx_coalesce > 1)
304 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
305 tx_coalesce);
306 if (np->coalesce)
307 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
308 KERN_INFO "rx_timeout: \t%d ns\n",
309 np->rx_coalesce, np->rx_timeout*640);
310 if (np->vlan)
311 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
312 return 0;
313
314 err_out_unmap_rx:
315 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
316 err_out_unmap_tx:
317 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
318 err_out_iounmap:
319 #ifdef MEM_MAPPING
320 iounmap ((void *) ioaddr);
321
322 err_out_dev:
323 #endif
324 free_netdev (dev);
325
326 err_out_res:
327 pci_release_regions (pdev);
328
329 err_out_disable:
330 pci_disable_device (pdev);
331 return err;
332 }
333
334 int
335 find_miiphy (struct net_device *dev)
336 {
337 int i, phy_found = 0;
338 struct netdev_private *np;
339 long ioaddr;
340 np = netdev_priv(dev);
341 ioaddr = dev->base_addr;
342 np->phy_addr = 1;
343
344 for (i = 31; i >= 0; i--) {
345 int mii_status = mii_read (dev, i, 1);
346 if (mii_status != 0xffff && mii_status != 0x0000) {
347 np->phy_addr = i;
348 phy_found++;
349 }
350 }
351 if (!phy_found) {
352 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
353 return -ENODEV;
354 }
355 return 0;
356 }
357
358 int
359 parse_eeprom (struct net_device *dev)
360 {
361 int i, j;
362 long ioaddr = dev->base_addr;
363 u8 sromdata[256];
364 u8 *psib;
365 u32 crc;
366 PSROM_t psrom = (PSROM_t) sromdata;
367 struct netdev_private *np = netdev_priv(dev);
368
369 int cid, next;
370
371 #ifdef MEM_MAPPING
372 ioaddr = pci_resource_start (np->pdev, 0);
373 #endif
374 /* Read eeprom */
375 for (i = 0; i < 128; i++) {
376 ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
377 }
378 #ifdef MEM_MAPPING
379 ioaddr = dev->base_addr;
380 #endif
381 /* Check CRC */
382 crc = ~ether_crc_le (256 - 4, sromdata);
383 if (psrom->crc != crc) {
384 printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
385 return -1;
386 }
387
388 /* Set MAC address */
389 for (i = 0; i < 6; i++)
390 dev->dev_addr[i] = psrom->mac_addr[i];
391
392 /* Parse Software Infomation Block */
393 i = 0x30;
394 psib = (u8 *) sromdata;
395 do {
396 cid = psib[i++];
397 next = psib[i++];
398 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
399 printk (KERN_ERR "Cell data error\n");
400 return -1;
401 }
402 switch (cid) {
403 case 0: /* Format version */
404 break;
405 case 1: /* End of cell */
406 return 0;
407 case 2: /* Duplex Polarity */
408 np->duplex_polarity = psib[i];
409 writeb (readb (ioaddr + PhyCtrl) | psib[i],
410 ioaddr + PhyCtrl);
411 break;
412 case 3: /* Wake Polarity */
413 np->wake_polarity = psib[i];
414 break;
415 case 9: /* Adapter description */
416 j = (next - i > 255) ? 255 : next - i;
417 memcpy (np->name, &(psib[i]), j);
418 break;
419 case 4:
420 case 5:
421 case 6:
422 case 7:
423 case 8: /* Reversed */
424 break;
425 default: /* Unknown cell */
426 return -1;
427 }
428 i = next;
429 } while (1);
430
431 return 0;
432 }
433
434 static int
435 rio_open (struct net_device *dev)
436 {
437 struct netdev_private *np = netdev_priv(dev);
438 long ioaddr = dev->base_addr;
439 int i;
440 u16 macctrl;
441
442 i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
443 if (i)
444 return i;
445
446 /* Reset all logic functions */
447 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
448 ioaddr + ASICCtrl + 2);
449 mdelay(10);
450
451 /* DebugCtrl bit 4, 5, 9 must set */
452 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
453
454 /* Jumbo frame */
455 if (np->jumbo != 0)
456 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
457
458 alloc_list (dev);
459
460 /* Get station address */
461 for (i = 0; i < 6; i++)
462 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
463
464 set_multicast (dev);
465 if (np->coalesce) {
466 writel (np->rx_coalesce | np->rx_timeout << 16,
467 ioaddr + RxDMAIntCtrl);
468 }
469 /* Set RIO to poll every N*320nsec. */
470 writeb (0x20, ioaddr + RxDMAPollPeriod);
471 writeb (0xff, ioaddr + TxDMAPollPeriod);
472 writeb (0x30, ioaddr + RxDMABurstThresh);
473 writeb (0x30, ioaddr + RxDMAUrgentThresh);
474 writel (0x0007ffff, ioaddr + RmonStatMask);
475 /* clear statistics */
476 clear_stats (dev);
477
478 /* VLAN supported */
479 if (np->vlan) {
480 /* priority field in RxDMAIntCtrl */
481 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
482 ioaddr + RxDMAIntCtrl);
483 /* VLANId */
484 writew (np->vlan, ioaddr + VLANId);
485 /* Length/Type should be 0x8100 */
486 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
487 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
488 VLAN information tagged by TFC' VID, CFI fields. */
489 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
490 ioaddr + MACCtrl);
491 }
492
493 init_timer (&np->timer);
494 np->timer.expires = jiffies + 1*HZ;
495 np->timer.data = (unsigned long) dev;
496 np->timer.function = &rio_timer;
497 add_timer (&np->timer);
498
499 /* Start Tx/Rx */
500 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
501 ioaddr + MACCtrl);
502
503 macctrl = 0;
504 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
505 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
506 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
507 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
508 writew(macctrl, ioaddr + MACCtrl);
509
510 netif_start_queue (dev);
511
512 /* Enable default interrupts */
513 EnableInt ();
514 return 0;
515 }
516
517 static void
518 rio_timer (unsigned long data)
519 {
520 struct net_device *dev = (struct net_device *)data;
521 struct netdev_private *np = netdev_priv(dev);
522 unsigned int entry;
523 int next_tick = 1*HZ;
524 unsigned long flags;
525
526 spin_lock_irqsave(&np->rx_lock, flags);
527 /* Recover rx ring exhausted error */
528 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
529 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
530 /* Re-allocate skbuffs to fill the descriptor ring */
531 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
532 struct sk_buff *skb;
533 entry = np->old_rx % RX_RING_SIZE;
534 /* Dropped packets don't need to re-allocate */
535 if (np->rx_skbuff[entry] == NULL) {
536 skb = dev_alloc_skb (np->rx_buf_sz);
537 if (skb == NULL) {
538 np->rx_ring[entry].fraginfo = 0;
539 printk (KERN_INFO
540 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
541 dev->name, entry);
542 break;
543 }
544 np->rx_skbuff[entry] = skb;
545 skb->dev = dev;
546 /* 16 byte align the IP header */
547 skb_reserve (skb, 2);
548 np->rx_ring[entry].fraginfo =
549 cpu_to_le64 (pci_map_single
550 (np->pdev, skb->tail, np->rx_buf_sz,
551 PCI_DMA_FROMDEVICE));
552 }
553 np->rx_ring[entry].fraginfo |=
554 cpu_to_le64 (np->rx_buf_sz) << 48;
555 np->rx_ring[entry].status = 0;
556 } /* end for */
557 } /* end if */
558 spin_unlock_irqrestore (&np->rx_lock, flags);
559 np->timer.expires = jiffies + next_tick;
560 add_timer(&np->timer);
561 }
562
563 static void
564 rio_tx_timeout (struct net_device *dev)
565 {
566 long ioaddr = dev->base_addr;
567
568 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
569 dev->name, readl (ioaddr + TxStatus));
570 rio_free_tx(dev, 0);
571 dev->if_port = 0;
572 dev->trans_start = jiffies;
573 }
574
575 /* allocate and initialize Tx and Rx descriptors */
576 static void
577 alloc_list (struct net_device *dev)
578 {
579 struct netdev_private *np = netdev_priv(dev);
580 int i;
581
582 np->cur_rx = np->cur_tx = 0;
583 np->old_rx = np->old_tx = 0;
584 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
585
586 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
587 for (i = 0; i < TX_RING_SIZE; i++) {
588 np->tx_skbuff[i] = NULL;
589 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
590 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
591 ((i+1)%TX_RING_SIZE) *
592 sizeof (struct netdev_desc));
593 }
594
595 /* Initialize Rx descriptors */
596 for (i = 0; i < RX_RING_SIZE; i++) {
597 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
598 ((i + 1) % RX_RING_SIZE) *
599 sizeof (struct netdev_desc));
600 np->rx_ring[i].status = 0;
601 np->rx_ring[i].fraginfo = 0;
602 np->rx_skbuff[i] = NULL;
603 }
604
605 /* Allocate the rx buffers */
606 for (i = 0; i < RX_RING_SIZE; i++) {
607 /* Allocated fixed size of skbuff */
608 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
609 np->rx_skbuff[i] = skb;
610 if (skb == NULL) {
611 printk (KERN_ERR
612 "%s: alloc_list: allocate Rx buffer error! ",
613 dev->name);
614 break;
615 }
616 skb->dev = dev; /* Mark as being used by this device. */
617 skb_reserve (skb, 2); /* 16 byte align the IP header. */
618 /* Rubicon now supports 40 bits of addressing space. */
619 np->rx_ring[i].fraginfo =
620 cpu_to_le64 ( pci_map_single (
621 np->pdev, skb->tail, np->rx_buf_sz,
622 PCI_DMA_FROMDEVICE));
623 np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
624 }
625
626 /* Set RFDListPtr */
627 writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
628 writel (0, dev->base_addr + RFDListPtr1);
629
630 return;
631 }
632
633 static int
634 start_xmit (struct sk_buff *skb, struct net_device *dev)
635 {
636 struct netdev_private *np = netdev_priv(dev);
637 struct netdev_desc *txdesc;
638 unsigned entry;
639 u32 ioaddr;
640 u64 tfc_vlan_tag = 0;
641
642 if (np->link_status == 0) { /* Link Down */
643 dev_kfree_skb(skb);
644 return 0;
645 }
646 ioaddr = dev->base_addr;
647 entry = np->cur_tx % TX_RING_SIZE;
648 np->tx_skbuff[entry] = skb;
649 txdesc = &np->tx_ring[entry];
650
651 #if 0
652 if (skb->ip_summed == CHECKSUM_HW) {
653 txdesc->status |=
654 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
655 IPChecksumEnable);
656 }
657 #endif
658 if (np->vlan) {
659 tfc_vlan_tag =
660 cpu_to_le64 (VLANTagInsert) |
661 (cpu_to_le64 (np->vlan) << 32) |
662 (cpu_to_le64 (skb->priority) << 45);
663 }
664 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
665 skb->len,
666 PCI_DMA_TODEVICE));
667 txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
668
669 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
670 * Work around: Always use 1 descriptor in 10Mbps mode */
671 if (entry % np->tx_coalesce == 0 || np->speed == 10)
672 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
673 WordAlignDisable |
674 TxDMAIndicate |
675 (1 << FragCountShift));
676 else
677 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
678 WordAlignDisable |
679 (1 << FragCountShift));
680
681 /* TxDMAPollNow */
682 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
683 /* Schedule ISR */
684 writel(10000, ioaddr + CountDown);
685 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
686 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
687 < TX_QUEUE_LEN - 1 && np->speed != 10) {
688 /* do nothing */
689 } else if (!netif_queue_stopped(dev)) {
690 netif_stop_queue (dev);
691 }
692
693 /* The first TFDListPtr */
694 if (readl (dev->base_addr + TFDListPtr0) == 0) {
695 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
696 dev->base_addr + TFDListPtr0);
697 writel (0, dev->base_addr + TFDListPtr1);
698 }
699
700 /* NETDEV WATCHDOG timer */
701 dev->trans_start = jiffies;
702 return 0;
703 }
704
705 static irqreturn_t
706 rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
707 {
708 struct net_device *dev = dev_instance;
709 struct netdev_private *np;
710 unsigned int_status;
711 long ioaddr;
712 int cnt = max_intrloop;
713 int handled = 0;
714
715 ioaddr = dev->base_addr;
716 np = netdev_priv(dev);
717 while (1) {
718 int_status = readw (ioaddr + IntStatus);
719 writew (int_status, ioaddr + IntStatus);
720 int_status &= DEFAULT_INTR;
721 if (int_status == 0 || --cnt < 0)
722 break;
723 handled = 1;
724 /* Processing received packets */
725 if (int_status & RxDMAComplete)
726 receive_packet (dev);
727 /* TxDMAComplete interrupt */
728 if ((int_status & (TxDMAComplete|IntRequested))) {
729 int tx_status;
730 tx_status = readl (ioaddr + TxStatus);
731 if (tx_status & 0x01)
732 tx_error (dev, tx_status);
733 /* Free used tx skbuffs */
734 rio_free_tx (dev, 1);
735 }
736
737 /* Handle uncommon events */
738 if (int_status &
739 (HostError | LinkEvent | UpdateStats))
740 rio_error (dev, int_status);
741 }
742 if (np->cur_tx != np->old_tx)
743 writel (100, ioaddr + CountDown);
744 return IRQ_RETVAL(handled);
745 }
746
747 static void
748 rio_free_tx (struct net_device *dev, int irq)
749 {
750 struct netdev_private *np = netdev_priv(dev);
751 int entry = np->old_tx % TX_RING_SIZE;
752 int tx_use = 0;
753 unsigned long flag = 0;
754
755 if (irq)
756 spin_lock(&np->tx_lock);
757 else
758 spin_lock_irqsave(&np->tx_lock, flag);
759
760 /* Free used tx skbuffs */
761 while (entry != np->cur_tx) {
762 struct sk_buff *skb;
763
764 if (!(np->tx_ring[entry].status & TFDDone))
765 break;
766 skb = np->tx_skbuff[entry];
767 pci_unmap_single (np->pdev,
768 np->tx_ring[entry].fraginfo,
769 skb->len, PCI_DMA_TODEVICE);
770 if (irq)
771 dev_kfree_skb_irq (skb);
772 else
773 dev_kfree_skb (skb);
774
775 np->tx_skbuff[entry] = NULL;
776 entry = (entry + 1) % TX_RING_SIZE;
777 tx_use++;
778 }
779 if (irq)
780 spin_unlock(&np->tx_lock);
781 else
782 spin_unlock_irqrestore(&np->tx_lock, flag);
783 np->old_tx = entry;
784
785 /* If the ring is no longer full, clear tx_full and
786 call netif_wake_queue() */
787
788 if (netif_queue_stopped(dev) &&
789 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
790 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
791 netif_wake_queue (dev);
792 }
793 }
794
795 static void
796 tx_error (struct net_device *dev, int tx_status)
797 {
798 struct netdev_private *np;
799 long ioaddr = dev->base_addr;
800 int frame_id;
801 int i;
802
803 np = netdev_priv(dev);
804
805 frame_id = (tx_status & 0xffff0000);
806 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
807 dev->name, tx_status, frame_id);
808 np->stats.tx_errors++;
809 /* Ttransmit Underrun */
810 if (tx_status & 0x10) {
811 np->stats.tx_fifo_errors++;
812 writew (readw (ioaddr + TxStartThresh) + 0x10,
813 ioaddr + TxStartThresh);
814 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
815 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
816 ioaddr + ASICCtrl + 2);
817 /* Wait for ResetBusy bit clear */
818 for (i = 50; i > 0; i--) {
819 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
820 break;
821 mdelay (1);
822 }
823 rio_free_tx (dev, 1);
824 /* Reset TFDListPtr */
825 writel (np->tx_ring_dma +
826 np->old_tx * sizeof (struct netdev_desc),
827 dev->base_addr + TFDListPtr0);
828 writel (0, dev->base_addr + TFDListPtr1);
829
830 /* Let TxStartThresh stay default value */
831 }
832 /* Late Collision */
833 if (tx_status & 0x04) {
834 np->stats.tx_fifo_errors++;
835 /* TxReset and clear FIFO */
836 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
837 /* Wait reset done */
838 for (i = 50; i > 0; i--) {
839 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
840 break;
841 mdelay (1);
842 }
843 /* Let TxStartThresh stay default value */
844 }
845 /* Maximum Collisions */
846 #ifdef ETHER_STATS
847 if (tx_status & 0x08)
848 np->stats.collisions16++;
849 #else
850 if (tx_status & 0x08)
851 np->stats.collisions++;
852 #endif
853 /* Restart the Tx */
854 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
855 }
856
857 static int
858 receive_packet (struct net_device *dev)
859 {
860 struct netdev_private *np = netdev_priv(dev);
861 int entry = np->cur_rx % RX_RING_SIZE;
862 int cnt = 30;
863
864 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
865 while (1) {
866 struct netdev_desc *desc = &np->rx_ring[entry];
867 int pkt_len;
868 u64 frame_status;
869
870 if (!(desc->status & RFDDone) ||
871 !(desc->status & FrameStart) || !(desc->status & FrameEnd))
872 break;
873
874 /* Chip omits the CRC. */
875 pkt_len = le64_to_cpu (desc->status & 0xffff);
876 frame_status = le64_to_cpu (desc->status);
877 if (--cnt < 0)
878 break;
879 /* Update rx error statistics, drop packet. */
880 if (frame_status & RFS_Errors) {
881 np->stats.rx_errors++;
882 if (frame_status & (RxRuntFrame | RxLengthError))
883 np->stats.rx_length_errors++;
884 if (frame_status & RxFCSError)
885 np->stats.rx_crc_errors++;
886 if (frame_status & RxAlignmentError && np->speed != 1000)
887 np->stats.rx_frame_errors++;
888 if (frame_status & RxFIFOOverrun)
889 np->stats.rx_fifo_errors++;
890 } else {
891 struct sk_buff *skb;
892
893 /* Small skbuffs for short packets */
894 if (pkt_len > copy_thresh) {
895 pci_unmap_single (np->pdev, desc->fraginfo,
896 np->rx_buf_sz,
897 PCI_DMA_FROMDEVICE);
898 skb_put (skb = np->rx_skbuff[entry], pkt_len);
899 np->rx_skbuff[entry] = NULL;
900 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
901 pci_dma_sync_single_for_cpu(np->pdev,
902 desc->fraginfo,
903 np->rx_buf_sz,
904 PCI_DMA_FROMDEVICE);
905 skb->dev = dev;
906 /* 16 byte align the IP header */
907 skb_reserve (skb, 2);
908 eth_copy_and_sum (skb,
909 np->rx_skbuff[entry]->tail,
910 pkt_len, 0);
911 skb_put (skb, pkt_len);
912 pci_dma_sync_single_for_device(np->pdev,
913 desc->fraginfo,
914 np->rx_buf_sz,
915 PCI_DMA_FROMDEVICE);
916 }
917 skb->protocol = eth_type_trans (skb, dev);
918 #if 0
919 /* Checksum done by hw, but csum value unavailable. */
920 if (np->pci_rev_id >= 0x0c &&
921 !(frame_status & (TCPError | UDPError | IPError))) {
922 skb->ip_summed = CHECKSUM_UNNECESSARY;
923 }
924 #endif
925 netif_rx (skb);
926 dev->last_rx = jiffies;
927 }
928 entry = (entry + 1) % RX_RING_SIZE;
929 }
930 spin_lock(&np->rx_lock);
931 np->cur_rx = entry;
932 /* Re-allocate skbuffs to fill the descriptor ring */
933 entry = np->old_rx;
934 while (entry != np->cur_rx) {
935 struct sk_buff *skb;
936 /* Dropped packets don't need to re-allocate */
937 if (np->rx_skbuff[entry] == NULL) {
938 skb = dev_alloc_skb (np->rx_buf_sz);
939 if (skb == NULL) {
940 np->rx_ring[entry].fraginfo = 0;
941 printk (KERN_INFO
942 "%s: receive_packet: "
943 "Unable to re-allocate Rx skbuff.#%d\n",
944 dev->name, entry);
945 break;
946 }
947 np->rx_skbuff[entry] = skb;
948 skb->dev = dev;
949 /* 16 byte align the IP header */
950 skb_reserve (skb, 2);
951 np->rx_ring[entry].fraginfo =
952 cpu_to_le64 (pci_map_single
953 (np->pdev, skb->tail, np->rx_buf_sz,
954 PCI_DMA_FROMDEVICE));
955 }
956 np->rx_ring[entry].fraginfo |=
957 cpu_to_le64 (np->rx_buf_sz) << 48;
958 np->rx_ring[entry].status = 0;
959 entry = (entry + 1) % RX_RING_SIZE;
960 }
961 np->old_rx = entry;
962 spin_unlock(&np->rx_lock);
963 return 0;
964 }
965
966 static void
967 rio_error (struct net_device *dev, int int_status)
968 {
969 long ioaddr = dev->base_addr;
970 struct netdev_private *np = netdev_priv(dev);
971 u16 macctrl;
972
973 /* Link change event */
974 if (int_status & LinkEvent) {
975 if (mii_wait_link (dev, 10) == 0) {
976 printk (KERN_INFO "%s: Link up\n", dev->name);
977 if (np->phy_media)
978 mii_get_media_pcs (dev);
979 else
980 mii_get_media (dev);
981 if (np->speed == 1000)
982 np->tx_coalesce = tx_coalesce;
983 else
984 np->tx_coalesce = 1;
985 macctrl = 0;
986 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
987 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
988 macctrl |= (np->tx_flow) ?
989 TxFlowControlEnable : 0;
990 macctrl |= (np->rx_flow) ?
991 RxFlowControlEnable : 0;
992 writew(macctrl, ioaddr + MACCtrl);
993 np->link_status = 1;
994 netif_carrier_on(dev);
995 } else {
996 printk (KERN_INFO "%s: Link off\n", dev->name);
997 np->link_status = 0;
998 netif_carrier_off(dev);
999 }
1000 }
1001
1002 /* UpdateStats statistics registers */
1003 if (int_status & UpdateStats) {
1004 get_stats (dev);
1005 }
1006
1007 /* PCI Error, a catastronphic error related to the bus interface
1008 occurs, set GlobalReset and HostReset to reset. */
1009 if (int_status & HostError) {
1010 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1011 dev->name, int_status);
1012 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
1013 mdelay (500);
1014 }
1015 }
1016
1017 static struct net_device_stats *
1018 get_stats (struct net_device *dev)
1019 {
1020 long ioaddr = dev->base_addr;
1021 struct netdev_private *np = netdev_priv(dev);
1022 #ifdef MEM_MAPPING
1023 int i;
1024 #endif
1025 unsigned int stat_reg;
1026
1027 /* All statistics registers need to be acknowledged,
1028 else statistic overflow could cause problems */
1029
1030 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1031 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1032 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1033 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1034
1035 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1036 np->stats.collisions += readl (ioaddr + SingleColFrames)
1037 + readl (ioaddr + MultiColFrames);
1038
1039 /* detailed tx errors */
1040 stat_reg = readw (ioaddr + FramesAbortXSColls);
1041 np->stats.tx_aborted_errors += stat_reg;
1042 np->stats.tx_errors += stat_reg;
1043
1044 stat_reg = readw (ioaddr + CarrierSenseErrors);
1045 np->stats.tx_carrier_errors += stat_reg;
1046 np->stats.tx_errors += stat_reg;
1047
1048 /* Clear all other statistic register. */
1049 readl (ioaddr + McstOctetXmtOk);
1050 readw (ioaddr + BcstFramesXmtdOk);
1051 readl (ioaddr + McstFramesXmtdOk);
1052 readw (ioaddr + BcstFramesRcvdOk);
1053 readw (ioaddr + MacControlFramesRcvd);
1054 readw (ioaddr + FrameTooLongErrors);
1055 readw (ioaddr + InRangeLengthErrors);
1056 readw (ioaddr + FramesCheckSeqErrors);
1057 readw (ioaddr + FramesLostRxErrors);
1058 readl (ioaddr + McstOctetXmtOk);
1059 readl (ioaddr + BcstOctetXmtOk);
1060 readl (ioaddr + McstFramesXmtdOk);
1061 readl (ioaddr + FramesWDeferredXmt);
1062 readl (ioaddr + LateCollisions);
1063 readw (ioaddr + BcstFramesXmtdOk);
1064 readw (ioaddr + MacControlFramesXmtd);
1065 readw (ioaddr + FramesWEXDeferal);
1066
1067 #ifdef MEM_MAPPING
1068 for (i = 0x100; i <= 0x150; i += 4)
1069 readl (ioaddr + i);
1070 #endif
1071 readw (ioaddr + TxJumboFrames);
1072 readw (ioaddr + RxJumboFrames);
1073 readw (ioaddr + TCPCheckSumErrors);
1074 readw (ioaddr + UDPCheckSumErrors);
1075 readw (ioaddr + IPCheckSumErrors);
1076 return &np->stats;
1077 }
1078
1079 static int
1080 clear_stats (struct net_device *dev)
1081 {
1082 long ioaddr = dev->base_addr;
1083 #ifdef MEM_MAPPING
1084 int i;
1085 #endif
1086
1087 /* All statistics registers need to be acknowledged,
1088 else statistic overflow could cause problems */
1089 readl (ioaddr + FramesRcvOk);
1090 readl (ioaddr + FramesXmtOk);
1091 readl (ioaddr + OctetRcvOk);
1092 readl (ioaddr + OctetXmtOk);
1093
1094 readl (ioaddr + McstFramesRcvdOk);
1095 readl (ioaddr + SingleColFrames);
1096 readl (ioaddr + MultiColFrames);
1097 readl (ioaddr + LateCollisions);
1098 /* detailed rx errors */
1099 readw (ioaddr + FrameTooLongErrors);
1100 readw (ioaddr + InRangeLengthErrors);
1101 readw (ioaddr + FramesCheckSeqErrors);
1102 readw (ioaddr + FramesLostRxErrors);
1103
1104 /* detailed tx errors */
1105 readw (ioaddr + FramesAbortXSColls);
1106 readw (ioaddr + CarrierSenseErrors);
1107
1108 /* Clear all other statistic register. */
1109 readl (ioaddr + McstOctetXmtOk);
1110 readw (ioaddr + BcstFramesXmtdOk);
1111 readl (ioaddr + McstFramesXmtdOk);
1112 readw (ioaddr + BcstFramesRcvdOk);
1113 readw (ioaddr + MacControlFramesRcvd);
1114 readl (ioaddr + McstOctetXmtOk);
1115 readl (ioaddr + BcstOctetXmtOk);
1116 readl (ioaddr + McstFramesXmtdOk);
1117 readl (ioaddr + FramesWDeferredXmt);
1118 readw (ioaddr + BcstFramesXmtdOk);
1119 readw (ioaddr + MacControlFramesXmtd);
1120 readw (ioaddr + FramesWEXDeferal);
1121 #ifdef MEM_MAPPING
1122 for (i = 0x100; i <= 0x150; i += 4)
1123 readl (ioaddr + i);
1124 #endif
1125 readw (ioaddr + TxJumboFrames);
1126 readw (ioaddr + RxJumboFrames);
1127 readw (ioaddr + TCPCheckSumErrors);
1128 readw (ioaddr + UDPCheckSumErrors);
1129 readw (ioaddr + IPCheckSumErrors);
1130 return 0;
1131 }
1132
1133
1134 int
1135 change_mtu (struct net_device *dev, int new_mtu)
1136 {
1137 struct netdev_private *np = netdev_priv(dev);
1138 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1139
1140 if ((new_mtu < 68) || (new_mtu > max)) {
1141 return -EINVAL;
1142 }
1143
1144 dev->mtu = new_mtu;
1145
1146 return 0;
1147 }
1148
1149 static void
1150 set_multicast (struct net_device *dev)
1151 {
1152 long ioaddr = dev->base_addr;
1153 u32 hash_table[2];
1154 u16 rx_mode = 0;
1155 struct netdev_private *np = netdev_priv(dev);
1156
1157 hash_table[0] = hash_table[1] = 0;
1158 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1159 hash_table[1] |= cpu_to_le32(0x02000000);
1160 if (dev->flags & IFF_PROMISC) {
1161 /* Receive all frames promiscuously. */
1162 rx_mode = ReceiveAllFrames;
1163 } else if ((dev->flags & IFF_ALLMULTI) ||
1164 (dev->mc_count > multicast_filter_limit)) {
1165 /* Receive broadcast and multicast frames */
1166 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1167 } else if (dev->mc_count > 0) {
1168 int i;
1169 struct dev_mc_list *mclist;
1170 /* Receive broadcast frames and multicast frames filtering
1171 by Hashtable */
1172 rx_mode =
1173 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1174 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1175 i++, mclist=mclist->next)
1176 {
1177 int bit, index = 0;
1178 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1179 /* The inverted high significant 6 bits of CRC are
1180 used as an index to hashtable */
1181 for (bit = 0; bit < 6; bit++)
1182 if (crc & (1 << (31 - bit)))
1183 index |= (1 << bit);
1184 hash_table[index / 32] |= (1 << (index % 32));
1185 }
1186 } else {
1187 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1188 }
1189 if (np->vlan) {
1190 /* ReceiveVLANMatch field in ReceiveMode */
1191 rx_mode |= ReceiveVLANMatch;
1192 }
1193
1194 writel (hash_table[0], ioaddr + HashTable0);
1195 writel (hash_table[1], ioaddr + HashTable1);
1196 writew (rx_mode, ioaddr + ReceiveMode);
1197 }
1198
1199 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1200 {
1201 struct netdev_private *np = netdev_priv(dev);
1202 strcpy(info->driver, "dl2k");
1203 strcpy(info->version, DRV_VERSION);
1204 strcpy(info->bus_info, pci_name(np->pdev));
1205 }
1206
1207 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1208 {
1209 struct netdev_private *np = netdev_priv(dev);
1210 if (np->phy_media) {
1211 /* fiber device */
1212 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1213 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1214 cmd->port = PORT_FIBRE;
1215 cmd->transceiver = XCVR_INTERNAL;
1216 } else {
1217 /* copper device */
1218 cmd->supported = SUPPORTED_10baseT_Half |
1219 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1220 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1221 SUPPORTED_Autoneg | SUPPORTED_MII;
1222 cmd->advertising = ADVERTISED_10baseT_Half |
1223 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1224 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1225 ADVERTISED_Autoneg | ADVERTISED_MII;
1226 cmd->port = PORT_MII;
1227 cmd->transceiver = XCVR_INTERNAL;
1228 }
1229 if ( np->link_status ) {
1230 cmd->speed = np->speed;
1231 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1232 } else {
1233 cmd->speed = -1;
1234 cmd->duplex = -1;
1235 }
1236 if ( np->an_enable)
1237 cmd->autoneg = AUTONEG_ENABLE;
1238 else
1239 cmd->autoneg = AUTONEG_DISABLE;
1240
1241 cmd->phy_address = np->phy_addr;
1242 return 0;
1243 }
1244
1245 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1246 {
1247 struct netdev_private *np = netdev_priv(dev);
1248 netif_carrier_off(dev);
1249 if (cmd->autoneg == AUTONEG_ENABLE) {
1250 if (np->an_enable)
1251 return 0;
1252 else {
1253 np->an_enable = 1;
1254 mii_set_media(dev);
1255 return 0;
1256 }
1257 } else {
1258 np->an_enable = 0;
1259 if (np->speed == 1000) {
1260 cmd->speed = SPEED_100;
1261 cmd->duplex = DUPLEX_FULL;
1262 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1263 }
1264 switch(cmd->speed + cmd->duplex) {
1265
1266 case SPEED_10 + DUPLEX_HALF:
1267 np->speed = 10;
1268 np->full_duplex = 0;
1269 break;
1270
1271 case SPEED_10 + DUPLEX_FULL:
1272 np->speed = 10;
1273 np->full_duplex = 1;
1274 break;
1275 case SPEED_100 + DUPLEX_HALF:
1276 np->speed = 100;
1277 np->full_duplex = 0;
1278 break;
1279 case SPEED_100 + DUPLEX_FULL:
1280 np->speed = 100;
1281 np->full_duplex = 1;
1282 break;
1283 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1284 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1285 default:
1286 return -EINVAL;
1287 }
1288 mii_set_media(dev);
1289 }
1290 return 0;
1291 }
1292
1293 static u32 rio_get_link(struct net_device *dev)
1294 {
1295 struct netdev_private *np = netdev_priv(dev);
1296 return np->link_status;
1297 }
1298
1299 static struct ethtool_ops ethtool_ops = {
1300 .get_drvinfo = rio_get_drvinfo,
1301 .get_settings = rio_get_settings,
1302 .set_settings = rio_set_settings,
1303 .get_link = rio_get_link,
1304 };
1305
1306 static int
1307 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1308 {
1309 int phy_addr;
1310 struct netdev_private *np = netdev_priv(dev);
1311 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1312
1313 struct netdev_desc *desc;
1314 int i;
1315
1316 phy_addr = np->phy_addr;
1317 switch (cmd) {
1318 case SIOCDEVPRIVATE:
1319 break;
1320
1321 case SIOCDEVPRIVATE + 1:
1322 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1323 break;
1324 case SIOCDEVPRIVATE + 2:
1325 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1326 break;
1327 case SIOCDEVPRIVATE + 3:
1328 break;
1329 case SIOCDEVPRIVATE + 4:
1330 break;
1331 case SIOCDEVPRIVATE + 5:
1332 netif_stop_queue (dev);
1333 break;
1334 case SIOCDEVPRIVATE + 6:
1335 netif_wake_queue (dev);
1336 break;
1337 case SIOCDEVPRIVATE + 7:
1338 printk
1339 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1340 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1341 np->old_rx);
1342 break;
1343 case SIOCDEVPRIVATE + 8:
1344 printk("TX ring:\n");
1345 for (i = 0; i < TX_RING_SIZE; i++) {
1346 desc = &np->tx_ring[i];
1347 printk
1348 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1349 i,
1350 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1351 (u32) desc->next_desc,
1352 (u32) desc->status, (u32) (desc->fraginfo >> 32),
1353 (u32) desc->fraginfo);
1354 printk ("\n");
1355 }
1356 printk ("\n");
1357 break;
1358
1359 default:
1360 return -EOPNOTSUPP;
1361 }
1362 return 0;
1363 }
1364
1365 #define EEP_READ 0x0200
1366 #define EEP_BUSY 0x8000
1367 /* Read the EEPROM word */
1368 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1369 int
1370 read_eeprom (long ioaddr, int eep_addr)
1371 {
1372 int i = 1000;
1373 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1374 while (i-- > 0) {
1375 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1376 return inw (ioaddr + EepromData);
1377 }
1378 }
1379 return 0;
1380 }
1381
1382 enum phy_ctrl_bits {
1383 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1384 MII_DUPLEX = 0x08,
1385 };
1386
1387 #define mii_delay() readb(ioaddr)
1388 static void
1389 mii_sendbit (struct net_device *dev, u32 data)
1390 {
1391 long ioaddr = dev->base_addr + PhyCtrl;
1392 data = (data) ? MII_DATA1 : 0;
1393 data |= MII_WRITE;
1394 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1395 writeb (data, ioaddr);
1396 mii_delay ();
1397 writeb (data | MII_CLK, ioaddr);
1398 mii_delay ();
1399 }
1400
1401 static int
1402 mii_getbit (struct net_device *dev)
1403 {
1404 long ioaddr = dev->base_addr + PhyCtrl;
1405 u8 data;
1406
1407 data = (readb (ioaddr) & 0xf8) | MII_READ;
1408 writeb (data, ioaddr);
1409 mii_delay ();
1410 writeb (data | MII_CLK, ioaddr);
1411 mii_delay ();
1412 return ((readb (ioaddr) >> 1) & 1);
1413 }
1414
1415 static void
1416 mii_send_bits (struct net_device *dev, u32 data, int len)
1417 {
1418 int i;
1419 for (i = len - 1; i >= 0; i--) {
1420 mii_sendbit (dev, data & (1 << i));
1421 }
1422 }
1423
1424 static int
1425 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1426 {
1427 u32 cmd;
1428 int i;
1429 u32 retval = 0;
1430
1431 /* Preamble */
1432 mii_send_bits (dev, 0xffffffff, 32);
1433 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1434 /* ST,OP = 0110'b for read operation */
1435 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1436 mii_send_bits (dev, cmd, 14);
1437 /* Turnaround */
1438 if (mii_getbit (dev))
1439 goto err_out;
1440 /* Read data */
1441 for (i = 0; i < 16; i++) {
1442 retval |= mii_getbit (dev);
1443 retval <<= 1;
1444 }
1445 /* End cycle */
1446 mii_getbit (dev);
1447 return (retval >> 1) & 0xffff;
1448
1449 err_out:
1450 return 0;
1451 }
1452 static int
1453 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1454 {
1455 u32 cmd;
1456
1457 /* Preamble */
1458 mii_send_bits (dev, 0xffffffff, 32);
1459 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1460 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1461 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1462 mii_send_bits (dev, cmd, 32);
1463 /* End cycle */
1464 mii_getbit (dev);
1465 return 0;
1466 }
1467 static int
1468 mii_wait_link (struct net_device *dev, int wait)
1469 {
1470 BMSR_t bmsr;
1471 int phy_addr;
1472 struct netdev_private *np;
1473
1474 np = netdev_priv(dev);
1475 phy_addr = np->phy_addr;
1476
1477 do {
1478 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1479 if (bmsr.bits.link_status)
1480 return 0;
1481 mdelay (1);
1482 } while (--wait > 0);
1483 return -1;
1484 }
1485 static int
1486 mii_get_media (struct net_device *dev)
1487 {
1488 ANAR_t negotiate;
1489 BMSR_t bmsr;
1490 BMCR_t bmcr;
1491 MSCR_t mscr;
1492 MSSR_t mssr;
1493 int phy_addr;
1494 struct netdev_private *np;
1495
1496 np = netdev_priv(dev);
1497 phy_addr = np->phy_addr;
1498
1499 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1500 if (np->an_enable) {
1501 if (!bmsr.bits.an_complete) {
1502 /* Auto-Negotiation not completed */
1503 return -1;
1504 }
1505 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
1506 mii_read (dev, phy_addr, MII_ANLPAR);
1507 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1508 mssr.image = mii_read (dev, phy_addr, MII_MSSR);
1509 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
1510 np->speed = 1000;
1511 np->full_duplex = 1;
1512 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1513 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
1514 np->speed = 1000;
1515 np->full_duplex = 0;
1516 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1517 } else if (negotiate.bits.media_100BX_FD) {
1518 np->speed = 100;
1519 np->full_duplex = 1;
1520 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1521 } else if (negotiate.bits.media_100BX_HD) {
1522 np->speed = 100;
1523 np->full_duplex = 0;
1524 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1525 } else if (negotiate.bits.media_10BT_FD) {
1526 np->speed = 10;
1527 np->full_duplex = 1;
1528 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1529 } else if (negotiate.bits.media_10BT_HD) {
1530 np->speed = 10;
1531 np->full_duplex = 0;
1532 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1533 }
1534 if (negotiate.bits.pause) {
1535 np->tx_flow &= 1;
1536 np->rx_flow &= 1;
1537 } else if (negotiate.bits.asymmetric) {
1538 np->tx_flow = 0;
1539 np->rx_flow &= 1;
1540 }
1541 /* else tx_flow, rx_flow = user select */
1542 } else {
1543 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1544 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
1545 printk (KERN_INFO "Operating at 100 Mbps, ");
1546 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
1547 printk (KERN_INFO "Operating at 10 Mbps, ");
1548 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1549 printk (KERN_INFO "Operating at 1000 Mbps, ");
1550 }
1551 if (bmcr.bits.duplex_mode) {
1552 printk ("Full duplex\n");
1553 } else {
1554 printk ("Half duplex\n");
1555 }
1556 }
1557 if (np->tx_flow)
1558 printk(KERN_INFO "Enable Tx Flow Control\n");
1559 else
1560 printk(KERN_INFO "Disable Tx Flow Control\n");
1561 if (np->rx_flow)
1562 printk(KERN_INFO "Enable Rx Flow Control\n");
1563 else
1564 printk(KERN_INFO "Disable Rx Flow Control\n");
1565
1566 return 0;
1567 }
1568
1569 static int
1570 mii_set_media (struct net_device *dev)
1571 {
1572 PHY_SCR_t pscr;
1573 BMCR_t bmcr;
1574 BMSR_t bmsr;
1575 ANAR_t anar;
1576 int phy_addr;
1577 struct netdev_private *np;
1578 np = netdev_priv(dev);
1579 phy_addr = np->phy_addr;
1580
1581 /* Does user set speed? */
1582 if (np->an_enable) {
1583 /* Advertise capabilities */
1584 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1585 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1586 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
1587 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
1588 anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
1589 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
1590 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
1591 anar.bits.pause = 1;
1592 anar.bits.asymmetric = 1;
1593 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1594
1595 /* Enable Auto crossover */
1596 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1597 pscr.bits.mdi_crossover_mode = 3; /* 11'b */
1598 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1599
1600 /* Soft reset PHY */
1601 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1602 bmcr.image = 0;
1603 bmcr.bits.an_enable = 1;
1604 bmcr.bits.restart_an = 1;
1605 bmcr.bits.reset = 1;
1606 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1607 mdelay(1);
1608 } else {
1609 /* Force speed setting */
1610 /* 1) Disable Auto crossover */
1611 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1612 pscr.bits.mdi_crossover_mode = 0;
1613 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1614
1615 /* 2) PHY Reset */
1616 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1617 bmcr.bits.reset = 1;
1618 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1619
1620 /* 3) Power Down */
1621 bmcr.image = 0x1940; /* must be 0x1940 */
1622 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1623 mdelay (100); /* wait a certain time */
1624
1625 /* 4) Advertise nothing */
1626 mii_write (dev, phy_addr, MII_ANAR, 0);
1627
1628 /* 5) Set media and Power Up */
1629 bmcr.image = 0;
1630 bmcr.bits.power_down = 1;
1631 if (np->speed == 100) {
1632 bmcr.bits.speed100 = 1;
1633 bmcr.bits.speed1000 = 0;
1634 printk (KERN_INFO "Manual 100 Mbps, ");
1635 } else if (np->speed == 10) {
1636 bmcr.bits.speed100 = 0;
1637 bmcr.bits.speed1000 = 0;
1638 printk (KERN_INFO "Manual 10 Mbps, ");
1639 }
1640 if (np->full_duplex) {
1641 bmcr.bits.duplex_mode = 1;
1642 printk ("Full duplex\n");
1643 } else {
1644 bmcr.bits.duplex_mode = 0;
1645 printk ("Half duplex\n");
1646 }
1647 #if 0
1648 /* Set 1000BaseT Master/Slave setting */
1649 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1650 mscr.bits.cfg_enable = 1;
1651 mscr.bits.cfg_value = 0;
1652 #endif
1653 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1654 mdelay(10);
1655 }
1656 return 0;
1657 }
1658
1659 static int
1660 mii_get_media_pcs (struct net_device *dev)
1661 {
1662 ANAR_PCS_t negotiate;
1663 BMSR_t bmsr;
1664 BMCR_t bmcr;
1665 int phy_addr;
1666 struct netdev_private *np;
1667
1668 np = netdev_priv(dev);
1669 phy_addr = np->phy_addr;
1670
1671 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
1672 if (np->an_enable) {
1673 if (!bmsr.bits.an_complete) {
1674 /* Auto-Negotiation not completed */
1675 return -1;
1676 }
1677 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
1678 mii_read (dev, phy_addr, PCS_ANLPAR);
1679 np->speed = 1000;
1680 if (negotiate.bits.full_duplex) {
1681 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1682 np->full_duplex = 1;
1683 } else {
1684 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1685 np->full_duplex = 0;
1686 }
1687 if (negotiate.bits.pause) {
1688 np->tx_flow &= 1;
1689 np->rx_flow &= 1;
1690 } else if (negotiate.bits.asymmetric) {
1691 np->tx_flow = 0;
1692 np->rx_flow &= 1;
1693 }
1694 /* else tx_flow, rx_flow = user select */
1695 } else {
1696 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
1697 printk (KERN_INFO "Operating at 1000 Mbps, ");
1698 if (bmcr.bits.duplex_mode) {
1699 printk ("Full duplex\n");
1700 } else {
1701 printk ("Half duplex\n");
1702 }
1703 }
1704 if (np->tx_flow)
1705 printk(KERN_INFO "Enable Tx Flow Control\n");
1706 else
1707 printk(KERN_INFO "Disable Tx Flow Control\n");
1708 if (np->rx_flow)
1709 printk(KERN_INFO "Enable Rx Flow Control\n");
1710 else
1711 printk(KERN_INFO "Disable Rx Flow Control\n");
1712
1713 return 0;
1714 }
1715
1716 static int
1717 mii_set_media_pcs (struct net_device *dev)
1718 {
1719 BMCR_t bmcr;
1720 ESR_t esr;
1721 ANAR_PCS_t anar;
1722 int phy_addr;
1723 struct netdev_private *np;
1724 np = netdev_priv(dev);
1725 phy_addr = np->phy_addr;
1726
1727 /* Auto-Negotiation? */
1728 if (np->an_enable) {
1729 /* Advertise capabilities */
1730 esr.image = mii_read (dev, phy_addr, PCS_ESR);
1731 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1732 anar.bits.half_duplex =
1733 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
1734 anar.bits.full_duplex =
1735 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
1736 anar.bits.pause = 1;
1737 anar.bits.asymmetric = 1;
1738 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1739
1740 /* Soft reset PHY */
1741 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1742 bmcr.image = 0;
1743 bmcr.bits.an_enable = 1;
1744 bmcr.bits.restart_an = 1;
1745 bmcr.bits.reset = 1;
1746 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1747 mdelay(1);
1748 } else {
1749 /* Force speed setting */
1750 /* PHY Reset */
1751 bmcr.image = 0;
1752 bmcr.bits.reset = 1;
1753 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1754 mdelay(10);
1755 bmcr.image = 0;
1756 bmcr.bits.an_enable = 0;
1757 if (np->full_duplex) {
1758 bmcr.bits.duplex_mode = 1;
1759 printk (KERN_INFO "Manual full duplex\n");
1760 } else {
1761 bmcr.bits.duplex_mode = 0;
1762 printk (KERN_INFO "Manual half duplex\n");
1763 }
1764 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1765 mdelay(10);
1766
1767 /* Advertise nothing */
1768 mii_write (dev, phy_addr, MII_ANAR, 0);
1769 }
1770 return 0;
1771 }
1772
1773
1774 static int
1775 rio_close (struct net_device *dev)
1776 {
1777 long ioaddr = dev->base_addr;
1778 struct netdev_private *np = netdev_priv(dev);
1779 struct sk_buff *skb;
1780 int i;
1781
1782 netif_stop_queue (dev);
1783
1784 /* Disable interrupts */
1785 writew (0, ioaddr + IntEnable);
1786
1787 /* Stop Tx and Rx logics */
1788 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1789 synchronize_irq (dev->irq);
1790 free_irq (dev->irq, dev);
1791 del_timer_sync (&np->timer);
1792
1793 /* Free all the skbuffs in the queue. */
1794 for (i = 0; i < RX_RING_SIZE; i++) {
1795 np->rx_ring[i].status = 0;
1796 np->rx_ring[i].fraginfo = 0;
1797 skb = np->rx_skbuff[i];
1798 if (skb) {
1799 pci_unmap_single (np->pdev, np->rx_ring[i].fraginfo,
1800 skb->len, PCI_DMA_FROMDEVICE);
1801 dev_kfree_skb (skb);
1802 np->rx_skbuff[i] = NULL;
1803 }
1804 }
1805 for (i = 0; i < TX_RING_SIZE; i++) {
1806 skb = np->tx_skbuff[i];
1807 if (skb) {
1808 pci_unmap_single (np->pdev, np->tx_ring[i].fraginfo,
1809 skb->len, PCI_DMA_TODEVICE);
1810 dev_kfree_skb (skb);
1811 np->tx_skbuff[i] = NULL;
1812 }
1813 }
1814
1815 return 0;
1816 }
1817
1818 static void __devexit
1819 rio_remove1 (struct pci_dev *pdev)
1820 {
1821 struct net_device *dev = pci_get_drvdata (pdev);
1822
1823 if (dev) {
1824 struct netdev_private *np = netdev_priv(dev);
1825
1826 unregister_netdev (dev);
1827 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1828 np->rx_ring_dma);
1829 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1830 np->tx_ring_dma);
1831 #ifdef MEM_MAPPING
1832 iounmap ((char *) (dev->base_addr));
1833 #endif
1834 free_netdev (dev);
1835 pci_release_regions (pdev);
1836 pci_disable_device (pdev);
1837 }
1838 pci_set_drvdata (pdev, NULL);
1839 }
1840
1841 static struct pci_driver rio_driver = {
1842 .name = "dl2k",
1843 .id_table = rio_pci_tbl,
1844 .probe = rio_probe1,
1845 .remove = __devexit_p(rio_remove1),
1846 };
1847
1848 static int __init
1849 rio_init (void)
1850 {
1851 return pci_module_init (&rio_driver);
1852 }
1853
1854 static void __exit
1855 rio_exit (void)
1856 {
1857 pci_unregister_driver (&rio_driver);
1858 }
1859
1860 module_init (rio_init);
1861 module_exit (rio_exit);
1862
1863 /*
1864
1865 Compile command:
1866
1867 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1868
1869 Read Documentation/networking/dl2k.txt for details.
1870
1871 */
1872
kernel source for telekom puls (alcatel/mediatek)