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bna: Brocade 10Gb Ethernet device driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bna / bna_txrx.c
1 /*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13 /*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18 #include "bna.h"
19 #include "bfa_sm.h"
20 #include "bfi.h"
21
22 /**
23 * IB
24 */
25 #define bna_ib_find_free_ibidx(_mask, _pos)\
26 do {\
27 (_pos) = 0;\
28 while (((_pos) < (BFI_IBIDX_MAX_SEGSIZE)) &&\
29 ((1 << (_pos)) & (_mask)))\
30 (_pos)++;\
31 } while (0)
32
33 #define bna_ib_count_ibidx(_mask, _count)\
34 do {\
35 int pos = 0;\
36 (_count) = 0;\
37 while (pos < (BFI_IBIDX_MAX_SEGSIZE)) {\
38 if ((1 << pos) & (_mask))\
39 (_count) = pos + 1;\
40 pos++;\
41 } \
42 } while (0)
43
44 #define bna_ib_select_segpool(_count, _q_idx)\
45 do {\
46 int i;\
47 (_q_idx) = -1;\
48 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {\
49 if ((_count <= ibidx_pool[i].pool_entry_size)) {\
50 (_q_idx) = i;\
51 break;\
52 } \
53 } \
54 } while (0)
55
56 struct bna_ibidx_pool {
57 int pool_size;
58 int pool_entry_size;
59 };
60 init_ibidx_pool(ibidx_pool);
61
62 static struct bna_intr *
63 bna_intr_get(struct bna_ib_mod *ib_mod, enum bna_intr_type intr_type,
64 int vector)
65 {
66 struct bna_intr *intr;
67 struct list_head *qe;
68
69 list_for_each(qe, &ib_mod->intr_active_q) {
70 intr = (struct bna_intr *)qe;
71
72 if ((intr->intr_type == intr_type) &&
73 (intr->vector == vector)) {
74 intr->ref_count++;
75 return intr;
76 }
77 }
78
79 if (list_empty(&ib_mod->intr_free_q))
80 return NULL;
81
82 bfa_q_deq(&ib_mod->intr_free_q, &intr);
83 bfa_q_qe_init(&intr->qe);
84
85 intr->ref_count = 1;
86 intr->intr_type = intr_type;
87 intr->vector = vector;
88
89 list_add_tail(&intr->qe, &ib_mod->intr_active_q);
90
91 return intr;
92 }
93
94 static void
95 bna_intr_put(struct bna_ib_mod *ib_mod,
96 struct bna_intr *intr)
97 {
98 intr->ref_count--;
99
100 if (intr->ref_count == 0) {
101 intr->ib = NULL;
102 list_del(&intr->qe);
103 bfa_q_qe_init(&intr->qe);
104 list_add_tail(&intr->qe, &ib_mod->intr_free_q);
105 }
106 }
107
108 void
109 bna_ib_mod_init(struct bna_ib_mod *ib_mod, struct bna *bna,
110 struct bna_res_info *res_info)
111 {
112 int i;
113 int j;
114 int count;
115 u8 offset;
116 struct bna_doorbell_qset *qset;
117 unsigned long off;
118
119 ib_mod->bna = bna;
120
121 ib_mod->ib = (struct bna_ib *)
122 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mdl[0].kva;
123 ib_mod->intr = (struct bna_intr *)
124 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mdl[0].kva;
125 ib_mod->idx_seg = (struct bna_ibidx_seg *)
126 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mdl[0].kva;
127
128 INIT_LIST_HEAD(&ib_mod->ib_free_q);
129 INIT_LIST_HEAD(&ib_mod->intr_free_q);
130 INIT_LIST_HEAD(&ib_mod->intr_active_q);
131
132 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++)
133 INIT_LIST_HEAD(&ib_mod->ibidx_seg_pool[i]);
134
135 for (i = 0; i < BFI_MAX_IB; i++) {
136 ib_mod->ib[i].ib_id = i;
137
138 ib_mod->ib[i].ib_seg_host_addr_kva =
139 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
140 ib_mod->ib[i].ib_seg_host_addr.lsb =
141 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
142 ib_mod->ib[i].ib_seg_host_addr.msb =
143 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
144
145 qset = (struct bna_doorbell_qset *)0;
146 off = (unsigned long)(&qset[i >> 1].ib0[(i & 0x1)
147 * (0x20 >> 2)]);
148 ib_mod->ib[i].door_bell.doorbell_addr = off +
149 BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
150
151 bfa_q_qe_init(&ib_mod->ib[i].qe);
152 list_add_tail(&ib_mod->ib[i].qe, &ib_mod->ib_free_q);
153
154 bfa_q_qe_init(&ib_mod->intr[i].qe);
155 list_add_tail(&ib_mod->intr[i].qe, &ib_mod->intr_free_q);
156 }
157
158 count = 0;
159 offset = 0;
160 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
161 for (j = 0; j < ibidx_pool[i].pool_size; j++) {
162 bfa_q_qe_init(&ib_mod->idx_seg[count]);
163 ib_mod->idx_seg[count].ib_seg_size =
164 ibidx_pool[i].pool_entry_size;
165 ib_mod->idx_seg[count].ib_idx_tbl_offset = offset;
166 list_add_tail(&ib_mod->idx_seg[count].qe,
167 &ib_mod->ibidx_seg_pool[i]);
168 count++;
169 offset += ibidx_pool[i].pool_entry_size;
170 }
171 }
172 }
173
174 void
175 bna_ib_mod_uninit(struct bna_ib_mod *ib_mod)
176 {
177 int i;
178 int j;
179 struct list_head *qe;
180
181 i = 0;
182 list_for_each(qe, &ib_mod->ib_free_q)
183 i++;
184
185 i = 0;
186 list_for_each(qe, &ib_mod->intr_free_q)
187 i++;
188
189 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
190 j = 0;
191 list_for_each(qe, &ib_mod->ibidx_seg_pool[i])
192 j++;
193 }
194
195 ib_mod->bna = NULL;
196 }
197
198 struct bna_ib *
199 bna_ib_get(struct bna_ib_mod *ib_mod,
200 enum bna_intr_type intr_type,
201 int vector)
202 {
203 struct bna_ib *ib;
204 struct bna_intr *intr;
205
206 if (intr_type == BNA_INTR_T_INTX)
207 vector = (1 << vector);
208
209 intr = bna_intr_get(ib_mod, intr_type, vector);
210 if (intr == NULL)
211 return NULL;
212
213 if (intr->ib) {
214 if (intr->ib->ref_count == BFI_IBIDX_MAX_SEGSIZE) {
215 bna_intr_put(ib_mod, intr);
216 return NULL;
217 }
218 intr->ib->ref_count++;
219 return intr->ib;
220 }
221
222 if (list_empty(&ib_mod->ib_free_q)) {
223 bna_intr_put(ib_mod, intr);
224 return NULL;
225 }
226
227 bfa_q_deq(&ib_mod->ib_free_q, &ib);
228 bfa_q_qe_init(&ib->qe);
229
230 ib->ref_count = 1;
231 ib->start_count = 0;
232 ib->idx_mask = 0;
233
234 ib->intr = intr;
235 ib->idx_seg = NULL;
236 intr->ib = ib;
237
238 ib->bna = ib_mod->bna;
239
240 return ib;
241 }
242
243 void
244 bna_ib_put(struct bna_ib_mod *ib_mod, struct bna_ib *ib)
245 {
246 bna_intr_put(ib_mod, ib->intr);
247
248 ib->ref_count--;
249
250 if (ib->ref_count == 0) {
251 ib->intr = NULL;
252 ib->bna = NULL;
253 list_add_tail(&ib->qe, &ib_mod->ib_free_q);
254 }
255 }
256
257 /* Returns index offset - starting from 0 */
258 int
259 bna_ib_reserve_idx(struct bna_ib *ib)
260 {
261 struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
262 struct bna_ibidx_seg *idx_seg;
263 int idx;
264 int num_idx;
265 int q_idx;
266
267 /* Find the first free index position */
268 bna_ib_find_free_ibidx(ib->idx_mask, idx);
269 if (idx == BFI_IBIDX_MAX_SEGSIZE)
270 return -1;
271
272 /*
273 * Calculate the total number of indexes held by this IB,
274 * including the index newly reserved above.
275 */
276 bna_ib_count_ibidx((ib->idx_mask | (1 << idx)), num_idx);
277
278 /* See if there is a free space in the index segment held by this IB */
279 if (ib->idx_seg && (num_idx <= ib->idx_seg->ib_seg_size)) {
280 ib->idx_mask |= (1 << idx);
281 return idx;
282 }
283
284 if (ib->start_count)
285 return -1;
286
287 /* Allocate a new segment */
288 bna_ib_select_segpool(num_idx, q_idx);
289 while (1) {
290 if (q_idx == BFI_IBIDX_TOTAL_POOLS)
291 return -1;
292 if (!list_empty(&ib_mod->ibidx_seg_pool[q_idx]))
293 break;
294 q_idx++;
295 }
296 bfa_q_deq(&ib_mod->ibidx_seg_pool[q_idx], &idx_seg);
297 bfa_q_qe_init(&idx_seg->qe);
298
299 /* Free the old segment */
300 if (ib->idx_seg) {
301 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, q_idx);
302 list_add_tail(&ib->idx_seg->qe, &ib_mod->ibidx_seg_pool[q_idx]);
303 }
304
305 ib->idx_seg = idx_seg;
306
307 ib->idx_mask |= (1 << idx);
308
309 return idx;
310 }
311
312 void
313 bna_ib_release_idx(struct bna_ib *ib, int idx)
314 {
315 struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
316 struct bna_ibidx_seg *idx_seg;
317 int num_idx;
318 int cur_q_idx;
319 int new_q_idx;
320
321 ib->idx_mask &= ~(1 << idx);
322
323 if (ib->start_count)
324 return;
325
326 bna_ib_count_ibidx(ib->idx_mask, num_idx);
327
328 /*
329 * Free the segment, if there are no more indexes in the segment
330 * held by this IB
331 */
332 if (!num_idx) {
333 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
334 list_add_tail(&ib->idx_seg->qe,
335 &ib_mod->ibidx_seg_pool[cur_q_idx]);
336 ib->idx_seg = NULL;
337 return;
338 }
339
340 /* See if we can move to a smaller segment */
341 bna_ib_select_segpool(num_idx, new_q_idx);
342 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
343 while (new_q_idx < cur_q_idx) {
344 if (!list_empty(&ib_mod->ibidx_seg_pool[new_q_idx]))
345 break;
346 new_q_idx++;
347 }
348 if (new_q_idx < cur_q_idx) {
349 /* Select the new smaller segment */
350 bfa_q_deq(&ib_mod->ibidx_seg_pool[new_q_idx], &idx_seg);
351 bfa_q_qe_init(&idx_seg->qe);
352 /* Free the old segment */
353 list_add_tail(&ib->idx_seg->qe,
354 &ib_mod->ibidx_seg_pool[cur_q_idx]);
355 ib->idx_seg = idx_seg;
356 }
357 }
358
359 int
360 bna_ib_config(struct bna_ib *ib, struct bna_ib_config *ib_config)
361 {
362 if (ib->start_count)
363 return -1;
364
365 ib->ib_config.coalescing_timeo = ib_config->coalescing_timeo;
366 ib->ib_config.interpkt_timeo = ib_config->interpkt_timeo;
367 ib->ib_config.interpkt_count = ib_config->interpkt_count;
368 ib->ib_config.ctrl_flags = ib_config->ctrl_flags;
369
370 ib->ib_config.ctrl_flags |= BFI_IB_CF_MASTER_ENABLE;
371 if (ib->intr->intr_type == BNA_INTR_T_MSIX)
372 ib->ib_config.ctrl_flags |= BFI_IB_CF_MSIX_MODE;
373
374 return 0;
375 }
376
377 void
378 bna_ib_start(struct bna_ib *ib)
379 {
380 struct bna_ib_blk_mem ib_cfg;
381 struct bna_ib_blk_mem *ib_mem;
382 u32 pg_num;
383 u32 intx_mask;
384 int i;
385 void __iomem *base_addr;
386 unsigned long off;
387
388 ib->start_count++;
389
390 if (ib->start_count > 1)
391 return;
392
393 ib_cfg.host_addr_lo = (u32)(ib->ib_seg_host_addr.lsb);
394 ib_cfg.host_addr_hi = (u32)(ib->ib_seg_host_addr.msb);
395
396 ib_cfg.clsc_n_ctrl_n_msix = (((u32)
397 ib->ib_config.coalescing_timeo << 16) |
398 ((u32)ib->ib_config.ctrl_flags << 8) |
399 (ib->intr->vector));
400 ib_cfg.ipkt_n_ent_n_idxof =
401 ((u32)
402 (ib->ib_config.interpkt_timeo & 0xf) << 16) |
403 ((u32)ib->idx_seg->ib_seg_size << 8) |
404 (ib->idx_seg->ib_idx_tbl_offset);
405 ib_cfg.ipkt_cnt_cfg_n_unacked = ((u32)
406 ib->ib_config.interpkt_count << 24);
407
408 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
409 HQM_IB_RAM_BASE_OFFSET);
410 writel(pg_num, ib->bna->regs.page_addr);
411
412 base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
413 HQM_IB_RAM_BASE_OFFSET);
414
415 ib_mem = (struct bna_ib_blk_mem *)0;
416 off = (unsigned long)&ib_mem[ib->ib_id].host_addr_lo;
417 writel(htonl(ib_cfg.host_addr_lo), base_addr + off);
418
419 off = (unsigned long)&ib_mem[ib->ib_id].host_addr_hi;
420 writel(htonl(ib_cfg.host_addr_hi), base_addr + off);
421
422 off = (unsigned long)&ib_mem[ib->ib_id].clsc_n_ctrl_n_msix;
423 writel(ib_cfg.clsc_n_ctrl_n_msix, base_addr + off);
424
425 off = (unsigned long)&ib_mem[ib->ib_id].ipkt_n_ent_n_idxof;
426 writel(ib_cfg.ipkt_n_ent_n_idxof, base_addr + off);
427
428 off = (unsigned long)&ib_mem[ib->ib_id].ipkt_cnt_cfg_n_unacked;
429 writel(ib_cfg.ipkt_cnt_cfg_n_unacked, base_addr + off);
430
431 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
432 (u32)ib->ib_config.coalescing_timeo, 0);
433
434 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
435 HQM_INDX_TBL_RAM_BASE_OFFSET);
436 writel(pg_num, ib->bna->regs.page_addr);
437
438 base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
439 HQM_INDX_TBL_RAM_BASE_OFFSET);
440 for (i = 0; i < ib->idx_seg->ib_seg_size; i++) {
441 off = (unsigned long)
442 ((ib->idx_seg->ib_idx_tbl_offset + i) * BFI_IBIDX_SIZE);
443 writel(0, base_addr + off);
444 }
445
446 if (ib->intr->intr_type == BNA_INTR_T_INTX) {
447 bna_intx_disable(ib->bna, intx_mask);
448 intx_mask &= ~(ib->intr->vector);
449 bna_intx_enable(ib->bna, intx_mask);
450 }
451 }
452
453 void
454 bna_ib_stop(struct bna_ib *ib)
455 {
456 u32 intx_mask;
457
458 ib->start_count--;
459
460 if (ib->start_count == 0) {
461 writel(BNA_DOORBELL_IB_INT_DISABLE,
462 ib->door_bell.doorbell_addr);
463 if (ib->intr->intr_type == BNA_INTR_T_INTX) {
464 bna_intx_disable(ib->bna, intx_mask);
465 intx_mask |= (ib->intr->vector);
466 bna_intx_enable(ib->bna, intx_mask);
467 }
468 }
469 }
470
471 void
472 bna_ib_fail(struct bna_ib *ib)
473 {
474 ib->start_count = 0;
475 }
476
477 /**
478 * RXF
479 */
480 static void rxf_enable(struct bna_rxf *rxf);
481 static void rxf_disable(struct bna_rxf *rxf);
482 static void __rxf_config_set(struct bna_rxf *rxf);
483 static void __rxf_rit_set(struct bna_rxf *rxf);
484 static void __bna_rxf_stat_clr(struct bna_rxf *rxf);
485 static int rxf_process_packet_filter(struct bna_rxf *rxf);
486 static int rxf_clear_packet_filter(struct bna_rxf *rxf);
487 static void rxf_reset_packet_filter(struct bna_rxf *rxf);
488 static void rxf_cb_enabled(void *arg, int status);
489 static void rxf_cb_disabled(void *arg, int status);
490 static void bna_rxf_cb_stats_cleared(void *arg, int status);
491 static void __rxf_enable(struct bna_rxf *rxf);
492 static void __rxf_disable(struct bna_rxf *rxf);
493
494 bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
495 enum bna_rxf_event);
496 bfa_fsm_state_decl(bna_rxf, start_wait, struct bna_rxf,
497 enum bna_rxf_event);
498 bfa_fsm_state_decl(bna_rxf, cam_fltr_mod_wait, struct bna_rxf,
499 enum bna_rxf_event);
500 bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
501 enum bna_rxf_event);
502 bfa_fsm_state_decl(bna_rxf, cam_fltr_clr_wait, struct bna_rxf,
503 enum bna_rxf_event);
504 bfa_fsm_state_decl(bna_rxf, stop_wait, struct bna_rxf,
505 enum bna_rxf_event);
506 bfa_fsm_state_decl(bna_rxf, pause_wait, struct bna_rxf,
507 enum bna_rxf_event);
508 bfa_fsm_state_decl(bna_rxf, resume_wait, struct bna_rxf,
509 enum bna_rxf_event);
510 bfa_fsm_state_decl(bna_rxf, stat_clr_wait, struct bna_rxf,
511 enum bna_rxf_event);
512
513 static struct bfa_sm_table rxf_sm_table[] = {
514 {BFA_SM(bna_rxf_sm_stopped), BNA_RXF_STOPPED},
515 {BFA_SM(bna_rxf_sm_start_wait), BNA_RXF_START_WAIT},
516 {BFA_SM(bna_rxf_sm_cam_fltr_mod_wait), BNA_RXF_CAM_FLTR_MOD_WAIT},
517 {BFA_SM(bna_rxf_sm_started), BNA_RXF_STARTED},
518 {BFA_SM(bna_rxf_sm_cam_fltr_clr_wait), BNA_RXF_CAM_FLTR_CLR_WAIT},
519 {BFA_SM(bna_rxf_sm_stop_wait), BNA_RXF_STOP_WAIT},
520 {BFA_SM(bna_rxf_sm_pause_wait), BNA_RXF_PAUSE_WAIT},
521 {BFA_SM(bna_rxf_sm_resume_wait), BNA_RXF_RESUME_WAIT},
522 {BFA_SM(bna_rxf_sm_stat_clr_wait), BNA_RXF_STAT_CLR_WAIT}
523 };
524
525 static void
526 bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
527 {
528 call_rxf_stop_cbfn(rxf, BNA_CB_SUCCESS);
529 }
530
531 static void
532 bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
533 {
534 switch (event) {
535 case RXF_E_START:
536 bfa_fsm_set_state(rxf, bna_rxf_sm_start_wait);
537 break;
538
539 case RXF_E_STOP:
540 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
541 break;
542
543 case RXF_E_FAIL:
544 /* No-op */
545 break;
546
547 case RXF_E_CAM_FLTR_MOD:
548 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
549 break;
550
551 case RXF_E_STARTED:
552 case RXF_E_STOPPED:
553 case RXF_E_CAM_FLTR_RESP:
554 /**
555 * These events are received due to flushing of mbox
556 * when device fails
557 */
558 /* No-op */
559 break;
560
561 case RXF_E_PAUSE:
562 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
563 call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
564 break;
565
566 case RXF_E_RESUME:
567 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
568 call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
569 break;
570
571 default:
572 bfa_sm_fault(rxf->rx->bna, event);
573 }
574 }
575
576 static void
577 bna_rxf_sm_start_wait_entry(struct bna_rxf *rxf)
578 {
579 __rxf_config_set(rxf);
580 __rxf_rit_set(rxf);
581 rxf_enable(rxf);
582 }
583
584 static void
585 bna_rxf_sm_start_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
586 {
587 switch (event) {
588 case RXF_E_STOP:
589 /**
590 * STOP is originated from bnad. When this happens,
591 * it can not be waiting for filter update
592 */
593 call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
594 bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
595 break;
596
597 case RXF_E_FAIL:
598 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
599 call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
600 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
601 break;
602
603 case RXF_E_CAM_FLTR_MOD:
604 /* No-op */
605 break;
606
607 case RXF_E_STARTED:
608 /**
609 * Force rxf_process_filter() to go through initial
610 * config
611 */
612 if ((rxf->ucast_active_mac != NULL) &&
613 (rxf->ucast_pending_set == 0))
614 rxf->ucast_pending_set = 1;
615
616 if (rxf->rss_status == BNA_STATUS_T_ENABLED)
617 rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
618
619 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
620
621 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
622 break;
623
624 case RXF_E_PAUSE:
625 case RXF_E_RESUME:
626 rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
627 break;
628
629 default:
630 bfa_sm_fault(rxf->rx->bna, event);
631 }
632 }
633
634 static void
635 bna_rxf_sm_cam_fltr_mod_wait_entry(struct bna_rxf *rxf)
636 {
637 if (!rxf_process_packet_filter(rxf)) {
638 /* No more pending CAM entries to update */
639 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
640 }
641 }
642
643 static void
644 bna_rxf_sm_cam_fltr_mod_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
645 {
646 switch (event) {
647 case RXF_E_STOP:
648 /**
649 * STOP is originated from bnad. When this happens,
650 * it can not be waiting for filter update
651 */
652 call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
653 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
654 break;
655
656 case RXF_E_FAIL:
657 rxf_reset_packet_filter(rxf);
658 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
659 call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
660 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
661 break;
662
663 case RXF_E_CAM_FLTR_MOD:
664 /* No-op */
665 break;
666
667 case RXF_E_CAM_FLTR_RESP:
668 if (!rxf_process_packet_filter(rxf)) {
669 /* No more pending CAM entries to update */
670 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
671 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
672 }
673 break;
674
675 case RXF_E_PAUSE:
676 case RXF_E_RESUME:
677 rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
678 break;
679
680 default:
681 bfa_sm_fault(rxf->rx->bna, event);
682 }
683 }
684
685 static void
686 bna_rxf_sm_started_entry(struct bna_rxf *rxf)
687 {
688 call_rxf_start_cbfn(rxf, BNA_CB_SUCCESS);
689
690 if (rxf->rxf_flags & BNA_RXF_FL_OPERSTATE_CHANGED) {
691 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
692 bfa_fsm_send_event(rxf, RXF_E_PAUSE);
693 else
694 bfa_fsm_send_event(rxf, RXF_E_RESUME);
695 }
696
697 }
698
699 static void
700 bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
701 {
702 switch (event) {
703 case RXF_E_STOP:
704 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
705 /* Hack to get FSM start clearing CAM entries */
706 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
707 break;
708
709 case RXF_E_FAIL:
710 rxf_reset_packet_filter(rxf);
711 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
712 break;
713
714 case RXF_E_CAM_FLTR_MOD:
715 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
716 break;
717
718 case RXF_E_PAUSE:
719 bfa_fsm_set_state(rxf, bna_rxf_sm_pause_wait);
720 break;
721
722 case RXF_E_RESUME:
723 bfa_fsm_set_state(rxf, bna_rxf_sm_resume_wait);
724 break;
725
726 default:
727 bfa_sm_fault(rxf->rx->bna, event);
728 }
729 }
730
731 static void
732 bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf)
733 {
734 /**
735 * Note: Do not add rxf_clear_packet_filter here.
736 * It will overstep mbox when this transition happens:
737 * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
738 */
739 }
740
741 static void
742 bna_rxf_sm_cam_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
743 {
744 switch (event) {
745 case RXF_E_FAIL:
746 /**
747 * FSM was in the process of stopping, initiated by
748 * bnad. When this happens, no one can be waiting for
749 * start or filter update
750 */
751 rxf_reset_packet_filter(rxf);
752 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
753 break;
754
755 case RXF_E_CAM_FLTR_RESP:
756 if (!rxf_clear_packet_filter(rxf)) {
757 /* No more pending CAM entries to clear */
758 bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
759 rxf_disable(rxf);
760 }
761 break;
762
763 default:
764 bfa_sm_fault(rxf->rx->bna, event);
765 }
766 }
767
768 static void
769 bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf)
770 {
771 /**
772 * NOTE: Do not add rxf_disable here.
773 * It will overstep mbox when this transition happens:
774 * start_wait -> stop_wait on RXF_E_STOP event
775 */
776 }
777
778 static void
779 bna_rxf_sm_stop_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
780 {
781 switch (event) {
782 case RXF_E_FAIL:
783 /**
784 * FSM was in the process of stopping, initiated by
785 * bnad. When this happens, no one can be waiting for
786 * start or filter update
787 */
788 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
789 break;
790
791 case RXF_E_STARTED:
792 /**
793 * This event is received due to abrupt transition from
794 * bna_rxf_sm_start_wait state on receiving
795 * RXF_E_STOP event
796 */
797 rxf_disable(rxf);
798 break;
799
800 case RXF_E_STOPPED:
801 /**
802 * FSM was in the process of stopping, initiated by
803 * bnad. When this happens, no one can be waiting for
804 * start or filter update
805 */
806 bfa_fsm_set_state(rxf, bna_rxf_sm_stat_clr_wait);
807 break;
808
809 case RXF_E_PAUSE:
810 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
811 break;
812
813 case RXF_E_RESUME:
814 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
815 break;
816
817 default:
818 bfa_sm_fault(rxf->rx->bna, event);
819 }
820 }
821
822 static void
823 bna_rxf_sm_pause_wait_entry(struct bna_rxf *rxf)
824 {
825 rxf->rxf_flags &=
826 ~(BNA_RXF_FL_OPERSTATE_CHANGED | BNA_RXF_FL_RXF_ENABLED);
827 __rxf_disable(rxf);
828 }
829
830 static void
831 bna_rxf_sm_pause_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
832 {
833 switch (event) {
834 case RXF_E_FAIL:
835 /**
836 * FSM was in the process of disabling rxf, initiated by
837 * bnad.
838 */
839 call_rxf_pause_cbfn(rxf, BNA_CB_FAIL);
840 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
841 break;
842
843 case RXF_E_STOPPED:
844 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
845 call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
846 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
847 break;
848
849 /*
850 * Since PAUSE/RESUME can only be sent by bnad, we don't expect
851 * any other event during these states
852 */
853 default:
854 bfa_sm_fault(rxf->rx->bna, event);
855 }
856 }
857
858 static void
859 bna_rxf_sm_resume_wait_entry(struct bna_rxf *rxf)
860 {
861 rxf->rxf_flags &= ~(BNA_RXF_FL_OPERSTATE_CHANGED);
862 rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
863 __rxf_enable(rxf);
864 }
865
866 static void
867 bna_rxf_sm_resume_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
868 {
869 switch (event) {
870 case RXF_E_FAIL:
871 /**
872 * FSM was in the process of disabling rxf, initiated by
873 * bnad.
874 */
875 call_rxf_resume_cbfn(rxf, BNA_CB_FAIL);
876 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
877 break;
878
879 case RXF_E_STARTED:
880 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
881 call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
882 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
883 break;
884
885 /*
886 * Since PAUSE/RESUME can only be sent by bnad, we don't expect
887 * any other event during these states
888 */
889 default:
890 bfa_sm_fault(rxf->rx->bna, event);
891 }
892 }
893
894 static void
895 bna_rxf_sm_stat_clr_wait_entry(struct bna_rxf *rxf)
896 {
897 __bna_rxf_stat_clr(rxf);
898 }
899
900 static void
901 bna_rxf_sm_stat_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
902 {
903 switch (event) {
904 case RXF_E_FAIL:
905 case RXF_E_STAT_CLEARED:
906 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
907 break;
908
909 default:
910 bfa_sm_fault(rxf->rx->bna, event);
911 }
912 }
913
914 static void
915 __rxf_enable(struct bna_rxf *rxf)
916 {
917 struct bfi_ll_rxf_multi_req ll_req;
918 u32 bm[2] = {0, 0};
919
920 if (rxf->rxf_id < 32)
921 bm[0] = 1 << rxf->rxf_id;
922 else
923 bm[1] = 1 << (rxf->rxf_id - 32);
924
925 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
926 ll_req.rxf_id_mask[0] = htonl(bm[0]);
927 ll_req.rxf_id_mask[1] = htonl(bm[1]);
928 ll_req.enable = 1;
929
930 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
931 rxf_cb_enabled, rxf);
932
933 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
934 }
935
936 static void
937 __rxf_disable(struct bna_rxf *rxf)
938 {
939 struct bfi_ll_rxf_multi_req ll_req;
940 u32 bm[2] = {0, 0};
941
942 if (rxf->rxf_id < 32)
943 bm[0] = 1 << rxf->rxf_id;
944 else
945 bm[1] = 1 << (rxf->rxf_id - 32);
946
947 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
948 ll_req.rxf_id_mask[0] = htonl(bm[0]);
949 ll_req.rxf_id_mask[1] = htonl(bm[1]);
950 ll_req.enable = 0;
951
952 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
953 rxf_cb_disabled, rxf);
954
955 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
956 }
957
958 static void
959 __rxf_config_set(struct bna_rxf *rxf)
960 {
961 u32 i;
962 struct bna_rss_mem *rss_mem;
963 struct bna_rx_fndb_ram *rx_fndb_ram;
964 struct bna *bna = rxf->rx->bna;
965 void __iomem *base_addr;
966 unsigned long off;
967
968 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
969 RSS_TABLE_BASE_OFFSET);
970
971 rss_mem = (struct bna_rss_mem *)0;
972
973 /* Configure RSS if required */
974 if (rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE) {
975 /* configure RSS Table */
976 writel(BNA_GET_PAGE_NUM(RAD0_MEM_BLK_BASE_PG_NUM +
977 bna->port_num, RSS_TABLE_BASE_OFFSET),
978 bna->regs.page_addr);
979
980 /* temporarily disable RSS, while hash value is written */
981 off = (unsigned long)&rss_mem[0].type_n_hash;
982 writel(0, base_addr + off);
983
984 for (i = 0; i < BFI_RSS_HASH_KEY_LEN; i++) {
985 off = (unsigned long)
986 &rss_mem[0].hash_key[(BFI_RSS_HASH_KEY_LEN - 1) - i];
987 writel(htonl(rxf->rss_cfg.toeplitz_hash_key[i]),
988 base_addr + off);
989 }
990
991 off = (unsigned long)&rss_mem[0].type_n_hash;
992 writel(rxf->rss_cfg.hash_type | rxf->rss_cfg.hash_mask,
993 base_addr + off);
994 }
995
996 /* Configure RxF */
997 writel(BNA_GET_PAGE_NUM(
998 LUT0_MEM_BLK_BASE_PG_NUM + (bna->port_num * 2),
999 RX_FNDB_RAM_BASE_OFFSET),
1000 bna->regs.page_addr);
1001
1002 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
1003 RX_FNDB_RAM_BASE_OFFSET);
1004
1005 rx_fndb_ram = (struct bna_rx_fndb_ram *)0;
1006
1007 /* We always use RSS table 0 */
1008 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rss_prop;
1009 writel(rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE,
1010 base_addr + off);
1011
1012 /* small large buffer enable/disable */
1013 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].size_routing_props;
1014 writel((rxf->ctrl_flags & BNA_RXF_CF_SM_LG_RXQ) | 0x80,
1015 base_addr + off);
1016
1017 /* RIT offset, HDS forced offset, multicast RxQ Id */
1018 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rit_hds_mcastq;
1019 writel((rxf->rit_segment->rit_offset << 16) |
1020 (rxf->forced_offset << 8) |
1021 (rxf->hds_cfg.hdr_type & BNA_HDS_FORCED) | rxf->mcast_rxq_id,
1022 base_addr + off);
1023
1024 /*
1025 * default vlan tag, default function enable, strip vlan bytes,
1026 * HDS type, header size
1027 */
1028
1029 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].control_flags;
1030 writel(((u32)rxf->default_vlan_tag << 16) |
1031 (rxf->ctrl_flags &
1032 (BNA_RXF_CF_DEFAULT_VLAN |
1033 BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE |
1034 BNA_RXF_CF_VLAN_STRIP)) |
1035 (rxf->hds_cfg.hdr_type & ~BNA_HDS_FORCED) |
1036 rxf->hds_cfg.header_size,
1037 base_addr + off);
1038 }
1039
1040 void
1041 __rxf_vlan_filter_set(struct bna_rxf *rxf, enum bna_status status)
1042 {
1043 struct bna *bna = rxf->rx->bna;
1044 int i;
1045
1046 writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
1047 (bna->port_num * 2), VLAN_RAM_BASE_OFFSET),
1048 bna->regs.page_addr);
1049
1050 if (status == BNA_STATUS_T_ENABLED) {
1051 /* enable VLAN filtering on this function */
1052 for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
1053 writel(rxf->vlan_filter_table[i],
1054 BNA_GET_VLAN_MEM_ENTRY_ADDR
1055 (bna->pcidev.pci_bar_kva, rxf->rxf_id,
1056 i * 32));
1057 }
1058 } else {
1059 /* disable VLAN filtering on this function */
1060 for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
1061 writel(0xffffffff,
1062 BNA_GET_VLAN_MEM_ENTRY_ADDR
1063 (bna->pcidev.pci_bar_kva, rxf->rxf_id,
1064 i * 32));
1065 }
1066 }
1067 }
1068
1069 static void
1070 __rxf_rit_set(struct bna_rxf *rxf)
1071 {
1072 struct bna *bna = rxf->rx->bna;
1073 struct bna_rit_mem *rit_mem;
1074 int i;
1075 void __iomem *base_addr;
1076 unsigned long off;
1077
1078 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
1079 FUNCTION_TO_RXQ_TRANSLATE);
1080
1081 rit_mem = (struct bna_rit_mem *)0;
1082
1083 writel(BNA_GET_PAGE_NUM(RXA0_MEM_BLK_BASE_PG_NUM + bna->port_num,
1084 FUNCTION_TO_RXQ_TRANSLATE),
1085 bna->regs.page_addr);
1086
1087 for (i = 0; i < rxf->rit_segment->rit_size; i++) {
1088 off = (unsigned long)&rit_mem[i + rxf->rit_segment->rit_offset];
1089 writel(rxf->rit_segment->rit[i].large_rxq_id << 6 |
1090 rxf->rit_segment->rit[i].small_rxq_id,
1091 base_addr + off);
1092 }
1093 }
1094
1095 static void
1096 __bna_rxf_stat_clr(struct bna_rxf *rxf)
1097 {
1098 struct bfi_ll_stats_req ll_req;
1099 u32 bm[2] = {0, 0};
1100
1101 if (rxf->rxf_id < 32)
1102 bm[0] = 1 << rxf->rxf_id;
1103 else
1104 bm[1] = 1 << (rxf->rxf_id - 32);
1105
1106 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
1107 ll_req.stats_mask = 0;
1108 ll_req.txf_id_mask[0] = 0;
1109 ll_req.txf_id_mask[1] = 0;
1110
1111 ll_req.rxf_id_mask[0] = htonl(bm[0]);
1112 ll_req.rxf_id_mask[1] = htonl(bm[1]);
1113
1114 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
1115 bna_rxf_cb_stats_cleared, rxf);
1116 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
1117 }
1118
1119 static void
1120 rxf_enable(struct bna_rxf *rxf)
1121 {
1122 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
1123 bfa_fsm_send_event(rxf, RXF_E_STARTED);
1124 else {
1125 rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
1126 __rxf_enable(rxf);
1127 }
1128 }
1129
1130 static void
1131 rxf_cb_enabled(void *arg, int status)
1132 {
1133 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1134
1135 bfa_q_qe_init(&rxf->mbox_qe.qe);
1136 bfa_fsm_send_event(rxf, RXF_E_STARTED);
1137 }
1138
1139 static void
1140 rxf_disable(struct bna_rxf *rxf)
1141 {
1142 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
1143 bfa_fsm_send_event(rxf, RXF_E_STOPPED);
1144 else
1145 rxf->rxf_flags &= ~BNA_RXF_FL_RXF_ENABLED;
1146 __rxf_disable(rxf);
1147 }
1148
1149 static void
1150 rxf_cb_disabled(void *arg, int status)
1151 {
1152 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1153
1154 bfa_q_qe_init(&rxf->mbox_qe.qe);
1155 bfa_fsm_send_event(rxf, RXF_E_STOPPED);
1156 }
1157
1158 void
1159 rxf_cb_cam_fltr_mbox_cmd(void *arg, int status)
1160 {
1161 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1162
1163 bfa_q_qe_init(&rxf->mbox_qe.qe);
1164
1165 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
1166 }
1167
1168 static void
1169 bna_rxf_cb_stats_cleared(void *arg, int status)
1170 {
1171 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1172
1173 bfa_q_qe_init(&rxf->mbox_qe.qe);
1174 bfa_fsm_send_event(rxf, RXF_E_STAT_CLEARED);
1175 }
1176
1177 void
1178 rxf_cam_mbox_cmd(struct bna_rxf *rxf, u8 cmd,
1179 const struct bna_mac *mac_addr)
1180 {
1181 struct bfi_ll_mac_addr_req req;
1182
1183 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
1184
1185 req.rxf_id = rxf->rxf_id;
1186 memcpy(&req.mac_addr, (void *)&mac_addr->addr, ETH_ALEN);
1187
1188 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
1189 rxf_cb_cam_fltr_mbox_cmd, rxf);
1190
1191 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
1192 }
1193
1194 static int
1195 rxf_process_packet_filter_mcast(struct bna_rxf *rxf)
1196 {
1197 struct bna_mac *mac = NULL;
1198 struct list_head *qe;
1199
1200 /* Add multicast entries */
1201 if (!list_empty(&rxf->mcast_pending_add_q)) {
1202 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
1203 bfa_q_qe_init(qe);
1204 mac = (struct bna_mac *)qe;
1205 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_ADD_REQ, mac);
1206 list_add_tail(&mac->qe, &rxf->mcast_active_q);
1207 return 1;
1208 }
1209
1210 /* Delete multicast entries previousely added */
1211 if (!list_empty(&rxf->mcast_pending_del_q)) {
1212 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1213 bfa_q_qe_init(qe);
1214 mac = (struct bna_mac *)qe;
1215 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1216 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1217 return 1;
1218 }
1219
1220 return 0;
1221 }
1222
1223 static int
1224 rxf_process_packet_filter_vlan(struct bna_rxf *rxf)
1225 {
1226 /* Apply the VLAN filter */
1227 if (rxf->rxf_flags & BNA_RXF_FL_VLAN_CONFIG_PENDING) {
1228 rxf->rxf_flags &= ~BNA_RXF_FL_VLAN_CONFIG_PENDING;
1229 if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC) &&
1230 !(rxf->rxmode_active & BNA_RXMODE_DEFAULT))
1231 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
1232 }
1233
1234 /* Apply RSS configuration */
1235 if (rxf->rxf_flags & BNA_RXF_FL_RSS_CONFIG_PENDING) {
1236 rxf->rxf_flags &= ~BNA_RXF_FL_RSS_CONFIG_PENDING;
1237 if (rxf->rss_status == BNA_STATUS_T_DISABLED) {
1238 /* RSS is being disabled */
1239 rxf->ctrl_flags &= ~BNA_RXF_CF_RSS_ENABLE;
1240 __rxf_rit_set(rxf);
1241 __rxf_config_set(rxf);
1242 } else {
1243 /* RSS is being enabled or reconfigured */
1244 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
1245 __rxf_rit_set(rxf);
1246 __rxf_config_set(rxf);
1247 }
1248 }
1249
1250 return 0;
1251 }
1252
1253 /**
1254 * Processes pending ucast, mcast entry addition/deletion and issues mailbox
1255 * command. Also processes pending filter configuration - promiscuous mode,
1256 * default mode, allmutli mode and issues mailbox command or directly applies
1257 * to h/w
1258 */
1259 static int
1260 rxf_process_packet_filter(struct bna_rxf *rxf)
1261 {
1262 /* Set the default MAC first */
1263 if (rxf->ucast_pending_set > 0) {
1264 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_SET_REQ,
1265 rxf->ucast_active_mac);
1266 rxf->ucast_pending_set--;
1267 return 1;
1268 }
1269
1270 if (rxf_process_packet_filter_ucast(rxf))
1271 return 1;
1272
1273 if (rxf_process_packet_filter_mcast(rxf))
1274 return 1;
1275
1276 if (rxf_process_packet_filter_promisc(rxf))
1277 return 1;
1278
1279 if (rxf_process_packet_filter_default(rxf))
1280 return 1;
1281
1282 if (rxf_process_packet_filter_allmulti(rxf))
1283 return 1;
1284
1285 if (rxf_process_packet_filter_vlan(rxf))
1286 return 1;
1287
1288 return 0;
1289 }
1290
1291 static int
1292 rxf_clear_packet_filter_mcast(struct bna_rxf *rxf)
1293 {
1294 struct bna_mac *mac = NULL;
1295 struct list_head *qe;
1296
1297 /* 3. delete pending mcast entries */
1298 if (!list_empty(&rxf->mcast_pending_del_q)) {
1299 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1300 bfa_q_qe_init(qe);
1301 mac = (struct bna_mac *)qe;
1302 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1303 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1304 return 1;
1305 }
1306
1307 /* 4. clear active mcast entries; move them to pending_add_q */
1308 if (!list_empty(&rxf->mcast_active_q)) {
1309 bfa_q_deq(&rxf->mcast_active_q, &qe);
1310 bfa_q_qe_init(qe);
1311 mac = (struct bna_mac *)qe;
1312 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1313 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1314 return 1;
1315 }
1316
1317 return 0;
1318 }
1319
1320 /**
1321 * In the rxf stop path, processes pending ucast/mcast delete queue and issues
1322 * the mailbox command. Moves the active ucast/mcast entries to pending add q,
1323 * so that they are added to CAM again in the rxf start path. Moves the current
1324 * filter settings - promiscuous, default, allmutli - to pending filter
1325 * configuration
1326 */
1327 static int
1328 rxf_clear_packet_filter(struct bna_rxf *rxf)
1329 {
1330 if (rxf_clear_packet_filter_ucast(rxf))
1331 return 1;
1332
1333 if (rxf_clear_packet_filter_mcast(rxf))
1334 return 1;
1335
1336 /* 5. clear active default MAC in the CAM */
1337 if (rxf->ucast_pending_set > 0)
1338 rxf->ucast_pending_set = 0;
1339
1340 if (rxf_clear_packet_filter_promisc(rxf))
1341 return 1;
1342
1343 if (rxf_clear_packet_filter_default(rxf))
1344 return 1;
1345
1346 if (rxf_clear_packet_filter_allmulti(rxf))
1347 return 1;
1348
1349 return 0;
1350 }
1351
1352 static void
1353 rxf_reset_packet_filter_mcast(struct bna_rxf *rxf)
1354 {
1355 struct list_head *qe;
1356 struct bna_mac *mac;
1357
1358 /* 3. Move active mcast entries to pending_add_q */
1359 while (!list_empty(&rxf->mcast_active_q)) {
1360 bfa_q_deq(&rxf->mcast_active_q, &qe);
1361 bfa_q_qe_init(qe);
1362 list_add_tail(qe, &rxf->mcast_pending_add_q);
1363 }
1364
1365 /* 4. Throw away delete pending mcast entries */
1366 while (!list_empty(&rxf->mcast_pending_del_q)) {
1367 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1368 bfa_q_qe_init(qe);
1369 mac = (struct bna_mac *)qe;
1370 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1371 }
1372 }
1373
1374 /**
1375 * In the rxf fail path, throws away the ucast/mcast entries pending for
1376 * deletion, moves all active ucast/mcast entries to pending queue so that
1377 * they are added back to CAM in the rxf start path. Also moves the current
1378 * filter configuration to pending filter configuration.
1379 */
1380 static void
1381 rxf_reset_packet_filter(struct bna_rxf *rxf)
1382 {
1383 rxf_reset_packet_filter_ucast(rxf);
1384
1385 rxf_reset_packet_filter_mcast(rxf);
1386
1387 /* 5. Turn off ucast set flag */
1388 rxf->ucast_pending_set = 0;
1389
1390 rxf_reset_packet_filter_promisc(rxf);
1391
1392 rxf_reset_packet_filter_default(rxf);
1393
1394 rxf_reset_packet_filter_allmulti(rxf);
1395 }
1396
1397 void
1398 bna_rxf_init(struct bna_rxf *rxf,
1399 struct bna_rx *rx,
1400 struct bna_rx_config *q_config)
1401 {
1402 struct list_head *qe;
1403 struct bna_rxp *rxp;
1404
1405 /* rxf_id is initialized during rx_mod init */
1406 rxf->rx = rx;
1407
1408 INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
1409 INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
1410 rxf->ucast_pending_set = 0;
1411 INIT_LIST_HEAD(&rxf->ucast_active_q);
1412 rxf->ucast_active_mac = NULL;
1413
1414 INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
1415 INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
1416 INIT_LIST_HEAD(&rxf->mcast_active_q);
1417
1418 bfa_q_qe_init(&rxf->mbox_qe.qe);
1419
1420 if (q_config->vlan_strip_status == BNA_STATUS_T_ENABLED)
1421 rxf->ctrl_flags |= BNA_RXF_CF_VLAN_STRIP;
1422
1423 rxf->rxf_oper_state = (q_config->paused) ?
1424 BNA_RXF_OPER_STATE_PAUSED : BNA_RXF_OPER_STATE_RUNNING;
1425
1426 bna_rxf_adv_init(rxf, rx, q_config);
1427
1428 rxf->rit_segment = bna_rit_mod_seg_get(&rxf->rx->bna->rit_mod,
1429 q_config->num_paths);
1430
1431 list_for_each(qe, &rx->rxp_q) {
1432 rxp = (struct bna_rxp *)qe;
1433 if (q_config->rxp_type == BNA_RXP_SINGLE)
1434 rxf->mcast_rxq_id = rxp->rxq.single.only->rxq_id;
1435 else
1436 rxf->mcast_rxq_id = rxp->rxq.slr.large->rxq_id;
1437 break;
1438 }
1439
1440 rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
1441 memset(rxf->vlan_filter_table, 0,
1442 (sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32)));
1443
1444 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
1445 }
1446
1447 void
1448 bna_rxf_uninit(struct bna_rxf *rxf)
1449 {
1450 struct bna_mac *mac;
1451
1452 bna_rit_mod_seg_put(&rxf->rx->bna->rit_mod, rxf->rit_segment);
1453 rxf->rit_segment = NULL;
1454
1455 rxf->ucast_pending_set = 0;
1456
1457 while (!list_empty(&rxf->ucast_pending_add_q)) {
1458 bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
1459 bfa_q_qe_init(&mac->qe);
1460 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
1461 }
1462
1463 if (rxf->ucast_active_mac) {
1464 bfa_q_qe_init(&rxf->ucast_active_mac->qe);
1465 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
1466 rxf->ucast_active_mac);
1467 rxf->ucast_active_mac = NULL;
1468 }
1469
1470 while (!list_empty(&rxf->mcast_pending_add_q)) {
1471 bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
1472 bfa_q_qe_init(&mac->qe);
1473 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1474 }
1475
1476 rxf->rx = NULL;
1477 }
1478
1479 void
1480 bna_rxf_start(struct bna_rxf *rxf)
1481 {
1482 rxf->start_cbfn = bna_rx_cb_rxf_started;
1483 rxf->start_cbarg = rxf->rx;
1484 rxf->rxf_flags &= ~BNA_RXF_FL_FAILED;
1485 bfa_fsm_send_event(rxf, RXF_E_START);
1486 }
1487
1488 void
1489 bna_rxf_stop(struct bna_rxf *rxf)
1490 {
1491 rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
1492 rxf->stop_cbarg = rxf->rx;
1493 bfa_fsm_send_event(rxf, RXF_E_STOP);
1494 }
1495
1496 void
1497 bna_rxf_fail(struct bna_rxf *rxf)
1498 {
1499 rxf->rxf_flags |= BNA_RXF_FL_FAILED;
1500 bfa_fsm_send_event(rxf, RXF_E_FAIL);
1501 }
1502
1503 int
1504 bna_rxf_state_get(struct bna_rxf *rxf)
1505 {
1506 return bfa_sm_to_state(rxf_sm_table, rxf->fsm);
1507 }
1508
1509 enum bna_cb_status
1510 bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
1511 void (*cbfn)(struct bnad *, struct bna_rx *,
1512 enum bna_cb_status))
1513 {
1514 struct bna_rxf *rxf = &rx->rxf;
1515
1516 if (rxf->ucast_active_mac == NULL) {
1517 rxf->ucast_active_mac =
1518 bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
1519 if (rxf->ucast_active_mac == NULL)
1520 return BNA_CB_UCAST_CAM_FULL;
1521 bfa_q_qe_init(&rxf->ucast_active_mac->qe);
1522 }
1523
1524 memcpy(rxf->ucast_active_mac->addr, ucmac, ETH_ALEN);
1525 rxf->ucast_pending_set++;
1526 rxf->cam_fltr_cbfn = cbfn;
1527 rxf->cam_fltr_cbarg = rx->bna->bnad;
1528
1529 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1530
1531 return BNA_CB_SUCCESS;
1532 }
1533
1534 enum bna_cb_status
1535 bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
1536 void (*cbfn)(struct bnad *, struct bna_rx *,
1537 enum bna_cb_status))
1538 {
1539 struct bna_rxf *rxf = &rx->rxf;
1540 struct list_head *qe;
1541 struct bna_mac *mac;
1542
1543 /* Check if already added */
1544 list_for_each(qe, &rxf->mcast_active_q) {
1545 mac = (struct bna_mac *)qe;
1546 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1547 if (cbfn)
1548 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1549 return BNA_CB_SUCCESS;
1550 }
1551 }
1552
1553 /* Check if pending addition */
1554 list_for_each(qe, &rxf->mcast_pending_add_q) {
1555 mac = (struct bna_mac *)qe;
1556 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1557 if (cbfn)
1558 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1559 return BNA_CB_SUCCESS;
1560 }
1561 }
1562
1563 mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
1564 if (mac == NULL)
1565 return BNA_CB_MCAST_LIST_FULL;
1566 bfa_q_qe_init(&mac->qe);
1567 memcpy(mac->addr, addr, ETH_ALEN);
1568 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1569
1570 rxf->cam_fltr_cbfn = cbfn;
1571 rxf->cam_fltr_cbarg = rx->bna->bnad;
1572
1573 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1574
1575 return BNA_CB_SUCCESS;
1576 }
1577
1578 enum bna_cb_status
1579 bna_rx_mcast_del(struct bna_rx *rx, u8 *addr,
1580 void (*cbfn)(struct bnad *, struct bna_rx *,
1581 enum bna_cb_status))
1582 {
1583 struct bna_rxf *rxf = &rx->rxf;
1584 struct list_head *qe;
1585 struct bna_mac *mac;
1586
1587 list_for_each(qe, &rxf->mcast_pending_add_q) {
1588 mac = (struct bna_mac *)qe;
1589 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1590 list_del(qe);
1591 bfa_q_qe_init(qe);
1592 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1593 if (cbfn)
1594 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1595 return BNA_CB_SUCCESS;
1596 }
1597 }
1598
1599 list_for_each(qe, &rxf->mcast_active_q) {
1600 mac = (struct bna_mac *)qe;
1601 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1602 list_del(qe);
1603 bfa_q_qe_init(qe);
1604 list_add_tail(qe, &rxf->mcast_pending_del_q);
1605 rxf->cam_fltr_cbfn = cbfn;
1606 rxf->cam_fltr_cbarg = rx->bna->bnad;
1607 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1608 return BNA_CB_SUCCESS;
1609 }
1610 }
1611
1612 return BNA_CB_INVALID_MAC;
1613 }
1614
1615 enum bna_cb_status
1616 bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
1617 void (*cbfn)(struct bnad *, struct bna_rx *,
1618 enum bna_cb_status))
1619 {
1620 struct bna_rxf *rxf = &rx->rxf;
1621 struct list_head list_head;
1622 struct list_head *qe;
1623 u8 *mcaddr;
1624 struct bna_mac *mac;
1625 struct bna_mac *mac1;
1626 int skip;
1627 int delete;
1628 int need_hw_config = 0;
1629 int i;
1630
1631 /* Allocate nodes */
1632 INIT_LIST_HEAD(&list_head);
1633 for (i = 0, mcaddr = mclist; i < count; i++) {
1634 mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
1635 if (mac == NULL)
1636 goto err_return;
1637 bfa_q_qe_init(&mac->qe);
1638 memcpy(mac->addr, mcaddr, ETH_ALEN);
1639 list_add_tail(&mac->qe, &list_head);
1640
1641 mcaddr += ETH_ALEN;
1642 }
1643
1644 /* Schedule for addition */
1645 while (!list_empty(&list_head)) {
1646 bfa_q_deq(&list_head, &qe);
1647 mac = (struct bna_mac *)qe;
1648 bfa_q_qe_init(&mac->qe);
1649
1650 skip = 0;
1651
1652 /* Skip if already added */
1653 list_for_each(qe, &rxf->mcast_active_q) {
1654 mac1 = (struct bna_mac *)qe;
1655 if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
1656 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
1657 mac);
1658 skip = 1;
1659 break;
1660 }
1661 }
1662
1663 if (skip)
1664 continue;
1665
1666 /* Skip if pending addition */
1667 list_for_each(qe, &rxf->mcast_pending_add_q) {
1668 mac1 = (struct bna_mac *)qe;
1669 if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
1670 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
1671 mac);
1672 skip = 1;
1673 break;
1674 }
1675 }
1676
1677 if (skip)
1678 continue;
1679
1680 need_hw_config = 1;
1681 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1682 }
1683
1684 /**
1685 * Delete the entries that are in the pending_add_q but not
1686 * in the new list
1687 */
1688 while (!list_empty(&rxf->mcast_pending_add_q)) {
1689 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
1690 mac = (struct bna_mac *)qe;
1691 bfa_q_qe_init(&mac->qe);
1692 for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
1693 if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
1694 delete = 0;
1695 break;
1696 }
1697 mcaddr += ETH_ALEN;
1698 }
1699 if (delete)
1700 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1701 else
1702 list_add_tail(&mac->qe, &list_head);
1703 }
1704 while (!list_empty(&list_head)) {
1705 bfa_q_deq(&list_head, &qe);
1706 mac = (struct bna_mac *)qe;
1707 bfa_q_qe_init(&mac->qe);
1708 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1709 }
1710
1711 /**
1712 * Schedule entries for deletion that are in the active_q but not
1713 * in the new list
1714 */
1715 while (!list_empty(&rxf->mcast_active_q)) {
1716 bfa_q_deq(&rxf->mcast_active_q, &qe);
1717 mac = (struct bna_mac *)qe;
1718 bfa_q_qe_init(&mac->qe);
1719 for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
1720 if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
1721 delete = 0;
1722 break;
1723 }
1724 mcaddr += ETH_ALEN;
1725 }
1726 if (delete) {
1727 list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
1728 need_hw_config = 1;
1729 } else {
1730 list_add_tail(&mac->qe, &list_head);
1731 }
1732 }
1733 while (!list_empty(&list_head)) {
1734 bfa_q_deq(&list_head, &qe);
1735 mac = (struct bna_mac *)qe;
1736 bfa_q_qe_init(&mac->qe);
1737 list_add_tail(&mac->qe, &rxf->mcast_active_q);
1738 }
1739
1740 if (need_hw_config) {
1741 rxf->cam_fltr_cbfn = cbfn;
1742 rxf->cam_fltr_cbarg = rx->bna->bnad;
1743 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1744 } else if (cbfn)
1745 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1746
1747 return BNA_CB_SUCCESS;
1748
1749 err_return:
1750 while (!list_empty(&list_head)) {
1751 bfa_q_deq(&list_head, &qe);
1752 mac = (struct bna_mac *)qe;
1753 bfa_q_qe_init(&mac->qe);
1754 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1755 }
1756
1757 return BNA_CB_MCAST_LIST_FULL;
1758 }
1759
1760 void
1761 bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
1762 {
1763 struct bna_rxf *rxf = &rx->rxf;
1764 int index = (vlan_id >> 5);
1765 int bit = (1 << (vlan_id & 0x1F));
1766
1767 rxf->vlan_filter_table[index] |= bit;
1768 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
1769 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
1770 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1771 }
1772 }
1773
1774 void
1775 bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
1776 {
1777 struct bna_rxf *rxf = &rx->rxf;
1778 int index = (vlan_id >> 5);
1779 int bit = (1 << (vlan_id & 0x1F));
1780
1781 rxf->vlan_filter_table[index] &= ~bit;
1782 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
1783 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
1784 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1785 }
1786 }
1787
1788 /**
1789 * RX
1790 */
1791 #define RXQ_RCB_INIT(q, rxp, qdepth, bna, _id, unmapq_mem) do { \
1792 struct bna_doorbell_qset *_qset; \
1793 unsigned long off; \
1794 (q)->rcb->producer_index = (q)->rcb->consumer_index = 0; \
1795 (q)->rcb->q_depth = (qdepth); \
1796 (q)->rcb->unmap_q = unmapq_mem; \
1797 (q)->rcb->rxq = (q); \
1798 (q)->rcb->cq = &(rxp)->cq; \
1799 (q)->rcb->bnad = (bna)->bnad; \
1800 _qset = (struct bna_doorbell_qset *)0; \
1801 off = (unsigned long)&_qset[(q)->rxq_id].rxq[0]; \
1802 (q)->rcb->q_dbell = off + \
1803 BNA_GET_DOORBELL_BASE_ADDR((bna)->pcidev.pci_bar_kva); \
1804 (q)->rcb->id = _id; \
1805 } while (0)
1806
1807 #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
1808 (qcfg)->num_paths : ((qcfg)->num_paths * 2))
1809
1810 #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
1811 (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
1812
1813 #define call_rx_stop_callback(rx, status) \
1814 if ((rx)->stop_cbfn) { \
1815 (*(rx)->stop_cbfn)((rx)->stop_cbarg, rx, (status)); \
1816 (rx)->stop_cbfn = NULL; \
1817 (rx)->stop_cbarg = NULL; \
1818 }
1819
1820 /*
1821 * Since rx_enable is synchronous callback, there is no start_cbfn required.
1822 * Instead, we'll call bnad_rx_post(rxp) so that bnad can post the buffers
1823 * for each rxpath.
1824 */
1825
1826 #define call_rx_disable_cbfn(rx, status) \
1827 if ((rx)->disable_cbfn) { \
1828 (*(rx)->disable_cbfn)((rx)->disable_cbarg, \
1829 status); \
1830 (rx)->disable_cbfn = NULL; \
1831 (rx)->disable_cbarg = NULL; \
1832 } \
1833
1834 #define rxqs_reqd(type, num_rxqs) \
1835 (((type) == BNA_RXP_SINGLE) ? (num_rxqs) : ((num_rxqs) * 2))
1836
1837 #define rx_ib_fail(rx) \
1838 do { \
1839 struct bna_rxp *rxp; \
1840 struct list_head *qe; \
1841 list_for_each(qe, &(rx)->rxp_q) { \
1842 rxp = (struct bna_rxp *)qe; \
1843 bna_ib_fail(rxp->cq.ib); \
1844 } \
1845 } while (0)
1846
1847 static void __bna_multi_rxq_stop(struct bna_rxp *, u32 *);
1848 static void __bna_rxq_start(struct bna_rxq *rxq);
1849 static void __bna_cq_start(struct bna_cq *cq);
1850 static void bna_rit_create(struct bna_rx *rx);
1851 static void bna_rx_cb_multi_rxq_stopped(void *arg, int status);
1852 static void bna_rx_cb_rxq_stopped_all(void *arg);
1853
1854 bfa_fsm_state_decl(bna_rx, stopped,
1855 struct bna_rx, enum bna_rx_event);
1856 bfa_fsm_state_decl(bna_rx, rxf_start_wait,
1857 struct bna_rx, enum bna_rx_event);
1858 bfa_fsm_state_decl(bna_rx, started,
1859 struct bna_rx, enum bna_rx_event);
1860 bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
1861 struct bna_rx, enum bna_rx_event);
1862 bfa_fsm_state_decl(bna_rx, rxq_stop_wait,
1863 struct bna_rx, enum bna_rx_event);
1864
1865 static struct bfa_sm_table rx_sm_table[] = {
1866 {BFA_SM(bna_rx_sm_stopped), BNA_RX_STOPPED},
1867 {BFA_SM(bna_rx_sm_rxf_start_wait), BNA_RX_RXF_START_WAIT},
1868 {BFA_SM(bna_rx_sm_started), BNA_RX_STARTED},
1869 {BFA_SM(bna_rx_sm_rxf_stop_wait), BNA_RX_RXF_STOP_WAIT},
1870 {BFA_SM(bna_rx_sm_rxq_stop_wait), BNA_RX_RXQ_STOP_WAIT},
1871 };
1872
1873 static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
1874 {
1875 struct bna_rxp *rxp;
1876 struct list_head *qe_rxp;
1877
1878 list_for_each(qe_rxp, &rx->rxp_q) {
1879 rxp = (struct bna_rxp *)qe_rxp;
1880 rx->rx_cleanup_cbfn(rx->bna->bnad, rxp->cq.ccb);
1881 }
1882
1883 call_rx_stop_callback(rx, BNA_CB_SUCCESS);
1884 }
1885
1886 static void bna_rx_sm_stopped(struct bna_rx *rx,
1887 enum bna_rx_event event)
1888 {
1889 switch (event) {
1890 case RX_E_START:
1891 bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
1892 break;
1893 case RX_E_STOP:
1894 call_rx_stop_callback(rx, BNA_CB_SUCCESS);
1895 break;
1896 case RX_E_FAIL:
1897 /* no-op */
1898 break;
1899 default:
1900 bfa_sm_fault(rx->bna, event);
1901 break;
1902 }
1903
1904 }
1905
1906 static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
1907 {
1908 struct bna_rxp *rxp;
1909 struct list_head *qe_rxp;
1910 struct bna_rxq *q0 = NULL, *q1 = NULL;
1911
1912 /* Setup the RIT */
1913 bna_rit_create(rx);
1914
1915 list_for_each(qe_rxp, &rx->rxp_q) {
1916 rxp = (struct bna_rxp *)qe_rxp;
1917 bna_ib_start(rxp->cq.ib);
1918 GET_RXQS(rxp, q0, q1);
1919 q0->buffer_size = bna_port_mtu_get(&rx->bna->port);
1920 __bna_rxq_start(q0);
1921 rx->rx_post_cbfn(rx->bna->bnad, q0->rcb);
1922 if (q1) {
1923 __bna_rxq_start(q1);
1924 rx->rx_post_cbfn(rx->bna->bnad, q1->rcb);
1925 }
1926 __bna_cq_start(&rxp->cq);
1927 }
1928
1929 bna_rxf_start(&rx->rxf);
1930 }
1931
1932 static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
1933 enum bna_rx_event event)
1934 {
1935 switch (event) {
1936 case RX_E_STOP:
1937 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
1938 break;
1939 case RX_E_FAIL:
1940 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
1941 rx_ib_fail(rx);
1942 bna_rxf_fail(&rx->rxf);
1943 break;
1944 case RX_E_RXF_STARTED:
1945 bfa_fsm_set_state(rx, bna_rx_sm_started);
1946 break;
1947 default:
1948 bfa_sm_fault(rx->bna, event);
1949 break;
1950 }
1951 }
1952
1953 void
1954 bna_rx_sm_started_entry(struct bna_rx *rx)
1955 {
1956 struct bna_rxp *rxp;
1957 struct list_head *qe_rxp;
1958
1959 /* Start IB */
1960 list_for_each(qe_rxp, &rx->rxp_q) {
1961 rxp = (struct bna_rxp *)qe_rxp;
1962 bna_ib_ack(&rxp->cq.ib->door_bell, 0);
1963 }
1964
1965 bna_llport_admin_up(&rx->bna->port.llport);
1966 }
1967
1968 void
1969 bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
1970 {
1971 switch (event) {
1972 case RX_E_FAIL:
1973 bna_llport_admin_down(&rx->bna->port.llport);
1974 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
1975 rx_ib_fail(rx);
1976 bna_rxf_fail(&rx->rxf);
1977 break;
1978 case RX_E_STOP:
1979 bna_llport_admin_down(&rx->bna->port.llport);
1980 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
1981 break;
1982 default:
1983 bfa_sm_fault(rx->bna, event);
1984 break;
1985 }
1986 }
1987
1988 void
1989 bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
1990 {
1991 bna_rxf_stop(&rx->rxf);
1992 }
1993
1994 void
1995 bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
1996 {
1997 switch (event) {
1998 case RX_E_RXF_STOPPED:
1999 bfa_fsm_set_state(rx, bna_rx_sm_rxq_stop_wait);
2000 break;
2001 case RX_E_RXF_STARTED:
2002 /**
2003 * RxF was in the process of starting up when
2004 * RXF_E_STOP was issued. Ignore this event
2005 */
2006 break;
2007 case RX_E_FAIL:
2008 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
2009 rx_ib_fail(rx);
2010 bna_rxf_fail(&rx->rxf);
2011 break;
2012 default:
2013 bfa_sm_fault(rx->bna, event);
2014 break;
2015 }
2016
2017 }
2018
2019 void
2020 bna_rx_sm_rxq_stop_wait_entry(struct bna_rx *rx)
2021 {
2022 struct bna_rxp *rxp = NULL;
2023 struct bna_rxq *q0 = NULL;
2024 struct bna_rxq *q1 = NULL;
2025 struct list_head *qe;
2026 u32 rxq_mask[2] = {0, 0};
2027
2028 /* Only one call to multi-rxq-stop for all RXPs in this RX */
2029 bfa_wc_up(&rx->rxq_stop_wc);
2030 list_for_each(qe, &rx->rxp_q) {
2031 rxp = (struct bna_rxp *)qe;
2032 GET_RXQS(rxp, q0, q1);
2033 if (q0->rxq_id < 32)
2034 rxq_mask[0] |= ((u32)1 << q0->rxq_id);
2035 else
2036 rxq_mask[1] |= ((u32)1 << (q0->rxq_id - 32));
2037 if (q1) {
2038 if (q1->rxq_id < 32)
2039 rxq_mask[0] |= ((u32)1 << q1->rxq_id);
2040 else
2041 rxq_mask[1] |= ((u32)
2042 1 << (q1->rxq_id - 32));
2043 }
2044 }
2045
2046 __bna_multi_rxq_stop(rxp, rxq_mask);
2047 }
2048
2049 void
2050 bna_rx_sm_rxq_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
2051 {
2052 struct bna_rxp *rxp = NULL;
2053 struct list_head *qe;
2054
2055 switch (event) {
2056 case RX_E_RXQ_STOPPED:
2057 list_for_each(qe, &rx->rxp_q) {
2058 rxp = (struct bna_rxp *)qe;
2059 bna_ib_stop(rxp->cq.ib);
2060 }
2061 /* Fall through */
2062 case RX_E_FAIL:
2063 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
2064 break;
2065 default:
2066 bfa_sm_fault(rx->bna, event);
2067 break;
2068 }
2069 }
2070
2071 void
2072 __bna_multi_rxq_stop(struct bna_rxp *rxp, u32 * rxq_id_mask)
2073 {
2074 struct bfi_ll_q_stop_req ll_req;
2075
2076 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RXQ_STOP_REQ, 0);
2077 ll_req.q_id_mask[0] = htonl(rxq_id_mask[0]);
2078 ll_req.q_id_mask[1] = htonl(rxq_id_mask[1]);
2079 bna_mbox_qe_fill(&rxp->mbox_qe, &ll_req, sizeof(ll_req),
2080 bna_rx_cb_multi_rxq_stopped, rxp);
2081 bna_mbox_send(rxp->rx->bna, &rxp->mbox_qe);
2082 }
2083
2084 void
2085 __bna_rxq_start(struct bna_rxq *rxq)
2086 {
2087 struct bna_rxtx_q_mem *q_mem;
2088 struct bna_rxq_mem rxq_cfg, *rxq_mem;
2089 struct bna_dma_addr cur_q_addr;
2090 /* struct bna_doorbell_qset *qset; */
2091 struct bna_qpt *qpt;
2092 u32 pg_num;
2093 struct bna *bna = rxq->rx->bna;
2094 void __iomem *base_addr;
2095 unsigned long off;
2096
2097 qpt = &rxq->qpt;
2098 cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
2099
2100 rxq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
2101 rxq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
2102 rxq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
2103 rxq_cfg.cur_q_entry_hi = cur_q_addr.msb;
2104
2105 rxq_cfg.pg_cnt_n_prd_ptr = ((u32)qpt->page_count << 16) | 0x0;
2106 rxq_cfg.entry_n_pg_size = ((u32)(BFI_RXQ_WI_SIZE >> 2) << 16) |
2107 (qpt->page_size >> 2);
2108 rxq_cfg.sg_n_cq_n_cns_ptr =
2109 ((u32)(rxq->rxp->cq.cq_id & 0xff) << 16) | 0x0;
2110 rxq_cfg.buf_sz_n_q_state = ((u32)rxq->buffer_size << 16) |
2111 BNA_Q_IDLE_STATE;
2112 rxq_cfg.next_qid = 0x0 | (0x3 << 8);
2113
2114 /* Write the page number register */
2115 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num,
2116 HQM_RXTX_Q_RAM_BASE_OFFSET);
2117 writel(pg_num, bna->regs.page_addr);
2118
2119 /* Write to h/w */
2120 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
2121 HQM_RXTX_Q_RAM_BASE_OFFSET);
2122
2123 q_mem = (struct bna_rxtx_q_mem *)0;
2124 rxq_mem = &q_mem[rxq->rxq_id].rxq;
2125
2126 off = (unsigned long)&rxq_mem->pg_tbl_addr_lo;
2127 writel(htonl(rxq_cfg.pg_tbl_addr_lo), base_addr + off);
2128
2129 off = (unsigned long)&rxq_mem->pg_tbl_addr_hi;
2130 writel(htonl(rxq_cfg.pg_tbl_addr_hi), base_addr + off);
2131
2132 off = (unsigned long)&rxq_mem->cur_q_entry_lo;
2133 writel(htonl(rxq_cfg.cur_q_entry_lo), base_addr + off);
2134
2135 off = (unsigned long)&rxq_mem->cur_q_entry_hi;
2136 writel(htonl(rxq_cfg.cur_q_entry_hi), base_addr + off);
2137
2138 off = (unsigned long)&rxq_mem->pg_cnt_n_prd_ptr;
2139 writel(rxq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
2140
2141 off = (unsigned long)&rxq_mem->entry_n_pg_size;
2142 writel(rxq_cfg.entry_n_pg_size, base_addr + off);
2143
2144 off = (unsigned long)&rxq_mem->sg_n_cq_n_cns_ptr;
2145 writel(rxq_cfg.sg_n_cq_n_cns_ptr, base_addr + off);
2146
2147 off = (unsigned long)&rxq_mem->buf_sz_n_q_state;
2148 writel(rxq_cfg.buf_sz_n_q_state, base_addr + off);
2149
2150 off = (unsigned long)&rxq_mem->next_qid;
2151 writel(rxq_cfg.next_qid, base_addr + off);
2152
2153 rxq->rcb->producer_index = 0;
2154 rxq->rcb->consumer_index = 0;
2155 }
2156
2157 void
2158 __bna_cq_start(struct bna_cq *cq)
2159 {
2160 struct bna_cq_mem cq_cfg, *cq_mem;
2161 const struct bna_qpt *qpt;
2162 struct bna_dma_addr cur_q_addr;
2163 u32 pg_num;
2164 struct bna *bna = cq->rx->bna;
2165 void __iomem *base_addr;
2166 unsigned long off;
2167
2168 qpt = &cq->qpt;
2169 cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
2170
2171 /*
2172 * Fill out structure, to be subsequently written
2173 * to hardware
2174 */
2175 cq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
2176 cq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
2177 cq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
2178 cq_cfg.cur_q_entry_hi = cur_q_addr.msb;
2179
2180 cq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0;
2181 cq_cfg.entry_n_pg_size =
2182 ((u32)(BFI_CQ_WI_SIZE >> 2) << 16) | (qpt->page_size >> 2);
2183 cq_cfg.int_blk_n_cns_ptr = ((((u32)cq->ib_seg_offset) << 24) |
2184 ((u32)(cq->ib->ib_id & 0xff) << 16) | 0x0);
2185 cq_cfg.q_state = BNA_Q_IDLE_STATE;
2186
2187 /* Write the page number register */
2188 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num,
2189 HQM_CQ_RAM_BASE_OFFSET);
2190
2191 writel(pg_num, bna->regs.page_addr);
2192
2193 /* H/W write */
2194 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
2195 HQM_CQ_RAM_BASE_OFFSET);
2196
2197 cq_mem = (struct bna_cq_mem *)0;
2198
2199 off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_lo;
2200 writel(htonl(cq_cfg.pg_tbl_addr_lo), base_addr + off);
2201
2202 off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_hi;
2203 writel(htonl(cq_cfg.pg_tbl_addr_hi), base_addr + off);
2204
2205 off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_lo;
2206 writel(htonl(cq_cfg.cur_q_entry_lo), base_addr + off);
2207
2208 off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_hi;
2209 writel(htonl(cq_cfg.cur_q_entry_hi), base_addr + off);
2210
2211 off = (unsigned long)&cq_mem[cq->cq_id].pg_cnt_n_prd_ptr;
2212 writel(cq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
2213
2214 off = (unsigned long)&cq_mem[cq->cq_id].entry_n_pg_size;
2215 writel(cq_cfg.entry_n_pg_size, base_addr + off);
2216
2217 off = (unsigned long)&cq_mem[cq->cq_id].int_blk_n_cns_ptr;
2218 writel(cq_cfg.int_blk_n_cns_ptr, base_addr + off);
2219
2220 off = (unsigned long)&cq_mem[cq->cq_id].q_state;
2221 writel(cq_cfg.q_state, base_addr + off);
2222
2223 cq->ccb->producer_index = 0;
2224 *(cq->ccb->hw_producer_index) = 0;
2225 }
2226
2227 void
2228 bna_rit_create(struct bna_rx *rx)
2229 {
2230 struct list_head *qe_rxp;
2231 struct bna *bna;
2232 struct bna_rxp *rxp;
2233 struct bna_rxq *q0 = NULL;
2234 struct bna_rxq *q1 = NULL;
2235 int offset;
2236
2237 bna = rx->bna;
2238
2239 offset = 0;
2240 list_for_each(qe_rxp, &rx->rxp_q) {
2241 rxp = (struct bna_rxp *)qe_rxp;
2242 GET_RXQS(rxp, q0, q1);
2243 rx->rxf.rit_segment->rit[offset].large_rxq_id = q0->rxq_id;
2244 rx->rxf.rit_segment->rit[offset].small_rxq_id =
2245 (q1 ? q1->rxq_id : 0);
2246 offset++;
2247 }
2248 }
2249
2250 int
2251 _rx_can_satisfy(struct bna_rx_mod *rx_mod,
2252 struct bna_rx_config *rx_cfg)
2253 {
2254 if ((rx_mod->rx_free_count == 0) ||
2255 (rx_mod->rxp_free_count == 0) ||
2256 (rx_mod->rxq_free_count == 0))
2257 return 0;
2258
2259 if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
2260 if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
2261 (rx_mod->rxq_free_count < rx_cfg->num_paths))
2262 return 0;
2263 } else {
2264 if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
2265 (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
2266 return 0;
2267 }
2268
2269 if (!bna_rit_mod_can_satisfy(&rx_mod->bna->rit_mod, rx_cfg->num_paths))
2270 return 0;
2271
2272 return 1;
2273 }
2274
2275 struct bna_rxq *
2276 _get_free_rxq(struct bna_rx_mod *rx_mod)
2277 {
2278 struct bna_rxq *rxq = NULL;
2279 struct list_head *qe = NULL;
2280
2281 bfa_q_deq(&rx_mod->rxq_free_q, &qe);
2282 if (qe) {
2283 rx_mod->rxq_free_count--;
2284 rxq = (struct bna_rxq *)qe;
2285 }
2286 return rxq;
2287 }
2288
2289 void
2290 _put_free_rxq(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
2291 {
2292 bfa_q_qe_init(&rxq->qe);
2293 list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
2294 rx_mod->rxq_free_count++;
2295 }
2296
2297 struct bna_rxp *
2298 _get_free_rxp(struct bna_rx_mod *rx_mod)
2299 {
2300 struct list_head *qe = NULL;
2301 struct bna_rxp *rxp = NULL;
2302
2303 bfa_q_deq(&rx_mod->rxp_free_q, &qe);
2304 if (qe) {
2305 rx_mod->rxp_free_count--;
2306
2307 rxp = (struct bna_rxp *)qe;
2308 }
2309
2310 return rxp;
2311 }
2312
2313 void
2314 _put_free_rxp(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
2315 {
2316 bfa_q_qe_init(&rxp->qe);
2317 list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
2318 rx_mod->rxp_free_count++;
2319 }
2320
2321 struct bna_rx *
2322 _get_free_rx(struct bna_rx_mod *rx_mod)
2323 {
2324 struct list_head *qe = NULL;
2325 struct bna_rx *rx = NULL;
2326
2327 bfa_q_deq(&rx_mod->rx_free_q, &qe);
2328 if (qe) {
2329 rx_mod->rx_free_count--;
2330
2331 rx = (struct bna_rx *)qe;
2332 bfa_q_qe_init(qe);
2333 list_add_tail(&rx->qe, &rx_mod->rx_active_q);
2334 }
2335
2336 return rx;
2337 }
2338
2339 void
2340 _put_free_rx(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
2341 {
2342 bfa_q_qe_init(&rx->qe);
2343 list_add_tail(&rx->qe, &rx_mod->rx_free_q);
2344 rx_mod->rx_free_count++;
2345 }
2346
2347 void
2348 _rx_init(struct bna_rx *rx, struct bna *bna)
2349 {
2350 rx->bna = bna;
2351 rx->rx_flags = 0;
2352
2353 INIT_LIST_HEAD(&rx->rxp_q);
2354
2355 rx->rxq_stop_wc.wc_resume = bna_rx_cb_rxq_stopped_all;
2356 rx->rxq_stop_wc.wc_cbarg = rx;
2357 rx->rxq_stop_wc.wc_count = 0;
2358
2359 rx->stop_cbfn = NULL;
2360 rx->stop_cbarg = NULL;
2361 }
2362
2363 void
2364 _rxp_add_rxqs(struct bna_rxp *rxp,
2365 struct bna_rxq *q0,
2366 struct bna_rxq *q1)
2367 {
2368 switch (rxp->type) {
2369 case BNA_RXP_SINGLE:
2370 rxp->rxq.single.only = q0;
2371 rxp->rxq.single.reserved = NULL;
2372 break;
2373 case BNA_RXP_SLR:
2374 rxp->rxq.slr.large = q0;
2375 rxp->rxq.slr.small = q1;
2376 break;
2377 case BNA_RXP_HDS:
2378 rxp->rxq.hds.data = q0;
2379 rxp->rxq.hds.hdr = q1;
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385
2386 void
2387 _rxq_qpt_init(struct bna_rxq *rxq,
2388 struct bna_rxp *rxp,
2389 u32 page_count,
2390 u32 page_size,
2391 struct bna_mem_descr *qpt_mem,
2392 struct bna_mem_descr *swqpt_mem,
2393 struct bna_mem_descr *page_mem)
2394 {
2395 int i;
2396
2397 rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
2398 rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
2399 rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
2400 rxq->qpt.page_count = page_count;
2401 rxq->qpt.page_size = page_size;
2402
2403 rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
2404
2405 for (i = 0; i < rxq->qpt.page_count; i++) {
2406 rxq->rcb->sw_qpt[i] = page_mem[i].kva;
2407 ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
2408 page_mem[i].dma.lsb;
2409 ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
2410 page_mem[i].dma.msb;
2411
2412 }
2413 }
2414
2415 void
2416 _rxp_cqpt_setup(struct bna_rxp *rxp,
2417 u32 page_count,
2418 u32 page_size,
2419 struct bna_mem_descr *qpt_mem,
2420 struct bna_mem_descr *swqpt_mem,
2421 struct bna_mem_descr *page_mem)
2422 {
2423 int i;
2424
2425 rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
2426 rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
2427 rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
2428 rxp->cq.qpt.page_count = page_count;
2429 rxp->cq.qpt.page_size = page_size;
2430
2431 rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
2432
2433 for (i = 0; i < rxp->cq.qpt.page_count; i++) {
2434 rxp->cq.ccb->sw_qpt[i] = page_mem[i].kva;
2435
2436 ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
2437 page_mem[i].dma.lsb;
2438 ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
2439 page_mem[i].dma.msb;
2440
2441 }
2442 }
2443
2444 void
2445 _rx_add_rxp(struct bna_rx *rx, struct bna_rxp *rxp)
2446 {
2447 list_add_tail(&rxp->qe, &rx->rxp_q);
2448 }
2449
2450 void
2451 _init_rxmod_queues(struct bna_rx_mod *rx_mod)
2452 {
2453 INIT_LIST_HEAD(&rx_mod->rx_free_q);
2454 INIT_LIST_HEAD(&rx_mod->rxq_free_q);
2455 INIT_LIST_HEAD(&rx_mod->rxp_free_q);
2456 INIT_LIST_HEAD(&rx_mod->rx_active_q);
2457
2458 rx_mod->rx_free_count = 0;
2459 rx_mod->rxq_free_count = 0;
2460 rx_mod->rxp_free_count = 0;
2461 }
2462
2463 void
2464 _rx_ctor(struct bna_rx *rx, int id)
2465 {
2466 bfa_q_qe_init(&rx->qe);
2467 INIT_LIST_HEAD(&rx->rxp_q);
2468 rx->bna = NULL;
2469
2470 rx->rxf.rxf_id = id;
2471
2472 /* FIXME: mbox_qe ctor()?? */
2473 bfa_q_qe_init(&rx->mbox_qe.qe);
2474
2475 rx->stop_cbfn = NULL;
2476 rx->stop_cbarg = NULL;
2477 }
2478
2479 void
2480 bna_rx_cb_multi_rxq_stopped(void *arg, int status)
2481 {
2482 struct bna_rxp *rxp = (struct bna_rxp *)arg;
2483
2484 bfa_wc_down(&rxp->rx->rxq_stop_wc);
2485 }
2486
2487 void
2488 bna_rx_cb_rxq_stopped_all(void *arg)
2489 {
2490 struct bna_rx *rx = (struct bna_rx *)arg;
2491
2492 bfa_fsm_send_event(rx, RX_E_RXQ_STOPPED);
2493 }
2494
2495 void
2496 bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx,
2497 enum bna_cb_status status)
2498 {
2499 struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
2500
2501 bfa_wc_down(&rx_mod->rx_stop_wc);
2502 }
2503
2504 void
2505 bna_rx_mod_cb_rx_stopped_all(void *arg)
2506 {
2507 struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
2508
2509 if (rx_mod->stop_cbfn)
2510 rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS);
2511 rx_mod->stop_cbfn = NULL;
2512 }
2513
2514 void
2515 bna_rx_start(struct bna_rx *rx)
2516 {
2517 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2518 if (rx->rx_flags & BNA_RX_F_ENABLE)
2519 bfa_fsm_send_event(rx, RX_E_START);
2520 }
2521
2522 void
2523 bna_rx_stop(struct bna_rx *rx)
2524 {
2525 rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED;
2526 if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
2527 bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx, BNA_CB_SUCCESS);
2528 else {
2529 rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
2530 rx->stop_cbarg = &rx->bna->rx_mod;
2531 bfa_fsm_send_event(rx, RX_E_STOP);
2532 }
2533 }
2534
2535 void
2536 bna_rx_fail(struct bna_rx *rx)
2537 {
2538 /* Indicate port is not enabled, and failed */
2539 rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED;
2540 rx->rx_flags |= BNA_RX_F_PORT_FAILED;
2541 bfa_fsm_send_event(rx, RX_E_FAIL);
2542 }
2543
2544 void
2545 bna_rx_cb_rxf_started(struct bna_rx *rx, enum bna_cb_status status)
2546 {
2547 bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
2548 if (rx->rxf.rxf_id < 32)
2549 rx->bna->rx_mod.rxf_bmap[0] |= ((u32)1 << rx->rxf.rxf_id);
2550 else
2551 rx->bna->rx_mod.rxf_bmap[1] |= ((u32)
2552 1 << (rx->rxf.rxf_id - 32));
2553 }
2554
2555 void
2556 bna_rx_cb_rxf_stopped(struct bna_rx *rx, enum bna_cb_status status)
2557 {
2558 bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
2559 if (rx->rxf.rxf_id < 32)
2560 rx->bna->rx_mod.rxf_bmap[0] &= ~(u32)1 << rx->rxf.rxf_id;
2561 else
2562 rx->bna->rx_mod.rxf_bmap[1] &= ~(u32)
2563 1 << (rx->rxf.rxf_id - 32);
2564 }
2565
2566 void
2567 bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
2568 {
2569 struct bna_rx *rx;
2570 struct list_head *qe;
2571
2572 rx_mod->flags |= BNA_RX_MOD_F_PORT_STARTED;
2573 if (type == BNA_RX_T_LOOPBACK)
2574 rx_mod->flags |= BNA_RX_MOD_F_PORT_LOOPBACK;
2575
2576 list_for_each(qe, &rx_mod->rx_active_q) {
2577 rx = (struct bna_rx *)qe;
2578 if (rx->type == type)
2579 bna_rx_start(rx);
2580 }
2581 }
2582
2583 void
2584 bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
2585 {
2586 struct bna_rx *rx;
2587 struct list_head *qe;
2588
2589 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED;
2590 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK;
2591
2592 rx_mod->stop_cbfn = bna_port_cb_rx_stopped;
2593
2594 /**
2595 * Before calling bna_rx_stop(), increment rx_stop_wc as many times
2596 * as we are going to call bna_rx_stop
2597 */
2598 list_for_each(qe, &rx_mod->rx_active_q) {
2599 rx = (struct bna_rx *)qe;
2600 if (rx->type == type)
2601 bfa_wc_up(&rx_mod->rx_stop_wc);
2602 }
2603
2604 if (rx_mod->rx_stop_wc.wc_count == 0) {
2605 rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS);
2606 rx_mod->stop_cbfn = NULL;
2607 return;
2608 }
2609
2610 list_for_each(qe, &rx_mod->rx_active_q) {
2611 rx = (struct bna_rx *)qe;
2612 if (rx->type == type)
2613 bna_rx_stop(rx);
2614 }
2615 }
2616
2617 void
2618 bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
2619 {
2620 struct bna_rx *rx;
2621 struct list_head *qe;
2622
2623 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED;
2624 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK;
2625
2626 list_for_each(qe, &rx_mod->rx_active_q) {
2627 rx = (struct bna_rx *)qe;
2628 bna_rx_fail(rx);
2629 }
2630 }
2631
2632 void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
2633 struct bna_res_info *res_info)
2634 {
2635 int index;
2636 struct bna_rx *rx_ptr;
2637 struct bna_rxp *rxp_ptr;
2638 struct bna_rxq *rxq_ptr;
2639
2640 rx_mod->bna = bna;
2641 rx_mod->flags = 0;
2642
2643 rx_mod->rx = (struct bna_rx *)
2644 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
2645 rx_mod->rxp = (struct bna_rxp *)
2646 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
2647 rx_mod->rxq = (struct bna_rxq *)
2648 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
2649
2650 /* Initialize the queues */
2651 _init_rxmod_queues(rx_mod);
2652
2653 /* Build RX queues */
2654 for (index = 0; index < BFI_MAX_RXQ; index++) {
2655 rx_ptr = &rx_mod->rx[index];
2656 _rx_ctor(rx_ptr, index);
2657 list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
2658 rx_mod->rx_free_count++;
2659 }
2660
2661 /* build RX-path queue */
2662 for (index = 0; index < BFI_MAX_RXQ; index++) {
2663 rxp_ptr = &rx_mod->rxp[index];
2664 rxp_ptr->cq.cq_id = index;
2665 bfa_q_qe_init(&rxp_ptr->qe);
2666 list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
2667 rx_mod->rxp_free_count++;
2668 }
2669
2670 /* build RXQ queue */
2671 for (index = 0; index < BFI_MAX_RXQ; index++) {
2672 rxq_ptr = &rx_mod->rxq[index];
2673 rxq_ptr->rxq_id = index;
2674
2675 bfa_q_qe_init(&rxq_ptr->qe);
2676 list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
2677 rx_mod->rxq_free_count++;
2678 }
2679
2680 rx_mod->rx_stop_wc.wc_resume = bna_rx_mod_cb_rx_stopped_all;
2681 rx_mod->rx_stop_wc.wc_cbarg = rx_mod;
2682 rx_mod->rx_stop_wc.wc_count = 0;
2683 }
2684
2685 void
2686 bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
2687 {
2688 struct list_head *qe;
2689 int i;
2690
2691 i = 0;
2692 list_for_each(qe, &rx_mod->rx_free_q)
2693 i++;
2694
2695 i = 0;
2696 list_for_each(qe, &rx_mod->rxp_free_q)
2697 i++;
2698
2699 i = 0;
2700 list_for_each(qe, &rx_mod->rxq_free_q)
2701 i++;
2702
2703 rx_mod->bna = NULL;
2704 }
2705
2706 int
2707 bna_rx_state_get(struct bna_rx *rx)
2708 {
2709 return bfa_sm_to_state(rx_sm_table, rx->fsm);
2710 }
2711
2712 void
2713 bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
2714 {
2715 u32 cq_size, hq_size, dq_size;
2716 u32 cpage_count, hpage_count, dpage_count;
2717 struct bna_mem_info *mem_info;
2718 u32 cq_depth;
2719 u32 hq_depth;
2720 u32 dq_depth;
2721
2722 dq_depth = q_cfg->q_depth;
2723 hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
2724 cq_depth = dq_depth + hq_depth;
2725
2726 BNA_TO_POWER_OF_2_HIGH(cq_depth);
2727 cq_size = cq_depth * BFI_CQ_WI_SIZE;
2728 cq_size = ALIGN(cq_size, PAGE_SIZE);
2729 cpage_count = SIZE_TO_PAGES(cq_size);
2730
2731 BNA_TO_POWER_OF_2_HIGH(dq_depth);
2732 dq_size = dq_depth * BFI_RXQ_WI_SIZE;
2733 dq_size = ALIGN(dq_size, PAGE_SIZE);
2734 dpage_count = SIZE_TO_PAGES(dq_size);
2735
2736 if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
2737 BNA_TO_POWER_OF_2_HIGH(hq_depth);
2738 hq_size = hq_depth * BFI_RXQ_WI_SIZE;
2739 hq_size = ALIGN(hq_size, PAGE_SIZE);
2740 hpage_count = SIZE_TO_PAGES(hq_size);
2741 } else {
2742 hpage_count = 0;
2743 }
2744
2745 /* CCB structures */
2746 res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
2747 mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
2748 mem_info->mem_type = BNA_MEM_T_KVA;
2749 mem_info->len = sizeof(struct bna_ccb);
2750 mem_info->num = q_cfg->num_paths;
2751
2752 /* RCB structures */
2753 res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
2754 mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
2755 mem_info->mem_type = BNA_MEM_T_KVA;
2756 mem_info->len = sizeof(struct bna_rcb);
2757 mem_info->num = BNA_GET_RXQS(q_cfg);
2758
2759 /* Completion QPT */
2760 res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
2761 mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
2762 mem_info->mem_type = BNA_MEM_T_DMA;
2763 mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
2764 mem_info->num = q_cfg->num_paths;
2765
2766 /* Completion s/w QPT */
2767 res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
2768 mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
2769 mem_info->mem_type = BNA_MEM_T_KVA;
2770 mem_info->len = cpage_count * sizeof(void *);
2771 mem_info->num = q_cfg->num_paths;
2772
2773 /* Completion QPT pages */
2774 res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
2775 mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
2776 mem_info->mem_type = BNA_MEM_T_DMA;
2777 mem_info->len = PAGE_SIZE;
2778 mem_info->num = cpage_count * q_cfg->num_paths;
2779
2780 /* Data QPTs */
2781 res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
2782 mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
2783 mem_info->mem_type = BNA_MEM_T_DMA;
2784 mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
2785 mem_info->num = q_cfg->num_paths;
2786
2787 /* Data s/w QPTs */
2788 res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
2789 mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
2790 mem_info->mem_type = BNA_MEM_T_KVA;
2791 mem_info->len = dpage_count * sizeof(void *);
2792 mem_info->num = q_cfg->num_paths;
2793
2794 /* Data QPT pages */
2795 res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
2796 mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
2797 mem_info->mem_type = BNA_MEM_T_DMA;
2798 mem_info->len = PAGE_SIZE;
2799 mem_info->num = dpage_count * q_cfg->num_paths;
2800
2801 /* Hdr QPTs */
2802 res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
2803 mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
2804 mem_info->mem_type = BNA_MEM_T_DMA;
2805 mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
2806 mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
2807
2808 /* Hdr s/w QPTs */
2809 res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
2810 mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
2811 mem_info->mem_type = BNA_MEM_T_KVA;
2812 mem_info->len = hpage_count * sizeof(void *);
2813 mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
2814
2815 /* Hdr QPT pages */
2816 res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
2817 mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
2818 mem_info->mem_type = BNA_MEM_T_DMA;
2819 mem_info->len = (hpage_count ? PAGE_SIZE : 0);
2820 mem_info->num = (hpage_count ? (hpage_count * q_cfg->num_paths) : 0);
2821
2822 /* RX Interrupts */
2823 res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
2824 res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
2825 res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
2826 }
2827
2828 struct bna_rx *
2829 bna_rx_create(struct bna *bna, struct bnad *bnad,
2830 struct bna_rx_config *rx_cfg,
2831 struct bna_rx_event_cbfn *rx_cbfn,
2832 struct bna_res_info *res_info,
2833 void *priv)
2834 {
2835 struct bna_rx_mod *rx_mod = &bna->rx_mod;
2836 struct bna_rx *rx;
2837 struct bna_rxp *rxp;
2838 struct bna_rxq *q0;
2839 struct bna_rxq *q1;
2840 struct bna_intr_info *intr_info;
2841 u32 page_count;
2842 struct bna_mem_descr *ccb_mem;
2843 struct bna_mem_descr *rcb_mem;
2844 struct bna_mem_descr *unmapq_mem;
2845 struct bna_mem_descr *cqpt_mem;
2846 struct bna_mem_descr *cswqpt_mem;
2847 struct bna_mem_descr *cpage_mem;
2848 struct bna_mem_descr *hqpt_mem; /* Header/Small Q qpt */
2849 struct bna_mem_descr *dqpt_mem; /* Data/Large Q qpt */
2850 struct bna_mem_descr *hsqpt_mem; /* s/w qpt for hdr */
2851 struct bna_mem_descr *dsqpt_mem; /* s/w qpt for data */
2852 struct bna_mem_descr *hpage_mem; /* hdr page mem */
2853 struct bna_mem_descr *dpage_mem; /* data page mem */
2854 int i, cpage_idx = 0, dpage_idx = 0, hpage_idx = 0, ret;
2855 int dpage_count, hpage_count, rcb_idx;
2856 struct bna_ib_config ibcfg;
2857 /* Fail if we don't have enough RXPs, RXQs */
2858 if (!_rx_can_satisfy(rx_mod, rx_cfg))
2859 return NULL;
2860
2861 /* Initialize resource pointers */
2862 intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2863 ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
2864 rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
2865 unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
2866 cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
2867 cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
2868 cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
2869 hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
2870 dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
2871 hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
2872 dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
2873 hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
2874 dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
2875
2876 /* Compute q depth & page count */
2877 page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.num /
2878 rx_cfg->num_paths;
2879
2880 dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.num /
2881 rx_cfg->num_paths;
2882
2883 hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.num /
2884 rx_cfg->num_paths;
2885 /* Get RX pointer */
2886 rx = _get_free_rx(rx_mod);
2887 _rx_init(rx, bna);
2888 rx->priv = priv;
2889 rx->type = rx_cfg->rx_type;
2890
2891 rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
2892 rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
2893 rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
2894 rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
2895 /* Following callbacks are mandatory */
2896 rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
2897 rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
2898
2899 if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_STARTED) {
2900 switch (rx->type) {
2901 case BNA_RX_T_REGULAR:
2902 if (!(rx->bna->rx_mod.flags &
2903 BNA_RX_MOD_F_PORT_LOOPBACK))
2904 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2905 break;
2906 case BNA_RX_T_LOOPBACK:
2907 if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_LOOPBACK)
2908 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2909 break;
2910 }
2911 }
2912
2913 for (i = 0, rcb_idx = 0; i < rx_cfg->num_paths; i++) {
2914 rxp = _get_free_rxp(rx_mod);
2915 rxp->type = rx_cfg->rxp_type;
2916 rxp->rx = rx;
2917 rxp->cq.rx = rx;
2918
2919 /* Get required RXQs, and queue them to rx-path */
2920 q0 = _get_free_rxq(rx_mod);
2921 if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
2922 q1 = NULL;
2923 else
2924 q1 = _get_free_rxq(rx_mod);
2925
2926 /* Initialize IB */
2927 if (1 == intr_info->num) {
2928 rxp->cq.ib = bna_ib_get(&bna->ib_mod,
2929 intr_info->intr_type,
2930 intr_info->idl[0].vector);
2931 rxp->vector = intr_info->idl[0].vector;
2932 } else {
2933 rxp->cq.ib = bna_ib_get(&bna->ib_mod,
2934 intr_info->intr_type,
2935 intr_info->idl[i].vector);
2936
2937 /* Map the MSI-x vector used for this RXP */
2938 rxp->vector = intr_info->idl[i].vector;
2939 }
2940
2941 rxp->cq.ib_seg_offset = bna_ib_reserve_idx(rxp->cq.ib);
2942
2943 ibcfg.coalescing_timeo = BFI_RX_COALESCING_TIMEO;
2944 ibcfg.interpkt_count = BFI_RX_INTERPKT_COUNT;
2945 ibcfg.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
2946 ibcfg.ctrl_flags = BFI_IB_CF_INT_ENABLE;
2947
2948 ret = bna_ib_config(rxp->cq.ib, &ibcfg);
2949
2950 /* Link rxqs to rxp */
2951 _rxp_add_rxqs(rxp, q0, q1);
2952
2953 /* Link rxp to rx */
2954 _rx_add_rxp(rx, rxp);
2955
2956 q0->rx = rx;
2957 q0->rxp = rxp;
2958
2959 /* Initialize RCB for the large / data q */
2960 q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
2961 RXQ_RCB_INIT(q0, rxp, rx_cfg->q_depth, bna, 0,
2962 (void *)unmapq_mem[rcb_idx].kva);
2963 rcb_idx++;
2964 (q0)->rx_packets = (q0)->rx_bytes = 0;
2965 (q0)->rx_packets_with_error = (q0)->rxbuf_alloc_failed = 0;
2966
2967 /* Initialize RXQs */
2968 _rxq_qpt_init(q0, rxp, dpage_count, PAGE_SIZE,
2969 &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[dpage_idx]);
2970 q0->rcb->page_idx = dpage_idx;
2971 q0->rcb->page_count = dpage_count;
2972 dpage_idx += dpage_count;
2973
2974 /* Call bnad to complete rcb setup */
2975 if (rx->rcb_setup_cbfn)
2976 rx->rcb_setup_cbfn(bnad, q0->rcb);
2977
2978 if (q1) {
2979 q1->rx = rx;
2980 q1->rxp = rxp;
2981
2982 q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
2983 RXQ_RCB_INIT(q1, rxp, rx_cfg->q_depth, bna, 1,
2984 (void *)unmapq_mem[rcb_idx].kva);
2985 rcb_idx++;
2986 (q1)->buffer_size = (rx_cfg)->small_buff_size;
2987 (q1)->rx_packets = (q1)->rx_bytes = 0;
2988 (q1)->rx_packets_with_error =
2989 (q1)->rxbuf_alloc_failed = 0;
2990
2991 _rxq_qpt_init(q1, rxp, hpage_count, PAGE_SIZE,
2992 &hqpt_mem[i], &hsqpt_mem[i],
2993 &hpage_mem[hpage_idx]);
2994 q1->rcb->page_idx = hpage_idx;
2995 q1->rcb->page_count = hpage_count;
2996 hpage_idx += hpage_count;
2997
2998 /* Call bnad to complete rcb setup */
2999 if (rx->rcb_setup_cbfn)
3000 rx->rcb_setup_cbfn(bnad, q1->rcb);
3001 }
3002 /* Setup RXP::CQ */
3003 rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
3004 _rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
3005 &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[cpage_idx]);
3006 rxp->cq.ccb->page_idx = cpage_idx;
3007 rxp->cq.ccb->page_count = page_count;
3008 cpage_idx += page_count;
3009
3010 rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
3011 rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
3012
3013 rxp->cq.ccb->producer_index = 0;
3014 rxp->cq.ccb->q_depth = rx_cfg->q_depth +
3015 ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
3016 0 : rx_cfg->q_depth);
3017 rxp->cq.ccb->i_dbell = &rxp->cq.ib->door_bell;
3018 rxp->cq.ccb->rcb[0] = q0->rcb;
3019 if (q1)
3020 rxp->cq.ccb->rcb[1] = q1->rcb;
3021 rxp->cq.ccb->cq = &rxp->cq;
3022 rxp->cq.ccb->bnad = bna->bnad;
3023 rxp->cq.ccb->hw_producer_index =
3024 ((volatile u32 *)rxp->cq.ib->ib_seg_host_addr_kva +
3025 (rxp->cq.ib_seg_offset * BFI_IBIDX_SIZE));
3026 *(rxp->cq.ccb->hw_producer_index) = 0;
3027 rxp->cq.ccb->intr_type = intr_info->intr_type;
3028 rxp->cq.ccb->intr_vector = (intr_info->num == 1) ?
3029 intr_info->idl[0].vector :
3030 intr_info->idl[i].vector;
3031 rxp->cq.ccb->rx_coalescing_timeo =
3032 rxp->cq.ib->ib_config.coalescing_timeo;
3033 rxp->cq.ccb->id = i;
3034
3035 /* Call bnad to complete CCB setup */
3036 if (rx->ccb_setup_cbfn)
3037 rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
3038
3039 } /* for each rx-path */
3040
3041 bna_rxf_init(&rx->rxf, rx, rx_cfg);
3042
3043 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
3044
3045 return rx;
3046 }
3047
3048 void
3049 bna_rx_destroy(struct bna_rx *rx)
3050 {
3051 struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
3052 struct bna_ib_mod *ib_mod = &rx->bna->ib_mod;
3053 struct bna_rxq *q0 = NULL;
3054 struct bna_rxq *q1 = NULL;
3055 struct bna_rxp *rxp;
3056 struct list_head *qe;
3057
3058 bna_rxf_uninit(&rx->rxf);
3059
3060 while (!list_empty(&rx->rxp_q)) {
3061 bfa_q_deq(&rx->rxp_q, &rxp);
3062 GET_RXQS(rxp, q0, q1);
3063 /* Callback to bnad for destroying RCB */
3064 if (rx->rcb_destroy_cbfn)
3065 rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
3066 q0->rcb = NULL;
3067 q0->rxp = NULL;
3068 q0->rx = NULL;
3069 _put_free_rxq(rx_mod, q0);
3070 if (q1) {
3071 /* Callback to bnad for destroying RCB */
3072 if (rx->rcb_destroy_cbfn)
3073 rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
3074 q1->rcb = NULL;
3075 q1->rxp = NULL;
3076 q1->rx = NULL;
3077 _put_free_rxq(rx_mod, q1);
3078 }
3079 rxp->rxq.slr.large = NULL;
3080 rxp->rxq.slr.small = NULL;
3081 if (rxp->cq.ib) {
3082 if (rxp->cq.ib_seg_offset != 0xff)
3083 bna_ib_release_idx(rxp->cq.ib,
3084 rxp->cq.ib_seg_offset);
3085 bna_ib_put(ib_mod, rxp->cq.ib);
3086 rxp->cq.ib = NULL;
3087 }
3088 /* Callback to bnad for destroying CCB */
3089 if (rx->ccb_destroy_cbfn)
3090 rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
3091 rxp->cq.ccb = NULL;
3092 rxp->rx = NULL;
3093 _put_free_rxp(rx_mod, rxp);
3094 }
3095
3096 list_for_each(qe, &rx_mod->rx_active_q) {
3097 if (qe == &rx->qe) {
3098 list_del(&rx->qe);
3099 bfa_q_qe_init(&rx->qe);
3100 break;
3101 }
3102 }
3103
3104 rx->bna = NULL;
3105 rx->priv = NULL;
3106 _put_free_rx(rx_mod, rx);
3107 }
3108
3109 void
3110 bna_rx_enable(struct bna_rx *rx)
3111 {
3112 if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
3113 return;
3114
3115 rx->rx_flags |= BNA_RX_F_ENABLE;
3116 if (rx->rx_flags & BNA_RX_F_PORT_ENABLED)
3117 bfa_fsm_send_event(rx, RX_E_START);
3118 }
3119
3120 void
3121 bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
3122 void (*cbfn)(void *, struct bna_rx *,
3123 enum bna_cb_status))
3124 {
3125 if (type == BNA_SOFT_CLEANUP) {
3126 /* h/w should not be accessed. Treat we're stopped */
3127 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
3128 } else {
3129 rx->stop_cbfn = cbfn;
3130 rx->stop_cbarg = rx->bna->bnad;
3131
3132 rx->rx_flags &= ~BNA_RX_F_ENABLE;
3133
3134 bfa_fsm_send_event(rx, RX_E_STOP);
3135 }
3136 }
3137
3138 /**
3139 * TX
3140 */
3141 #define call_tx_stop_cbfn(tx, status)\
3142 do {\
3143 if ((tx)->stop_cbfn)\
3144 (tx)->stop_cbfn((tx)->stop_cbarg, (tx), status);\
3145 (tx)->stop_cbfn = NULL;\
3146 (tx)->stop_cbarg = NULL;\
3147 } while (0)
3148
3149 #define call_tx_prio_change_cbfn(tx, status)\
3150 do {\
3151 if ((tx)->prio_change_cbfn)\
3152 (tx)->prio_change_cbfn((tx)->bna->bnad, (tx), status);\
3153 (tx)->prio_change_cbfn = NULL;\
3154 } while (0)
3155
3156 static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx,
3157 enum bna_cb_status status);
3158 static void bna_tx_cb_txq_stopped(void *arg, int status);
3159 static void bna_tx_cb_stats_cleared(void *arg, int status);
3160 static void __bna_tx_stop(struct bna_tx *tx);
3161 static void __bna_tx_start(struct bna_tx *tx);
3162 static void __bna_txf_stat_clr(struct bna_tx *tx);
3163
3164 enum bna_tx_event {
3165 TX_E_START = 1,
3166 TX_E_STOP = 2,
3167 TX_E_FAIL = 3,
3168 TX_E_TXQ_STOPPED = 4,
3169 TX_E_PRIO_CHANGE = 5,
3170 TX_E_STAT_CLEARED = 6,
3171 };
3172
3173 enum bna_tx_state {
3174 BNA_TX_STOPPED = 1,
3175 BNA_TX_STARTED = 2,
3176 BNA_TX_TXQ_STOP_WAIT = 3,
3177 BNA_TX_PRIO_STOP_WAIT = 4,
3178 BNA_TX_STAT_CLR_WAIT = 5,
3179 };
3180
3181 bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx,
3182 enum bna_tx_event);
3183 bfa_fsm_state_decl(bna_tx, started, struct bna_tx,
3184 enum bna_tx_event);
3185 bfa_fsm_state_decl(bna_tx, txq_stop_wait, struct bna_tx,
3186 enum bna_tx_event);
3187 bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
3188 enum bna_tx_event);
3189 bfa_fsm_state_decl(bna_tx, stat_clr_wait, struct bna_tx,
3190 enum bna_tx_event);
3191
3192 static struct bfa_sm_table tx_sm_table[] = {
3193 {BFA_SM(bna_tx_sm_stopped), BNA_TX_STOPPED},
3194 {BFA_SM(bna_tx_sm_started), BNA_TX_STARTED},
3195 {BFA_SM(bna_tx_sm_txq_stop_wait), BNA_TX_TXQ_STOP_WAIT},
3196 {BFA_SM(bna_tx_sm_prio_stop_wait), BNA_TX_PRIO_STOP_WAIT},
3197 {BFA_SM(bna_tx_sm_stat_clr_wait), BNA_TX_STAT_CLR_WAIT},
3198 };
3199
3200 static void
3201 bna_tx_sm_stopped_entry(struct bna_tx *tx)
3202 {
3203 struct bna_txq *txq;
3204 struct list_head *qe;
3205
3206 list_for_each(qe, &tx->txq_q) {
3207 txq = (struct bna_txq *)qe;
3208 (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb);
3209 }
3210
3211 call_tx_stop_cbfn(tx, BNA_CB_SUCCESS);
3212 }
3213
3214 static void
3215 bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
3216 {
3217 switch (event) {
3218 case TX_E_START:
3219 bfa_fsm_set_state(tx, bna_tx_sm_started);
3220 break;
3221
3222 case TX_E_STOP:
3223 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3224 break;
3225
3226 case TX_E_FAIL:
3227 /* No-op */
3228 break;
3229
3230 case TX_E_PRIO_CHANGE:
3231 call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS);
3232 break;
3233
3234 case TX_E_TXQ_STOPPED:
3235 /**
3236 * This event is received due to flushing of mbox when
3237 * device fails
3238 */
3239 /* No-op */
3240 break;
3241
3242 default:
3243 bfa_sm_fault(tx->bna, event);
3244 }
3245 }
3246
3247 static void
3248 bna_tx_sm_started_entry(struct bna_tx *tx)
3249 {
3250 struct bna_txq *txq;
3251 struct list_head *qe;
3252
3253 __bna_tx_start(tx);
3254
3255 /* Start IB */
3256 list_for_each(qe, &tx->txq_q) {
3257 txq = (struct bna_txq *)qe;
3258 bna_ib_ack(&txq->ib->door_bell, 0);
3259 }
3260 }
3261
3262 static void
3263 bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
3264 {
3265 struct bna_txq *txq;
3266 struct list_head *qe;
3267
3268 switch (event) {
3269 case TX_E_STOP:
3270 bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait);
3271 __bna_tx_stop(tx);
3272 break;
3273
3274 case TX_E_FAIL:
3275 list_for_each(qe, &tx->txq_q) {
3276 txq = (struct bna_txq *)qe;
3277 bna_ib_fail(txq->ib);
3278 (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb);
3279 }
3280 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3281 break;
3282
3283 case TX_E_PRIO_CHANGE:
3284 bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
3285 break;
3286
3287 default:
3288 bfa_sm_fault(tx->bna, event);
3289 }
3290 }
3291
3292 static void
3293 bna_tx_sm_txq_stop_wait_entry(struct bna_tx *tx)
3294 {
3295 }
3296
3297 static void
3298 bna_tx_sm_txq_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
3299 {
3300 struct bna_txq *txq;
3301 struct list_head *qe;
3302
3303 switch (event) {
3304 case TX_E_FAIL:
3305 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3306 break;
3307
3308 case TX_E_TXQ_STOPPED:
3309 list_for_each(qe, &tx->txq_q) {
3310 txq = (struct bna_txq *)qe;
3311 bna_ib_stop(txq->ib);
3312 }
3313 bfa_fsm_set_state(tx, bna_tx_sm_stat_clr_wait);
3314 break;
3315
3316 case TX_E_PRIO_CHANGE:
3317 /* No-op */
3318 break;
3319
3320 default:
3321 bfa_sm_fault(tx->bna, event);
3322 }
3323 }
3324
3325 static void
3326 bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
3327 {
3328 __bna_tx_stop(tx);
3329 }
3330
3331 static void
3332 bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
3333 {
3334 struct bna_txq *txq;
3335 struct list_head *qe;
3336
3337 switch (event) {
3338 case TX_E_STOP:
3339 bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait);
3340 break;
3341
3342 case TX_E_FAIL:
3343 call_tx_prio_change_cbfn(tx, BNA_CB_FAIL);
3344 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3345 break;
3346
3347 case TX_E_TXQ_STOPPED:
3348 list_for_each(qe, &tx->txq_q) {
3349 txq = (struct bna_txq *)qe;
3350 bna_ib_stop(txq->ib);
3351 (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb);
3352 }
3353 call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS);
3354 bfa_fsm_set_state(tx, bna_tx_sm_started);
3355 break;
3356
3357 case TX_E_PRIO_CHANGE:
3358 /* No-op */
3359 break;
3360
3361 default:
3362 bfa_sm_fault(tx->bna, event);
3363 }
3364 }
3365
3366 static void
3367 bna_tx_sm_stat_clr_wait_entry(struct bna_tx *tx)
3368 {
3369 __bna_txf_stat_clr(tx);
3370 }
3371
3372 static void
3373 bna_tx_sm_stat_clr_wait(struct bna_tx *tx, enum bna_tx_event event)
3374 {
3375 switch (event) {
3376 case TX_E_FAIL:
3377 case TX_E_STAT_CLEARED:
3378 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3379 break;
3380
3381 default:
3382 bfa_sm_fault(tx->bna, event);
3383 }
3384 }
3385
3386 static void
3387 __bna_txq_start(struct bna_tx *tx, struct bna_txq *txq)
3388 {
3389 struct bna_rxtx_q_mem *q_mem;
3390 struct bna_txq_mem txq_cfg;
3391 struct bna_txq_mem *txq_mem;
3392 struct bna_dma_addr cur_q_addr;
3393 u32 pg_num;
3394 void __iomem *base_addr;
3395 unsigned long off;
3396
3397 /* Fill out structure, to be subsequently written to hardware */
3398 txq_cfg.pg_tbl_addr_lo = txq->qpt.hw_qpt_ptr.lsb;
3399 txq_cfg.pg_tbl_addr_hi = txq->qpt.hw_qpt_ptr.msb;
3400 cur_q_addr = *((struct bna_dma_addr *)(txq->qpt.kv_qpt_ptr));
3401 txq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
3402 txq_cfg.cur_q_entry_hi = cur_q_addr.msb;
3403
3404 txq_cfg.pg_cnt_n_prd_ptr = (txq->qpt.page_count << 16) | 0x0;
3405
3406 txq_cfg.entry_n_pg_size = ((u32)(BFI_TXQ_WI_SIZE >> 2) << 16) |
3407 (txq->qpt.page_size >> 2);
3408 txq_cfg.int_blk_n_cns_ptr = ((((u32)txq->ib_seg_offset) << 24) |
3409 ((u32)(txq->ib->ib_id & 0xff) << 16) | 0x0);
3410
3411 txq_cfg.cns_ptr2_n_q_state = BNA_Q_IDLE_STATE;
3412 txq_cfg.nxt_qid_n_fid_n_pri = (((tx->txf.txf_id & 0x3f) << 3) |
3413 (txq->priority & 0x3));
3414 txq_cfg.wvc_n_cquota_n_rquota =
3415 ((((u32)BFI_TX_MAX_WRR_QUOTA & 0xfff) << 12) |
3416 (BFI_TX_MAX_WRR_QUOTA & 0xfff));
3417
3418 /* Setup the page and write to H/W */
3419
3420 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + tx->bna->port_num,
3421 HQM_RXTX_Q_RAM_BASE_OFFSET);
3422 writel(pg_num, tx->bna->regs.page_addr);
3423
3424 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3425 HQM_RXTX_Q_RAM_BASE_OFFSET);
3426 q_mem = (struct bna_rxtx_q_mem *)0;
3427 txq_mem = &q_mem[txq->txq_id].txq;
3428
3429 /*
3430 * The following 4 lines, is a hack b'cos the H/W needs to read
3431 * these DMA addresses as little endian
3432 */
3433
3434 off = (unsigned long)&txq_mem->pg_tbl_addr_lo;
3435 writel(htonl(txq_cfg.pg_tbl_addr_lo), base_addr + off);
3436
3437 off = (unsigned long)&txq_mem->pg_tbl_addr_hi;
3438 writel(htonl(txq_cfg.pg_tbl_addr_hi), base_addr + off);
3439
3440 off = (unsigned long)&txq_mem->cur_q_entry_lo;
3441 writel(htonl(txq_cfg.cur_q_entry_lo), base_addr + off);
3442
3443 off = (unsigned long)&txq_mem->cur_q_entry_hi;
3444 writel(htonl(txq_cfg.cur_q_entry_hi), base_addr + off);
3445
3446 off = (unsigned long)&txq_mem->pg_cnt_n_prd_ptr;
3447 writel(txq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
3448
3449 off = (unsigned long)&txq_mem->entry_n_pg_size;
3450 writel(txq_cfg.entry_n_pg_size, base_addr + off);
3451
3452 off = (unsigned long)&txq_mem->int_blk_n_cns_ptr;
3453 writel(txq_cfg.int_blk_n_cns_ptr, base_addr + off);
3454
3455 off = (unsigned long)&txq_mem->cns_ptr2_n_q_state;
3456 writel(txq_cfg.cns_ptr2_n_q_state, base_addr + off);
3457
3458 off = (unsigned long)&txq_mem->nxt_qid_n_fid_n_pri;
3459 writel(txq_cfg.nxt_qid_n_fid_n_pri, base_addr + off);
3460
3461 off = (unsigned long)&txq_mem->wvc_n_cquota_n_rquota;
3462 writel(txq_cfg.wvc_n_cquota_n_rquota, base_addr + off);
3463
3464 txq->tcb->producer_index = 0;
3465 txq->tcb->consumer_index = 0;
3466 *(txq->tcb->hw_consumer_index) = 0;
3467
3468 }
3469
3470 static void
3471 __bna_txq_stop(struct bna_tx *tx, struct bna_txq *txq)
3472 {
3473 struct bfi_ll_q_stop_req ll_req;
3474 u32 bit_mask[2] = {0, 0};
3475 if (txq->txq_id < 32)
3476 bit_mask[0] = (u32)1 << txq->txq_id;
3477 else
3478 bit_mask[1] = (u32)1 << (txq->txq_id - 32);
3479
3480 memset(&ll_req, 0, sizeof(ll_req));
3481 ll_req.mh.msg_class = BFI_MC_LL;
3482 ll_req.mh.msg_id = BFI_LL_H2I_TXQ_STOP_REQ;
3483 ll_req.mh.mtag.h2i.lpu_id = 0;
3484 ll_req.q_id_mask[0] = htonl(bit_mask[0]);
3485 ll_req.q_id_mask[1] = htonl(bit_mask[1]);
3486
3487 bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req),
3488 bna_tx_cb_txq_stopped, tx);
3489
3490 bna_mbox_send(tx->bna, &tx->mbox_qe);
3491 }
3492
3493 static void
3494 __bna_txf_start(struct bna_tx *tx)
3495 {
3496 struct bna_tx_fndb_ram *tx_fndb;
3497 struct bna_txf *txf = &tx->txf;
3498 void __iomem *base_addr;
3499 unsigned long off;
3500
3501 writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
3502 (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET),
3503 tx->bna->regs.page_addr);
3504
3505 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3506 TX_FNDB_RAM_BASE_OFFSET);
3507
3508 tx_fndb = (struct bna_tx_fndb_ram *)0;
3509 off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags;
3510
3511 writel(((u32)txf->vlan << 16) | txf->ctrl_flags,
3512 base_addr + off);
3513
3514 if (tx->txf.txf_id < 32)
3515 tx->bna->tx_mod.txf_bmap[0] |= ((u32)1 << tx->txf.txf_id);
3516 else
3517 tx->bna->tx_mod.txf_bmap[1] |= ((u32)
3518 1 << (tx->txf.txf_id - 32));
3519 }
3520
3521 static void
3522 __bna_txf_stop(struct bna_tx *tx)
3523 {
3524 struct bna_tx_fndb_ram *tx_fndb;
3525 u32 page_num;
3526 u32 ctl_flags;
3527 struct bna_txf *txf = &tx->txf;
3528 void __iomem *base_addr;
3529 unsigned long off;
3530
3531 /* retrieve the running txf_flags & turn off enable bit */
3532 page_num = BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
3533 (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET);
3534 writel(page_num, tx->bna->regs.page_addr);
3535
3536 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3537 TX_FNDB_RAM_BASE_OFFSET);
3538 tx_fndb = (struct bna_tx_fndb_ram *)0;
3539 off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags;
3540
3541 ctl_flags = readl(base_addr + off);
3542 ctl_flags &= ~BFI_TXF_CF_ENABLE;
3543
3544 writel(ctl_flags, base_addr + off);
3545
3546 if (tx->txf.txf_id < 32)
3547 tx->bna->tx_mod.txf_bmap[0] &= ~((u32)1 << tx->txf.txf_id);
3548 else
3549 tx->bna->tx_mod.txf_bmap[0] &= ~((u32)
3550 1 << (tx->txf.txf_id - 32));
3551 }
3552
3553 static void
3554 __bna_txf_stat_clr(struct bna_tx *tx)
3555 {
3556 struct bfi_ll_stats_req ll_req;
3557 u32 txf_bmap[2] = {0, 0};
3558 if (tx->txf.txf_id < 32)
3559 txf_bmap[0] = ((u32)1 << tx->txf.txf_id);
3560 else
3561 txf_bmap[1] = ((u32)1 << (tx->txf.txf_id - 32));
3562 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
3563 ll_req.stats_mask = 0;
3564 ll_req.rxf_id_mask[0] = 0;
3565 ll_req.rxf_id_mask[1] = 0;
3566 ll_req.txf_id_mask[0] = htonl(txf_bmap[0]);
3567 ll_req.txf_id_mask[1] = htonl(txf_bmap[1]);
3568
3569 bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req),
3570 bna_tx_cb_stats_cleared, tx);
3571 bna_mbox_send(tx->bna, &tx->mbox_qe);
3572 }
3573
3574 static void
3575 __bna_tx_start(struct bna_tx *tx)
3576 {
3577 struct bna_txq *txq;
3578 struct list_head *qe;
3579
3580 list_for_each(qe, &tx->txq_q) {
3581 txq = (struct bna_txq *)qe;
3582 bna_ib_start(txq->ib);
3583 __bna_txq_start(tx, txq);
3584 }
3585
3586 __bna_txf_start(tx);
3587
3588 list_for_each(qe, &tx->txq_q) {
3589 txq = (struct bna_txq *)qe;
3590 txq->tcb->priority = txq->priority;
3591 (tx->tx_resume_cbfn)(tx->bna->bnad, txq->tcb);
3592 }
3593 }
3594
3595 static void
3596 __bna_tx_stop(struct bna_tx *tx)
3597 {
3598 struct bna_txq *txq;
3599 struct list_head *qe;
3600
3601 list_for_each(qe, &tx->txq_q) {
3602 txq = (struct bna_txq *)qe;
3603 (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb);
3604 }
3605
3606 __bna_txf_stop(tx);
3607
3608 list_for_each(qe, &tx->txq_q) {
3609 txq = (struct bna_txq *)qe;
3610 bfa_wc_up(&tx->txq_stop_wc);
3611 }
3612
3613 list_for_each(qe, &tx->txq_q) {
3614 txq = (struct bna_txq *)qe;
3615 __bna_txq_stop(tx, txq);
3616 }
3617 }
3618
3619 static void
3620 bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
3621 struct bna_mem_descr *qpt_mem,
3622 struct bna_mem_descr *swqpt_mem,
3623 struct bna_mem_descr *page_mem)
3624 {
3625 int i;
3626
3627 txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
3628 txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
3629 txq->qpt.kv_qpt_ptr = qpt_mem->kva;
3630 txq->qpt.page_count = page_count;
3631 txq->qpt.page_size = page_size;
3632
3633 txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
3634
3635 for (i = 0; i < page_count; i++) {
3636 txq->tcb->sw_qpt[i] = page_mem[i].kva;
3637
3638 ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
3639 page_mem[i].dma.lsb;
3640 ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
3641 page_mem[i].dma.msb;
3642
3643 }
3644 }
3645
3646 static void
3647 bna_tx_free(struct bna_tx *tx)
3648 {
3649 struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
3650 struct bna_txq *txq;
3651 struct bna_ib_mod *ib_mod = &tx->bna->ib_mod;
3652 struct list_head *qe;
3653
3654 while (!list_empty(&tx->txq_q)) {
3655 bfa_q_deq(&tx->txq_q, &txq);
3656 bfa_q_qe_init(&txq->qe);
3657 if (txq->ib) {
3658 if (txq->ib_seg_offset != -1)
3659 bna_ib_release_idx(txq->ib,
3660 txq->ib_seg_offset);
3661 bna_ib_put(ib_mod, txq->ib);
3662 txq->ib = NULL;
3663 }
3664 txq->tcb = NULL;
3665 txq->tx = NULL;
3666 list_add_tail(&txq->qe, &tx_mod->txq_free_q);
3667 }
3668
3669 list_for_each(qe, &tx_mod->tx_active_q) {
3670 if (qe == &tx->qe) {
3671 list_del(&tx->qe);
3672 bfa_q_qe_init(&tx->qe);
3673 break;
3674 }
3675 }
3676
3677 tx->bna = NULL;
3678 tx->priv = NULL;
3679 list_add_tail(&tx->qe, &tx_mod->tx_free_q);
3680 }
3681
3682 static void
3683 bna_tx_cb_txq_stopped(void *arg, int status)
3684 {
3685 struct bna_tx *tx = (struct bna_tx *)arg;
3686
3687 bfa_q_qe_init(&tx->mbox_qe.qe);
3688 bfa_wc_down(&tx->txq_stop_wc);
3689 }
3690
3691 static void
3692 bna_tx_cb_txq_stopped_all(void *arg)
3693 {
3694 struct bna_tx *tx = (struct bna_tx *)arg;
3695
3696 bfa_fsm_send_event(tx, TX_E_TXQ_STOPPED);
3697 }
3698
3699 static void
3700 bna_tx_cb_stats_cleared(void *arg, int status)
3701 {
3702 struct bna_tx *tx = (struct bna_tx *)arg;
3703
3704 bfa_q_qe_init(&tx->mbox_qe.qe);
3705
3706 bfa_fsm_send_event(tx, TX_E_STAT_CLEARED);
3707 }
3708
3709 static void
3710 bna_tx_start(struct bna_tx *tx)
3711 {
3712 tx->flags |= BNA_TX_F_PORT_STARTED;
3713 if (tx->flags & BNA_TX_F_ENABLED)
3714 bfa_fsm_send_event(tx, TX_E_START);
3715 }
3716
3717 static void
3718 bna_tx_stop(struct bna_tx *tx)
3719 {
3720 tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
3721 tx->stop_cbarg = &tx->bna->tx_mod;
3722
3723 tx->flags &= ~BNA_TX_F_PORT_STARTED;
3724 bfa_fsm_send_event(tx, TX_E_STOP);
3725 }
3726
3727 static void
3728 bna_tx_fail(struct bna_tx *tx)
3729 {
3730 tx->flags &= ~BNA_TX_F_PORT_STARTED;
3731 bfa_fsm_send_event(tx, TX_E_FAIL);
3732 }
3733
3734 void
3735 bna_tx_prio_changed(struct bna_tx *tx, int prio)
3736 {
3737 struct bna_txq *txq;
3738 struct list_head *qe;
3739
3740 list_for_each(qe, &tx->txq_q) {
3741 txq = (struct bna_txq *)qe;
3742 txq->priority = prio;
3743 }
3744
3745 bfa_fsm_send_event(tx, TX_E_PRIO_CHANGE);
3746 }
3747
3748 static void
3749 bna_tx_cee_link_status(struct bna_tx *tx, int cee_link)
3750 {
3751 if (cee_link)
3752 tx->flags |= BNA_TX_F_PRIO_LOCK;
3753 else
3754 tx->flags &= ~BNA_TX_F_PRIO_LOCK;
3755 }
3756
3757 static void
3758 bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx,
3759 enum bna_cb_status status)
3760 {
3761 struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
3762
3763 bfa_wc_down(&tx_mod->tx_stop_wc);
3764 }
3765
3766 static void
3767 bna_tx_mod_cb_tx_stopped_all(void *arg)
3768 {
3769 struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
3770
3771 if (tx_mod->stop_cbfn)
3772 tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS);
3773 tx_mod->stop_cbfn = NULL;
3774 }
3775
3776 void
3777 bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
3778 {
3779 u32 q_size;
3780 u32 page_count;
3781 struct bna_mem_info *mem_info;
3782
3783 res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
3784 mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
3785 mem_info->mem_type = BNA_MEM_T_KVA;
3786 mem_info->len = sizeof(struct bna_tcb);
3787 mem_info->num = num_txq;
3788
3789 q_size = txq_depth * BFI_TXQ_WI_SIZE;
3790 q_size = ALIGN(q_size, PAGE_SIZE);
3791 page_count = q_size >> PAGE_SHIFT;
3792
3793 res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
3794 mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
3795 mem_info->mem_type = BNA_MEM_T_DMA;
3796 mem_info->len = page_count * sizeof(struct bna_dma_addr);
3797 mem_info->num = num_txq;
3798
3799 res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
3800 mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
3801 mem_info->mem_type = BNA_MEM_T_KVA;
3802 mem_info->len = page_count * sizeof(void *);
3803 mem_info->num = num_txq;
3804
3805 res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
3806 mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
3807 mem_info->mem_type = BNA_MEM_T_DMA;
3808 mem_info->len = PAGE_SIZE;
3809 mem_info->num = num_txq * page_count;
3810
3811 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
3812 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
3813 BNA_INTR_T_MSIX;
3814 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
3815 }
3816
3817 struct bna_tx *
3818 bna_tx_create(struct bna *bna, struct bnad *bnad,
3819 struct bna_tx_config *tx_cfg,
3820 struct bna_tx_event_cbfn *tx_cbfn,
3821 struct bna_res_info *res_info, void *priv)
3822 {
3823 struct bna_intr_info *intr_info;
3824 struct bna_tx_mod *tx_mod = &bna->tx_mod;
3825 struct bna_tx *tx;
3826 struct bna_txq *txq;
3827 struct list_head *qe;
3828 struct bna_ib_mod *ib_mod = &bna->ib_mod;
3829 struct bna_doorbell_qset *qset;
3830 struct bna_ib_config ib_config;
3831 int page_count;
3832 int page_size;
3833 int page_idx;
3834 int i;
3835 unsigned long off;
3836
3837 intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
3838 page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.num) /
3839 tx_cfg->num_txq;
3840 page_size = res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len;
3841
3842 /**
3843 * Get resources
3844 */
3845
3846 if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
3847 return NULL;
3848
3849 /* Tx */
3850
3851 if (list_empty(&tx_mod->tx_free_q))
3852 return NULL;
3853 bfa_q_deq(&tx_mod->tx_free_q, &tx);
3854 bfa_q_qe_init(&tx->qe);
3855
3856 /* TxQs */
3857
3858 INIT_LIST_HEAD(&tx->txq_q);
3859 for (i = 0; i < tx_cfg->num_txq; i++) {
3860 if (list_empty(&tx_mod->txq_free_q))
3861 goto err_return;
3862
3863 bfa_q_deq(&tx_mod->txq_free_q, &txq);
3864 bfa_q_qe_init(&txq->qe);
3865 list_add_tail(&txq->qe, &tx->txq_q);
3866 txq->ib = NULL;
3867 txq->ib_seg_offset = -1;
3868 txq->tx = tx;
3869 }
3870
3871 /* IBs */
3872 i = 0;
3873 list_for_each(qe, &tx->txq_q) {
3874 txq = (struct bna_txq *)qe;
3875
3876 if (intr_info->num == 1)
3877 txq->ib = bna_ib_get(ib_mod, intr_info->intr_type,
3878 intr_info->idl[0].vector);
3879 else
3880 txq->ib = bna_ib_get(ib_mod, intr_info->intr_type,
3881 intr_info->idl[i].vector);
3882
3883 if (txq->ib == NULL)
3884 goto err_return;
3885
3886 txq->ib_seg_offset = bna_ib_reserve_idx(txq->ib);
3887 if (txq->ib_seg_offset == -1)
3888 goto err_return;
3889
3890 i++;
3891 }
3892
3893 /*
3894 * Initialize
3895 */
3896
3897 /* Tx */
3898
3899 tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
3900 tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
3901 /* Following callbacks are mandatory */
3902 tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
3903 tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
3904 tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
3905
3906 list_add_tail(&tx->qe, &tx_mod->tx_active_q);
3907 tx->bna = bna;
3908 tx->priv = priv;
3909 tx->txq_stop_wc.wc_resume = bna_tx_cb_txq_stopped_all;
3910 tx->txq_stop_wc.wc_cbarg = tx;
3911 tx->txq_stop_wc.wc_count = 0;
3912
3913 tx->type = tx_cfg->tx_type;
3914
3915 tx->flags = 0;
3916 if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_STARTED) {
3917 switch (tx->type) {
3918 case BNA_TX_T_REGULAR:
3919 if (!(tx->bna->tx_mod.flags &
3920 BNA_TX_MOD_F_PORT_LOOPBACK))
3921 tx->flags |= BNA_TX_F_PORT_STARTED;
3922 break;
3923 case BNA_TX_T_LOOPBACK:
3924 if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_LOOPBACK)
3925 tx->flags |= BNA_TX_F_PORT_STARTED;
3926 break;
3927 }
3928 }
3929 if (tx->bna->tx_mod.cee_link)
3930 tx->flags |= BNA_TX_F_PRIO_LOCK;
3931
3932 /* TxQ */
3933
3934 i = 0;
3935 page_idx = 0;
3936 list_for_each(qe, &tx->txq_q) {
3937 txq = (struct bna_txq *)qe;
3938 txq->priority = tx_mod->priority;
3939 txq->tcb = (struct bna_tcb *)
3940 res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
3941 txq->tx_packets = 0;
3942 txq->tx_bytes = 0;
3943
3944 /* IB */
3945
3946 ib_config.coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3947 ib_config.interpkt_timeo = 0; /* Not used */
3948 ib_config.interpkt_count = BFI_TX_INTERPKT_COUNT;
3949 ib_config.ctrl_flags = (BFI_IB_CF_INTER_PKT_DMA |
3950 BFI_IB_CF_INT_ENABLE |
3951 BFI_IB_CF_COALESCING_MODE);
3952 bna_ib_config(txq->ib, &ib_config);
3953
3954 /* TCB */
3955
3956 txq->tcb->producer_index = 0;
3957 txq->tcb->consumer_index = 0;
3958 txq->tcb->hw_consumer_index = (volatile u32 *)
3959 ((volatile u8 *)txq->ib->ib_seg_host_addr_kva +
3960 (txq->ib_seg_offset * BFI_IBIDX_SIZE));
3961 *(txq->tcb->hw_consumer_index) = 0;
3962 txq->tcb->q_depth = tx_cfg->txq_depth;
3963 txq->tcb->unmap_q = (void *)
3964 res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
3965 qset = (struct bna_doorbell_qset *)0;
3966 off = (unsigned long)&qset[txq->txq_id].txq[0];
3967 txq->tcb->q_dbell = off +
3968 BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
3969 txq->tcb->i_dbell = &txq->ib->door_bell;
3970 txq->tcb->intr_type = intr_info->intr_type;
3971 txq->tcb->intr_vector = (intr_info->num == 1) ?
3972 intr_info->idl[0].vector :
3973 intr_info->idl[i].vector;
3974 txq->tcb->txq = txq;
3975 txq->tcb->bnad = bnad;
3976 txq->tcb->id = i;
3977
3978 /* QPT, SWQPT, Pages */
3979 bna_txq_qpt_setup(txq, page_count, page_size,
3980 &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
3981 &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
3982 &res_info[BNA_TX_RES_MEM_T_PAGE].
3983 res_u.mem_info.mdl[page_idx]);
3984 txq->tcb->page_idx = page_idx;
3985 txq->tcb->page_count = page_count;
3986 page_idx += page_count;
3987
3988 /* Callback to bnad for setting up TCB */
3989 if (tx->tcb_setup_cbfn)
3990 (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
3991
3992 i++;
3993 }
3994
3995 /* TxF */
3996
3997 tx->txf.ctrl_flags = BFI_TXF_CF_ENABLE | BFI_TXF_CF_VLAN_WI_BASED;
3998 tx->txf.vlan = 0;
3999
4000 /* Mbox element */
4001 bfa_q_qe_init(&tx->mbox_qe.qe);
4002
4003 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
4004
4005 return tx;
4006
4007 err_return:
4008 bna_tx_free(tx);
4009 return NULL;
4010 }
4011
4012 void
4013 bna_tx_destroy(struct bna_tx *tx)
4014 {
4015 /* Callback to bnad for destroying TCB */
4016 if (tx->tcb_destroy_cbfn) {
4017 struct bna_txq *txq;
4018 struct list_head *qe;
4019
4020 list_for_each(qe, &tx->txq_q) {
4021 txq = (struct bna_txq *)qe;
4022 (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
4023 }
4024 }
4025
4026 bna_tx_free(tx);
4027 }
4028
4029 void
4030 bna_tx_enable(struct bna_tx *tx)
4031 {
4032 if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
4033 return;
4034
4035 tx->flags |= BNA_TX_F_ENABLED;
4036
4037 if (tx->flags & BNA_TX_F_PORT_STARTED)
4038 bfa_fsm_send_event(tx, TX_E_START);
4039 }
4040
4041 void
4042 bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
4043 void (*cbfn)(void *, struct bna_tx *, enum bna_cb_status))
4044 {
4045 if (type == BNA_SOFT_CLEANUP) {
4046 (*cbfn)(tx->bna->bnad, tx, BNA_CB_SUCCESS);
4047 return;
4048 }
4049
4050 tx->stop_cbfn = cbfn;
4051 tx->stop_cbarg = tx->bna->bnad;
4052
4053 tx->flags &= ~BNA_TX_F_ENABLED;
4054
4055 bfa_fsm_send_event(tx, TX_E_STOP);
4056 }
4057
4058 int
4059 bna_tx_state_get(struct bna_tx *tx)
4060 {
4061 return bfa_sm_to_state(tx_sm_table, tx->fsm);
4062 }
4063
4064 void
4065 bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
4066 struct bna_res_info *res_info)
4067 {
4068 int i;
4069
4070 tx_mod->bna = bna;
4071 tx_mod->flags = 0;
4072
4073 tx_mod->tx = (struct bna_tx *)
4074 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
4075 tx_mod->txq = (struct bna_txq *)
4076 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
4077
4078 INIT_LIST_HEAD(&tx_mod->tx_free_q);
4079 INIT_LIST_HEAD(&tx_mod->tx_active_q);
4080
4081 INIT_LIST_HEAD(&tx_mod->txq_free_q);
4082
4083 for (i = 0; i < BFI_MAX_TXQ; i++) {
4084 tx_mod->tx[i].txf.txf_id = i;
4085 bfa_q_qe_init(&tx_mod->tx[i].qe);
4086 list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
4087
4088 tx_mod->txq[i].txq_id = i;
4089 bfa_q_qe_init(&tx_mod->txq[i].qe);
4090 list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
4091 }
4092
4093 tx_mod->tx_stop_wc.wc_resume = bna_tx_mod_cb_tx_stopped_all;
4094 tx_mod->tx_stop_wc.wc_cbarg = tx_mod;
4095 tx_mod->tx_stop_wc.wc_count = 0;
4096 }
4097
4098 void
4099 bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
4100 {
4101 struct list_head *qe;
4102 int i;
4103
4104 i = 0;
4105 list_for_each(qe, &tx_mod->tx_free_q)
4106 i++;
4107
4108 i = 0;
4109 list_for_each(qe, &tx_mod->txq_free_q)
4110 i++;
4111
4112 tx_mod->bna = NULL;
4113 }
4114
4115 void
4116 bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
4117 {
4118 struct bna_tx *tx;
4119 struct list_head *qe;
4120
4121 tx_mod->flags |= BNA_TX_MOD_F_PORT_STARTED;
4122 if (type == BNA_TX_T_LOOPBACK)
4123 tx_mod->flags |= BNA_TX_MOD_F_PORT_LOOPBACK;
4124
4125 list_for_each(qe, &tx_mod->tx_active_q) {
4126 tx = (struct bna_tx *)qe;
4127 if (tx->type == type)
4128 bna_tx_start(tx);
4129 }
4130 }
4131
4132 void
4133 bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
4134 {
4135 struct bna_tx *tx;
4136 struct list_head *qe;
4137
4138 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED;
4139 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK;
4140
4141 tx_mod->stop_cbfn = bna_port_cb_tx_stopped;
4142
4143 /**
4144 * Before calling bna_tx_stop(), increment tx_stop_wc as many times
4145 * as we are going to call bna_tx_stop
4146 */
4147 list_for_each(qe, &tx_mod->tx_active_q) {
4148 tx = (struct bna_tx *)qe;
4149 if (tx->type == type)
4150 bfa_wc_up(&tx_mod->tx_stop_wc);
4151 }
4152
4153 if (tx_mod->tx_stop_wc.wc_count == 0) {
4154 tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS);
4155 tx_mod->stop_cbfn = NULL;
4156 return;
4157 }
4158
4159 list_for_each(qe, &tx_mod->tx_active_q) {
4160 tx = (struct bna_tx *)qe;
4161 if (tx->type == type)
4162 bna_tx_stop(tx);
4163 }
4164 }
4165
4166 void
4167 bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
4168 {
4169 struct bna_tx *tx;
4170 struct list_head *qe;
4171
4172 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED;
4173 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK;
4174
4175 list_for_each(qe, &tx_mod->tx_active_q) {
4176 tx = (struct bna_tx *)qe;
4177 bna_tx_fail(tx);
4178 }
4179 }
4180
4181 void
4182 bna_tx_mod_prio_changed(struct bna_tx_mod *tx_mod, int prio)
4183 {
4184 struct bna_tx *tx;
4185 struct list_head *qe;
4186
4187 if (prio != tx_mod->priority) {
4188 tx_mod->priority = prio;
4189
4190 list_for_each(qe, &tx_mod->tx_active_q) {
4191 tx = (struct bna_tx *)qe;
4192 bna_tx_prio_changed(tx, prio);
4193 }
4194 }
4195 }
4196
4197 void
4198 bna_tx_mod_cee_link_status(struct bna_tx_mod *tx_mod, int cee_link)
4199 {
4200 struct bna_tx *tx;
4201 struct list_head *qe;
4202
4203 tx_mod->cee_link = cee_link;
4204
4205 list_for_each(qe, &tx_mod->tx_active_q) {
4206 tx = (struct bna_tx *)qe;
4207 bna_tx_cee_link_status(tx, cee_link);
4208 }
4209 }
kernel source for telekom puls (alcatel/mediatek)