2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
20 static int be_mbox_db_ready_wait(void __iomem
*db
)
22 int cnt
= 0, wait
= 5;
26 ready
= ioread32(db
) & MPU_MAILBOX_DB_RDY_MASK
;
31 printk(KERN_WARNING DRV_NAME
32 ": mbox_db poll timed out\n");
46 * Insert the mailbox address into the doorbell in two steps
48 static int be_mbox_db_ring(struct be_ctrl_info
*ctrl
)
51 u16 compl_status
, extd_status
;
53 void __iomem
*db
= ctrl
->db
+ MPU_MAILBOX_DB_OFFSET
;
54 struct be_dma_mem
*mbox_mem
= &ctrl
->mbox_mem
;
55 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
56 struct be_mcc_cq_entry
*cqe
= &mbox
->cqe
;
58 memset(cqe
, 0, sizeof(*cqe
));
60 val
&= ~MPU_MAILBOX_DB_RDY_MASK
;
61 val
|= MPU_MAILBOX_DB_HI_MASK
;
62 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
63 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
66 /* wait for ready to be set */
67 status
= be_mbox_db_ready_wait(db
);
72 val
&= ~MPU_MAILBOX_DB_RDY_MASK
;
73 val
&= ~MPU_MAILBOX_DB_HI_MASK
;
74 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
75 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
78 status
= be_mbox_db_ready_wait(db
);
82 /* compl entry has been made now */
83 be_dws_le_to_cpu(cqe
, sizeof(*cqe
));
84 if (!(cqe
->flags
& CQE_FLAGS_VALID_MASK
)) {
85 printk(KERN_WARNING DRV_NAME
": ERROR invalid mbox compl\n");
89 compl_status
= (cqe
->status
>> CQE_STATUS_COMPL_SHIFT
) &
90 CQE_STATUS_COMPL_MASK
;
91 if (compl_status
!= MCC_STATUS_SUCCESS
) {
92 extd_status
= (cqe
->status
>> CQE_STATUS_EXTD_SHIFT
) &
94 printk(KERN_WARNING DRV_NAME
95 ": ERROR in cmd compl. status(compl/extd)=%d/%d\n",
96 compl_status
, extd_status
);
102 static int be_POST_stage_get(struct be_ctrl_info
*ctrl
, u16
*stage
)
104 u32 sem
= ioread32(ctrl
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
106 *stage
= sem
& EP_SEMAPHORE_POST_STAGE_MASK
;
107 if ((sem
>> EP_SEMAPHORE_POST_ERR_SHIFT
) & EP_SEMAPHORE_POST_ERR_MASK
)
113 static int be_POST_stage_poll(struct be_ctrl_info
*ctrl
, u16 poll_stage
)
115 u16 stage
, cnt
, error
;
116 for (cnt
= 0; cnt
< 5000; cnt
++) {
117 error
= be_POST_stage_get(ctrl
, &stage
);
121 if (stage
== poll_stage
)
125 if (stage
!= poll_stage
)
131 int be_cmd_POST(struct be_ctrl_info
*ctrl
)
135 error
= be_POST_stage_get(ctrl
, &stage
);
139 if (stage
== POST_STAGE_ARMFW_RDY
)
142 if (stage
!= POST_STAGE_AWAITING_HOST_RDY
)
145 /* On awaiting host rdy, reset and again poll on awaiting host rdy */
146 iowrite32(POST_STAGE_BE_RESET
, ctrl
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
147 error
= be_POST_stage_poll(ctrl
, POST_STAGE_AWAITING_HOST_RDY
);
151 /* Now kickoff POST and poll on armfw ready */
152 iowrite32(POST_STAGE_HOST_RDY
, ctrl
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
153 error
= be_POST_stage_poll(ctrl
, POST_STAGE_ARMFW_RDY
);
159 printk(KERN_WARNING DRV_NAME
": ERROR, stage=%d\n", stage
);
163 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
165 return wrb
->payload
.embedded_payload
;
168 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
170 return &wrb
->payload
.sgl
[0];
173 /* Don't touch the hdr after it's prepared */
174 static void be_wrb_hdr_prepare(struct be_mcc_wrb
*wrb
, int payload_len
,
175 bool embedded
, u8 sge_cnt
)
178 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
180 wrb
->embedded
|= (sge_cnt
& MCC_WRB_SGE_CNT_MASK
) <<
181 MCC_WRB_SGE_CNT_SHIFT
;
182 wrb
->payload_length
= payload_len
;
183 be_dws_cpu_to_le(wrb
, 20);
186 /* Don't touch the hdr after it's prepared */
187 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
188 u8 subsystem
, u8 opcode
, int cmd_len
)
190 req_hdr
->opcode
= opcode
;
191 req_hdr
->subsystem
= subsystem
;
192 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
195 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
196 struct be_dma_mem
*mem
)
198 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
199 u64 dma
= (u64
)mem
->dma
;
201 for (i
= 0; i
< buf_pages
; i
++) {
202 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
203 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
208 /* Converts interrupt delay in microseconds to multiplier value */
209 static u32
eq_delay_to_mult(u32 usec_delay
)
211 #define MAX_INTR_RATE 651042
212 const u32 round
= 10;
218 u32 interrupt_rate
= 1000000 / usec_delay
;
219 /* Max delay, corresponding to the lowest interrupt rate */
220 if (interrupt_rate
== 0)
223 multiplier
= (MAX_INTR_RATE
- interrupt_rate
) * round
;
224 multiplier
/= interrupt_rate
;
225 /* Round the multiplier to the closest value.*/
226 multiplier
= (multiplier
+ round
/2) / round
;
227 multiplier
= min(multiplier
, (u32
)1023);
233 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_dma_mem
*mbox_mem
)
235 return &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
238 int be_cmd_eq_create(struct be_ctrl_info
*ctrl
,
239 struct be_queue_info
*eq
, int eq_delay
)
241 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
242 struct be_cmd_req_eq_create
*req
= embedded_payload(wrb
);
243 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
244 struct be_dma_mem
*q_mem
= &eq
->dma_mem
;
247 spin_lock(&ctrl
->cmd_lock
);
248 memset(wrb
, 0, sizeof(*wrb
));
250 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
252 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
253 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
));
255 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
257 AMAP_SET_BITS(struct amap_eq_context
, func
, req
->context
,
259 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
261 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
262 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
263 __ilog2_u32(eq
->len
/256));
264 AMAP_SET_BITS(struct amap_eq_context
, delaymult
, req
->context
,
265 eq_delay_to_mult(eq_delay
));
266 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
268 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
270 status
= be_mbox_db_ring(ctrl
);
272 eq
->id
= le16_to_cpu(resp
->eq_id
);
275 spin_unlock(&ctrl
->cmd_lock
);
279 int be_cmd_mac_addr_query(struct be_ctrl_info
*ctrl
, u8
*mac_addr
,
280 u8 type
, bool permanent
, u32 if_handle
)
282 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
283 struct be_cmd_req_mac_query
*req
= embedded_payload(wrb
);
284 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
287 spin_lock(&ctrl
->cmd_lock
);
288 memset(wrb
, 0, sizeof(*wrb
));
290 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
292 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
293 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
));
299 req
->if_id
= cpu_to_le16((u16
)if_handle
);
303 status
= be_mbox_db_ring(ctrl
);
305 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
307 spin_unlock(&ctrl
->cmd_lock
);
311 int be_cmd_pmac_add(struct be_ctrl_info
*ctrl
, u8
*mac_addr
,
312 u32 if_id
, u32
*pmac_id
)
314 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
315 struct be_cmd_req_pmac_add
*req
= embedded_payload(wrb
);
318 spin_lock(&ctrl
->cmd_lock
);
319 memset(wrb
, 0, sizeof(*wrb
));
321 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
323 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
324 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
));
326 req
->if_id
= cpu_to_le32(if_id
);
327 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
329 status
= be_mbox_db_ring(ctrl
);
331 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
332 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
335 spin_unlock(&ctrl
->cmd_lock
);
339 int be_cmd_pmac_del(struct be_ctrl_info
*ctrl
, u32 if_id
, u32 pmac_id
)
341 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
342 struct be_cmd_req_pmac_del
*req
= embedded_payload(wrb
);
345 spin_lock(&ctrl
->cmd_lock
);
346 memset(wrb
, 0, sizeof(*wrb
));
348 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
350 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
351 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
));
353 req
->if_id
= cpu_to_le32(if_id
);
354 req
->pmac_id
= cpu_to_le32(pmac_id
);
356 status
= be_mbox_db_ring(ctrl
);
357 spin_unlock(&ctrl
->cmd_lock
);
362 int be_cmd_cq_create(struct be_ctrl_info
*ctrl
,
363 struct be_queue_info
*cq
, struct be_queue_info
*eq
,
364 bool sol_evts
, bool no_delay
, int coalesce_wm
)
366 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
367 struct be_cmd_req_cq_create
*req
= embedded_payload(wrb
);
368 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
369 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
370 void *ctxt
= &req
->context
;
373 spin_lock(&ctrl
->cmd_lock
);
374 memset(wrb
, 0, sizeof(*wrb
));
376 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
378 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
379 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
));
381 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
383 AMAP_SET_BITS(struct amap_cq_context
, coalescwm
, ctxt
, coalesce_wm
);
384 AMAP_SET_BITS(struct amap_cq_context
, nodelay
, ctxt
, no_delay
);
385 AMAP_SET_BITS(struct amap_cq_context
, count
, ctxt
,
386 __ilog2_u32(cq
->len
/256));
387 AMAP_SET_BITS(struct amap_cq_context
, valid
, ctxt
, 1);
388 AMAP_SET_BITS(struct amap_cq_context
, solevent
, ctxt
, sol_evts
);
389 AMAP_SET_BITS(struct amap_cq_context
, eventable
, ctxt
, 1);
390 AMAP_SET_BITS(struct amap_cq_context
, eqid
, ctxt
, eq
->id
);
391 AMAP_SET_BITS(struct amap_cq_context
, armed
, ctxt
, 0);
392 AMAP_SET_BITS(struct amap_cq_context
, func
, ctxt
, ctrl
->pci_func
);
393 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
395 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
397 status
= be_mbox_db_ring(ctrl
);
399 cq
->id
= le16_to_cpu(resp
->cq_id
);
402 spin_unlock(&ctrl
->cmd_lock
);
407 int be_cmd_txq_create(struct be_ctrl_info
*ctrl
,
408 struct be_queue_info
*txq
,
409 struct be_queue_info
*cq
)
411 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
412 struct be_cmd_req_eth_tx_create
*req
= embedded_payload(wrb
);
413 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
414 void *ctxt
= &req
->context
;
418 spin_lock(&ctrl
->cmd_lock
);
419 memset(wrb
, 0, sizeof(*wrb
));
421 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
423 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
, OPCODE_ETH_TX_CREATE
,
426 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
427 req
->ulp_num
= BE_ULP1_NUM
;
428 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
430 len_encoded
= fls(txq
->len
); /* log2(len) + 1 */
431 if (len_encoded
== 16)
433 AMAP_SET_BITS(struct amap_tx_context
, tx_ring_size
, ctxt
, len_encoded
);
434 AMAP_SET_BITS(struct amap_tx_context
, pci_func_id
, ctxt
,
436 AMAP_SET_BITS(struct amap_tx_context
, ctx_valid
, ctxt
, 1);
437 AMAP_SET_BITS(struct amap_tx_context
, cq_id_send
, ctxt
, cq
->id
);
439 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
441 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
443 status
= be_mbox_db_ring(ctrl
);
445 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(wrb
);
446 txq
->id
= le16_to_cpu(resp
->cid
);
449 spin_unlock(&ctrl
->cmd_lock
);
454 int be_cmd_rxq_create(struct be_ctrl_info
*ctrl
,
455 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
456 u16 max_frame_size
, u32 if_id
, u32 rss
)
458 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
459 struct be_cmd_req_eth_rx_create
*req
= embedded_payload(wrb
);
460 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
463 spin_lock(&ctrl
->cmd_lock
);
464 memset(wrb
, 0, sizeof(*wrb
));
466 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
468 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
, OPCODE_ETH_RX_CREATE
,
471 req
->cq_id
= cpu_to_le16(cq_id
);
472 req
->frag_size
= fls(frag_size
) - 1;
474 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
475 req
->interface_id
= cpu_to_le32(if_id
);
476 req
->max_frame_size
= cpu_to_le16(max_frame_size
);
477 req
->rss_queue
= cpu_to_le32(rss
);
479 status
= be_mbox_db_ring(ctrl
);
481 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
482 rxq
->id
= le16_to_cpu(resp
->id
);
485 spin_unlock(&ctrl
->cmd_lock
);
490 /* Generic destroyer function for all types of queues */
491 int be_cmd_q_destroy(struct be_ctrl_info
*ctrl
, struct be_queue_info
*q
,
494 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
495 struct be_cmd_req_q_destroy
*req
= embedded_payload(wrb
);
496 u8 subsys
= 0, opcode
= 0;
499 spin_lock(&ctrl
->cmd_lock
);
501 memset(wrb
, 0, sizeof(*wrb
));
502 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
504 switch (queue_type
) {
506 subsys
= CMD_SUBSYSTEM_COMMON
;
507 opcode
= OPCODE_COMMON_EQ_DESTROY
;
510 subsys
= CMD_SUBSYSTEM_COMMON
;
511 opcode
= OPCODE_COMMON_CQ_DESTROY
;
514 subsys
= CMD_SUBSYSTEM_ETH
;
515 opcode
= OPCODE_ETH_TX_DESTROY
;
518 subsys
= CMD_SUBSYSTEM_ETH
;
519 opcode
= OPCODE_ETH_RX_DESTROY
;
522 printk(KERN_WARNING DRV_NAME
":bad Q type in Q destroy cmd\n");
526 be_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
));
527 req
->id
= cpu_to_le16(q
->id
);
529 status
= be_mbox_db_ring(ctrl
);
531 spin_unlock(&ctrl
->cmd_lock
);
536 /* Create an rx filtering policy configuration on an i/f */
537 int be_cmd_if_create(struct be_ctrl_info
*ctrl
, u32 flags
, u8
*mac
,
538 bool pmac_invalid
, u32
*if_handle
, u32
*pmac_id
)
540 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
541 struct be_cmd_req_if_create
*req
= embedded_payload(wrb
);
544 spin_lock(&ctrl
->cmd_lock
);
545 memset(wrb
, 0, sizeof(*wrb
));
547 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
549 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
550 OPCODE_COMMON_NTWK_INTERFACE_CREATE
, sizeof(*req
));
552 req
->capability_flags
= cpu_to_le32(flags
);
553 req
->enable_flags
= cpu_to_le32(flags
);
555 memcpy(req
->mac_addr
, mac
, ETH_ALEN
);
557 status
= be_mbox_db_ring(ctrl
);
559 struct be_cmd_resp_if_create
*resp
= embedded_payload(wrb
);
560 *if_handle
= le32_to_cpu(resp
->interface_id
);
562 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
565 spin_unlock(&ctrl
->cmd_lock
);
569 int be_cmd_if_destroy(struct be_ctrl_info
*ctrl
, u32 interface_id
)
571 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
572 struct be_cmd_req_if_destroy
*req
= embedded_payload(wrb
);
575 spin_lock(&ctrl
->cmd_lock
);
576 memset(wrb
, 0, sizeof(*wrb
));
578 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
580 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
581 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
, sizeof(*req
));
583 req
->interface_id
= cpu_to_le32(interface_id
);
584 status
= be_mbox_db_ring(ctrl
);
586 spin_unlock(&ctrl
->cmd_lock
);
591 /* Get stats is a non embedded command: the request is not embedded inside
592 * WRB but is a separate dma memory block
594 int be_cmd_get_stats(struct be_ctrl_info
*ctrl
, struct be_dma_mem
*nonemb_cmd
)
596 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
597 struct be_cmd_req_get_stats
*req
= nonemb_cmd
->va
;
598 struct be_sge
*sge
= nonembedded_sgl(wrb
);
601 spin_lock(&ctrl
->cmd_lock
);
602 memset(wrb
, 0, sizeof(*wrb
));
604 memset(req
, 0, sizeof(*req
));
606 be_wrb_hdr_prepare(wrb
, sizeof(*req
), false, 1);
608 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
609 OPCODE_ETH_GET_STATISTICS
, sizeof(*req
));
610 sge
->pa_hi
= cpu_to_le32(upper_32_bits(nonemb_cmd
->dma
));
611 sge
->pa_lo
= cpu_to_le32(nonemb_cmd
->dma
& 0xFFFFFFFF);
612 sge
->len
= cpu_to_le32(nonemb_cmd
->size
);
614 status
= be_mbox_db_ring(ctrl
);
616 struct be_cmd_resp_get_stats
*resp
= nonemb_cmd
->va
;
617 be_dws_le_to_cpu(&resp
->hw_stats
, sizeof(resp
->hw_stats
));
620 spin_unlock(&ctrl
->cmd_lock
);
624 int be_cmd_link_status_query(struct be_ctrl_info
*ctrl
,
625 struct be_link_info
*link
)
627 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
628 struct be_cmd_req_link_status
*req
= embedded_payload(wrb
);
631 spin_lock(&ctrl
->cmd_lock
);
632 memset(wrb
, 0, sizeof(*wrb
));
634 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
636 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
637 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
, sizeof(*req
));
639 status
= be_mbox_db_ring(ctrl
);
641 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
642 link
->speed
= resp
->mac_speed
;
643 link
->duplex
= resp
->mac_duplex
;
644 link
->fault
= resp
->mac_fault
;
646 link
->speed
= PHY_LINK_SPEED_ZERO
;
649 spin_unlock(&ctrl
->cmd_lock
);
653 int be_cmd_get_fw_ver(struct be_ctrl_info
*ctrl
, char *fw_ver
)
655 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
656 struct be_cmd_req_get_fw_version
*req
= embedded_payload(wrb
);
659 spin_lock(&ctrl
->cmd_lock
);
660 memset(wrb
, 0, sizeof(*wrb
));
662 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
664 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
665 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
));
667 status
= be_mbox_db_ring(ctrl
);
669 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
670 strncpy(fw_ver
, resp
->firmware_version_string
, FW_VER_LEN
);
673 spin_unlock(&ctrl
->cmd_lock
);
677 /* set the EQ delay interval of an EQ to specified value */
678 int be_cmd_modify_eqd(struct be_ctrl_info
*ctrl
, u32 eq_id
, u32 eqd
)
680 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
681 struct be_cmd_req_modify_eq_delay
*req
= embedded_payload(wrb
);
684 spin_lock(&ctrl
->cmd_lock
);
685 memset(wrb
, 0, sizeof(*wrb
));
687 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
689 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
690 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
));
692 req
->num_eq
= cpu_to_le32(1);
693 req
->delay
[0].eq_id
= cpu_to_le32(eq_id
);
694 req
->delay
[0].phase
= 0;
695 req
->delay
[0].delay_multiplier
= cpu_to_le32(eqd
);
697 status
= be_mbox_db_ring(ctrl
);
699 spin_unlock(&ctrl
->cmd_lock
);
703 int be_cmd_vlan_config(struct be_ctrl_info
*ctrl
, u32 if_id
, u16
*vtag_array
,
704 u32 num
, bool untagged
, bool promiscuous
)
706 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
707 struct be_cmd_req_vlan_config
*req
= embedded_payload(wrb
);
710 spin_lock(&ctrl
->cmd_lock
);
711 memset(wrb
, 0, sizeof(*wrb
));
713 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
715 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
716 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
));
718 req
->interface_id
= if_id
;
719 req
->promiscuous
= promiscuous
;
720 req
->untagged
= untagged
;
723 memcpy(req
->normal_vlan
, vtag_array
,
724 req
->num_vlan
* sizeof(vtag_array
[0]));
727 status
= be_mbox_db_ring(ctrl
);
729 spin_unlock(&ctrl
->cmd_lock
);
733 int be_cmd_promiscuous_config(struct be_ctrl_info
*ctrl
, u8 port_num
, bool en
)
735 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
736 struct be_cmd_req_promiscuous_config
*req
= embedded_payload(wrb
);
739 spin_lock(&ctrl
->cmd_lock
);
740 memset(wrb
, 0, sizeof(*wrb
));
742 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
744 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
745 OPCODE_ETH_PROMISCUOUS
, sizeof(*req
));
748 req
->port1_promiscuous
= en
;
750 req
->port0_promiscuous
= en
;
752 status
= be_mbox_db_ring(ctrl
);
754 spin_unlock(&ctrl
->cmd_lock
);
758 int be_cmd_mcast_mac_set(struct be_ctrl_info
*ctrl
, u32 if_id
, u8
*mac_table
,
759 u32 num
, bool promiscuous
)
761 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
762 struct be_cmd_req_mcast_mac_config
*req
= embedded_payload(wrb
);
765 spin_lock(&ctrl
->cmd_lock
);
766 memset(wrb
, 0, sizeof(*wrb
));
768 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
770 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
771 OPCODE_COMMON_NTWK_MULTICAST_SET
, sizeof(*req
));
773 req
->interface_id
= if_id
;
774 req
->promiscuous
= promiscuous
;
776 req
->num_mac
= cpu_to_le16(num
);
778 memcpy(req
->mac
, mac_table
, ETH_ALEN
* num
);
781 status
= be_mbox_db_ring(ctrl
);
783 spin_unlock(&ctrl
->cmd_lock
);
787 int be_cmd_set_flow_control(struct be_ctrl_info
*ctrl
, u32 tx_fc
, u32 rx_fc
)
789 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
790 struct be_cmd_req_set_flow_control
*req
= embedded_payload(wrb
);
793 spin_lock(&ctrl
->cmd_lock
);
795 memset(wrb
, 0, sizeof(*wrb
));
797 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
799 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
800 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
));
802 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
803 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
805 status
= be_mbox_db_ring(ctrl
);
807 spin_unlock(&ctrl
->cmd_lock
);
811 int be_cmd_get_flow_control(struct be_ctrl_info
*ctrl
, u32
*tx_fc
, u32
*rx_fc
)
813 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
814 struct be_cmd_req_get_flow_control
*req
= embedded_payload(wrb
);
817 spin_lock(&ctrl
->cmd_lock
);
819 memset(wrb
, 0, sizeof(*wrb
));
821 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
823 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
824 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
));
826 status
= be_mbox_db_ring(ctrl
);
828 struct be_cmd_resp_get_flow_control
*resp
=
829 embedded_payload(wrb
);
830 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
831 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
834 spin_unlock(&ctrl
->cmd_lock
);
838 int be_cmd_query_fw_cfg(struct be_ctrl_info
*ctrl
, u32
*port_num
)
840 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
841 struct be_cmd_req_query_fw_cfg
*req
= embedded_payload(wrb
);
844 spin_lock(&ctrl
->cmd_lock
);
846 memset(wrb
, 0, sizeof(*wrb
));
848 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
850 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
851 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
, sizeof(*req
));
853 status
= be_mbox_db_ring(ctrl
);
855 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
856 *port_num
= le32_to_cpu(resp
->phys_port
);
859 spin_unlock(&ctrl
->cmd_lock
);