projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / atlx / atl2.c
1 /*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <asm/atomic.h>
24 #include <linux/crc32.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/hardirq.h>
29 #include <linux/if_vlan.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ip.h>
33 #include <linux/irqflags.h>
34 #include <linux/irqreturn.h>
35 #include <linux/mii.h>
36 #include <linux/net.h>
37 #include <linux/netdevice.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/pm.h>
41 #include <linux/skbuff.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/string.h>
45 #include <linux/tcp.h>
46 #include <linux/timer.h>
47 #include <linux/types.h>
48 #include <linux/workqueue.h>
49
50 #include "atl2.h"
51
52 #define ATL2_DRV_VERSION "2.2.3"
53
54 static char atl2_driver_name[] = "atl2";
55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
56 static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57 static char atl2_driver_version[] = ATL2_DRV_VERSION;
58
59 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
60 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
61 MODULE_LICENSE("GPL");
62 MODULE_VERSION(ATL2_DRV_VERSION);
63
64 /*
65 * atl2_pci_tbl - PCI Device ID Table
66 */
67 static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = {
68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
69 /* required last entry */
70 {0,}
71 };
72 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
73
74 static void atl2_set_ethtool_ops(struct net_device *netdev);
75
76 static void atl2_check_options(struct atl2_adapter *adapter);
77
78 /*
79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
80 * @adapter: board private structure to initialize
81 *
82 * atl2_sw_init initializes the Adapter private data structure.
83 * Fields are initialized based on PCI device information and
84 * OS network device settings (MTU size).
85 */
86 static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
87 {
88 struct atl2_hw *hw = &adapter->hw;
89 struct pci_dev *pdev = adapter->pdev;
90
91 /* PCI config space info */
92 hw->vendor_id = pdev->vendor;
93 hw->device_id = pdev->device;
94 hw->subsystem_vendor_id = pdev->subsystem_vendor;
95 hw->subsystem_id = pdev->subsystem_device;
96
97 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
99
100 adapter->wol = 0;
101 adapter->ict = 50000; /* ~100ms */
102 adapter->link_speed = SPEED_0; /* hardware init */
103 adapter->link_duplex = FULL_DUPLEX;
104
105 hw->phy_configured = false;
106 hw->preamble_len = 7;
107 hw->ipgt = 0x60;
108 hw->min_ifg = 0x50;
109 hw->ipgr1 = 0x40;
110 hw->ipgr2 = 0x60;
111 hw->retry_buf = 2;
112 hw->max_retry = 0xf;
113 hw->lcol = 0x37;
114 hw->jam_ipg = 7;
115 hw->fc_rxd_hi = 0;
116 hw->fc_rxd_lo = 0;
117 hw->max_frame_size = adapter->netdev->mtu;
118
119 spin_lock_init(&adapter->stats_lock);
120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124 }
125
126 /*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135 static void atl2_set_multi(struct net_device *netdev)
136 {
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
139 struct dev_mc_list *mc_ptr;
140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
161 netdev_for_each_mc_addr(mc_ptr, netdev) {
162 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
163 atl2_hash_set(hw, hash_value);
164 }
165 }
166
167 static void init_ring_ptrs(struct atl2_adapter *adapter)
168 {
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178 }
179
180 /*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186 static int atl2_configure(struct atl2_adapter *adapter)
187 {
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222 /*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225 */
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284 }
285
286 /*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293 {
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
315 offset);
316
317 /* Init TXS Ring */
318 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
319 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
320 adapter->txs_dma += offset;
321 adapter->txs_ring = (struct tx_pkt_status *)
322 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
323
324 /* Init RXD Ring */
325 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
326 offset = (adapter->rxd_dma & 127) ?
327 (128 - (adapter->rxd_dma & 127)) : 0;
328 if (offset > 7)
329 offset -= 8;
330 else
331 offset += (128 - 8);
332
333 adapter->rxd_dma += offset;
334 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
335 (adapter->txs_ring_size * 4 + offset));
336
337 /*
338 * Read / Write Ptr Initialize:
339 * init_ring_ptrs(adapter);
340 */
341 return 0;
342 }
343
344 /*
345 * atl2_irq_enable - Enable default interrupt generation settings
346 * @adapter: board private structure
347 */
348 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
349 {
350 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
351 ATL2_WRITE_FLUSH(&adapter->hw);
352 }
353
354 /*
355 * atl2_irq_disable - Mask off interrupt generation on the NIC
356 * @adapter: board private structure
357 */
358 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
359 {
360 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
361 ATL2_WRITE_FLUSH(&adapter->hw);
362 synchronize_irq(adapter->pdev->irq);
363 }
364
365 #ifdef NETIF_F_HW_VLAN_TX
366 static void atl2_vlan_rx_register(struct net_device *netdev,
367 struct vlan_group *grp)
368 {
369 struct atl2_adapter *adapter = netdev_priv(netdev);
370 u32 ctrl;
371
372 atl2_irq_disable(adapter);
373 adapter->vlgrp = grp;
374
375 if (grp) {
376 /* enable VLAN tag insert/strip */
377 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
378 ctrl |= MAC_CTRL_RMV_VLAN;
379 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
380 } else {
381 /* disable VLAN tag insert/strip */
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 ctrl &= ~MAC_CTRL_RMV_VLAN;
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385 }
386
387 atl2_irq_enable(adapter);
388 }
389
390 static void atl2_restore_vlan(struct atl2_adapter *adapter)
391 {
392 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
393 }
394 #endif
395
396 static void atl2_intr_rx(struct atl2_adapter *adapter)
397 {
398 struct net_device *netdev = adapter->netdev;
399 struct rx_desc *rxd;
400 struct sk_buff *skb;
401
402 do {
403 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
404 if (!rxd->status.update)
405 break; /* end of tx */
406
407 /* clear this flag at once */
408 rxd->status.update = 0;
409
410 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
411 int rx_size = (int)(rxd->status.pkt_size - 4);
412 /* alloc new buffer */
413 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
414 if (NULL == skb) {
415 printk(KERN_WARNING
416 "%s: Mem squeeze, deferring packet.\n",
417 netdev->name);
418 /*
419 * Check that some rx space is free. If not,
420 * free one and mark stats->rx_dropped++.
421 */
422 netdev->stats.rx_dropped++;
423 break;
424 }
425 skb->dev = netdev;
426 memcpy(skb->data, rxd->packet, rx_size);
427 skb_put(skb, rx_size);
428 skb->protocol = eth_type_trans(skb, netdev);
429 #ifdef NETIF_F_HW_VLAN_TX
430 if (adapter->vlgrp && (rxd->status.vlan)) {
431 u16 vlan_tag = (rxd->status.vtag>>4) |
432 ((rxd->status.vtag&7) << 13) |
433 ((rxd->status.vtag&8) << 9);
434 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
435 } else
436 #endif
437 netif_rx(skb);
438 netdev->stats.rx_bytes += rx_size;
439 netdev->stats.rx_packets++;
440 } else {
441 netdev->stats.rx_errors++;
442
443 if (rxd->status.ok && rxd->status.pkt_size <= 60)
444 netdev->stats.rx_length_errors++;
445 if (rxd->status.mcast)
446 netdev->stats.multicast++;
447 if (rxd->status.crc)
448 netdev->stats.rx_crc_errors++;
449 if (rxd->status.align)
450 netdev->stats.rx_frame_errors++;
451 }
452
453 /* advance write ptr */
454 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
455 adapter->rxd_write_ptr = 0;
456 } while (1);
457
458 /* update mailbox? */
459 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
460 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
461 }
462
463 static void atl2_intr_tx(struct atl2_adapter *adapter)
464 {
465 struct net_device *netdev = adapter->netdev;
466 u32 txd_read_ptr;
467 u32 txs_write_ptr;
468 struct tx_pkt_status *txs;
469 struct tx_pkt_header *txph;
470 int free_hole = 0;
471
472 do {
473 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
474 txs = adapter->txs_ring + txs_write_ptr;
475 if (!txs->update)
476 break; /* tx stop here */
477
478 free_hole = 1;
479 txs->update = 0;
480
481 if (++txs_write_ptr == adapter->txs_ring_size)
482 txs_write_ptr = 0;
483 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
484
485 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
486 txph = (struct tx_pkt_header *)
487 (((u8 *)adapter->txd_ring) + txd_read_ptr);
488
489 if (txph->pkt_size != txs->pkt_size) {
490 struct tx_pkt_status *old_txs = txs;
491 printk(KERN_WARNING
492 "%s: txs packet size not consistent with txd"
493 " txd_:0x%08x, txs_:0x%08x!\n",
494 adapter->netdev->name,
495 *(u32 *)txph, *(u32 *)txs);
496 printk(KERN_WARNING
497 "txd read ptr: 0x%x\n",
498 txd_read_ptr);
499 txs = adapter->txs_ring + txs_write_ptr;
500 printk(KERN_WARNING
501 "txs-behind:0x%08x\n",
502 *(u32 *)txs);
503 if (txs_write_ptr < 2) {
504 txs = adapter->txs_ring +
505 (adapter->txs_ring_size +
506 txs_write_ptr - 2);
507 } else {
508 txs = adapter->txs_ring + (txs_write_ptr - 2);
509 }
510 printk(KERN_WARNING
511 "txs-before:0x%08x\n",
512 *(u32 *)txs);
513 txs = old_txs;
514 }
515
516 /* 4for TPH */
517 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
518 if (txd_read_ptr >= adapter->txd_ring_size)
519 txd_read_ptr -= adapter->txd_ring_size;
520
521 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
522
523 /* tx statistics: */
524 if (txs->ok) {
525 netdev->stats.tx_bytes += txs->pkt_size;
526 netdev->stats.tx_packets++;
527 }
528 else
529 netdev->stats.tx_errors++;
530
531 if (txs->defer)
532 netdev->stats.collisions++;
533 if (txs->abort_col)
534 netdev->stats.tx_aborted_errors++;
535 if (txs->late_col)
536 netdev->stats.tx_window_errors++;
537 if (txs->underun)
538 netdev->stats.tx_fifo_errors++;
539 } while (1);
540
541 if (free_hole) {
542 if (netif_queue_stopped(adapter->netdev) &&
543 netif_carrier_ok(adapter->netdev))
544 netif_wake_queue(adapter->netdev);
545 }
546 }
547
548 static void atl2_check_for_link(struct atl2_adapter *adapter)
549 {
550 struct net_device *netdev = adapter->netdev;
551 u16 phy_data = 0;
552
553 spin_lock(&adapter->stats_lock);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 spin_unlock(&adapter->stats_lock);
557
558 /* notify upper layer link down ASAP */
559 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
560 if (netif_carrier_ok(netdev)) { /* old link state: Up */
561 printk(KERN_INFO "%s: %s NIC Link is Down\n",
562 atl2_driver_name, netdev->name);
563 adapter->link_speed = SPEED_0;
564 netif_carrier_off(netdev);
565 netif_stop_queue(netdev);
566 }
567 }
568 schedule_work(&adapter->link_chg_task);
569 }
570
571 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
572 {
573 u16 phy_data;
574 spin_lock(&adapter->stats_lock);
575 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
576 spin_unlock(&adapter->stats_lock);
577 }
578
579 /*
580 * atl2_intr - Interrupt Handler
581 * @irq: interrupt number
582 * @data: pointer to a network interface device structure
583 * @pt_regs: CPU registers structure
584 */
585 static irqreturn_t atl2_intr(int irq, void *data)
586 {
587 struct atl2_adapter *adapter = netdev_priv(data);
588 struct atl2_hw *hw = &adapter->hw;
589 u32 status;
590
591 status = ATL2_READ_REG(hw, REG_ISR);
592 if (0 == status)
593 return IRQ_NONE;
594
595 /* link event */
596 if (status & ISR_PHY)
597 atl2_clear_phy_int(adapter);
598
599 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
600 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
601
602 /* check if PCIE PHY Link down */
603 if (status & ISR_PHY_LINKDOWN) {
604 if (netif_running(adapter->netdev)) { /* reset MAC */
605 ATL2_WRITE_REG(hw, REG_ISR, 0);
606 ATL2_WRITE_REG(hw, REG_IMR, 0);
607 ATL2_WRITE_FLUSH(hw);
608 schedule_work(&adapter->reset_task);
609 return IRQ_HANDLED;
610 }
611 }
612
613 /* check if DMA read/write error? */
614 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
615 ATL2_WRITE_REG(hw, REG_ISR, 0);
616 ATL2_WRITE_REG(hw, REG_IMR, 0);
617 ATL2_WRITE_FLUSH(hw);
618 schedule_work(&adapter->reset_task);
619 return IRQ_HANDLED;
620 }
621
622 /* link event */
623 if (status & (ISR_PHY | ISR_MANUAL)) {
624 adapter->netdev->stats.tx_carrier_errors++;
625 atl2_check_for_link(adapter);
626 }
627
628 /* transmit event */
629 if (status & ISR_TX_EVENT)
630 atl2_intr_tx(adapter);
631
632 /* rx exception */
633 if (status & ISR_RX_EVENT)
634 atl2_intr_rx(adapter);
635
636 /* re-enable Interrupt */
637 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
638 return IRQ_HANDLED;
639 }
640
641 static int atl2_request_irq(struct atl2_adapter *adapter)
642 {
643 struct net_device *netdev = adapter->netdev;
644 int flags, err = 0;
645
646 flags = IRQF_SHARED;
647 adapter->have_msi = true;
648 err = pci_enable_msi(adapter->pdev);
649 if (err)
650 adapter->have_msi = false;
651
652 if (adapter->have_msi)
653 flags &= ~IRQF_SHARED;
654
655 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
656 netdev);
657 }
658
659 /*
660 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
661 * @adapter: board private structure
662 *
663 * Free all transmit software resources
664 */
665 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
666 {
667 struct pci_dev *pdev = adapter->pdev;
668 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
669 adapter->ring_dma);
670 }
671
672 /*
673 * atl2_open - Called when a network interface is made active
674 * @netdev: network interface device structure
675 *
676 * Returns 0 on success, negative value on failure
677 *
678 * The open entry point is called when a network interface is made
679 * active by the system (IFF_UP). At this point all resources needed
680 * for transmit and receive operations are allocated, the interrupt
681 * handler is registered with the OS, the watchdog timer is started,
682 * and the stack is notified that the interface is ready.
683 */
684 static int atl2_open(struct net_device *netdev)
685 {
686 struct atl2_adapter *adapter = netdev_priv(netdev);
687 int err;
688 u32 val;
689
690 /* disallow open during test */
691 if (test_bit(__ATL2_TESTING, &adapter->flags))
692 return -EBUSY;
693
694 /* allocate transmit descriptors */
695 err = atl2_setup_ring_resources(adapter);
696 if (err)
697 return err;
698
699 err = atl2_init_hw(&adapter->hw);
700 if (err) {
701 err = -EIO;
702 goto err_init_hw;
703 }
704
705 /* hardware has been reset, we need to reload some things */
706 atl2_set_multi(netdev);
707 init_ring_ptrs(adapter);
708
709 #ifdef NETIF_F_HW_VLAN_TX
710 atl2_restore_vlan(adapter);
711 #endif
712
713 if (atl2_configure(adapter)) {
714 err = -EIO;
715 goto err_config;
716 }
717
718 err = atl2_request_irq(adapter);
719 if (err)
720 goto err_req_irq;
721
722 clear_bit(__ATL2_DOWN, &adapter->flags);
723
724 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
725
726 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
727 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
728 val | MASTER_CTRL_MANUAL_INT);
729
730 atl2_irq_enable(adapter);
731
732 return 0;
733
734 err_init_hw:
735 err_req_irq:
736 err_config:
737 atl2_free_ring_resources(adapter);
738 atl2_reset_hw(&adapter->hw);
739
740 return err;
741 }
742
743 static void atl2_down(struct atl2_adapter *adapter)
744 {
745 struct net_device *netdev = adapter->netdev;
746
747 /* signal that we're down so the interrupt handler does not
748 * reschedule our watchdog timer */
749 set_bit(__ATL2_DOWN, &adapter->flags);
750
751 netif_tx_disable(netdev);
752
753 /* reset MAC to disable all RX/TX */
754 atl2_reset_hw(&adapter->hw);
755 msleep(1);
756
757 atl2_irq_disable(adapter);
758
759 del_timer_sync(&adapter->watchdog_timer);
760 del_timer_sync(&adapter->phy_config_timer);
761 clear_bit(0, &adapter->cfg_phy);
762
763 netif_carrier_off(netdev);
764 adapter->link_speed = SPEED_0;
765 adapter->link_duplex = -1;
766 }
767
768 static void atl2_free_irq(struct atl2_adapter *adapter)
769 {
770 struct net_device *netdev = adapter->netdev;
771
772 free_irq(adapter->pdev->irq, netdev);
773
774 #ifdef CONFIG_PCI_MSI
775 if (adapter->have_msi)
776 pci_disable_msi(adapter->pdev);
777 #endif
778 }
779
780 /*
781 * atl2_close - Disables a network interface
782 * @netdev: network interface device structure
783 *
784 * Returns 0, this is not allowed to fail
785 *
786 * The close entry point is called when an interface is de-activated
787 * by the OS. The hardware is still under the drivers control, but
788 * needs to be disabled. A global MAC reset is issued to stop the
789 * hardware, and all transmit and receive resources are freed.
790 */
791 static int atl2_close(struct net_device *netdev)
792 {
793 struct atl2_adapter *adapter = netdev_priv(netdev);
794
795 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
796
797 atl2_down(adapter);
798 atl2_free_irq(adapter);
799 atl2_free_ring_resources(adapter);
800
801 return 0;
802 }
803
804 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
805 {
806 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
807
808 return (adapter->txs_next_clear >= txs_write_ptr) ?
809 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
810 txs_write_ptr - 1) :
811 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
812 }
813
814 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
815 {
816 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
817
818 return (adapter->txd_write_ptr >= txd_read_ptr) ?
819 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
820 txd_read_ptr - 1) :
821 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
822 }
823
824 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
825 struct net_device *netdev)
826 {
827 struct atl2_adapter *adapter = netdev_priv(netdev);
828 struct tx_pkt_header *txph;
829 u32 offset, copy_len;
830 int txs_unused;
831 int txbuf_unused;
832
833 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
834 dev_kfree_skb_any(skb);
835 return NETDEV_TX_OK;
836 }
837
838 if (unlikely(skb->len <= 0)) {
839 dev_kfree_skb_any(skb);
840 return NETDEV_TX_OK;
841 }
842
843 txs_unused = TxsFreeUnit(adapter);
844 txbuf_unused = TxdFreeBytes(adapter);
845
846 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
847 txs_unused < 1) {
848 /* not enough resources */
849 netif_stop_queue(netdev);
850 return NETDEV_TX_BUSY;
851 }
852
853 offset = adapter->txd_write_ptr;
854
855 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
856
857 *(u32 *)txph = 0;
858 txph->pkt_size = skb->len;
859
860 offset += 4;
861 if (offset >= adapter->txd_ring_size)
862 offset -= adapter->txd_ring_size;
863 copy_len = adapter->txd_ring_size - offset;
864 if (copy_len >= skb->len) {
865 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
866 offset += ((u32)(skb->len + 3) & ~3);
867 } else {
868 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
869 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
870 skb->len-copy_len);
871 offset = ((u32)(skb->len-copy_len + 3) & ~3);
872 }
873 #ifdef NETIF_F_HW_VLAN_TX
874 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
875 u16 vlan_tag = vlan_tx_tag_get(skb);
876 vlan_tag = (vlan_tag << 4) |
877 (vlan_tag >> 13) |
878 ((vlan_tag >> 9) & 0x8);
879 txph->ins_vlan = 1;
880 txph->vlan = vlan_tag;
881 }
882 #endif
883 if (offset >= adapter->txd_ring_size)
884 offset -= adapter->txd_ring_size;
885 adapter->txd_write_ptr = offset;
886
887 /* clear txs before send */
888 adapter->txs_ring[adapter->txs_next_clear].update = 0;
889 if (++adapter->txs_next_clear == adapter->txs_ring_size)
890 adapter->txs_next_clear = 0;
891
892 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
893 (adapter->txd_write_ptr >> 2));
894
895 mmiowb();
896 netdev->trans_start = jiffies;
897 dev_kfree_skb_any(skb);
898 return NETDEV_TX_OK;
899 }
900
901 /*
902 * atl2_change_mtu - Change the Maximum Transfer Unit
903 * @netdev: network interface device structure
904 * @new_mtu: new value for maximum frame size
905 *
906 * Returns 0 on success, negative on failure
907 */
908 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
909 {
910 struct atl2_adapter *adapter = netdev_priv(netdev);
911 struct atl2_hw *hw = &adapter->hw;
912
913 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
914 return -EINVAL;
915
916 /* set MTU */
917 if (hw->max_frame_size != new_mtu) {
918 netdev->mtu = new_mtu;
919 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
920 VLAN_SIZE + ETHERNET_FCS_SIZE);
921 }
922
923 return 0;
924 }
925
926 /*
927 * atl2_set_mac - Change the Ethernet Address of the NIC
928 * @netdev: network interface device structure
929 * @p: pointer to an address structure
930 *
931 * Returns 0 on success, negative on failure
932 */
933 static int atl2_set_mac(struct net_device *netdev, void *p)
934 {
935 struct atl2_adapter *adapter = netdev_priv(netdev);
936 struct sockaddr *addr = p;
937
938 if (!is_valid_ether_addr(addr->sa_data))
939 return -EADDRNOTAVAIL;
940
941 if (netif_running(netdev))
942 return -EBUSY;
943
944 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
945 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
946
947 atl2_set_mac_addr(&adapter->hw);
948
949 return 0;
950 }
951
952 /*
953 * atl2_mii_ioctl -
954 * @netdev:
955 * @ifreq:
956 * @cmd:
957 */
958 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
959 {
960 struct atl2_adapter *adapter = netdev_priv(netdev);
961 struct mii_ioctl_data *data = if_mii(ifr);
962 unsigned long flags;
963
964 switch (cmd) {
965 case SIOCGMIIPHY:
966 data->phy_id = 0;
967 break;
968 case SIOCGMIIREG:
969 spin_lock_irqsave(&adapter->stats_lock, flags);
970 if (atl2_read_phy_reg(&adapter->hw,
971 data->reg_num & 0x1F, &data->val_out)) {
972 spin_unlock_irqrestore(&adapter->stats_lock, flags);
973 return -EIO;
974 }
975 spin_unlock_irqrestore(&adapter->stats_lock, flags);
976 break;
977 case SIOCSMIIREG:
978 if (data->reg_num & ~(0x1F))
979 return -EFAULT;
980 spin_lock_irqsave(&adapter->stats_lock, flags);
981 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
982 data->val_in)) {
983 spin_unlock_irqrestore(&adapter->stats_lock, flags);
984 return -EIO;
985 }
986 spin_unlock_irqrestore(&adapter->stats_lock, flags);
987 break;
988 default:
989 return -EOPNOTSUPP;
990 }
991 return 0;
992 }
993
994 /*
995 * atl2_ioctl -
996 * @netdev:
997 * @ifreq:
998 * @cmd:
999 */
1000 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1001 {
1002 switch (cmd) {
1003 case SIOCGMIIPHY:
1004 case SIOCGMIIREG:
1005 case SIOCSMIIREG:
1006 return atl2_mii_ioctl(netdev, ifr, cmd);
1007 #ifdef ETHTOOL_OPS_COMPAT
1008 case SIOCETHTOOL:
1009 return ethtool_ioctl(ifr);
1010 #endif
1011 default:
1012 return -EOPNOTSUPP;
1013 }
1014 }
1015
1016 /*
1017 * atl2_tx_timeout - Respond to a Tx Hang
1018 * @netdev: network interface device structure
1019 */
1020 static void atl2_tx_timeout(struct net_device *netdev)
1021 {
1022 struct atl2_adapter *adapter = netdev_priv(netdev);
1023
1024 /* Do the reset outside of interrupt context */
1025 schedule_work(&adapter->reset_task);
1026 }
1027
1028 /*
1029 * atl2_watchdog - Timer Call-back
1030 * @data: pointer to netdev cast into an unsigned long
1031 */
1032 static void atl2_watchdog(unsigned long data)
1033 {
1034 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1035
1036 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1037 u32 drop_rxd, drop_rxs;
1038 unsigned long flags;
1039
1040 spin_lock_irqsave(&adapter->stats_lock, flags);
1041 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1042 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1043 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1044
1045 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1046
1047 /* Reset the timer */
1048 mod_timer(&adapter->watchdog_timer,
1049 round_jiffies(jiffies + 4 * HZ));
1050 }
1051 }
1052
1053 /*
1054 * atl2_phy_config - Timer Call-back
1055 * @data: pointer to netdev cast into an unsigned long
1056 */
1057 static void atl2_phy_config(unsigned long data)
1058 {
1059 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1060 struct atl2_hw *hw = &adapter->hw;
1061 unsigned long flags;
1062
1063 spin_lock_irqsave(&adapter->stats_lock, flags);
1064 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1065 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1066 MII_CR_RESTART_AUTO_NEG);
1067 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1068 clear_bit(0, &adapter->cfg_phy);
1069 }
1070
1071 static int atl2_up(struct atl2_adapter *adapter)
1072 {
1073 struct net_device *netdev = adapter->netdev;
1074 int err = 0;
1075 u32 val;
1076
1077 /* hardware has been reset, we need to reload some things */
1078
1079 err = atl2_init_hw(&adapter->hw);
1080 if (err) {
1081 err = -EIO;
1082 return err;
1083 }
1084
1085 atl2_set_multi(netdev);
1086 init_ring_ptrs(adapter);
1087
1088 #ifdef NETIF_F_HW_VLAN_TX
1089 atl2_restore_vlan(adapter);
1090 #endif
1091
1092 if (atl2_configure(adapter)) {
1093 err = -EIO;
1094 goto err_up;
1095 }
1096
1097 clear_bit(__ATL2_DOWN, &adapter->flags);
1098
1099 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1100 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1101 MASTER_CTRL_MANUAL_INT);
1102
1103 atl2_irq_enable(adapter);
1104
1105 err_up:
1106 return err;
1107 }
1108
1109 static void atl2_reinit_locked(struct atl2_adapter *adapter)
1110 {
1111 WARN_ON(in_interrupt());
1112 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1113 msleep(1);
1114 atl2_down(adapter);
1115 atl2_up(adapter);
1116 clear_bit(__ATL2_RESETTING, &adapter->flags);
1117 }
1118
1119 static void atl2_reset_task(struct work_struct *work)
1120 {
1121 struct atl2_adapter *adapter;
1122 adapter = container_of(work, struct atl2_adapter, reset_task);
1123
1124 atl2_reinit_locked(adapter);
1125 }
1126
1127 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1128 {
1129 u32 value;
1130 struct atl2_hw *hw = &adapter->hw;
1131 struct net_device *netdev = adapter->netdev;
1132
1133 /* Config MAC CTRL Register */
1134 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1135
1136 /* duplex */
1137 if (FULL_DUPLEX == adapter->link_duplex)
1138 value |= MAC_CTRL_DUPLX;
1139
1140 /* flow control */
1141 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1142
1143 /* PAD & CRC */
1144 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1145
1146 /* preamble length */
1147 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1148 MAC_CTRL_PRMLEN_SHIFT);
1149
1150 /* vlan */
1151 if (adapter->vlgrp)
1152 value |= MAC_CTRL_RMV_VLAN;
1153
1154 /* filter mode */
1155 value |= MAC_CTRL_BC_EN;
1156 if (netdev->flags & IFF_PROMISC)
1157 value |= MAC_CTRL_PROMIS_EN;
1158 else if (netdev->flags & IFF_ALLMULTI)
1159 value |= MAC_CTRL_MC_ALL_EN;
1160
1161 /* half retry buffer */
1162 value |= (((u32)(adapter->hw.retry_buf &
1163 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1164
1165 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1166 }
1167
1168 static int atl2_check_link(struct atl2_adapter *adapter)
1169 {
1170 struct atl2_hw *hw = &adapter->hw;
1171 struct net_device *netdev = adapter->netdev;
1172 int ret_val;
1173 u16 speed, duplex, phy_data;
1174 int reconfig = 0;
1175
1176 /* MII_BMSR must read twise */
1177 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1178 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1179 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1180 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1181 u32 value;
1182 /* disable rx */
1183 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1184 value &= ~MAC_CTRL_RX_EN;
1185 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1186 adapter->link_speed = SPEED_0;
1187 netif_carrier_off(netdev);
1188 netif_stop_queue(netdev);
1189 }
1190 return 0;
1191 }
1192
1193 /* Link Up */
1194 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1195 if (ret_val)
1196 return ret_val;
1197 switch (hw->MediaType) {
1198 case MEDIA_TYPE_100M_FULL:
1199 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1200 reconfig = 1;
1201 break;
1202 case MEDIA_TYPE_100M_HALF:
1203 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1204 reconfig = 1;
1205 break;
1206 case MEDIA_TYPE_10M_FULL:
1207 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1208 reconfig = 1;
1209 break;
1210 case MEDIA_TYPE_10M_HALF:
1211 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1212 reconfig = 1;
1213 break;
1214 }
1215 /* link result is our setting */
1216 if (reconfig == 0) {
1217 if (adapter->link_speed != speed ||
1218 adapter->link_duplex != duplex) {
1219 adapter->link_speed = speed;
1220 adapter->link_duplex = duplex;
1221 atl2_setup_mac_ctrl(adapter);
1222 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1223 atl2_driver_name, netdev->name,
1224 adapter->link_speed,
1225 adapter->link_duplex == FULL_DUPLEX ?
1226 "Full Duplex" : "Half Duplex");
1227 }
1228
1229 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1230 netif_carrier_on(netdev);
1231 netif_wake_queue(netdev);
1232 }
1233 return 0;
1234 }
1235
1236 /* change original link status */
1237 if (netif_carrier_ok(netdev)) {
1238 u32 value;
1239 /* disable rx */
1240 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1241 value &= ~MAC_CTRL_RX_EN;
1242 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1243
1244 adapter->link_speed = SPEED_0;
1245 netif_carrier_off(netdev);
1246 netif_stop_queue(netdev);
1247 }
1248
1249 /* auto-neg, insert timer to re-config phy
1250 * (if interval smaller than 5 seconds, something strange) */
1251 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1252 if (!test_and_set_bit(0, &adapter->cfg_phy))
1253 mod_timer(&adapter->phy_config_timer,
1254 round_jiffies(jiffies + 5 * HZ));
1255 }
1256
1257 return 0;
1258 }
1259
1260 /*
1261 * atl2_link_chg_task - deal with link change event Out of interrupt context
1262 * @netdev: network interface device structure
1263 */
1264 static void atl2_link_chg_task(struct work_struct *work)
1265 {
1266 struct atl2_adapter *adapter;
1267 unsigned long flags;
1268
1269 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1270
1271 spin_lock_irqsave(&adapter->stats_lock, flags);
1272 atl2_check_link(adapter);
1273 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1274 }
1275
1276 static void atl2_setup_pcicmd(struct pci_dev *pdev)
1277 {
1278 u16 cmd;
1279
1280 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1281
1282 if (cmd & PCI_COMMAND_INTX_DISABLE)
1283 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1284 if (cmd & PCI_COMMAND_IO)
1285 cmd &= ~PCI_COMMAND_IO;
1286 if (0 == (cmd & PCI_COMMAND_MEMORY))
1287 cmd |= PCI_COMMAND_MEMORY;
1288 if (0 == (cmd & PCI_COMMAND_MASTER))
1289 cmd |= PCI_COMMAND_MASTER;
1290 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1291
1292 /*
1293 * some motherboards BIOS(PXE/EFI) driver may set PME
1294 * while they transfer control to OS (Windows/Linux)
1295 * so we should clear this bit before NIC work normally
1296 */
1297 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1298 }
1299
1300 #ifdef CONFIG_NET_POLL_CONTROLLER
1301 static void atl2_poll_controller(struct net_device *netdev)
1302 {
1303 disable_irq(netdev->irq);
1304 atl2_intr(netdev->irq, netdev);
1305 enable_irq(netdev->irq);
1306 }
1307 #endif
1308
1309
1310 static const struct net_device_ops atl2_netdev_ops = {
1311 .ndo_open = atl2_open,
1312 .ndo_stop = atl2_close,
1313 .ndo_start_xmit = atl2_xmit_frame,
1314 .ndo_set_multicast_list = atl2_set_multi,
1315 .ndo_validate_addr = eth_validate_addr,
1316 .ndo_set_mac_address = atl2_set_mac,
1317 .ndo_change_mtu = atl2_change_mtu,
1318 .ndo_do_ioctl = atl2_ioctl,
1319 .ndo_tx_timeout = atl2_tx_timeout,
1320 .ndo_vlan_rx_register = atl2_vlan_rx_register,
1321 #ifdef CONFIG_NET_POLL_CONTROLLER
1322 .ndo_poll_controller = atl2_poll_controller,
1323 #endif
1324 };
1325
1326 /*
1327 * atl2_probe - Device Initialization Routine
1328 * @pdev: PCI device information struct
1329 * @ent: entry in atl2_pci_tbl
1330 *
1331 * Returns 0 on success, negative on failure
1332 *
1333 * atl2_probe initializes an adapter identified by a pci_dev structure.
1334 * The OS initialization, configuring of the adapter private structure,
1335 * and a hardware reset occur.
1336 */
1337 static int __devinit atl2_probe(struct pci_dev *pdev,
1338 const struct pci_device_id *ent)
1339 {
1340 struct net_device *netdev;
1341 struct atl2_adapter *adapter;
1342 static int cards_found;
1343 unsigned long mmio_start;
1344 int mmio_len;
1345 int err;
1346
1347 cards_found = 0;
1348
1349 err = pci_enable_device(pdev);
1350 if (err)
1351 return err;
1352
1353 /*
1354 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1355 * until the kernel has the proper infrastructure to support 64-bit DMA
1356 * on these devices.
1357 */
1358 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1359 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1360 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1361 goto err_dma;
1362 }
1363
1364 /* Mark all PCI regions associated with PCI device
1365 * pdev as being reserved by owner atl2_driver_name */
1366 err = pci_request_regions(pdev, atl2_driver_name);
1367 if (err)
1368 goto err_pci_reg;
1369
1370 /* Enables bus-mastering on the device and calls
1371 * pcibios_set_master to do the needed arch specific settings */
1372 pci_set_master(pdev);
1373
1374 err = -ENOMEM;
1375 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1376 if (!netdev)
1377 goto err_alloc_etherdev;
1378
1379 SET_NETDEV_DEV(netdev, &pdev->dev);
1380
1381 pci_set_drvdata(pdev, netdev);
1382 adapter = netdev_priv(netdev);
1383 adapter->netdev = netdev;
1384 adapter->pdev = pdev;
1385 adapter->hw.back = adapter;
1386
1387 mmio_start = pci_resource_start(pdev, 0x0);
1388 mmio_len = pci_resource_len(pdev, 0x0);
1389
1390 adapter->hw.mem_rang = (u32)mmio_len;
1391 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1392 if (!adapter->hw.hw_addr) {
1393 err = -EIO;
1394 goto err_ioremap;
1395 }
1396
1397 atl2_setup_pcicmd(pdev);
1398
1399 netdev->netdev_ops = &atl2_netdev_ops;
1400 atl2_set_ethtool_ops(netdev);
1401 netdev->watchdog_timeo = 5 * HZ;
1402 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1403
1404 netdev->mem_start = mmio_start;
1405 netdev->mem_end = mmio_start + mmio_len;
1406 adapter->bd_number = cards_found;
1407 adapter->pci_using_64 = false;
1408
1409 /* setup the private structure */
1410 err = atl2_sw_init(adapter);
1411 if (err)
1412 goto err_sw_init;
1413
1414 err = -EIO;
1415
1416 #ifdef NETIF_F_HW_VLAN_TX
1417 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1418 #endif
1419
1420 /* Init PHY as early as possible due to power saving issue */
1421 atl2_phy_init(&adapter->hw);
1422
1423 /* reset the controller to
1424 * put the device in a known good starting state */
1425
1426 if (atl2_reset_hw(&adapter->hw)) {
1427 err = -EIO;
1428 goto err_reset;
1429 }
1430
1431 /* copy the MAC address out of the EEPROM */
1432 atl2_read_mac_addr(&adapter->hw);
1433 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1434 /* FIXME: do we still need this? */
1435 #ifdef ETHTOOL_GPERMADDR
1436 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1437
1438 if (!is_valid_ether_addr(netdev->perm_addr)) {
1439 #else
1440 if (!is_valid_ether_addr(netdev->dev_addr)) {
1441 #endif
1442 err = -EIO;
1443 goto err_eeprom;
1444 }
1445
1446 atl2_check_options(adapter);
1447
1448 init_timer(&adapter->watchdog_timer);
1449 adapter->watchdog_timer.function = &atl2_watchdog;
1450 adapter->watchdog_timer.data = (unsigned long) adapter;
1451
1452 init_timer(&adapter->phy_config_timer);
1453 adapter->phy_config_timer.function = &atl2_phy_config;
1454 adapter->phy_config_timer.data = (unsigned long) adapter;
1455
1456 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1457 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1458
1459 strcpy(netdev->name, "eth%d"); /* ?? */
1460 err = register_netdev(netdev);
1461 if (err)
1462 goto err_register;
1463
1464 /* assume we have no link for now */
1465 netif_carrier_off(netdev);
1466 netif_stop_queue(netdev);
1467
1468 cards_found++;
1469
1470 return 0;
1471
1472 err_reset:
1473 err_register:
1474 err_sw_init:
1475 err_eeprom:
1476 iounmap(adapter->hw.hw_addr);
1477 err_ioremap:
1478 free_netdev(netdev);
1479 err_alloc_etherdev:
1480 pci_release_regions(pdev);
1481 err_pci_reg:
1482 err_dma:
1483 pci_disable_device(pdev);
1484 return err;
1485 }
1486
1487 /*
1488 * atl2_remove - Device Removal Routine
1489 * @pdev: PCI device information struct
1490 *
1491 * atl2_remove is called by the PCI subsystem to alert the driver
1492 * that it should release a PCI device. The could be caused by a
1493 * Hot-Plug event, or because the driver is going to be removed from
1494 * memory.
1495 */
1496 /* FIXME: write the original MAC address back in case it was changed from a
1497 * BIOS-set value, as in atl1 -- CHS */
1498 static void __devexit atl2_remove(struct pci_dev *pdev)
1499 {
1500 struct net_device *netdev = pci_get_drvdata(pdev);
1501 struct atl2_adapter *adapter = netdev_priv(netdev);
1502
1503 /* flush_scheduled work may reschedule our watchdog task, so
1504 * explicitly disable watchdog tasks from being rescheduled */
1505 set_bit(__ATL2_DOWN, &adapter->flags);
1506
1507 del_timer_sync(&adapter->watchdog_timer);
1508 del_timer_sync(&adapter->phy_config_timer);
1509
1510 flush_scheduled_work();
1511
1512 unregister_netdev(netdev);
1513
1514 atl2_force_ps(&adapter->hw);
1515
1516 iounmap(adapter->hw.hw_addr);
1517 pci_release_regions(pdev);
1518
1519 free_netdev(netdev);
1520
1521 pci_disable_device(pdev);
1522 }
1523
1524 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1525 {
1526 struct net_device *netdev = pci_get_drvdata(pdev);
1527 struct atl2_adapter *adapter = netdev_priv(netdev);
1528 struct atl2_hw *hw = &adapter->hw;
1529 u16 speed, duplex;
1530 u32 ctrl = 0;
1531 u32 wufc = adapter->wol;
1532
1533 #ifdef CONFIG_PM
1534 int retval = 0;
1535 #endif
1536
1537 netif_device_detach(netdev);
1538
1539 if (netif_running(netdev)) {
1540 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1541 atl2_down(adapter);
1542 }
1543
1544 #ifdef CONFIG_PM
1545 retval = pci_save_state(pdev);
1546 if (retval)
1547 return retval;
1548 #endif
1549
1550 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1551 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1552 if (ctrl & BMSR_LSTATUS)
1553 wufc &= ~ATLX_WUFC_LNKC;
1554
1555 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1556 u32 ret_val;
1557 /* get current link speed & duplex */
1558 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1559 if (ret_val) {
1560 printk(KERN_DEBUG
1561 "%s: get speed&duplex error while suspend\n",
1562 atl2_driver_name);
1563 goto wol_dis;
1564 }
1565
1566 ctrl = 0;
1567
1568 /* turn on magic packet wol */
1569 if (wufc & ATLX_WUFC_MAG)
1570 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1571
1572 /* ignore Link Chg event when Link is up */
1573 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1574
1575 /* Config MAC CTRL Register */
1576 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1577 if (FULL_DUPLEX == adapter->link_duplex)
1578 ctrl |= MAC_CTRL_DUPLX;
1579 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1580 ctrl |= (((u32)adapter->hw.preamble_len &
1581 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1582 ctrl |= (((u32)(adapter->hw.retry_buf &
1583 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1584 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1585 if (wufc & ATLX_WUFC_MAG) {
1586 /* magic packet maybe Broadcast&multicast&Unicast */
1587 ctrl |= MAC_CTRL_BC_EN;
1588 }
1589
1590 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1591
1592 /* pcie patch */
1593 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1594 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1595 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1596 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1597 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1598 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1599
1600 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1601 goto suspend_exit;
1602 }
1603
1604 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1605 /* link is down, so only LINK CHG WOL event enable */
1606 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1607 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1608 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1609
1610 /* pcie patch */
1611 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1612 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1613 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1614 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1615 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1616 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1617
1618 hw->phy_configured = false; /* re-init PHY when resume */
1619
1620 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1621
1622 goto suspend_exit;
1623 }
1624
1625 wol_dis:
1626 /* WOL disabled */
1627 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1628
1629 /* pcie patch */
1630 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1631 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1632 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1633 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1634 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1635 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1636
1637 atl2_force_ps(hw);
1638 hw->phy_configured = false; /* re-init PHY when resume */
1639
1640 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1641
1642 suspend_exit:
1643 if (netif_running(netdev))
1644 atl2_free_irq(adapter);
1645
1646 pci_disable_device(pdev);
1647
1648 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1649
1650 return 0;
1651 }
1652
1653 #ifdef CONFIG_PM
1654 static int atl2_resume(struct pci_dev *pdev)
1655 {
1656 struct net_device *netdev = pci_get_drvdata(pdev);
1657 struct atl2_adapter *adapter = netdev_priv(netdev);
1658 u32 err;
1659
1660 pci_set_power_state(pdev, PCI_D0);
1661 pci_restore_state(pdev);
1662
1663 err = pci_enable_device(pdev);
1664 if (err) {
1665 printk(KERN_ERR
1666 "atl2: Cannot enable PCI device from suspend\n");
1667 return err;
1668 }
1669
1670 pci_set_master(pdev);
1671
1672 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1673
1674 pci_enable_wake(pdev, PCI_D3hot, 0);
1675 pci_enable_wake(pdev, PCI_D3cold, 0);
1676
1677 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1678
1679 if (netif_running(netdev)) {
1680 err = atl2_request_irq(adapter);
1681 if (err)
1682 return err;
1683 }
1684
1685 atl2_reset_hw(&adapter->hw);
1686
1687 if (netif_running(netdev))
1688 atl2_up(adapter);
1689
1690 netif_device_attach(netdev);
1691
1692 return 0;
1693 }
1694 #endif
1695
1696 static void atl2_shutdown(struct pci_dev *pdev)
1697 {
1698 atl2_suspend(pdev, PMSG_SUSPEND);
1699 }
1700
1701 static struct pci_driver atl2_driver = {
1702 .name = atl2_driver_name,
1703 .id_table = atl2_pci_tbl,
1704 .probe = atl2_probe,
1705 .remove = __devexit_p(atl2_remove),
1706 /* Power Managment Hooks */
1707 .suspend = atl2_suspend,
1708 #ifdef CONFIG_PM
1709 .resume = atl2_resume,
1710 #endif
1711 .shutdown = atl2_shutdown,
1712 };
1713
1714 /*
1715 * atl2_init_module - Driver Registration Routine
1716 *
1717 * atl2_init_module is the first routine called when the driver is
1718 * loaded. All it does is register with the PCI subsystem.
1719 */
1720 static int __init atl2_init_module(void)
1721 {
1722 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1723 atl2_driver_version);
1724 printk(KERN_INFO "%s\n", atl2_copyright);
1725 return pci_register_driver(&atl2_driver);
1726 }
1727 module_init(atl2_init_module);
1728
1729 /*
1730 * atl2_exit_module - Driver Exit Cleanup Routine
1731 *
1732 * atl2_exit_module is called just before the driver is removed
1733 * from memory.
1734 */
1735 static void __exit atl2_exit_module(void)
1736 {
1737 pci_unregister_driver(&atl2_driver);
1738 }
1739 module_exit(atl2_exit_module);
1740
1741 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1742 {
1743 struct atl2_adapter *adapter = hw->back;
1744 pci_read_config_word(adapter->pdev, reg, value);
1745 }
1746
1747 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1748 {
1749 struct atl2_adapter *adapter = hw->back;
1750 pci_write_config_word(adapter->pdev, reg, *value);
1751 }
1752
1753 static int atl2_get_settings(struct net_device *netdev,
1754 struct ethtool_cmd *ecmd)
1755 {
1756 struct atl2_adapter *adapter = netdev_priv(netdev);
1757 struct atl2_hw *hw = &adapter->hw;
1758
1759 ecmd->supported = (SUPPORTED_10baseT_Half |
1760 SUPPORTED_10baseT_Full |
1761 SUPPORTED_100baseT_Half |
1762 SUPPORTED_100baseT_Full |
1763 SUPPORTED_Autoneg |
1764 SUPPORTED_TP);
1765 ecmd->advertising = ADVERTISED_TP;
1766
1767 ecmd->advertising |= ADVERTISED_Autoneg;
1768 ecmd->advertising |= hw->autoneg_advertised;
1769
1770 ecmd->port = PORT_TP;
1771 ecmd->phy_address = 0;
1772 ecmd->transceiver = XCVR_INTERNAL;
1773
1774 if (adapter->link_speed != SPEED_0) {
1775 ecmd->speed = adapter->link_speed;
1776 if (adapter->link_duplex == FULL_DUPLEX)
1777 ecmd->duplex = DUPLEX_FULL;
1778 else
1779 ecmd->duplex = DUPLEX_HALF;
1780 } else {
1781 ecmd->speed = -1;
1782 ecmd->duplex = -1;
1783 }
1784
1785 ecmd->autoneg = AUTONEG_ENABLE;
1786 return 0;
1787 }
1788
1789 static int atl2_set_settings(struct net_device *netdev,
1790 struct ethtool_cmd *ecmd)
1791 {
1792 struct atl2_adapter *adapter = netdev_priv(netdev);
1793 struct atl2_hw *hw = &adapter->hw;
1794
1795 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1796 msleep(1);
1797
1798 if (ecmd->autoneg == AUTONEG_ENABLE) {
1799 #define MY_ADV_MASK (ADVERTISE_10_HALF | \
1800 ADVERTISE_10_FULL | \
1801 ADVERTISE_100_HALF| \
1802 ADVERTISE_100_FULL)
1803
1804 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1805 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1806 hw->autoneg_advertised = MY_ADV_MASK;
1807 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1808 ADVERTISE_100_FULL) {
1809 hw->MediaType = MEDIA_TYPE_100M_FULL;
1810 hw->autoneg_advertised = ADVERTISE_100_FULL;
1811 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1812 ADVERTISE_100_HALF) {
1813 hw->MediaType = MEDIA_TYPE_100M_HALF;
1814 hw->autoneg_advertised = ADVERTISE_100_HALF;
1815 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1816 ADVERTISE_10_FULL) {
1817 hw->MediaType = MEDIA_TYPE_10M_FULL;
1818 hw->autoneg_advertised = ADVERTISE_10_FULL;
1819 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1820 ADVERTISE_10_HALF) {
1821 hw->MediaType = MEDIA_TYPE_10M_HALF;
1822 hw->autoneg_advertised = ADVERTISE_10_HALF;
1823 } else {
1824 clear_bit(__ATL2_RESETTING, &adapter->flags);
1825 return -EINVAL;
1826 }
1827 ecmd->advertising = hw->autoneg_advertised |
1828 ADVERTISED_TP | ADVERTISED_Autoneg;
1829 } else {
1830 clear_bit(__ATL2_RESETTING, &adapter->flags);
1831 return -EINVAL;
1832 }
1833
1834 /* reset the link */
1835 if (netif_running(adapter->netdev)) {
1836 atl2_down(adapter);
1837 atl2_up(adapter);
1838 } else
1839 atl2_reset_hw(&adapter->hw);
1840
1841 clear_bit(__ATL2_RESETTING, &adapter->flags);
1842 return 0;
1843 }
1844
1845 static u32 atl2_get_tx_csum(struct net_device *netdev)
1846 {
1847 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1848 }
1849
1850 static u32 atl2_get_msglevel(struct net_device *netdev)
1851 {
1852 return 0;
1853 }
1854
1855 /*
1856 * It's sane for this to be empty, but we might want to take advantage of this.
1857 */
1858 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1859 {
1860 }
1861
1862 static int atl2_get_regs_len(struct net_device *netdev)
1863 {
1864 #define ATL2_REGS_LEN 42
1865 return sizeof(u32) * ATL2_REGS_LEN;
1866 }
1867
1868 static void atl2_get_regs(struct net_device *netdev,
1869 struct ethtool_regs *regs, void *p)
1870 {
1871 struct atl2_adapter *adapter = netdev_priv(netdev);
1872 struct atl2_hw *hw = &adapter->hw;
1873 u32 *regs_buff = p;
1874 u16 phy_data;
1875
1876 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1877
1878 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1879
1880 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1881 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1882 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1883 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1884 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1885 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1886 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1887 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1888 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1889 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1890 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1891 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1892 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1893 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1894 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1895 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1896 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1897 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1898 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1899 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1900 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1901 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1902 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1903 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1904 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1905 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1906 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1907 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1908 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1909 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1910 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1911 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1912 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1913 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1914 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1915 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1916 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1917 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1918 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1919
1920 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1921 regs_buff[40] = (u32)phy_data;
1922 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1923 regs_buff[41] = (u32)phy_data;
1924 }
1925
1926 static int atl2_get_eeprom_len(struct net_device *netdev)
1927 {
1928 struct atl2_adapter *adapter = netdev_priv(netdev);
1929
1930 if (!atl2_check_eeprom_exist(&adapter->hw))
1931 return 512;
1932 else
1933 return 0;
1934 }
1935
1936 static int atl2_get_eeprom(struct net_device *netdev,
1937 struct ethtool_eeprom *eeprom, u8 *bytes)
1938 {
1939 struct atl2_adapter *adapter = netdev_priv(netdev);
1940 struct atl2_hw *hw = &adapter->hw;
1941 u32 *eeprom_buff;
1942 int first_dword, last_dword;
1943 int ret_val = 0;
1944 int i;
1945
1946 if (eeprom->len == 0)
1947 return -EINVAL;
1948
1949 if (atl2_check_eeprom_exist(hw))
1950 return -EINVAL;
1951
1952 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1953
1954 first_dword = eeprom->offset >> 2;
1955 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1956
1957 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1958 GFP_KERNEL);
1959 if (!eeprom_buff)
1960 return -ENOMEM;
1961
1962 for (i = first_dword; i < last_dword; i++) {
1963 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1964 ret_val = -EIO;
1965 goto free;
1966 }
1967 }
1968
1969 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1970 eeprom->len);
1971 free:
1972 kfree(eeprom_buff);
1973
1974 return ret_val;
1975 }
1976
1977 static int atl2_set_eeprom(struct net_device *netdev,
1978 struct ethtool_eeprom *eeprom, u8 *bytes)
1979 {
1980 struct atl2_adapter *adapter = netdev_priv(netdev);
1981 struct atl2_hw *hw = &adapter->hw;
1982 u32 *eeprom_buff;
1983 u32 *ptr;
1984 int max_len, first_dword, last_dword, ret_val = 0;
1985 int i;
1986
1987 if (eeprom->len == 0)
1988 return -EOPNOTSUPP;
1989
1990 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1991 return -EFAULT;
1992
1993 max_len = 512;
1994
1995 first_dword = eeprom->offset >> 2;
1996 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1997 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1998 if (!eeprom_buff)
1999 return -ENOMEM;
2000
2001 ptr = (u32 *)eeprom_buff;
2002
2003 if (eeprom->offset & 3) {
2004 /* need read/modify/write of first changed EEPROM word */
2005 /* only the second byte of the word is being modified */
2006 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2007 return -EIO;
2008 ptr++;
2009 }
2010 if (((eeprom->offset + eeprom->len) & 3)) {
2011 /*
2012 * need read/modify/write of last changed EEPROM word
2013 * only the first byte of the word is being modified
2014 */
2015 if (!atl2_read_eeprom(hw, last_dword * 4,
2016 &(eeprom_buff[last_dword - first_dword])))
2017 return -EIO;
2018 }
2019
2020 /* Device's eeprom is always little-endian, word addressable */
2021 memcpy(ptr, bytes, eeprom->len);
2022
2023 for (i = 0; i < last_dword - first_dword + 1; i++) {
2024 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2025 return -EIO;
2026 }
2027
2028 kfree(eeprom_buff);
2029 return ret_val;
2030 }
2031
2032 static void atl2_get_drvinfo(struct net_device *netdev,
2033 struct ethtool_drvinfo *drvinfo)
2034 {
2035 struct atl2_adapter *adapter = netdev_priv(netdev);
2036
2037 strncpy(drvinfo->driver, atl2_driver_name, 32);
2038 strncpy(drvinfo->version, atl2_driver_version, 32);
2039 strncpy(drvinfo->fw_version, "L2", 32);
2040 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2041 drvinfo->n_stats = 0;
2042 drvinfo->testinfo_len = 0;
2043 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2044 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2045 }
2046
2047 static void atl2_get_wol(struct net_device *netdev,
2048 struct ethtool_wolinfo *wol)
2049 {
2050 struct atl2_adapter *adapter = netdev_priv(netdev);
2051
2052 wol->supported = WAKE_MAGIC;
2053 wol->wolopts = 0;
2054
2055 if (adapter->wol & ATLX_WUFC_EX)
2056 wol->wolopts |= WAKE_UCAST;
2057 if (adapter->wol & ATLX_WUFC_MC)
2058 wol->wolopts |= WAKE_MCAST;
2059 if (adapter->wol & ATLX_WUFC_BC)
2060 wol->wolopts |= WAKE_BCAST;
2061 if (adapter->wol & ATLX_WUFC_MAG)
2062 wol->wolopts |= WAKE_MAGIC;
2063 if (adapter->wol & ATLX_WUFC_LNKC)
2064 wol->wolopts |= WAKE_PHY;
2065 }
2066
2067 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2068 {
2069 struct atl2_adapter *adapter = netdev_priv(netdev);
2070
2071 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2072 return -EOPNOTSUPP;
2073
2074 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
2075 return -EOPNOTSUPP;
2076
2077 /* these settings will always override what we currently have */
2078 adapter->wol = 0;
2079
2080 if (wol->wolopts & WAKE_MAGIC)
2081 adapter->wol |= ATLX_WUFC_MAG;
2082 if (wol->wolopts & WAKE_PHY)
2083 adapter->wol |= ATLX_WUFC_LNKC;
2084
2085 return 0;
2086 }
2087
2088 static int atl2_nway_reset(struct net_device *netdev)
2089 {
2090 struct atl2_adapter *adapter = netdev_priv(netdev);
2091 if (netif_running(netdev))
2092 atl2_reinit_locked(adapter);
2093 return 0;
2094 }
2095
2096 static const struct ethtool_ops atl2_ethtool_ops = {
2097 .get_settings = atl2_get_settings,
2098 .set_settings = atl2_set_settings,
2099 .get_drvinfo = atl2_get_drvinfo,
2100 .get_regs_len = atl2_get_regs_len,
2101 .get_regs = atl2_get_regs,
2102 .get_wol = atl2_get_wol,
2103 .set_wol = atl2_set_wol,
2104 .get_msglevel = atl2_get_msglevel,
2105 .set_msglevel = atl2_set_msglevel,
2106 .nway_reset = atl2_nway_reset,
2107 .get_link = ethtool_op_get_link,
2108 .get_eeprom_len = atl2_get_eeprom_len,
2109 .get_eeprom = atl2_get_eeprom,
2110 .set_eeprom = atl2_set_eeprom,
2111 .get_tx_csum = atl2_get_tx_csum,
2112 .get_sg = ethtool_op_get_sg,
2113 .set_sg = ethtool_op_set_sg,
2114 #ifdef NETIF_F_TSO
2115 .get_tso = ethtool_op_get_tso,
2116 #endif
2117 };
2118
2119 static void atl2_set_ethtool_ops(struct net_device *netdev)
2120 {
2121 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2122 }
2123
2124 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2125 (((a) & 0xff00ff00) >> 8))
2126 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2127 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2128
2129 /*
2130 * Reset the transmit and receive units; mask and clear all interrupts.
2131 *
2132 * hw - Struct containing variables accessed by shared code
2133 * return : 0 or idle status (if error)
2134 */
2135 static s32 atl2_reset_hw(struct atl2_hw *hw)
2136 {
2137 u32 icr;
2138 u16 pci_cfg_cmd_word;
2139 int i;
2140
2141 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2142 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2143 if ((pci_cfg_cmd_word &
2144 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2145 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2146 pci_cfg_cmd_word |=
2147 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2148 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2149 }
2150
2151 /* Clear Interrupt mask to stop board from generating
2152 * interrupts & Clear any pending interrupt events
2153 */
2154 /* FIXME */
2155 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2156 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2157
2158 /* Issue Soft Reset to the MAC. This will reset the chip's
2159 * transmit, receive, DMA. It will not effect
2160 * the current PCI configuration. The global reset bit is self-
2161 * clearing, and should clear within a microsecond.
2162 */
2163 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2164 wmb();
2165 msleep(1); /* delay about 1ms */
2166
2167 /* Wait at least 10ms for All module to be Idle */
2168 for (i = 0; i < 10; i++) {
2169 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2170 if (!icr)
2171 break;
2172 msleep(1); /* delay 1 ms */
2173 cpu_relax();
2174 }
2175
2176 if (icr)
2177 return icr;
2178
2179 return 0;
2180 }
2181
2182 #define CUSTOM_SPI_CS_SETUP 2
2183 #define CUSTOM_SPI_CLK_HI 2
2184 #define CUSTOM_SPI_CLK_LO 2
2185 #define CUSTOM_SPI_CS_HOLD 2
2186 #define CUSTOM_SPI_CS_HI 3
2187
2188 static struct atl2_spi_flash_dev flash_table[] =
2189 {
2190 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2191 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2192 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2193 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2194 };
2195
2196 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2197 {
2198 int i;
2199 u32 value;
2200
2201 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2202 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2203
2204 value = SPI_FLASH_CTRL_WAIT_READY |
2205 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2206 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2207 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2208 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2209 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2210 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2211 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2212 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2213 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2214 SPI_FLASH_CTRL_CS_HI_SHIFT |
2215 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2216
2217 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2218
2219 value |= SPI_FLASH_CTRL_START;
2220
2221 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2222
2223 for (i = 0; i < 10; i++) {
2224 msleep(1);
2225 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2226 if (!(value & SPI_FLASH_CTRL_START))
2227 break;
2228 }
2229
2230 if (value & SPI_FLASH_CTRL_START)
2231 return false;
2232
2233 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2234
2235 return true;
2236 }
2237
2238 /*
2239 * get_permanent_address
2240 * return 0 if get valid mac address,
2241 */
2242 static int get_permanent_address(struct atl2_hw *hw)
2243 {
2244 u32 Addr[2];
2245 u32 i, Control;
2246 u16 Register;
2247 u8 EthAddr[NODE_ADDRESS_SIZE];
2248 bool KeyValid;
2249
2250 if (is_valid_ether_addr(hw->perm_mac_addr))
2251 return 0;
2252
2253 Addr[0] = 0;
2254 Addr[1] = 0;
2255
2256 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2257 Register = 0;
2258 KeyValid = false;
2259
2260 /* Read out all EEPROM content */
2261 i = 0;
2262 while (1) {
2263 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2264 if (KeyValid) {
2265 if (Register == REG_MAC_STA_ADDR)
2266 Addr[0] = Control;
2267 else if (Register ==
2268 (REG_MAC_STA_ADDR + 4))
2269 Addr[1] = Control;
2270 KeyValid = false;
2271 } else if ((Control & 0xff) == 0x5A) {
2272 KeyValid = true;
2273 Register = (u16) (Control >> 16);
2274 } else {
2275 /* assume data end while encount an invalid KEYWORD */
2276 break;
2277 }
2278 } else {
2279 break; /* read error */
2280 }
2281 i += 4;
2282 }
2283
2284 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2285 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2286
2287 if (is_valid_ether_addr(EthAddr)) {
2288 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2289 return 0;
2290 }
2291 return 1;
2292 }
2293
2294 /* see if SPI flash exists? */
2295 Addr[0] = 0;
2296 Addr[1] = 0;
2297 Register = 0;
2298 KeyValid = false;
2299 i = 0;
2300 while (1) {
2301 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2302 if (KeyValid) {
2303 if (Register == REG_MAC_STA_ADDR)
2304 Addr[0] = Control;
2305 else if (Register == (REG_MAC_STA_ADDR + 4))
2306 Addr[1] = Control;
2307 KeyValid = false;
2308 } else if ((Control & 0xff) == 0x5A) {
2309 KeyValid = true;
2310 Register = (u16) (Control >> 16);
2311 } else {
2312 break; /* data end */
2313 }
2314 } else {
2315 break; /* read error */
2316 }
2317 i += 4;
2318 }
2319
2320 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2321 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2322 if (is_valid_ether_addr(EthAddr)) {
2323 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2324 return 0;
2325 }
2326 /* maybe MAC-address is from BIOS */
2327 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2328 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2329 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2330 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2331
2332 if (is_valid_ether_addr(EthAddr)) {
2333 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2334 return 0;
2335 }
2336
2337 return 1;
2338 }
2339
2340 /*
2341 * Reads the adapter's MAC address from the EEPROM
2342 *
2343 * hw - Struct containing variables accessed by shared code
2344 */
2345 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2346 {
2347 u16 i;
2348
2349 if (get_permanent_address(hw)) {
2350 /* for test */
2351 /* FIXME: shouldn't we use random_ether_addr() here? */
2352 hw->perm_mac_addr[0] = 0x00;
2353 hw->perm_mac_addr[1] = 0x13;
2354 hw->perm_mac_addr[2] = 0x74;
2355 hw->perm_mac_addr[3] = 0x00;
2356 hw->perm_mac_addr[4] = 0x5c;
2357 hw->perm_mac_addr[5] = 0x38;
2358 }
2359
2360 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2361 hw->mac_addr[i] = hw->perm_mac_addr[i];
2362
2363 return 0;
2364 }
2365
2366 /*
2367 * Hashes an address to determine its location in the multicast table
2368 *
2369 * hw - Struct containing variables accessed by shared code
2370 * mc_addr - the multicast address to hash
2371 *
2372 * atl2_hash_mc_addr
2373 * purpose
2374 * set hash value for a multicast address
2375 * hash calcu processing :
2376 * 1. calcu 32bit CRC for multicast address
2377 * 2. reverse crc with MSB to LSB
2378 */
2379 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2380 {
2381 u32 crc32, value;
2382 int i;
2383
2384 value = 0;
2385 crc32 = ether_crc_le(6, mc_addr);
2386
2387 for (i = 0; i < 32; i++)
2388 value |= (((crc32 >> i) & 1) << (31 - i));
2389
2390 return value;
2391 }
2392
2393 /*
2394 * Sets the bit in the multicast table corresponding to the hash value.
2395 *
2396 * hw - Struct containing variables accessed by shared code
2397 * hash_value - Multicast address hash value
2398 */
2399 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2400 {
2401 u32 hash_bit, hash_reg;
2402 u32 mta;
2403
2404 /* The HASH Table is a register array of 2 32-bit registers.
2405 * It is treated like an array of 64 bits. We want to set
2406 * bit BitArray[hash_value]. So we figure out what register
2407 * the bit is in, read it, OR in the new bit, then write
2408 * back the new value. The register is determined by the
2409 * upper 7 bits of the hash value and the bit within that
2410 * register are determined by the lower 5 bits of the value.
2411 */
2412 hash_reg = (hash_value >> 31) & 0x1;
2413 hash_bit = (hash_value >> 26) & 0x1F;
2414
2415 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2416
2417 mta |= (1 << hash_bit);
2418
2419 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2420 }
2421
2422 /*
2423 * atl2_init_pcie - init PCIE module
2424 */
2425 static void atl2_init_pcie(struct atl2_hw *hw)
2426 {
2427 u32 value;
2428 value = LTSSM_TEST_MODE_DEF;
2429 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2430
2431 value = PCIE_DLL_TX_CTRL1_DEF;
2432 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2433 }
2434
2435 static void atl2_init_flash_opcode(struct atl2_hw *hw)
2436 {
2437 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2438 hw->flash_vendor = 0; /* ATMEL */
2439
2440 /* Init OP table */
2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2442 flash_table[hw->flash_vendor].cmdPROGRAM);
2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2444 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2446 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2448 flash_table[hw->flash_vendor].cmdRDID);
2449 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2450 flash_table[hw->flash_vendor].cmdWREN);
2451 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2452 flash_table[hw->flash_vendor].cmdRDSR);
2453 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2454 flash_table[hw->flash_vendor].cmdWRSR);
2455 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2456 flash_table[hw->flash_vendor].cmdREAD);
2457 }
2458
2459 /********************************************************************
2460 * Performs basic configuration of the adapter.
2461 *
2462 * hw - Struct containing variables accessed by shared code
2463 * Assumes that the controller has previously been reset and is in a
2464 * post-reset uninitialized state. Initializes multicast table,
2465 * and Calls routines to setup link
2466 * Leaves the transmit and receive units disabled and uninitialized.
2467 ********************************************************************/
2468 static s32 atl2_init_hw(struct atl2_hw *hw)
2469 {
2470 u32 ret_val = 0;
2471
2472 atl2_init_pcie(hw);
2473
2474 /* Zero out the Multicast HASH table */
2475 /* clear the old settings from the multicast hash table */
2476 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2477 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2478
2479 atl2_init_flash_opcode(hw);
2480
2481 ret_val = atl2_phy_init(hw);
2482
2483 return ret_val;
2484 }
2485
2486 /*
2487 * Detects the current speed and duplex settings of the hardware.
2488 *
2489 * hw - Struct containing variables accessed by shared code
2490 * speed - Speed of the connection
2491 * duplex - Duplex setting of the connection
2492 */
2493 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2494 u16 *duplex)
2495 {
2496 s32 ret_val;
2497 u16 phy_data;
2498
2499 /* Read PHY Specific Status Register (17) */
2500 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2501 if (ret_val)
2502 return ret_val;
2503
2504 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2505 return ATLX_ERR_PHY_RES;
2506
2507 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2508 case MII_ATLX_PSSR_100MBS:
2509 *speed = SPEED_100;
2510 break;
2511 case MII_ATLX_PSSR_10MBS:
2512 *speed = SPEED_10;
2513 break;
2514 default:
2515 return ATLX_ERR_PHY_SPEED;
2516 break;
2517 }
2518
2519 if (phy_data & MII_ATLX_PSSR_DPLX)
2520 *duplex = FULL_DUPLEX;
2521 else
2522 *duplex = HALF_DUPLEX;
2523
2524 return 0;
2525 }
2526
2527 /*
2528 * Reads the value from a PHY register
2529 * hw - Struct containing variables accessed by shared code
2530 * reg_addr - address of the PHY register to read
2531 */
2532 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2533 {
2534 u32 val;
2535 int i;
2536
2537 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2538 MDIO_START |
2539 MDIO_SUP_PREAMBLE |
2540 MDIO_RW |
2541 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2542 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2543
2544 wmb();
2545
2546 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2547 udelay(2);
2548 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2549 if (!(val & (MDIO_START | MDIO_BUSY)))
2550 break;
2551 wmb();
2552 }
2553 if (!(val & (MDIO_START | MDIO_BUSY))) {
2554 *phy_data = (u16)val;
2555 return 0;
2556 }
2557
2558 return ATLX_ERR_PHY;
2559 }
2560
2561 /*
2562 * Writes a value to a PHY register
2563 * hw - Struct containing variables accessed by shared code
2564 * reg_addr - address of the PHY register to write
2565 * data - data to write to the PHY
2566 */
2567 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2568 {
2569 int i;
2570 u32 val;
2571
2572 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2573 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2574 MDIO_SUP_PREAMBLE |
2575 MDIO_START |
2576 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2577 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2578
2579 wmb();
2580
2581 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2582 udelay(2);
2583 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2584 if (!(val & (MDIO_START | MDIO_BUSY)))
2585 break;
2586
2587 wmb();
2588 }
2589
2590 if (!(val & (MDIO_START | MDIO_BUSY)))
2591 return 0;
2592
2593 return ATLX_ERR_PHY;
2594 }
2595
2596 /*
2597 * Configures PHY autoneg and flow control advertisement settings
2598 *
2599 * hw - Struct containing variables accessed by shared code
2600 */
2601 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2602 {
2603 s32 ret_val;
2604 s16 mii_autoneg_adv_reg;
2605
2606 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2607 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2608
2609 /* Need to parse autoneg_advertised and set up
2610 * the appropriate PHY registers. First we will parse for
2611 * autoneg_advertised software override. Since we can advertise
2612 * a plethora of combinations, we need to check each bit
2613 * individually.
2614 */
2615
2616 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2617 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2618 * the 1000Base-T Control Register (Address 9). */
2619 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2620
2621 /* Need to parse MediaType and setup the
2622 * appropriate PHY registers. */
2623 switch (hw->MediaType) {
2624 case MEDIA_TYPE_AUTO_SENSOR:
2625 mii_autoneg_adv_reg |=
2626 (MII_AR_10T_HD_CAPS |
2627 MII_AR_10T_FD_CAPS |
2628 MII_AR_100TX_HD_CAPS|
2629 MII_AR_100TX_FD_CAPS);
2630 hw->autoneg_advertised =
2631 ADVERTISE_10_HALF |
2632 ADVERTISE_10_FULL |
2633 ADVERTISE_100_HALF|
2634 ADVERTISE_100_FULL;
2635 break;
2636 case MEDIA_TYPE_100M_FULL:
2637 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2638 hw->autoneg_advertised = ADVERTISE_100_FULL;
2639 break;
2640 case MEDIA_TYPE_100M_HALF:
2641 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2642 hw->autoneg_advertised = ADVERTISE_100_HALF;
2643 break;
2644 case MEDIA_TYPE_10M_FULL:
2645 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2646 hw->autoneg_advertised = ADVERTISE_10_FULL;
2647 break;
2648 default:
2649 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2650 hw->autoneg_advertised = ADVERTISE_10_HALF;
2651 break;
2652 }
2653
2654 /* flow control fixed to enable all */
2655 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2656
2657 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2658
2659 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2660
2661 if (ret_val)
2662 return ret_val;
2663
2664 return 0;
2665 }
2666
2667 /*
2668 * Resets the PHY and make all config validate
2669 *
2670 * hw - Struct containing variables accessed by shared code
2671 *
2672 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2673 */
2674 static s32 atl2_phy_commit(struct atl2_hw *hw)
2675 {
2676 s32 ret_val;
2677 u16 phy_data;
2678
2679 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2680 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2681 if (ret_val) {
2682 u32 val;
2683 int i;
2684 /* pcie serdes link may be down ! */
2685 for (i = 0; i < 25; i++) {
2686 msleep(1);
2687 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2688 if (!(val & (MDIO_START | MDIO_BUSY)))
2689 break;
2690 }
2691
2692 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2693 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2694 return ret_val;
2695 }
2696 }
2697 return 0;
2698 }
2699
2700 static s32 atl2_phy_init(struct atl2_hw *hw)
2701 {
2702 s32 ret_val;
2703 u16 phy_val;
2704
2705 if (hw->phy_configured)
2706 return 0;
2707
2708 /* Enable PHY */
2709 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2710 ATL2_WRITE_FLUSH(hw);
2711 msleep(1);
2712
2713 /* check if the PHY is in powersaving mode */
2714 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2715 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2716
2717 /* 024E / 124E 0r 0274 / 1274 ? */
2718 if (phy_val & 0x1000) {
2719 phy_val &= ~0x1000;
2720 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2721 }
2722
2723 msleep(1);
2724
2725 /*Enable PHY LinkChange Interrupt */
2726 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2727 if (ret_val)
2728 return ret_val;
2729
2730 /* setup AutoNeg parameters */
2731 ret_val = atl2_phy_setup_autoneg_adv(hw);
2732 if (ret_val)
2733 return ret_val;
2734
2735 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2736 ret_val = atl2_phy_commit(hw);
2737 if (ret_val)
2738 return ret_val;
2739
2740 hw->phy_configured = true;
2741
2742 return ret_val;
2743 }
2744
2745 static void atl2_set_mac_addr(struct atl2_hw *hw)
2746 {
2747 u32 value;
2748 /* 00-0B-6A-F6-00-DC
2749 * 0: 6AF600DC 1: 000B
2750 * low dword */
2751 value = (((u32)hw->mac_addr[2]) << 24) |
2752 (((u32)hw->mac_addr[3]) << 16) |
2753 (((u32)hw->mac_addr[4]) << 8) |
2754 (((u32)hw->mac_addr[5]));
2755 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2756 /* hight dword */
2757 value = (((u32)hw->mac_addr[0]) << 8) |
2758 (((u32)hw->mac_addr[1]));
2759 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2760 }
2761
2762 /*
2763 * check_eeprom_exist
2764 * return 0 if eeprom exist
2765 */
2766 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2767 {
2768 u32 value;
2769
2770 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2771 if (value & SPI_FLASH_CTRL_EN_VPD) {
2772 value &= ~SPI_FLASH_CTRL_EN_VPD;
2773 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2774 }
2775 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2776 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2777 }
2778
2779 /* FIXME: This doesn't look right. -- CHS */
2780 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2781 {
2782 return true;
2783 }
2784
2785 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2786 {
2787 int i;
2788 u32 Control;
2789
2790 if (Offset & 0x3)
2791 return false; /* address do not align */
2792
2793 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2794 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2795 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2796
2797 for (i = 0; i < 10; i++) {
2798 msleep(2);
2799 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2800 if (Control & VPD_CAP_VPD_FLAG)
2801 break;
2802 }
2803
2804 if (Control & VPD_CAP_VPD_FLAG) {
2805 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2806 return true;
2807 }
2808 return false; /* timeout */
2809 }
2810
2811 static void atl2_force_ps(struct atl2_hw *hw)
2812 {
2813 u16 phy_val;
2814
2815 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2816 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2817 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2818
2819 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2820 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2821 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2822 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2823 }
2824
2825 /* This is the only thing that needs to be changed to adjust the
2826 * maximum number of ports that the driver can manage.
2827 */
2828 #define ATL2_MAX_NIC 4
2829
2830 #define OPTION_UNSET -1
2831 #define OPTION_DISABLED 0
2832 #define OPTION_ENABLED 1
2833
2834 /* All parameters are treated the same, as an integer array of values.
2835 * This macro just reduces the need to repeat the same declaration code
2836 * over and over (plus this helps to avoid typo bugs).
2837 */
2838 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2839 #ifndef module_param_array
2840 /* Module Parameters are always initialized to -1, so that the driver
2841 * can tell the difference between no user specified value or the
2842 * user asking for the default value.
2843 * The true default values are loaded in when atl2_check_options is called.
2844 *
2845 * This is a GCC extension to ANSI C.
2846 * See the item "Labeled Elements in Initializers" in the section
2847 * "Extensions to the C Language Family" of the GCC documentation.
2848 */
2849
2850 #define ATL2_PARAM(X, desc) \
2851 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2852 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2853 MODULE_PARM_DESC(X, desc);
2854 #else
2855 #define ATL2_PARAM(X, desc) \
2856 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2857 static unsigned int num_##X; \
2858 module_param_array_named(X, X, int, &num_##X, 0); \
2859 MODULE_PARM_DESC(X, desc);
2860 #endif
2861
2862 /*
2863 * Transmit Memory Size
2864 * Valid Range: 64-2048
2865 * Default Value: 128
2866 */
2867 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2868 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2869 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2870 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2871
2872 /*
2873 * Receive Memory Block Count
2874 * Valid Range: 16-512
2875 * Default Value: 128
2876 */
2877 #define ATL2_MIN_RXD_COUNT 16
2878 #define ATL2_MAX_RXD_COUNT 512
2879 #define ATL2_DEFAULT_RXD_COUNT 64
2880 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2881
2882 /*
2883 * User Specified MediaType Override
2884 *
2885 * Valid Range: 0-5
2886 * - 0 - auto-negotiate at all supported speeds
2887 * - 1 - only link at 1000Mbps Full Duplex
2888 * - 2 - only link at 100Mbps Full Duplex
2889 * - 3 - only link at 100Mbps Half Duplex
2890 * - 4 - only link at 10Mbps Full Duplex
2891 * - 5 - only link at 10Mbps Half Duplex
2892 * Default Value: 0
2893 */
2894 ATL2_PARAM(MediaType, "MediaType Select");
2895
2896 /*
2897 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2898 * Valid Range: 10-65535
2899 * Default Value: 45000(90ms)
2900 */
2901 #define INT_MOD_DEFAULT_CNT 100 /* 200us */
2902 #define INT_MOD_MAX_CNT 65000
2903 #define INT_MOD_MIN_CNT 50
2904 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2905
2906 /*
2907 * FlashVendor
2908 * Valid Range: 0-2
2909 * 0 - Atmel
2910 * 1 - SST
2911 * 2 - ST
2912 */
2913 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2914
2915 #define AUTONEG_ADV_DEFAULT 0x2F
2916 #define AUTONEG_ADV_MASK 0x2F
2917 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2918
2919 #define FLASH_VENDOR_DEFAULT 0
2920 #define FLASH_VENDOR_MIN 0
2921 #define FLASH_VENDOR_MAX 2
2922
2923 struct atl2_option {
2924 enum { enable_option, range_option, list_option } type;
2925 char *name;
2926 char *err;
2927 int def;
2928 union {
2929 struct { /* range_option info */
2930 int min;
2931 int max;
2932 } r;
2933 struct { /* list_option info */
2934 int nr;
2935 struct atl2_opt_list { int i; char *str; } *p;
2936 } l;
2937 } arg;
2938 };
2939
2940 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2941 {
2942 int i;
2943 struct atl2_opt_list *ent;
2944
2945 if (*value == OPTION_UNSET) {
2946 *value = opt->def;
2947 return 0;
2948 }
2949
2950 switch (opt->type) {
2951 case enable_option:
2952 switch (*value) {
2953 case OPTION_ENABLED:
2954 printk(KERN_INFO "%s Enabled\n", opt->name);
2955 return 0;
2956 break;
2957 case OPTION_DISABLED:
2958 printk(KERN_INFO "%s Disabled\n", opt->name);
2959 return 0;
2960 break;
2961 }
2962 break;
2963 case range_option:
2964 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2965 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2966 return 0;
2967 }
2968 break;
2969 case list_option:
2970 for (i = 0; i < opt->arg.l.nr; i++) {
2971 ent = &opt->arg.l.p[i];
2972 if (*value == ent->i) {
2973 if (ent->str[0] != '\0')
2974 printk(KERN_INFO "%s\n", ent->str);
2975 return 0;
2976 }
2977 }
2978 break;
2979 default:
2980 BUG();
2981 }
2982
2983 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2984 opt->name, *value, opt->err);
2985 *value = opt->def;
2986 return -1;
2987 }
2988
2989 /*
2990 * atl2_check_options - Range Checking for Command Line Parameters
2991 * @adapter: board private structure
2992 *
2993 * This routine checks all command line parameters for valid user
2994 * input. If an invalid value is given, or if no user specified
2995 * value exists, a default value is used. The final value is stored
2996 * in a variable in the adapter structure.
2997 */
2998 static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2999 {
3000 int val;
3001 struct atl2_option opt;
3002 int bd = adapter->bd_number;
3003 if (bd >= ATL2_MAX_NIC) {
3004 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3005 bd);
3006 printk(KERN_NOTICE "Using defaults for all values\n");
3007 #ifndef module_param_array
3008 bd = ATL2_MAX_NIC;
3009 #endif
3010 }
3011
3012 /* Bytes of Transmit Memory */
3013 opt.type = range_option;
3014 opt.name = "Bytes of Transmit Memory";
3015 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3016 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3017 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3018 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3019 #ifdef module_param_array
3020 if (num_TxMemSize > bd) {
3021 #endif
3022 val = TxMemSize[bd];
3023 atl2_validate_option(&val, &opt);
3024 adapter->txd_ring_size = ((u32) val) * 1024;
3025 #ifdef module_param_array
3026 } else
3027 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3028 #endif
3029 /* txs ring size: */
3030 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3031 if (adapter->txs_ring_size > 160)
3032 adapter->txs_ring_size = 160;
3033
3034 /* Receive Memory Block Count */
3035 opt.type = range_option;
3036 opt.name = "Number of receive memory block";
3037 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3038 opt.def = ATL2_DEFAULT_RXD_COUNT;
3039 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3040 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3041 #ifdef module_param_array
3042 if (num_RxMemBlock > bd) {
3043 #endif
3044 val = RxMemBlock[bd];
3045 atl2_validate_option(&val, &opt);
3046 adapter->rxd_ring_size = (u32)val;
3047 /* FIXME */
3048 /* ((u16)val)&~1; */ /* even number */
3049 #ifdef module_param_array
3050 } else
3051 adapter->rxd_ring_size = (u32)opt.def;
3052 #endif
3053 /* init RXD Flow control value */
3054 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3055 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3056 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3057 (adapter->rxd_ring_size / 12);
3058
3059 /* Interrupt Moderate Timer */
3060 opt.type = range_option;
3061 opt.name = "Interrupt Moderate Timer";
3062 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3063 opt.def = INT_MOD_DEFAULT_CNT;
3064 opt.arg.r.min = INT_MOD_MIN_CNT;
3065 opt.arg.r.max = INT_MOD_MAX_CNT;
3066 #ifdef module_param_array
3067 if (num_IntModTimer > bd) {
3068 #endif
3069 val = IntModTimer[bd];
3070 atl2_validate_option(&val, &opt);
3071 adapter->imt = (u16) val;
3072 #ifdef module_param_array
3073 } else
3074 adapter->imt = (u16)(opt.def);
3075 #endif
3076 /* Flash Vendor */
3077 opt.type = range_option;
3078 opt.name = "SPI Flash Vendor";
3079 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3080 opt.def = FLASH_VENDOR_DEFAULT;
3081 opt.arg.r.min = FLASH_VENDOR_MIN;
3082 opt.arg.r.max = FLASH_VENDOR_MAX;
3083 #ifdef module_param_array
3084 if (num_FlashVendor > bd) {
3085 #endif
3086 val = FlashVendor[bd];
3087 atl2_validate_option(&val, &opt);
3088 adapter->hw.flash_vendor = (u8) val;
3089 #ifdef module_param_array
3090 } else
3091 adapter->hw.flash_vendor = (u8)(opt.def);
3092 #endif
3093 /* MediaType */
3094 opt.type = range_option;
3095 opt.name = "Speed/Duplex Selection";
3096 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3097 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3098 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3099 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3100 #ifdef module_param_array
3101 if (num_MediaType > bd) {
3102 #endif
3103 val = MediaType[bd];
3104 atl2_validate_option(&val, &opt);
3105 adapter->hw.MediaType = (u16) val;
3106 #ifdef module_param_array
3107 } else
3108 adapter->hw.MediaType = (u16)(opt.def);
3109 #endif
3110 }
kernel source for telekom puls (alcatel/mediatek)