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mtd: replace DEBUG() with pr_debug()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
39
40 #define DRIVER_NAME "mxc_nand"
41
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() cpu_is_mx51()
45 #define nfc_is_v3() nfc_is_v3_2()
46
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
67 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
70
71 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
72 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
77 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
78 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
81
82 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
83
84 /*
85 * Operation modes for the NFC. Valid for v1, v2 and v3
86 * type controllers.
87 */
88 #define NFC_CMD (1 << 0)
89 #define NFC_ADDR (1 << 1)
90 #define NFC_INPUT (1 << 2)
91 #define NFC_OUTPUT (1 << 3)
92 #define NFC_ID (1 << 4)
93 #define NFC_STATUS (1 << 5)
94
95 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
97
98 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
100 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
101
102 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
103
104 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
105
106 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
107 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108 #define NFC_V3_WRPROT_LOCK (1 << 1)
109 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
110 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
111
112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
113
114 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
116 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
128
129 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131 #define NFC_V3_CONFIG3_FW8 (1 << 3)
132 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
136
137 #define NFC_V3_IPC (host->regs_ip + 0x2C)
138 #define NFC_V3_IPC_CREQ (1 << 0)
139 #define NFC_V3_IPC_INT (1 << 31)
140
141 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
142
143 struct mxc_nand_host {
144 struct mtd_info mtd;
145 struct nand_chip nand;
146 struct device *dev;
147
148 void *spare0;
149 void *main_area0;
150
151 void __iomem *base;
152 void __iomem *regs;
153 void __iomem *regs_axi;
154 void __iomem *regs_ip;
155 int status_request;
156 struct clk *clk;
157 int clk_act;
158 int irq;
159 int eccsize;
160 int active_cs;
161
162 struct completion op_completion;
163
164 uint8_t *data_buf;
165 unsigned int buf_start;
166 int spare_len;
167
168 void (*preset)(struct mtd_info *);
169 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
170 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
171 void (*send_page)(struct mtd_info *, unsigned int);
172 void (*send_read_id)(struct mxc_nand_host *);
173 uint16_t (*get_dev_status)(struct mxc_nand_host *);
174 int (*check_int)(struct mxc_nand_host *);
175 void (*irq_control)(struct mxc_nand_host *, int);
176 };
177
178 /* OOB placement block for use with hardware ecc generation */
179 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
180 .eccbytes = 5,
181 .eccpos = {6, 7, 8, 9, 10},
182 .oobfree = {{0, 5}, {12, 4}, }
183 };
184
185 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
186 .eccbytes = 20,
187 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
188 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
189 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
190 };
191
192 /* OOB description for 512 byte pages with 16 byte OOB */
193 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
194 .eccbytes = 1 * 9,
195 .eccpos = {
196 7, 8, 9, 10, 11, 12, 13, 14, 15
197 },
198 .oobfree = {
199 {.offset = 0, .length = 5}
200 }
201 };
202
203 /* OOB description for 2048 byte pages with 64 byte OOB */
204 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
205 .eccbytes = 4 * 9,
206 .eccpos = {
207 7, 8, 9, 10, 11, 12, 13, 14, 15,
208 23, 24, 25, 26, 27, 28, 29, 30, 31,
209 39, 40, 41, 42, 43, 44, 45, 46, 47,
210 55, 56, 57, 58, 59, 60, 61, 62, 63
211 },
212 .oobfree = {
213 {.offset = 2, .length = 4},
214 {.offset = 16, .length = 7},
215 {.offset = 32, .length = 7},
216 {.offset = 48, .length = 7}
217 }
218 };
219
220 /* OOB description for 4096 byte pages with 128 byte OOB */
221 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
222 .eccbytes = 8 * 9,
223 .eccpos = {
224 7, 8, 9, 10, 11, 12, 13, 14, 15,
225 23, 24, 25, 26, 27, 28, 29, 30, 31,
226 39, 40, 41, 42, 43, 44, 45, 46, 47,
227 55, 56, 57, 58, 59, 60, 61, 62, 63,
228 71, 72, 73, 74, 75, 76, 77, 78, 79,
229 87, 88, 89, 90, 91, 92, 93, 94, 95,
230 103, 104, 105, 106, 107, 108, 109, 110, 111,
231 119, 120, 121, 122, 123, 124, 125, 126, 127,
232 },
233 .oobfree = {
234 {.offset = 2, .length = 4},
235 {.offset = 16, .length = 7},
236 {.offset = 32, .length = 7},
237 {.offset = 48, .length = 7},
238 {.offset = 64, .length = 7},
239 {.offset = 80, .length = 7},
240 {.offset = 96, .length = 7},
241 {.offset = 112, .length = 7},
242 }
243 };
244
245 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
246
247 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
248 {
249 struct mxc_nand_host *host = dev_id;
250
251 if (!host->check_int(host))
252 return IRQ_NONE;
253
254 host->irq_control(host, 0);
255
256 complete(&host->op_completion);
257
258 return IRQ_HANDLED;
259 }
260
261 static int check_int_v3(struct mxc_nand_host *host)
262 {
263 uint32_t tmp;
264
265 tmp = readl(NFC_V3_IPC);
266 if (!(tmp & NFC_V3_IPC_INT))
267 return 0;
268
269 tmp &= ~NFC_V3_IPC_INT;
270 writel(tmp, NFC_V3_IPC);
271
272 return 1;
273 }
274
275 static int check_int_v1_v2(struct mxc_nand_host *host)
276 {
277 uint32_t tmp;
278
279 tmp = readw(NFC_V1_V2_CONFIG2);
280 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
281 return 0;
282
283 if (!cpu_is_mx21())
284 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
285
286 return 1;
287 }
288
289 /*
290 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
291 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
292 * driver can enable/disable the irq line rather than simply masking the
293 * interrupts.
294 */
295 static void irq_control_mx21(struct mxc_nand_host *host, int activate)
296 {
297 if (activate)
298 enable_irq(host->irq);
299 else
300 disable_irq_nosync(host->irq);
301 }
302
303 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
304 {
305 uint16_t tmp;
306
307 tmp = readw(NFC_V1_V2_CONFIG1);
308
309 if (activate)
310 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
311 else
312 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
313
314 writew(tmp, NFC_V1_V2_CONFIG1);
315 }
316
317 static void irq_control_v3(struct mxc_nand_host *host, int activate)
318 {
319 uint32_t tmp;
320
321 tmp = readl(NFC_V3_CONFIG2);
322
323 if (activate)
324 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
325 else
326 tmp |= NFC_V3_CONFIG2_INT_MSK;
327
328 writel(tmp, NFC_V3_CONFIG2);
329 }
330
331 /* This function polls the NANDFC to wait for the basic operation to
332 * complete by checking the INT bit of config2 register.
333 */
334 static void wait_op_done(struct mxc_nand_host *host, int useirq)
335 {
336 int max_retries = 8000;
337
338 if (useirq) {
339 if (!host->check_int(host)) {
340 INIT_COMPLETION(host->op_completion);
341 host->irq_control(host, 1);
342 wait_for_completion(&host->op_completion);
343 }
344 } else {
345 while (max_retries-- > 0) {
346 if (host->check_int(host))
347 break;
348
349 udelay(1);
350 }
351 if (max_retries < 0)
352 pr_debug("%s: INT not set\n",
353 __func__);
354 }
355 }
356
357 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
358 {
359 /* fill command */
360 writel(cmd, NFC_V3_FLASH_CMD);
361
362 /* send out command */
363 writel(NFC_CMD, NFC_V3_LAUNCH);
364
365 /* Wait for operation to complete */
366 wait_op_done(host, useirq);
367 }
368
369 /* This function issues the specified command to the NAND device and
370 * waits for completion. */
371 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
372 {
373 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
374
375 writew(cmd, NFC_V1_V2_FLASH_CMD);
376 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
377
378 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
379 int max_retries = 100;
380 /* Reset completion is indicated by NFC_CONFIG2 */
381 /* being set to 0 */
382 while (max_retries-- > 0) {
383 if (readw(NFC_V1_V2_CONFIG2) == 0) {
384 break;
385 }
386 udelay(1);
387 }
388 if (max_retries < 0)
389 pr_debug("%s: RESET failed\n",
390 __func__);
391 } else {
392 /* Wait for operation to complete */
393 wait_op_done(host, useirq);
394 }
395 }
396
397 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
398 {
399 /* fill address */
400 writel(addr, NFC_V3_FLASH_ADDR0);
401
402 /* send out address */
403 writel(NFC_ADDR, NFC_V3_LAUNCH);
404
405 wait_op_done(host, 0);
406 }
407
408 /* This function sends an address (or partial address) to the
409 * NAND device. The address is used to select the source/destination for
410 * a NAND command. */
411 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
412 {
413 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
414
415 writew(addr, NFC_V1_V2_FLASH_ADDR);
416 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
417
418 /* Wait for operation to complete */
419 wait_op_done(host, islast);
420 }
421
422 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
423 {
424 struct nand_chip *nand_chip = mtd->priv;
425 struct mxc_nand_host *host = nand_chip->priv;
426 uint32_t tmp;
427
428 tmp = readl(NFC_V3_CONFIG1);
429 tmp &= ~(7 << 4);
430 writel(tmp, NFC_V3_CONFIG1);
431
432 /* transfer data from NFC ram to nand */
433 writel(ops, NFC_V3_LAUNCH);
434
435 wait_op_done(host, false);
436 }
437
438 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
439 {
440 struct nand_chip *nand_chip = mtd->priv;
441 struct mxc_nand_host *host = nand_chip->priv;
442 int bufs, i;
443
444 if (nfc_is_v1() && mtd->writesize > 512)
445 bufs = 4;
446 else
447 bufs = 1;
448
449 for (i = 0; i < bufs; i++) {
450
451 /* NANDFC buffer 0 is used for page read/write */
452 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
453
454 writew(ops, NFC_V1_V2_CONFIG2);
455
456 /* Wait for operation to complete */
457 wait_op_done(host, true);
458 }
459 }
460
461 static void send_read_id_v3(struct mxc_nand_host *host)
462 {
463 /* Read ID into main buffer */
464 writel(NFC_ID, NFC_V3_LAUNCH);
465
466 wait_op_done(host, true);
467
468 memcpy(host->data_buf, host->main_area0, 16);
469 }
470
471 /* Request the NANDFC to perform a read of the NAND device ID. */
472 static void send_read_id_v1_v2(struct mxc_nand_host *host)
473 {
474 struct nand_chip *this = &host->nand;
475
476 /* NANDFC buffer 0 is used for device ID output */
477 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
478
479 writew(NFC_ID, NFC_V1_V2_CONFIG2);
480
481 /* Wait for operation to complete */
482 wait_op_done(host, true);
483
484 memcpy(host->data_buf, host->main_area0, 16);
485
486 if (this->options & NAND_BUSWIDTH_16) {
487 /* compress the ID info */
488 host->data_buf[1] = host->data_buf[2];
489 host->data_buf[2] = host->data_buf[4];
490 host->data_buf[3] = host->data_buf[6];
491 host->data_buf[4] = host->data_buf[8];
492 host->data_buf[5] = host->data_buf[10];
493 }
494 }
495
496 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
497 {
498 writew(NFC_STATUS, NFC_V3_LAUNCH);
499 wait_op_done(host, true);
500
501 return readl(NFC_V3_CONFIG1) >> 16;
502 }
503
504 /* This function requests the NANDFC to perform a read of the
505 * NAND device status and returns the current status. */
506 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
507 {
508 void __iomem *main_buf = host->main_area0;
509 uint32_t store;
510 uint16_t ret;
511
512 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
513
514 /*
515 * The device status is stored in main_area0. To
516 * prevent corruption of the buffer save the value
517 * and restore it afterwards.
518 */
519 store = readl(main_buf);
520
521 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
522 wait_op_done(host, true);
523
524 ret = readw(main_buf);
525
526 writel(store, main_buf);
527
528 return ret;
529 }
530
531 /* This functions is used by upper layer to checks if device is ready */
532 static int mxc_nand_dev_ready(struct mtd_info *mtd)
533 {
534 /*
535 * NFC handles R/B internally. Therefore, this function
536 * always returns status as ready.
537 */
538 return 1;
539 }
540
541 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
542 {
543 /*
544 * If HW ECC is enabled, we turn it on during init. There is
545 * no need to enable again here.
546 */
547 }
548
549 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
550 u_char *read_ecc, u_char *calc_ecc)
551 {
552 struct nand_chip *nand_chip = mtd->priv;
553 struct mxc_nand_host *host = nand_chip->priv;
554
555 /*
556 * 1-Bit errors are automatically corrected in HW. No need for
557 * additional correction. 2-Bit errors cannot be corrected by
558 * HW ECC, so we need to return failure
559 */
560 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
561
562 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
563 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
564 return -1;
565 }
566
567 return 0;
568 }
569
570 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
571 u_char *read_ecc, u_char *calc_ecc)
572 {
573 struct nand_chip *nand_chip = mtd->priv;
574 struct mxc_nand_host *host = nand_chip->priv;
575 u32 ecc_stat, err;
576 int no_subpages = 1;
577 int ret = 0;
578 u8 ecc_bit_mask, err_limit;
579
580 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
581 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
582
583 no_subpages = mtd->writesize >> 9;
584
585 if (nfc_is_v21())
586 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
587 else
588 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
589
590 do {
591 err = ecc_stat & ecc_bit_mask;
592 if (err > err_limit) {
593 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
594 return -1;
595 } else {
596 ret += err;
597 }
598 ecc_stat >>= 4;
599 } while (--no_subpages);
600
601 mtd->ecc_stats.corrected += ret;
602 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
603
604 return ret;
605 }
606
607 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
608 u_char *ecc_code)
609 {
610 return 0;
611 }
612
613 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
614 {
615 struct nand_chip *nand_chip = mtd->priv;
616 struct mxc_nand_host *host = nand_chip->priv;
617 uint8_t ret;
618
619 /* Check for status request */
620 if (host->status_request)
621 return host->get_dev_status(host) & 0xFF;
622
623 ret = *(uint8_t *)(host->data_buf + host->buf_start);
624 host->buf_start++;
625
626 return ret;
627 }
628
629 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
630 {
631 struct nand_chip *nand_chip = mtd->priv;
632 struct mxc_nand_host *host = nand_chip->priv;
633 uint16_t ret;
634
635 ret = *(uint16_t *)(host->data_buf + host->buf_start);
636 host->buf_start += 2;
637
638 return ret;
639 }
640
641 /* Write data of length len to buffer buf. The data to be
642 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
643 * Operation by the NFC, the data is written to NAND Flash */
644 static void mxc_nand_write_buf(struct mtd_info *mtd,
645 const u_char *buf, int len)
646 {
647 struct nand_chip *nand_chip = mtd->priv;
648 struct mxc_nand_host *host = nand_chip->priv;
649 u16 col = host->buf_start;
650 int n = mtd->oobsize + mtd->writesize - col;
651
652 n = min(n, len);
653
654 memcpy(host->data_buf + col, buf, n);
655
656 host->buf_start += n;
657 }
658
659 /* Read the data buffer from the NAND Flash. To read the data from NAND
660 * Flash first the data output cycle is initiated by the NFC, which copies
661 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
662 */
663 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
664 {
665 struct nand_chip *nand_chip = mtd->priv;
666 struct mxc_nand_host *host = nand_chip->priv;
667 u16 col = host->buf_start;
668 int n = mtd->oobsize + mtd->writesize - col;
669
670 n = min(n, len);
671
672 memcpy(buf, host->data_buf + col, n);
673
674 host->buf_start += n;
675 }
676
677 /* Used by the upper layer to verify the data in NAND Flash
678 * with the data in the buf. */
679 static int mxc_nand_verify_buf(struct mtd_info *mtd,
680 const u_char *buf, int len)
681 {
682 return -EFAULT;
683 }
684
685 /* This function is used by upper layer for select and
686 * deselect of the NAND chip */
687 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
688 {
689 struct nand_chip *nand_chip = mtd->priv;
690 struct mxc_nand_host *host = nand_chip->priv;
691
692 if (chip == -1) {
693 /* Disable the NFC clock */
694 if (host->clk_act) {
695 clk_disable(host->clk);
696 host->clk_act = 0;
697 }
698 return;
699 }
700
701 if (!host->clk_act) {
702 /* Enable the NFC clock */
703 clk_enable(host->clk);
704 host->clk_act = 1;
705 }
706
707 if (nfc_is_v21()) {
708 host->active_cs = chip;
709 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
710 }
711 }
712
713 /*
714 * Function to transfer data to/from spare area.
715 */
716 static void copy_spare(struct mtd_info *mtd, bool bfrom)
717 {
718 struct nand_chip *this = mtd->priv;
719 struct mxc_nand_host *host = this->priv;
720 u16 i, j;
721 u16 n = mtd->writesize >> 9;
722 u8 *d = host->data_buf + mtd->writesize;
723 u8 *s = host->spare0;
724 u16 t = host->spare_len;
725
726 j = (mtd->oobsize / n >> 1) << 1;
727
728 if (bfrom) {
729 for (i = 0; i < n - 1; i++)
730 memcpy(d + i * j, s + i * t, j);
731
732 /* the last section */
733 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
734 } else {
735 for (i = 0; i < n - 1; i++)
736 memcpy(&s[i * t], &d[i * j], j);
737
738 /* the last section */
739 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
740 }
741 }
742
743 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
744 {
745 struct nand_chip *nand_chip = mtd->priv;
746 struct mxc_nand_host *host = nand_chip->priv;
747
748 /* Write out column address, if necessary */
749 if (column != -1) {
750 /*
751 * MXC NANDFC can only perform full page+spare or
752 * spare-only read/write. When the upper layers
753 * perform a read/write buf operation, the saved column
754 * address is used to index into the full page.
755 */
756 host->send_addr(host, 0, page_addr == -1);
757 if (mtd->writesize > 512)
758 /* another col addr cycle for 2k page */
759 host->send_addr(host, 0, false);
760 }
761
762 /* Write out page address, if necessary */
763 if (page_addr != -1) {
764 /* paddr_0 - p_addr_7 */
765 host->send_addr(host, (page_addr & 0xff), false);
766
767 if (mtd->writesize > 512) {
768 if (mtd->size >= 0x10000000) {
769 /* paddr_8 - paddr_15 */
770 host->send_addr(host, (page_addr >> 8) & 0xff, false);
771 host->send_addr(host, (page_addr >> 16) & 0xff, true);
772 } else
773 /* paddr_8 - paddr_15 */
774 host->send_addr(host, (page_addr >> 8) & 0xff, true);
775 } else {
776 /* One more address cycle for higher density devices */
777 if (mtd->size >= 0x4000000) {
778 /* paddr_8 - paddr_15 */
779 host->send_addr(host, (page_addr >> 8) & 0xff, false);
780 host->send_addr(host, (page_addr >> 16) & 0xff, true);
781 } else
782 /* paddr_8 - paddr_15 */
783 host->send_addr(host, (page_addr >> 8) & 0xff, true);
784 }
785 }
786 }
787
788 /*
789 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
790 * on how much oob the nand chip has. For 8bit ecc we need at least
791 * 26 bytes of oob data per 512 byte block.
792 */
793 static int get_eccsize(struct mtd_info *mtd)
794 {
795 int oobbytes_per_512 = 0;
796
797 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
798
799 if (oobbytes_per_512 < 26)
800 return 4;
801 else
802 return 8;
803 }
804
805 static void preset_v1_v2(struct mtd_info *mtd)
806 {
807 struct nand_chip *nand_chip = mtd->priv;
808 struct mxc_nand_host *host = nand_chip->priv;
809 uint16_t config1 = 0;
810
811 if (nand_chip->ecc.mode == NAND_ECC_HW)
812 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
813
814 if (nfc_is_v21())
815 config1 |= NFC_V2_CONFIG1_FP_INT;
816
817 if (!cpu_is_mx21())
818 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
819
820 if (nfc_is_v21() && mtd->writesize) {
821 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
822
823 host->eccsize = get_eccsize(mtd);
824 if (host->eccsize == 4)
825 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
826
827 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
828 } else {
829 host->eccsize = 1;
830 }
831
832 writew(config1, NFC_V1_V2_CONFIG1);
833 /* preset operation */
834
835 /* Unlock the internal RAM Buffer */
836 writew(0x2, NFC_V1_V2_CONFIG);
837
838 /* Blocks to be unlocked */
839 if (nfc_is_v21()) {
840 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
841 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
842 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
843 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
844 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
845 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
846 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
847 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
848 } else if (nfc_is_v1()) {
849 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
850 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
851 } else
852 BUG();
853
854 /* Unlock Block Command for given address range */
855 writew(0x4, NFC_V1_V2_WRPROT);
856 }
857
858 static void preset_v3(struct mtd_info *mtd)
859 {
860 struct nand_chip *chip = mtd->priv;
861 struct mxc_nand_host *host = chip->priv;
862 uint32_t config2, config3;
863 int i, addr_phases;
864
865 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
866 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
867
868 /* Unlock the internal RAM Buffer */
869 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
870 NFC_V3_WRPROT);
871
872 /* Blocks to be unlocked */
873 for (i = 0; i < NAND_MAX_CHIPS; i++)
874 writel(0x0 | (0xffff << 16),
875 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
876
877 writel(0, NFC_V3_IPC);
878
879 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
880 NFC_V3_CONFIG2_2CMD_PHASES |
881 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
882 NFC_V3_CONFIG2_ST_CMD(0x70) |
883 NFC_V3_CONFIG2_INT_MSK |
884 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
885
886 if (chip->ecc.mode == NAND_ECC_HW)
887 config2 |= NFC_V3_CONFIG2_ECC_EN;
888
889 addr_phases = fls(chip->pagemask) >> 3;
890
891 if (mtd->writesize == 2048) {
892 config2 |= NFC_V3_CONFIG2_PS_2048;
893 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
894 } else if (mtd->writesize == 4096) {
895 config2 |= NFC_V3_CONFIG2_PS_4096;
896 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
897 } else {
898 config2 |= NFC_V3_CONFIG2_PS_512;
899 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
900 }
901
902 if (mtd->writesize) {
903 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
904 host->eccsize = get_eccsize(mtd);
905 if (host->eccsize == 8)
906 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
907 }
908
909 writel(config2, NFC_V3_CONFIG2);
910
911 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
912 NFC_V3_CONFIG3_NO_SDMA |
913 NFC_V3_CONFIG3_RBB_MODE |
914 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
915 NFC_V3_CONFIG3_ADD_OP(0);
916
917 if (!(chip->options & NAND_BUSWIDTH_16))
918 config3 |= NFC_V3_CONFIG3_FW8;
919
920 writel(config3, NFC_V3_CONFIG3);
921
922 writel(0, NFC_V3_DELAY_LINE);
923 }
924
925 /* Used by the upper layer to write command to NAND Flash for
926 * different operations to be carried out on NAND Flash */
927 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
928 int column, int page_addr)
929 {
930 struct nand_chip *nand_chip = mtd->priv;
931 struct mxc_nand_host *host = nand_chip->priv;
932
933 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
934 command, column, page_addr);
935
936 /* Reset command state information */
937 host->status_request = false;
938
939 /* Command pre-processing step */
940 switch (command) {
941 case NAND_CMD_RESET:
942 host->preset(mtd);
943 host->send_cmd(host, command, false);
944 break;
945
946 case NAND_CMD_STATUS:
947 host->buf_start = 0;
948 host->status_request = true;
949
950 host->send_cmd(host, command, true);
951 mxc_do_addr_cycle(mtd, column, page_addr);
952 break;
953
954 case NAND_CMD_READ0:
955 case NAND_CMD_READOOB:
956 if (command == NAND_CMD_READ0)
957 host->buf_start = column;
958 else
959 host->buf_start = column + mtd->writesize;
960
961 command = NAND_CMD_READ0; /* only READ0 is valid */
962
963 host->send_cmd(host, command, false);
964 mxc_do_addr_cycle(mtd, column, page_addr);
965
966 if (mtd->writesize > 512)
967 host->send_cmd(host, NAND_CMD_READSTART, true);
968
969 host->send_page(mtd, NFC_OUTPUT);
970
971 memcpy(host->data_buf, host->main_area0, mtd->writesize);
972 copy_spare(mtd, true);
973 break;
974
975 case NAND_CMD_SEQIN:
976 if (column >= mtd->writesize)
977 /* call ourself to read a page */
978 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
979
980 host->buf_start = column;
981
982 host->send_cmd(host, command, false);
983 mxc_do_addr_cycle(mtd, column, page_addr);
984 break;
985
986 case NAND_CMD_PAGEPROG:
987 memcpy(host->main_area0, host->data_buf, mtd->writesize);
988 copy_spare(mtd, false);
989 host->send_page(mtd, NFC_INPUT);
990 host->send_cmd(host, command, true);
991 mxc_do_addr_cycle(mtd, column, page_addr);
992 break;
993
994 case NAND_CMD_READID:
995 host->send_cmd(host, command, true);
996 mxc_do_addr_cycle(mtd, column, page_addr);
997 host->send_read_id(host);
998 host->buf_start = column;
999 break;
1000
1001 case NAND_CMD_ERASE1:
1002 case NAND_CMD_ERASE2:
1003 host->send_cmd(host, command, false);
1004 mxc_do_addr_cycle(mtd, column, page_addr);
1005
1006 break;
1007 }
1008 }
1009
1010 /*
1011 * The generic flash bbt decriptors overlap with our ecc
1012 * hardware, so define some i.MX specific ones.
1013 */
1014 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1015 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1016
1017 static struct nand_bbt_descr bbt_main_descr = {
1018 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1019 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1020 .offs = 0,
1021 .len = 4,
1022 .veroffs = 4,
1023 .maxblocks = 4,
1024 .pattern = bbt_pattern,
1025 };
1026
1027 static struct nand_bbt_descr bbt_mirror_descr = {
1028 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1029 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1030 .offs = 0,
1031 .len = 4,
1032 .veroffs = 4,
1033 .maxblocks = 4,
1034 .pattern = mirror_pattern,
1035 };
1036
1037 static int __init mxcnd_probe(struct platform_device *pdev)
1038 {
1039 struct nand_chip *this;
1040 struct mtd_info *mtd;
1041 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1042 struct mxc_nand_host *host;
1043 struct resource *res;
1044 int err = 0;
1045 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1046
1047 /* Allocate memory for MTD device structure and private data */
1048 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1049 NAND_MAX_OOBSIZE, GFP_KERNEL);
1050 if (!host)
1051 return -ENOMEM;
1052
1053 host->data_buf = (uint8_t *)(host + 1);
1054
1055 host->dev = &pdev->dev;
1056 /* structures must be linked */
1057 this = &host->nand;
1058 mtd = &host->mtd;
1059 mtd->priv = this;
1060 mtd->owner = THIS_MODULE;
1061 mtd->dev.parent = &pdev->dev;
1062 mtd->name = DRIVER_NAME;
1063
1064 /* 50 us command delay time */
1065 this->chip_delay = 5;
1066
1067 this->priv = host;
1068 this->dev_ready = mxc_nand_dev_ready;
1069 this->cmdfunc = mxc_nand_command;
1070 this->select_chip = mxc_nand_select_chip;
1071 this->read_byte = mxc_nand_read_byte;
1072 this->read_word = mxc_nand_read_word;
1073 this->write_buf = mxc_nand_write_buf;
1074 this->read_buf = mxc_nand_read_buf;
1075 this->verify_buf = mxc_nand_verify_buf;
1076
1077 host->clk = clk_get(&pdev->dev, "nfc");
1078 if (IS_ERR(host->clk)) {
1079 err = PTR_ERR(host->clk);
1080 goto eclk;
1081 }
1082
1083 clk_enable(host->clk);
1084 host->clk_act = 1;
1085
1086 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1087 if (!res) {
1088 err = -ENODEV;
1089 goto eres;
1090 }
1091
1092 host->base = ioremap(res->start, resource_size(res));
1093 if (!host->base) {
1094 err = -ENOMEM;
1095 goto eres;
1096 }
1097
1098 host->main_area0 = host->base;
1099
1100 if (nfc_is_v1() || nfc_is_v21()) {
1101 host->preset = preset_v1_v2;
1102 host->send_cmd = send_cmd_v1_v2;
1103 host->send_addr = send_addr_v1_v2;
1104 host->send_page = send_page_v1_v2;
1105 host->send_read_id = send_read_id_v1_v2;
1106 host->get_dev_status = get_dev_status_v1_v2;
1107 host->check_int = check_int_v1_v2;
1108 if (cpu_is_mx21())
1109 host->irq_control = irq_control_mx21;
1110 else
1111 host->irq_control = irq_control_v1_v2;
1112 }
1113
1114 if (nfc_is_v21()) {
1115 host->regs = host->base + 0x1e00;
1116 host->spare0 = host->base + 0x1000;
1117 host->spare_len = 64;
1118 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1119 oob_largepage = &nandv2_hw_eccoob_largepage;
1120 this->ecc.bytes = 9;
1121 } else if (nfc_is_v1()) {
1122 host->regs = host->base + 0xe00;
1123 host->spare0 = host->base + 0x800;
1124 host->spare_len = 16;
1125 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1126 oob_largepage = &nandv1_hw_eccoob_largepage;
1127 this->ecc.bytes = 3;
1128 host->eccsize = 1;
1129 } else if (nfc_is_v3_2()) {
1130 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1131 if (!res) {
1132 err = -ENODEV;
1133 goto eirq;
1134 }
1135 host->regs_ip = ioremap(res->start, resource_size(res));
1136 if (!host->regs_ip) {
1137 err = -ENOMEM;
1138 goto eirq;
1139 }
1140 host->regs_axi = host->base + 0x1e00;
1141 host->spare0 = host->base + 0x1000;
1142 host->spare_len = 64;
1143 host->preset = preset_v3;
1144 host->send_cmd = send_cmd_v3;
1145 host->send_addr = send_addr_v3;
1146 host->send_page = send_page_v3;
1147 host->send_read_id = send_read_id_v3;
1148 host->check_int = check_int_v3;
1149 host->get_dev_status = get_dev_status_v3;
1150 host->irq_control = irq_control_v3;
1151 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1152 oob_largepage = &nandv2_hw_eccoob_largepage;
1153 } else
1154 BUG();
1155
1156 this->ecc.size = 512;
1157 this->ecc.layout = oob_smallpage;
1158
1159 if (pdata->hw_ecc) {
1160 this->ecc.calculate = mxc_nand_calculate_ecc;
1161 this->ecc.hwctl = mxc_nand_enable_hwecc;
1162 if (nfc_is_v1())
1163 this->ecc.correct = mxc_nand_correct_data_v1;
1164 else
1165 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1166 this->ecc.mode = NAND_ECC_HW;
1167 } else {
1168 this->ecc.mode = NAND_ECC_SOFT;
1169 }
1170
1171 /* NAND bus width determines access funtions used by upper layer */
1172 if (pdata->width == 2)
1173 this->options |= NAND_BUSWIDTH_16;
1174
1175 if (pdata->flash_bbt) {
1176 this->bbt_td = &bbt_main_descr;
1177 this->bbt_md = &bbt_mirror_descr;
1178 /* update flash based bbt */
1179 this->bbt_options |= NAND_BBT_USE_FLASH;
1180 }
1181
1182 init_completion(&host->op_completion);
1183
1184 host->irq = platform_get_irq(pdev, 0);
1185
1186 /*
1187 * mask the interrupt. For i.MX21 explicitely call
1188 * irq_control_v1_v2 to use the mask bit. We can't call
1189 * disable_irq_nosync() for an interrupt we do not own yet.
1190 */
1191 if (cpu_is_mx21())
1192 irq_control_v1_v2(host, 0);
1193 else
1194 host->irq_control(host, 0);
1195
1196 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1197 if (err)
1198 goto eirq;
1199
1200 host->irq_control(host, 0);
1201
1202 /*
1203 * Now that the interrupt is disabled make sure the interrupt
1204 * mask bit is cleared on i.MX21. Otherwise we can't read
1205 * the interrupt status bit on this machine.
1206 */
1207 if (cpu_is_mx21())
1208 irq_control_v1_v2(host, 1);
1209
1210 /* first scan to find the device and get the page size */
1211 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1212 err = -ENXIO;
1213 goto escan;
1214 }
1215
1216 /* Call preset again, with correct writesize this time */
1217 host->preset(mtd);
1218
1219 if (mtd->writesize == 2048)
1220 this->ecc.layout = oob_largepage;
1221 if (nfc_is_v21() && mtd->writesize == 4096)
1222 this->ecc.layout = &nandv2_hw_eccoob_4k;
1223
1224 /* second phase scan */
1225 if (nand_scan_tail(mtd)) {
1226 err = -ENXIO;
1227 goto escan;
1228 }
1229
1230 /* Register the partitions */
1231 mtd_device_parse_register(mtd, part_probes, 0,
1232 pdata->parts, pdata->nr_parts);
1233
1234 platform_set_drvdata(pdev, host);
1235
1236 return 0;
1237
1238 escan:
1239 free_irq(host->irq, host);
1240 eirq:
1241 if (host->regs_ip)
1242 iounmap(host->regs_ip);
1243 iounmap(host->base);
1244 eres:
1245 clk_put(host->clk);
1246 eclk:
1247 kfree(host);
1248
1249 return err;
1250 }
1251
1252 static int __devexit mxcnd_remove(struct platform_device *pdev)
1253 {
1254 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1255
1256 clk_put(host->clk);
1257
1258 platform_set_drvdata(pdev, NULL);
1259
1260 nand_release(&host->mtd);
1261 free_irq(host->irq, host);
1262 if (host->regs_ip)
1263 iounmap(host->regs_ip);
1264 iounmap(host->base);
1265 kfree(host);
1266
1267 return 0;
1268 }
1269
1270 static struct platform_driver mxcnd_driver = {
1271 .driver = {
1272 .name = DRIVER_NAME,
1273 },
1274 .remove = __devexit_p(mxcnd_remove),
1275 };
1276
1277 static int __init mxc_nd_init(void)
1278 {
1279 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1280 }
1281
1282 static void __exit mxc_nd_cleanup(void)
1283 {
1284 /* Unregister the device structure */
1285 platform_driver_unregister(&mxcnd_driver);
1286 }
1287
1288 module_init(mxc_nd_init);
1289 module_exit(mxc_nd_cleanup);
1290
1291 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1292 MODULE_DESCRIPTION("MXC NAND MTD driver");
1293 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)