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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
32
33 #include "sdhci.h"
34
35 #define DRIVER_NAME "sdhci"
36
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
43 #endif
44
45 #define MAX_TUNING_LOOP 40
46
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
49
50 static void sdhci_finish_data(struct sdhci_host *);
51
52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_tuning_timer(unsigned long data);
56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57
58 #ifdef CONFIG_PM_RUNTIME
59 static int sdhci_runtime_pm_get(struct sdhci_host *host);
60 static int sdhci_runtime_pm_put(struct sdhci_host *host);
61 #else
62 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
63 {
64 return 0;
65 }
66 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
67 {
68 return 0;
69 }
70 #endif
71
72 static void sdhci_dumpregs(struct sdhci_host *host)
73 {
74 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
75 mmc_hostname(host->mmc));
76
77 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
78 sdhci_readl(host, SDHCI_DMA_ADDRESS),
79 sdhci_readw(host, SDHCI_HOST_VERSION));
80 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
81 sdhci_readw(host, SDHCI_BLOCK_SIZE),
82 sdhci_readw(host, SDHCI_BLOCK_COUNT));
83 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
84 sdhci_readl(host, SDHCI_ARGUMENT),
85 sdhci_readw(host, SDHCI_TRANSFER_MODE));
86 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
87 sdhci_readl(host, SDHCI_PRESENT_STATE),
88 sdhci_readb(host, SDHCI_HOST_CONTROL));
89 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
90 sdhci_readb(host, SDHCI_POWER_CONTROL),
91 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
92 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
93 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
94 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
95 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
96 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
97 sdhci_readl(host, SDHCI_INT_STATUS));
98 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
99 sdhci_readl(host, SDHCI_INT_ENABLE),
100 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
101 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
102 sdhci_readw(host, SDHCI_ACMD12_ERR),
103 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
104 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
105 sdhci_readl(host, SDHCI_CAPABILITIES),
106 sdhci_readl(host, SDHCI_CAPABILITIES_1));
107 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
108 sdhci_readw(host, SDHCI_COMMAND),
109 sdhci_readl(host, SDHCI_MAX_CURRENT));
110 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
111 sdhci_readw(host, SDHCI_HOST_CONTROL2));
112
113 if (host->flags & SDHCI_USE_ADMA)
114 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
115 readl(host->ioaddr + SDHCI_ADMA_ERROR),
116 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
117
118 pr_debug(DRIVER_NAME ": ===========================================\n");
119 }
120
121 /*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125 \*****************************************************************************/
126
127 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
128 {
129 u32 ier;
130
131 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
132 ier &= ~clear;
133 ier |= set;
134 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
135 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
136 }
137
138 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
139 {
140 sdhci_clear_set_irqs(host, 0, irqs);
141 }
142
143 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
144 {
145 sdhci_clear_set_irqs(host, irqs, 0);
146 }
147
148 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
149 {
150 u32 present, irqs;
151
152 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
153 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
154 return;
155
156 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
157 SDHCI_CARD_PRESENT;
158 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
159
160 if (enable)
161 sdhci_unmask_irqs(host, irqs);
162 else
163 sdhci_mask_irqs(host, irqs);
164 }
165
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 {
168 sdhci_set_card_detection(host, true);
169 }
170
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 {
173 sdhci_set_card_detection(host, false);
174 }
175
176 static void sdhci_reset(struct sdhci_host *host, u8 mask)
177 {
178 unsigned long timeout;
179 u32 uninitialized_var(ier);
180
181 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
182 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
183 SDHCI_CARD_PRESENT))
184 return;
185 }
186
187 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
188 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
189
190 if (host->ops->platform_reset_enter)
191 host->ops->platform_reset_enter(host, mask);
192
193 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
194
195 if (mask & SDHCI_RESET_ALL)
196 host->clock = 0;
197
198 /* Wait max 100 ms */
199 timeout = 100;
200
201 /* hw clears the bit when it's done */
202 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
203 if (timeout == 0) {
204 pr_err("%s: Reset 0x%x never completed.\n",
205 mmc_hostname(host->mmc), (int)mask);
206 sdhci_dumpregs(host);
207 return;
208 }
209 timeout--;
210 mdelay(1);
211 }
212
213 if (host->ops->platform_reset_exit)
214 host->ops->platform_reset_exit(host, mask);
215
216 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
217 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
218
219 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
221 host->ops->enable_dma(host);
222 }
223 }
224
225 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
226
227 static void sdhci_init(struct sdhci_host *host, int soft)
228 {
229 if (soft)
230 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
231 else
232 sdhci_reset(host, SDHCI_RESET_ALL);
233
234 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
235 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
237 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
238 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
243 sdhci_set_ios(host->mmc, &host->mmc->ios);
244 }
245 }
246
247 static void sdhci_reinit(struct sdhci_host *host)
248 {
249 sdhci_init(host, 0);
250 /*
251 * Retuning stuffs are affected by different cards inserted and only
252 * applicable to UHS-I cards. So reset these fields to their initial
253 * value when card is removed.
254 */
255 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
256 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
257
258 del_timer_sync(&host->tuning_timer);
259 host->flags &= ~SDHCI_NEEDS_RETUNING;
260 host->mmc->max_blk_count =
261 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
262 }
263 sdhci_enable_card_detection(host);
264 }
265
266 static void sdhci_activate_led(struct sdhci_host *host)
267 {
268 u8 ctrl;
269
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl |= SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 }
274
275 static void sdhci_deactivate_led(struct sdhci_host *host)
276 {
277 u8 ctrl;
278
279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
280 ctrl &= ~SDHCI_CTRL_LED;
281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
282 }
283
284 #ifdef SDHCI_USE_LEDS_CLASS
285 static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
287 {
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 unsigned long flags;
290
291 spin_lock_irqsave(&host->lock, flags);
292
293 if (host->runtime_suspended)
294 goto out;
295
296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
298 else
299 sdhci_activate_led(host);
300 out:
301 spin_unlock_irqrestore(&host->lock, flags);
302 }
303 #endif
304
305 /*****************************************************************************\
306 * *
307 * Core functions *
308 * *
309 \*****************************************************************************/
310
311 static void sdhci_read_block_pio(struct sdhci_host *host)
312 {
313 unsigned long flags;
314 size_t blksize, len, chunk;
315 u32 uninitialized_var(scratch);
316 u8 *buf;
317
318 DBG("PIO reading\n");
319
320 blksize = host->data->blksz;
321 chunk = 0;
322
323 local_irq_save(flags);
324
325 while (blksize) {
326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
328
329 len = min(host->sg_miter.length, blksize);
330
331 blksize -= len;
332 host->sg_miter.consumed = len;
333
334 buf = host->sg_miter.addr;
335
336 while (len) {
337 if (chunk == 0) {
338 scratch = sdhci_readl(host, SDHCI_BUFFER);
339 chunk = 4;
340 }
341
342 *buf = scratch & 0xFF;
343
344 buf++;
345 scratch >>= 8;
346 chunk--;
347 len--;
348 }
349 }
350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
354 }
355
356 static void sdhci_write_block_pio(struct sdhci_host *host)
357 {
358 unsigned long flags;
359 size_t blksize, len, chunk;
360 u32 scratch;
361 u8 *buf;
362
363 DBG("PIO writing\n");
364
365 blksize = host->data->blksz;
366 chunk = 0;
367 scratch = 0;
368
369 local_irq_save(flags);
370
371 while (blksize) {
372 if (!sg_miter_next(&host->sg_miter))
373 BUG();
374
375 len = min(host->sg_miter.length, blksize);
376
377 blksize -= len;
378 host->sg_miter.consumed = len;
379
380 buf = host->sg_miter.addr;
381
382 while (len) {
383 scratch |= (u32)*buf << (chunk * 8);
384
385 buf++;
386 chunk++;
387 len--;
388
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
390 sdhci_writel(host, scratch, SDHCI_BUFFER);
391 chunk = 0;
392 scratch = 0;
393 }
394 }
395 }
396
397 sg_miter_stop(&host->sg_miter);
398
399 local_irq_restore(flags);
400 }
401
402 static void sdhci_transfer_pio(struct sdhci_host *host)
403 {
404 u32 mask;
405
406 BUG_ON(!host->data);
407
408 if (host->blocks == 0)
409 return;
410
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
413 else
414 mask = SDHCI_SPACE_AVAILABLE;
415
416 /*
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
420 */
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
423 mask = ~0;
424
425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 udelay(100);
428
429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
431 else
432 sdhci_write_block_pio(host);
433
434 host->blocks--;
435 if (host->blocks == 0)
436 break;
437 }
438
439 DBG("PIO transfer complete.\n");
440 }
441
442 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443 {
444 local_irq_save(*flags);
445 return kmap_atomic(sg_page(sg)) + sg->offset;
446 }
447
448 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449 {
450 kunmap_atomic(buffer);
451 local_irq_restore(*flags);
452 }
453
454 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
455 {
456 __le32 *dataddr = (__le32 __force *)(desc + 4);
457 __le16 *cmdlen = (__le16 __force *)desc;
458
459 /* SDHCI specification says ADMA descriptors should be 4 byte
460 * aligned, so using 16 or 32bit operations should be safe. */
461
462 cmdlen[0] = cpu_to_le16(cmd);
463 cmdlen[1] = cpu_to_le16(len);
464
465 dataddr[0] = cpu_to_le32(addr);
466 }
467
468 static int sdhci_adma_table_pre(struct sdhci_host *host,
469 struct mmc_data *data)
470 {
471 int direction;
472
473 u8 *desc;
474 u8 *align;
475 dma_addr_t addr;
476 dma_addr_t align_addr;
477 int len, offset;
478
479 struct scatterlist *sg;
480 int i;
481 char *buffer;
482 unsigned long flags;
483
484 /*
485 * The spec does not specify endianness of descriptor table.
486 * We currently guess that it is LE.
487 */
488
489 if (data->flags & MMC_DATA_READ)
490 direction = DMA_FROM_DEVICE;
491 else
492 direction = DMA_TO_DEVICE;
493
494 /*
495 * The ADMA descriptor table is mapped further down as we
496 * need to fill it with data first.
497 */
498
499 host->align_addr = dma_map_single(mmc_dev(host->mmc),
500 host->align_buffer, 128 * 4, direction);
501 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
502 goto fail;
503 BUG_ON(host->align_addr & 0x3);
504
505 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
506 data->sg, data->sg_len, direction);
507 if (host->sg_count == 0)
508 goto unmap_align;
509
510 desc = host->adma_desc;
511 align = host->align_buffer;
512
513 align_addr = host->align_addr;
514
515 for_each_sg(data->sg, sg, host->sg_count, i) {
516 addr = sg_dma_address(sg);
517 len = sg_dma_len(sg);
518
519 /*
520 * The SDHCI specification states that ADMA
521 * addresses must be 32-bit aligned. If they
522 * aren't, then we use a bounce buffer for
523 * the (up to three) bytes that screw up the
524 * alignment.
525 */
526 offset = (4 - (addr & 0x3)) & 0x3;
527 if (offset) {
528 if (data->flags & MMC_DATA_WRITE) {
529 buffer = sdhci_kmap_atomic(sg, &flags);
530 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
531 memcpy(align, buffer, offset);
532 sdhci_kunmap_atomic(buffer, &flags);
533 }
534
535 /* tran, valid */
536 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
537
538 BUG_ON(offset > 65536);
539
540 align += 4;
541 align_addr += 4;
542
543 desc += 8;
544
545 addr += offset;
546 len -= offset;
547 }
548
549 BUG_ON(len > 65536);
550
551 /* tran, valid */
552 sdhci_set_adma_desc(desc, addr, len, 0x21);
553 desc += 8;
554
555 /*
556 * If this triggers then we have a calculation bug
557 * somewhere. :/
558 */
559 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
560 }
561
562 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
563 /*
564 * Mark the last descriptor as the terminating descriptor
565 */
566 if (desc != host->adma_desc) {
567 desc -= 8;
568 desc[0] |= 0x2; /* end */
569 }
570 } else {
571 /*
572 * Add a terminating entry.
573 */
574
575 /* nop, end, valid */
576 sdhci_set_adma_desc(desc, 0, 0, 0x3);
577 }
578
579 /*
580 * Resync align buffer as we might have changed it.
581 */
582 if (data->flags & MMC_DATA_WRITE) {
583 dma_sync_single_for_device(mmc_dev(host->mmc),
584 host->align_addr, 128 * 4, direction);
585 }
586
587 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
588 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
589 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
590 goto unmap_entries;
591 BUG_ON(host->adma_addr & 0x3);
592
593 return 0;
594
595 unmap_entries:
596 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
597 data->sg_len, direction);
598 unmap_align:
599 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
600 128 * 4, direction);
601 fail:
602 return -EINVAL;
603 }
604
605 static void sdhci_adma_table_post(struct sdhci_host *host,
606 struct mmc_data *data)
607 {
608 int direction;
609
610 struct scatterlist *sg;
611 int i, size;
612 u8 *align;
613 char *buffer;
614 unsigned long flags;
615
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
618 else
619 direction = DMA_TO_DEVICE;
620
621 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
622 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
623
624 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
625 128 * 4, direction);
626
627 if (data->flags & MMC_DATA_READ) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
629 data->sg_len, direction);
630
631 align = host->align_buffer;
632
633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & 0x3) {
635 size = 4 - (sg_dma_address(sg) & 0x3);
636
637 buffer = sdhci_kmap_atomic(sg, &flags);
638 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
641
642 align += 4;
643 }
644 }
645 }
646
647 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
648 data->sg_len, direction);
649 }
650
651 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
652 {
653 u8 count;
654 struct mmc_data *data = cmd->data;
655 unsigned target_timeout, current_timeout;
656
657 /*
658 * If the host controller provides us with an incorrect timeout
659 * value, just skip the check and use 0xE. The hardware may take
660 * longer to time out, but that's much better than having a too-short
661 * timeout value.
662 */
663 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
664 return 0xE;
665
666 /* Unspecified timeout, assume max */
667 if (!data && !cmd->cmd_timeout_ms)
668 return 0xE;
669
670 /* timeout in us */
671 if (!data)
672 target_timeout = cmd->cmd_timeout_ms * 1000;
673 else {
674 target_timeout = data->timeout_ns / 1000;
675 if (host->clock)
676 target_timeout += data->timeout_clks / host->clock;
677 }
678
679 /*
680 * Figure out needed cycles.
681 * We do this in steps in order to fit inside a 32 bit int.
682 * The first step is the minimum timeout, which will have a
683 * minimum resolution of 6 bits:
684 * (1) 2^13*1000 > 2^22,
685 * (2) host->timeout_clk < 2^16
686 * =>
687 * (1) / (2) > 2^6
688 */
689 count = 0;
690 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
691 while (current_timeout < target_timeout) {
692 count++;
693 current_timeout <<= 1;
694 if (count >= 0xF)
695 break;
696 }
697
698 if (count >= 0xF) {
699 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
700 mmc_hostname(host->mmc), count, cmd->opcode);
701 count = 0xE;
702 }
703
704 return count;
705 }
706
707 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708 {
709 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
710 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711
712 if (host->flags & SDHCI_REQ_USE_DMA)
713 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
714 else
715 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
716 }
717
718 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
719 {
720 u8 count;
721 u8 ctrl;
722 struct mmc_data *data = cmd->data;
723 int ret;
724
725 WARN_ON(host->data);
726
727 if (data || (cmd->flags & MMC_RSP_BUSY)) {
728 count = sdhci_calc_timeout(host, cmd);
729 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
730 }
731
732 if (!data)
733 return;
734
735 /* Sanity checks */
736 BUG_ON(data->blksz * data->blocks > 524288);
737 BUG_ON(data->blksz > host->mmc->max_blk_size);
738 BUG_ON(data->blocks > 65535);
739
740 host->data = data;
741 host->data_early = 0;
742 host->data->bytes_xfered = 0;
743
744 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
745 host->flags |= SDHCI_REQ_USE_DMA;
746
747 /*
748 * FIXME: This doesn't account for merging when mapping the
749 * scatterlist.
750 */
751 if (host->flags & SDHCI_REQ_USE_DMA) {
752 int broken, i;
753 struct scatterlist *sg;
754
755 broken = 0;
756 if (host->flags & SDHCI_USE_ADMA) {
757 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
758 broken = 1;
759 } else {
760 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
761 broken = 1;
762 }
763
764 if (unlikely(broken)) {
765 for_each_sg(data->sg, sg, data->sg_len, i) {
766 if (sg->length & 0x3) {
767 DBG("Reverting to PIO because of "
768 "transfer size (%d)\n",
769 sg->length);
770 host->flags &= ~SDHCI_REQ_USE_DMA;
771 break;
772 }
773 }
774 }
775 }
776
777 /*
778 * The assumption here being that alignment is the same after
779 * translation to device address space.
780 */
781 if (host->flags & SDHCI_REQ_USE_DMA) {
782 int broken, i;
783 struct scatterlist *sg;
784
785 broken = 0;
786 if (host->flags & SDHCI_USE_ADMA) {
787 /*
788 * As we use 3 byte chunks to work around
789 * alignment problems, we need to check this
790 * quirk.
791 */
792 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
793 broken = 1;
794 } else {
795 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
796 broken = 1;
797 }
798
799 if (unlikely(broken)) {
800 for_each_sg(data->sg, sg, data->sg_len, i) {
801 if (sg->offset & 0x3) {
802 DBG("Reverting to PIO because of "
803 "bad alignment\n");
804 host->flags &= ~SDHCI_REQ_USE_DMA;
805 break;
806 }
807 }
808 }
809 }
810
811 if (host->flags & SDHCI_REQ_USE_DMA) {
812 if (host->flags & SDHCI_USE_ADMA) {
813 ret = sdhci_adma_table_pre(host, data);
814 if (ret) {
815 /*
816 * This only happens when someone fed
817 * us an invalid request.
818 */
819 WARN_ON(1);
820 host->flags &= ~SDHCI_REQ_USE_DMA;
821 } else {
822 sdhci_writel(host, host->adma_addr,
823 SDHCI_ADMA_ADDRESS);
824 }
825 } else {
826 int sg_cnt;
827
828 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
829 data->sg, data->sg_len,
830 (data->flags & MMC_DATA_READ) ?
831 DMA_FROM_DEVICE :
832 DMA_TO_DEVICE);
833 if (sg_cnt == 0) {
834 /*
835 * This only happens when someone fed
836 * us an invalid request.
837 */
838 WARN_ON(1);
839 host->flags &= ~SDHCI_REQ_USE_DMA;
840 } else {
841 WARN_ON(sg_cnt != 1);
842 sdhci_writel(host, sg_dma_address(data->sg),
843 SDHCI_DMA_ADDRESS);
844 }
845 }
846 }
847
848 /*
849 * Always adjust the DMA selection as some controllers
850 * (e.g. JMicron) can't do PIO properly when the selection
851 * is ADMA.
852 */
853 if (host->version >= SDHCI_SPEC_200) {
854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
855 ctrl &= ~SDHCI_CTRL_DMA_MASK;
856 if ((host->flags & SDHCI_REQ_USE_DMA) &&
857 (host->flags & SDHCI_USE_ADMA))
858 ctrl |= SDHCI_CTRL_ADMA32;
859 else
860 ctrl |= SDHCI_CTRL_SDMA;
861 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
862 }
863
864 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
865 int flags;
866
867 flags = SG_MITER_ATOMIC;
868 if (host->data->flags & MMC_DATA_READ)
869 flags |= SG_MITER_TO_SG;
870 else
871 flags |= SG_MITER_FROM_SG;
872 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
873 host->blocks = data->blocks;
874 }
875
876 sdhci_set_transfer_irqs(host);
877
878 /* Set the DMA boundary value and block size */
879 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
880 data->blksz), SDHCI_BLOCK_SIZE);
881 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
882 }
883
884 static void sdhci_set_transfer_mode(struct sdhci_host *host,
885 struct mmc_command *cmd)
886 {
887 u16 mode;
888 struct mmc_data *data = cmd->data;
889
890 if (data == NULL)
891 return;
892
893 WARN_ON(!host->data);
894
895 mode = SDHCI_TRNS_BLK_CNT_EN;
896 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
897 mode |= SDHCI_TRNS_MULTI;
898 /*
899 * If we are sending CMD23, CMD12 never gets sent
900 * on successful completion (so no Auto-CMD12).
901 */
902 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
903 mode |= SDHCI_TRNS_AUTO_CMD12;
904 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
905 mode |= SDHCI_TRNS_AUTO_CMD23;
906 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
907 }
908 }
909
910 if (data->flags & MMC_DATA_READ)
911 mode |= SDHCI_TRNS_READ;
912 if (host->flags & SDHCI_REQ_USE_DMA)
913 mode |= SDHCI_TRNS_DMA;
914
915 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
916 }
917
918 static void sdhci_finish_data(struct sdhci_host *host)
919 {
920 struct mmc_data *data;
921
922 BUG_ON(!host->data);
923
924 data = host->data;
925 host->data = NULL;
926
927 if (host->flags & SDHCI_REQ_USE_DMA) {
928 if (host->flags & SDHCI_USE_ADMA)
929 sdhci_adma_table_post(host, data);
930 else {
931 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
932 data->sg_len, (data->flags & MMC_DATA_READ) ?
933 DMA_FROM_DEVICE : DMA_TO_DEVICE);
934 }
935 }
936
937 /*
938 * The specification states that the block count register must
939 * be updated, but it does not specify at what point in the
940 * data flow. That makes the register entirely useless to read
941 * back so we have to assume that nothing made it to the card
942 * in the event of an error.
943 */
944 if (data->error)
945 data->bytes_xfered = 0;
946 else
947 data->bytes_xfered = data->blksz * data->blocks;
948
949 /*
950 * Need to send CMD12 if -
951 * a) open-ended multiblock transfer (no CMD23)
952 * b) error in multiblock transfer
953 */
954 if (data->stop &&
955 (data->error ||
956 !host->mrq->sbc)) {
957
958 /*
959 * The controller needs a reset of internal state machines
960 * upon error conditions.
961 */
962 if (data->error) {
963 sdhci_reset(host, SDHCI_RESET_CMD);
964 sdhci_reset(host, SDHCI_RESET_DATA);
965 }
966
967 sdhci_send_command(host, data->stop);
968 } else
969 tasklet_schedule(&host->finish_tasklet);
970 }
971
972 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
973 {
974 int flags;
975 u32 mask;
976 unsigned long timeout;
977
978 WARN_ON(host->cmd);
979
980 /* Wait max 10 ms */
981 timeout = 10;
982
983 mask = SDHCI_CMD_INHIBIT;
984 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
985 mask |= SDHCI_DATA_INHIBIT;
986
987 /* We shouldn't wait for data inihibit for stop commands, even
988 though they might use busy signaling */
989 if (host->mrq->data && (cmd == host->mrq->data->stop))
990 mask &= ~SDHCI_DATA_INHIBIT;
991
992 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
993 if (timeout == 0) {
994 pr_err("%s: Controller never released "
995 "inhibit bit(s).\n", mmc_hostname(host->mmc));
996 sdhci_dumpregs(host);
997 cmd->error = -EIO;
998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
1001 timeout--;
1002 mdelay(1);
1003 }
1004
1005 mod_timer(&host->timer, jiffies + 10 * HZ);
1006
1007 host->cmd = cmd;
1008
1009 sdhci_prepare_data(host, cmd);
1010
1011 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1012
1013 sdhci_set_transfer_mode(host, cmd);
1014
1015 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1016 pr_err("%s: Unsupported response type!\n",
1017 mmc_hostname(host->mmc));
1018 cmd->error = -EINVAL;
1019 tasklet_schedule(&host->finish_tasklet);
1020 return;
1021 }
1022
1023 if (!(cmd->flags & MMC_RSP_PRESENT))
1024 flags = SDHCI_CMD_RESP_NONE;
1025 else if (cmd->flags & MMC_RSP_136)
1026 flags = SDHCI_CMD_RESP_LONG;
1027 else if (cmd->flags & MMC_RSP_BUSY)
1028 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1029 else
1030 flags = SDHCI_CMD_RESP_SHORT;
1031
1032 if (cmd->flags & MMC_RSP_CRC)
1033 flags |= SDHCI_CMD_CRC;
1034 if (cmd->flags & MMC_RSP_OPCODE)
1035 flags |= SDHCI_CMD_INDEX;
1036
1037 /* CMD19 is special in that the Data Present Select should be set */
1038 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1039 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1040 flags |= SDHCI_CMD_DATA;
1041
1042 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1043 }
1044
1045 static void sdhci_finish_command(struct sdhci_host *host)
1046 {
1047 int i;
1048
1049 BUG_ON(host->cmd == NULL);
1050
1051 if (host->cmd->flags & MMC_RSP_PRESENT) {
1052 if (host->cmd->flags & MMC_RSP_136) {
1053 /* CRC is stripped so we need to do some shifting. */
1054 for (i = 0;i < 4;i++) {
1055 host->cmd->resp[i] = sdhci_readl(host,
1056 SDHCI_RESPONSE + (3-i)*4) << 8;
1057 if (i != 3)
1058 host->cmd->resp[i] |=
1059 sdhci_readb(host,
1060 SDHCI_RESPONSE + (3-i)*4-1);
1061 }
1062 } else {
1063 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1064 }
1065 }
1066
1067 host->cmd->error = 0;
1068
1069 /* Finished CMD23, now send actual command. */
1070 if (host->cmd == host->mrq->sbc) {
1071 host->cmd = NULL;
1072 sdhci_send_command(host, host->mrq->cmd);
1073 } else {
1074
1075 /* Processed actual command. */
1076 if (host->data && host->data_early)
1077 sdhci_finish_data(host);
1078
1079 if (!host->cmd->data)
1080 tasklet_schedule(&host->finish_tasklet);
1081
1082 host->cmd = NULL;
1083 }
1084 }
1085
1086 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1087 {
1088 u16 ctrl, preset = 0;
1089
1090 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1091
1092 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1093 case SDHCI_CTRL_UHS_SDR12:
1094 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1095 break;
1096 case SDHCI_CTRL_UHS_SDR25:
1097 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1098 break;
1099 case SDHCI_CTRL_UHS_SDR50:
1100 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1101 break;
1102 case SDHCI_CTRL_UHS_SDR104:
1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1104 break;
1105 case SDHCI_CTRL_UHS_DDR50:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1107 break;
1108 default:
1109 pr_warn("%s: Invalid UHS-I mode selected\n",
1110 mmc_hostname(host->mmc));
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1112 break;
1113 }
1114 return preset;
1115 }
1116
1117 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1118 {
1119 int div = 0; /* Initialized for compiler warning */
1120 int real_div = div, clk_mul = 1;
1121 u16 clk = 0;
1122 unsigned long timeout;
1123
1124 if (clock && clock == host->clock)
1125 return;
1126
1127 host->mmc->actual_clock = 0;
1128
1129 if (host->ops->set_clock) {
1130 host->ops->set_clock(host, clock);
1131 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1132 return;
1133 }
1134
1135 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1136
1137 if (clock == 0)
1138 goto out;
1139
1140 if (host->version >= SDHCI_SPEC_300) {
1141 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1142 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1143 u16 pre_val;
1144
1145 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1146 pre_val = sdhci_get_preset_value(host);
1147 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1148 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1149 if (host->clk_mul &&
1150 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1151 clk = SDHCI_PROG_CLOCK_MODE;
1152 real_div = div + 1;
1153 clk_mul = host->clk_mul;
1154 } else {
1155 real_div = max_t(int, 1, div << 1);
1156 }
1157 goto clock_set;
1158 }
1159
1160 /*
1161 * Check if the Host Controller supports Programmable Clock
1162 * Mode.
1163 */
1164 if (host->clk_mul) {
1165 for (div = 1; div <= 1024; div++) {
1166 if ((host->max_clk * host->clk_mul / div)
1167 <= clock)
1168 break;
1169 }
1170 /*
1171 * Set Programmable Clock Mode in the Clock
1172 * Control register.
1173 */
1174 clk = SDHCI_PROG_CLOCK_MODE;
1175 real_div = div;
1176 clk_mul = host->clk_mul;
1177 div--;
1178 } else {
1179 /* Version 3.00 divisors must be a multiple of 2. */
1180 if (host->max_clk <= clock)
1181 div = 1;
1182 else {
1183 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1184 div += 2) {
1185 if ((host->max_clk / div) <= clock)
1186 break;
1187 }
1188 }
1189 real_div = div;
1190 div >>= 1;
1191 }
1192 } else {
1193 /* Version 2.00 divisors must be a power of 2. */
1194 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1195 if ((host->max_clk / div) <= clock)
1196 break;
1197 }
1198 real_div = div;
1199 div >>= 1;
1200 }
1201
1202 clock_set:
1203 if (real_div)
1204 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1205
1206 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1207 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1208 << SDHCI_DIVIDER_HI_SHIFT;
1209 clk |= SDHCI_CLOCK_INT_EN;
1210 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1211
1212 /* Wait max 20 ms */
1213 timeout = 20;
1214 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1215 & SDHCI_CLOCK_INT_STABLE)) {
1216 if (timeout == 0) {
1217 pr_err("%s: Internal clock never "
1218 "stabilised.\n", mmc_hostname(host->mmc));
1219 sdhci_dumpregs(host);
1220 return;
1221 }
1222 timeout--;
1223 mdelay(1);
1224 }
1225
1226 clk |= SDHCI_CLOCK_CARD_EN;
1227 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1228
1229 out:
1230 host->clock = clock;
1231 }
1232
1233 static inline void sdhci_update_clock(struct sdhci_host *host)
1234 {
1235 unsigned int clock;
1236
1237 clock = host->clock;
1238 host->clock = 0;
1239 sdhci_set_clock(host, clock);
1240 }
1241
1242 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1243 {
1244 u8 pwr = 0;
1245
1246 if (power != (unsigned short)-1) {
1247 switch (1 << power) {
1248 case MMC_VDD_165_195:
1249 pwr = SDHCI_POWER_180;
1250 break;
1251 case MMC_VDD_29_30:
1252 case MMC_VDD_30_31:
1253 pwr = SDHCI_POWER_300;
1254 break;
1255 case MMC_VDD_32_33:
1256 case MMC_VDD_33_34:
1257 pwr = SDHCI_POWER_330;
1258 break;
1259 default:
1260 BUG();
1261 }
1262 }
1263
1264 if (host->pwr == pwr)
1265 return -1;
1266
1267 host->pwr = pwr;
1268
1269 if (pwr == 0) {
1270 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1271 return 0;
1272 }
1273
1274 /*
1275 * Spec says that we should clear the power reg before setting
1276 * a new value. Some controllers don't seem to like this though.
1277 */
1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1280
1281 /*
1282 * At least the Marvell CaFe chip gets confused if we set the voltage
1283 * and set turn on power at the same time, so set the voltage first.
1284 */
1285 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1286 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1287
1288 pwr |= SDHCI_POWER_ON;
1289
1290 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1291
1292 /*
1293 * Some controllers need an extra 10ms delay of 10ms before they
1294 * can apply clock after applying power
1295 */
1296 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1297 mdelay(10);
1298
1299 return power;
1300 }
1301
1302 /*****************************************************************************\
1303 * *
1304 * MMC callbacks *
1305 * *
1306 \*****************************************************************************/
1307
1308 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1309 {
1310 struct sdhci_host *host;
1311 int present;
1312 unsigned long flags;
1313 u32 tuning_opcode;
1314
1315 host = mmc_priv(mmc);
1316
1317 sdhci_runtime_pm_get(host);
1318
1319 present = mmc_gpio_get_cd(host->mmc);
1320
1321 spin_lock_irqsave(&host->lock, flags);
1322
1323 WARN_ON(host->mrq != NULL);
1324
1325 #ifndef SDHCI_USE_LEDS_CLASS
1326 sdhci_activate_led(host);
1327 #endif
1328
1329 /*
1330 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1331 * requests if Auto-CMD12 is enabled.
1332 */
1333 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1334 if (mrq->stop) {
1335 mrq->data->stop = NULL;
1336 mrq->stop = NULL;
1337 }
1338 }
1339
1340 host->mrq = mrq;
1341
1342 /*
1343 * Firstly check card presence from cd-gpio. The return could
1344 * be one of the following possibilities:
1345 * negative: cd-gpio is not available
1346 * zero: cd-gpio is used, and card is removed
1347 * one: cd-gpio is used, and card is present
1348 */
1349 if (present < 0) {
1350 /* If polling, assume that the card is always present. */
1351 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1352 present = 1;
1353 else
1354 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1355 SDHCI_CARD_PRESENT;
1356 }
1357
1358 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1359 host->mrq->cmd->error = -ENOMEDIUM;
1360 tasklet_schedule(&host->finish_tasklet);
1361 } else {
1362 u32 present_state;
1363
1364 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1365 /*
1366 * Check if the re-tuning timer has already expired and there
1367 * is no on-going data transfer. If so, we need to execute
1368 * tuning procedure before sending command.
1369 */
1370 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1371 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1372 if (mmc->card) {
1373 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1374 tuning_opcode =
1375 mmc->card->type == MMC_TYPE_MMC ?
1376 MMC_SEND_TUNING_BLOCK_HS200 :
1377 MMC_SEND_TUNING_BLOCK;
1378 spin_unlock_irqrestore(&host->lock, flags);
1379 sdhci_execute_tuning(mmc, tuning_opcode);
1380 spin_lock_irqsave(&host->lock, flags);
1381
1382 /* Restore original mmc_request structure */
1383 host->mrq = mrq;
1384 }
1385 }
1386
1387 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1388 sdhci_send_command(host, mrq->sbc);
1389 else
1390 sdhci_send_command(host, mrq->cmd);
1391 }
1392
1393 mmiowb();
1394 spin_unlock_irqrestore(&host->lock, flags);
1395 }
1396
1397 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1398 {
1399 unsigned long flags;
1400 int vdd_bit = -1;
1401 u8 ctrl;
1402
1403 spin_lock_irqsave(&host->lock, flags);
1404
1405 if (host->flags & SDHCI_DEVICE_DEAD) {
1406 spin_unlock_irqrestore(&host->lock, flags);
1407 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1408 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1409 return;
1410 }
1411
1412 /*
1413 * Reset the chip on each power off.
1414 * Should clear out any weird states.
1415 */
1416 if (ios->power_mode == MMC_POWER_OFF) {
1417 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1418 sdhci_reinit(host);
1419 }
1420
1421 if (host->version >= SDHCI_SPEC_300 &&
1422 (ios->power_mode == MMC_POWER_UP))
1423 sdhci_enable_preset_value(host, false);
1424
1425 sdhci_set_clock(host, ios->clock);
1426
1427 if (ios->power_mode == MMC_POWER_OFF)
1428 vdd_bit = sdhci_set_power(host, -1);
1429 else
1430 vdd_bit = sdhci_set_power(host, ios->vdd);
1431
1432 if (host->vmmc && vdd_bit != -1) {
1433 spin_unlock_irqrestore(&host->lock, flags);
1434 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1435 spin_lock_irqsave(&host->lock, flags);
1436 }
1437
1438 if (host->ops->platform_send_init_74_clocks)
1439 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1440
1441 /*
1442 * If your platform has 8-bit width support but is not a v3 controller,
1443 * or if it requires special setup code, you should implement that in
1444 * platform_bus_width().
1445 */
1446 if (host->ops->platform_bus_width) {
1447 host->ops->platform_bus_width(host, ios->bus_width);
1448 } else {
1449 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1450 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1451 ctrl &= ~SDHCI_CTRL_4BITBUS;
1452 if (host->version >= SDHCI_SPEC_300)
1453 ctrl |= SDHCI_CTRL_8BITBUS;
1454 } else {
1455 if (host->version >= SDHCI_SPEC_300)
1456 ctrl &= ~SDHCI_CTRL_8BITBUS;
1457 if (ios->bus_width == MMC_BUS_WIDTH_4)
1458 ctrl |= SDHCI_CTRL_4BITBUS;
1459 else
1460 ctrl &= ~SDHCI_CTRL_4BITBUS;
1461 }
1462 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1463 }
1464
1465 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1466
1467 if ((ios->timing == MMC_TIMING_SD_HS ||
1468 ios->timing == MMC_TIMING_MMC_HS)
1469 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1470 ctrl |= SDHCI_CTRL_HISPD;
1471 else
1472 ctrl &= ~SDHCI_CTRL_HISPD;
1473
1474 if (host->version >= SDHCI_SPEC_300) {
1475 u16 clk, ctrl_2;
1476
1477 /* In case of UHS-I modes, set High Speed Enable */
1478 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1479 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1480 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1481 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1482 (ios->timing == MMC_TIMING_UHS_SDR25))
1483 ctrl |= SDHCI_CTRL_HISPD;
1484
1485 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1486 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1487 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1488 /*
1489 * We only need to set Driver Strength if the
1490 * preset value enable is not set.
1491 */
1492 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1493 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1494 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1495 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1496 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1497
1498 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1499 } else {
1500 /*
1501 * According to SDHC Spec v3.00, if the Preset Value
1502 * Enable in the Host Control 2 register is set, we
1503 * need to reset SD Clock Enable before changing High
1504 * Speed Enable to avoid generating clock gliches.
1505 */
1506
1507 /* Reset SD Clock Enable */
1508 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1509 clk &= ~SDHCI_CLOCK_CARD_EN;
1510 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1511
1512 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1513
1514 /* Re-enable SD Clock */
1515 sdhci_update_clock(host);
1516 }
1517
1518
1519 /* Reset SD Clock Enable */
1520 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1521 clk &= ~SDHCI_CLOCK_CARD_EN;
1522 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1523
1524 if (host->ops->set_uhs_signaling)
1525 host->ops->set_uhs_signaling(host, ios->timing);
1526 else {
1527 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1528 /* Select Bus Speed Mode for host */
1529 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1530 if (ios->timing == MMC_TIMING_MMC_HS200)
1531 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1532 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1533 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1534 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1535 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1536 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1537 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1538 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1539 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1540 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1541 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1542 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1543 }
1544
1545 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1546 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1548 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1549 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1550 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1551 u16 preset;
1552
1553 sdhci_enable_preset_value(host, true);
1554 preset = sdhci_get_preset_value(host);
1555 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1556 >> SDHCI_PRESET_DRV_SHIFT;
1557 }
1558
1559 /* Re-enable SD Clock */
1560 sdhci_update_clock(host);
1561 } else
1562 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1563
1564 /*
1565 * Some (ENE) controllers go apeshit on some ios operation,
1566 * signalling timeout and CRC errors even on CMD0. Resetting
1567 * it on each ios seems to solve the problem.
1568 */
1569 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1570 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1571
1572 mmiowb();
1573 spin_unlock_irqrestore(&host->lock, flags);
1574 }
1575
1576 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1577 {
1578 struct sdhci_host *host = mmc_priv(mmc);
1579
1580 sdhci_runtime_pm_get(host);
1581 sdhci_do_set_ios(host, ios);
1582 sdhci_runtime_pm_put(host);
1583 }
1584
1585 static int sdhci_do_get_cd(struct sdhci_host *host)
1586 {
1587 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1588
1589 if (host->flags & SDHCI_DEVICE_DEAD)
1590 return 0;
1591
1592 /* If polling/nonremovable, assume that the card is always present. */
1593 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1594 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1595 return 1;
1596
1597 /* Try slot gpio detect */
1598 if (!IS_ERR_VALUE(gpio_cd))
1599 return !!gpio_cd;
1600
1601 /* Host native card detect */
1602 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1603 }
1604
1605 static int sdhci_get_cd(struct mmc_host *mmc)
1606 {
1607 struct sdhci_host *host = mmc_priv(mmc);
1608 int ret;
1609
1610 sdhci_runtime_pm_get(host);
1611 ret = sdhci_do_get_cd(host);
1612 sdhci_runtime_pm_put(host);
1613 return ret;
1614 }
1615
1616 static int sdhci_check_ro(struct sdhci_host *host)
1617 {
1618 unsigned long flags;
1619 int is_readonly;
1620
1621 spin_lock_irqsave(&host->lock, flags);
1622
1623 if (host->flags & SDHCI_DEVICE_DEAD)
1624 is_readonly = 0;
1625 else if (host->ops->get_ro)
1626 is_readonly = host->ops->get_ro(host);
1627 else
1628 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1629 & SDHCI_WRITE_PROTECT);
1630
1631 spin_unlock_irqrestore(&host->lock, flags);
1632
1633 /* This quirk needs to be replaced by a callback-function later */
1634 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1635 !is_readonly : is_readonly;
1636 }
1637
1638 #define SAMPLE_COUNT 5
1639
1640 static int sdhci_do_get_ro(struct sdhci_host *host)
1641 {
1642 int i, ro_count;
1643
1644 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1645 return sdhci_check_ro(host);
1646
1647 ro_count = 0;
1648 for (i = 0; i < SAMPLE_COUNT; i++) {
1649 if (sdhci_check_ro(host)) {
1650 if (++ro_count > SAMPLE_COUNT / 2)
1651 return 1;
1652 }
1653 msleep(30);
1654 }
1655 return 0;
1656 }
1657
1658 static void sdhci_hw_reset(struct mmc_host *mmc)
1659 {
1660 struct sdhci_host *host = mmc_priv(mmc);
1661
1662 if (host->ops && host->ops->hw_reset)
1663 host->ops->hw_reset(host);
1664 }
1665
1666 static int sdhci_get_ro(struct mmc_host *mmc)
1667 {
1668 struct sdhci_host *host = mmc_priv(mmc);
1669 int ret;
1670
1671 sdhci_runtime_pm_get(host);
1672 ret = sdhci_do_get_ro(host);
1673 sdhci_runtime_pm_put(host);
1674 return ret;
1675 }
1676
1677 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1678 {
1679 if (host->flags & SDHCI_DEVICE_DEAD)
1680 goto out;
1681
1682 if (enable)
1683 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1684 else
1685 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1686
1687 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1688 if (host->runtime_suspended)
1689 goto out;
1690
1691 if (enable)
1692 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1693 else
1694 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1695 out:
1696 mmiowb();
1697 }
1698
1699 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1700 {
1701 struct sdhci_host *host = mmc_priv(mmc);
1702 unsigned long flags;
1703
1704 spin_lock_irqsave(&host->lock, flags);
1705 sdhci_enable_sdio_irq_nolock(host, enable);
1706 spin_unlock_irqrestore(&host->lock, flags);
1707 }
1708
1709 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1710 struct mmc_ios *ios)
1711 {
1712 u16 ctrl;
1713 int ret;
1714
1715 /*
1716 * Signal Voltage Switching is only applicable for Host Controllers
1717 * v3.00 and above.
1718 */
1719 if (host->version < SDHCI_SPEC_300)
1720 return 0;
1721
1722 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1723
1724 switch (ios->signal_voltage) {
1725 case MMC_SIGNAL_VOLTAGE_330:
1726 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1727 ctrl &= ~SDHCI_CTRL_VDD_180;
1728 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1729
1730 if (host->vqmmc) {
1731 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1732 if (ret) {
1733 pr_warning("%s: Switching to 3.3V signalling voltage "
1734 " failed\n", mmc_hostname(host->mmc));
1735 return -EIO;
1736 }
1737 }
1738 /* Wait for 5ms */
1739 usleep_range(5000, 5500);
1740
1741 /* 3.3V regulator output should be stable within 5 ms */
1742 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1743 if (!(ctrl & SDHCI_CTRL_VDD_180))
1744 return 0;
1745
1746 pr_warning("%s: 3.3V regulator output did not became stable\n",
1747 mmc_hostname(host->mmc));
1748
1749 return -EAGAIN;
1750 case MMC_SIGNAL_VOLTAGE_180:
1751 if (host->vqmmc) {
1752 ret = regulator_set_voltage(host->vqmmc,
1753 1700000, 1950000);
1754 if (ret) {
1755 pr_warning("%s: Switching to 1.8V signalling voltage "
1756 " failed\n", mmc_hostname(host->mmc));
1757 return -EIO;
1758 }
1759 }
1760
1761 /*
1762 * Enable 1.8V Signal Enable in the Host Control2
1763 * register
1764 */
1765 ctrl |= SDHCI_CTRL_VDD_180;
1766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1767
1768 /* Wait for 5ms */
1769 usleep_range(5000, 5500);
1770
1771 /* 1.8V regulator output should be stable within 5 ms */
1772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773 if (ctrl & SDHCI_CTRL_VDD_180)
1774 return 0;
1775
1776 pr_warning("%s: 1.8V regulator output did not became stable\n",
1777 mmc_hostname(host->mmc));
1778
1779 return -EAGAIN;
1780 case MMC_SIGNAL_VOLTAGE_120:
1781 if (host->vqmmc) {
1782 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1783 if (ret) {
1784 pr_warning("%s: Switching to 1.2V signalling voltage "
1785 " failed\n", mmc_hostname(host->mmc));
1786 return -EIO;
1787 }
1788 }
1789 return 0;
1790 default:
1791 /* No signal voltage switch required */
1792 return 0;
1793 }
1794 }
1795
1796 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1797 struct mmc_ios *ios)
1798 {
1799 struct sdhci_host *host = mmc_priv(mmc);
1800 int err;
1801
1802 if (host->version < SDHCI_SPEC_300)
1803 return 0;
1804 sdhci_runtime_pm_get(host);
1805 err = sdhci_do_start_signal_voltage_switch(host, ios);
1806 sdhci_runtime_pm_put(host);
1807 return err;
1808 }
1809
1810 static int sdhci_card_busy(struct mmc_host *mmc)
1811 {
1812 struct sdhci_host *host = mmc_priv(mmc);
1813 u32 present_state;
1814
1815 sdhci_runtime_pm_get(host);
1816 /* Check whether DAT[3:0] is 0000 */
1817 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1818 sdhci_runtime_pm_put(host);
1819
1820 return !(present_state & SDHCI_DATA_LVL_MASK);
1821 }
1822
1823 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1824 {
1825 struct sdhci_host *host;
1826 u16 ctrl;
1827 u32 ier;
1828 int tuning_loop_counter = MAX_TUNING_LOOP;
1829 unsigned long timeout;
1830 int err = 0;
1831 bool requires_tuning_nonuhs = false;
1832
1833 host = mmc_priv(mmc);
1834
1835 sdhci_runtime_pm_get(host);
1836 disable_irq(host->irq);
1837 spin_lock(&host->lock);
1838
1839 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1840
1841 /*
1842 * The Host Controller needs tuning only in case of SDR104 mode
1843 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1844 * Capabilities register.
1845 * If the Host Controller supports the HS200 mode then the
1846 * tuning function has to be executed.
1847 */
1848 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1849 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1850 host->flags & SDHCI_HS200_NEEDS_TUNING))
1851 requires_tuning_nonuhs = true;
1852
1853 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1854 requires_tuning_nonuhs)
1855 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1856 else {
1857 spin_unlock(&host->lock);
1858 enable_irq(host->irq);
1859 sdhci_runtime_pm_put(host);
1860 return 0;
1861 }
1862
1863 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1864
1865 /*
1866 * As per the Host Controller spec v3.00, tuning command
1867 * generates Buffer Read Ready interrupt, so enable that.
1868 *
1869 * Note: The spec clearly says that when tuning sequence
1870 * is being performed, the controller does not generate
1871 * interrupts other than Buffer Read Ready interrupt. But
1872 * to make sure we don't hit a controller bug, we _only_
1873 * enable Buffer Read Ready interrupt here.
1874 */
1875 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1876 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1877
1878 /*
1879 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1880 * of loops reaches 40 times or a timeout of 150ms occurs.
1881 */
1882 timeout = 150;
1883 do {
1884 struct mmc_command cmd = {0};
1885 struct mmc_request mrq = {NULL};
1886
1887 if (!tuning_loop_counter && !timeout)
1888 break;
1889
1890 cmd.opcode = opcode;
1891 cmd.arg = 0;
1892 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1893 cmd.retries = 0;
1894 cmd.data = NULL;
1895 cmd.error = 0;
1896
1897 mrq.cmd = &cmd;
1898 host->mrq = &mrq;
1899
1900 /*
1901 * In response to CMD19, the card sends 64 bytes of tuning
1902 * block to the Host Controller. So we set the block size
1903 * to 64 here.
1904 */
1905 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1906 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1907 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1908 SDHCI_BLOCK_SIZE);
1909 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1910 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1911 SDHCI_BLOCK_SIZE);
1912 } else {
1913 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1914 SDHCI_BLOCK_SIZE);
1915 }
1916
1917 /*
1918 * The tuning block is sent by the card to the host controller.
1919 * So we set the TRNS_READ bit in the Transfer Mode register.
1920 * This also takes care of setting DMA Enable and Multi Block
1921 * Select in the same register to 0.
1922 */
1923 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1924
1925 sdhci_send_command(host, &cmd);
1926
1927 host->cmd = NULL;
1928 host->mrq = NULL;
1929
1930 spin_unlock(&host->lock);
1931 enable_irq(host->irq);
1932
1933 /* Wait for Buffer Read Ready interrupt */
1934 wait_event_interruptible_timeout(host->buf_ready_int,
1935 (host->tuning_done == 1),
1936 msecs_to_jiffies(50));
1937 disable_irq(host->irq);
1938 spin_lock(&host->lock);
1939
1940 if (!host->tuning_done) {
1941 pr_info(DRIVER_NAME ": Timeout waiting for "
1942 "Buffer Read Ready interrupt during tuning "
1943 "procedure, falling back to fixed sampling "
1944 "clock\n");
1945 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1946 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1947 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1948 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1949
1950 err = -EIO;
1951 goto out;
1952 }
1953
1954 host->tuning_done = 0;
1955
1956 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1957 tuning_loop_counter--;
1958 timeout--;
1959 mdelay(1);
1960 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1961
1962 /*
1963 * The Host Driver has exhausted the maximum number of loops allowed,
1964 * so use fixed sampling frequency.
1965 */
1966 if (!tuning_loop_counter || !timeout) {
1967 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1968 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1969 } else {
1970 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1971 pr_info(DRIVER_NAME ": Tuning procedure"
1972 " failed, falling back to fixed sampling"
1973 " clock\n");
1974 err = -EIO;
1975 }
1976 }
1977
1978 out:
1979 /*
1980 * If this is the very first time we are here, we start the retuning
1981 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1982 * flag won't be set, we check this condition before actually starting
1983 * the timer.
1984 */
1985 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1986 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1987 host->flags |= SDHCI_USING_RETUNING_TIMER;
1988 mod_timer(&host->tuning_timer, jiffies +
1989 host->tuning_count * HZ);
1990 /* Tuning mode 1 limits the maximum data length to 4MB */
1991 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1992 } else {
1993 host->flags &= ~SDHCI_NEEDS_RETUNING;
1994 /* Reload the new initial value for timer */
1995 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1996 mod_timer(&host->tuning_timer, jiffies +
1997 host->tuning_count * HZ);
1998 }
1999
2000 /*
2001 * In case tuning fails, host controllers which support re-tuning can
2002 * try tuning again at a later time, when the re-tuning timer expires.
2003 * So for these controllers, we return 0. Since there might be other
2004 * controllers who do not have this capability, we return error for
2005 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2006 * a retuning timer to do the retuning for the card.
2007 */
2008 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2009 err = 0;
2010
2011 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2012 spin_unlock(&host->lock);
2013 enable_irq(host->irq);
2014 sdhci_runtime_pm_put(host);
2015
2016 return err;
2017 }
2018
2019
2020 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2021 {
2022 u16 ctrl;
2023
2024 /* Host Controller v3.00 defines preset value registers */
2025 if (host->version < SDHCI_SPEC_300)
2026 return;
2027
2028 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2029
2030 /*
2031 * We only enable or disable Preset Value if they are not already
2032 * enabled or disabled respectively. Otherwise, we bail out.
2033 */
2034 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2035 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2036 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2037 host->flags |= SDHCI_PV_ENABLED;
2038 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2039 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2040 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2041 host->flags &= ~SDHCI_PV_ENABLED;
2042 }
2043 }
2044
2045 static void sdhci_card_event(struct mmc_host *mmc)
2046 {
2047 struct sdhci_host *host = mmc_priv(mmc);
2048 unsigned long flags;
2049
2050 spin_lock_irqsave(&host->lock, flags);
2051
2052 /* Check host->mrq first in case we are runtime suspended */
2053 if (host->mrq &&
2054 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2055 pr_err("%s: Card removed during transfer!\n",
2056 mmc_hostname(host->mmc));
2057 pr_err("%s: Resetting controller.\n",
2058 mmc_hostname(host->mmc));
2059
2060 sdhci_reset(host, SDHCI_RESET_CMD);
2061 sdhci_reset(host, SDHCI_RESET_DATA);
2062
2063 host->mrq->cmd->error = -ENOMEDIUM;
2064 tasklet_schedule(&host->finish_tasklet);
2065 }
2066
2067 spin_unlock_irqrestore(&host->lock, flags);
2068 }
2069
2070 static const struct mmc_host_ops sdhci_ops = {
2071 .request = sdhci_request,
2072 .set_ios = sdhci_set_ios,
2073 .get_cd = sdhci_get_cd,
2074 .get_ro = sdhci_get_ro,
2075 .hw_reset = sdhci_hw_reset,
2076 .enable_sdio_irq = sdhci_enable_sdio_irq,
2077 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2078 .execute_tuning = sdhci_execute_tuning,
2079 .card_event = sdhci_card_event,
2080 .card_busy = sdhci_card_busy,
2081 };
2082
2083 /*****************************************************************************\
2084 * *
2085 * Tasklets *
2086 * *
2087 \*****************************************************************************/
2088
2089 static void sdhci_tasklet_card(unsigned long param)
2090 {
2091 struct sdhci_host *host = (struct sdhci_host*)param;
2092
2093 sdhci_card_event(host->mmc);
2094
2095 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2096 }
2097
2098 static void sdhci_tasklet_finish(unsigned long param)
2099 {
2100 struct sdhci_host *host;
2101 unsigned long flags;
2102 struct mmc_request *mrq;
2103
2104 host = (struct sdhci_host*)param;
2105
2106 spin_lock_irqsave(&host->lock, flags);
2107
2108 /*
2109 * If this tasklet gets rescheduled while running, it will
2110 * be run again afterwards but without any active request.
2111 */
2112 if (!host->mrq) {
2113 spin_unlock_irqrestore(&host->lock, flags);
2114 return;
2115 }
2116
2117 del_timer(&host->timer);
2118
2119 mrq = host->mrq;
2120
2121 /*
2122 * The controller needs a reset of internal state machines
2123 * upon error conditions.
2124 */
2125 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2126 ((mrq->cmd && mrq->cmd->error) ||
2127 (mrq->data && (mrq->data->error ||
2128 (mrq->data->stop && mrq->data->stop->error))) ||
2129 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2130
2131 /* Some controllers need this kick or reset won't work here */
2132 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2133 /* This is to force an update */
2134 sdhci_update_clock(host);
2135
2136 /* Spec says we should do both at the same time, but Ricoh
2137 controllers do not like that. */
2138 sdhci_reset(host, SDHCI_RESET_CMD);
2139 sdhci_reset(host, SDHCI_RESET_DATA);
2140 }
2141
2142 host->mrq = NULL;
2143 host->cmd = NULL;
2144 host->data = NULL;
2145
2146 #ifndef SDHCI_USE_LEDS_CLASS
2147 sdhci_deactivate_led(host);
2148 #endif
2149
2150 mmiowb();
2151 spin_unlock_irqrestore(&host->lock, flags);
2152
2153 mmc_request_done(host->mmc, mrq);
2154 sdhci_runtime_pm_put(host);
2155 }
2156
2157 static void sdhci_timeout_timer(unsigned long data)
2158 {
2159 struct sdhci_host *host;
2160 unsigned long flags;
2161
2162 host = (struct sdhci_host*)data;
2163
2164 spin_lock_irqsave(&host->lock, flags);
2165
2166 if (host->mrq) {
2167 pr_err("%s: Timeout waiting for hardware "
2168 "interrupt.\n", mmc_hostname(host->mmc));
2169 sdhci_dumpregs(host);
2170
2171 if (host->data) {
2172 host->data->error = -ETIMEDOUT;
2173 sdhci_finish_data(host);
2174 } else {
2175 if (host->cmd)
2176 host->cmd->error = -ETIMEDOUT;
2177 else
2178 host->mrq->cmd->error = -ETIMEDOUT;
2179
2180 tasklet_schedule(&host->finish_tasklet);
2181 }
2182 }
2183
2184 mmiowb();
2185 spin_unlock_irqrestore(&host->lock, flags);
2186 }
2187
2188 static void sdhci_tuning_timer(unsigned long data)
2189 {
2190 struct sdhci_host *host;
2191 unsigned long flags;
2192
2193 host = (struct sdhci_host *)data;
2194
2195 spin_lock_irqsave(&host->lock, flags);
2196
2197 host->flags |= SDHCI_NEEDS_RETUNING;
2198
2199 spin_unlock_irqrestore(&host->lock, flags);
2200 }
2201
2202 /*****************************************************************************\
2203 * *
2204 * Interrupt handling *
2205 * *
2206 \*****************************************************************************/
2207
2208 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2209 {
2210 BUG_ON(intmask == 0);
2211
2212 if (!host->cmd) {
2213 pr_err("%s: Got command interrupt 0x%08x even "
2214 "though no command operation was in progress.\n",
2215 mmc_hostname(host->mmc), (unsigned)intmask);
2216 sdhci_dumpregs(host);
2217 return;
2218 }
2219
2220 if (intmask & SDHCI_INT_TIMEOUT)
2221 host->cmd->error = -ETIMEDOUT;
2222 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2223 SDHCI_INT_INDEX))
2224 host->cmd->error = -EILSEQ;
2225
2226 if (host->cmd->error) {
2227 tasklet_schedule(&host->finish_tasklet);
2228 return;
2229 }
2230
2231 /*
2232 * The host can send and interrupt when the busy state has
2233 * ended, allowing us to wait without wasting CPU cycles.
2234 * Unfortunately this is overloaded on the "data complete"
2235 * interrupt, so we need to take some care when handling
2236 * it.
2237 *
2238 * Note: The 1.0 specification is a bit ambiguous about this
2239 * feature so there might be some problems with older
2240 * controllers.
2241 */
2242 if (host->cmd->flags & MMC_RSP_BUSY) {
2243 if (host->cmd->data)
2244 DBG("Cannot wait for busy signal when also "
2245 "doing a data transfer");
2246 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2247 return;
2248
2249 /* The controller does not support the end-of-busy IRQ,
2250 * fall through and take the SDHCI_INT_RESPONSE */
2251 }
2252
2253 if (intmask & SDHCI_INT_RESPONSE)
2254 sdhci_finish_command(host);
2255 }
2256
2257 #ifdef CONFIG_MMC_DEBUG
2258 static void sdhci_show_adma_error(struct sdhci_host *host)
2259 {
2260 const char *name = mmc_hostname(host->mmc);
2261 u8 *desc = host->adma_desc;
2262 __le32 *dma;
2263 __le16 *len;
2264 u8 attr;
2265
2266 sdhci_dumpregs(host);
2267
2268 while (true) {
2269 dma = (__le32 *)(desc + 4);
2270 len = (__le16 *)(desc + 2);
2271 attr = *desc;
2272
2273 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2274 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2275
2276 desc += 8;
2277
2278 if (attr & 2)
2279 break;
2280 }
2281 }
2282 #else
2283 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2284 #endif
2285
2286 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2287 {
2288 u32 command;
2289 BUG_ON(intmask == 0);
2290
2291 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2292 if (intmask & SDHCI_INT_DATA_AVAIL) {
2293 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2294 if (command == MMC_SEND_TUNING_BLOCK ||
2295 command == MMC_SEND_TUNING_BLOCK_HS200) {
2296 host->tuning_done = 1;
2297 wake_up(&host->buf_ready_int);
2298 return;
2299 }
2300 }
2301
2302 if (!host->data) {
2303 /*
2304 * The "data complete" interrupt is also used to
2305 * indicate that a busy state has ended. See comment
2306 * above in sdhci_cmd_irq().
2307 */
2308 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2309 if (intmask & SDHCI_INT_DATA_END) {
2310 sdhci_finish_command(host);
2311 return;
2312 }
2313 }
2314
2315 pr_err("%s: Got data interrupt 0x%08x even "
2316 "though no data operation was in progress.\n",
2317 mmc_hostname(host->mmc), (unsigned)intmask);
2318 sdhci_dumpregs(host);
2319
2320 return;
2321 }
2322
2323 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2324 host->data->error = -ETIMEDOUT;
2325 else if (intmask & SDHCI_INT_DATA_END_BIT)
2326 host->data->error = -EILSEQ;
2327 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2328 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2329 != MMC_BUS_TEST_R)
2330 host->data->error = -EILSEQ;
2331 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2332 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2333 sdhci_show_adma_error(host);
2334 host->data->error = -EIO;
2335 if (host->ops->adma_workaround)
2336 host->ops->adma_workaround(host, intmask);
2337 }
2338
2339 if (host->data->error)
2340 sdhci_finish_data(host);
2341 else {
2342 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2343 sdhci_transfer_pio(host);
2344
2345 /*
2346 * We currently don't do anything fancy with DMA
2347 * boundaries, but as we can't disable the feature
2348 * we need to at least restart the transfer.
2349 *
2350 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2351 * should return a valid address to continue from, but as
2352 * some controllers are faulty, don't trust them.
2353 */
2354 if (intmask & SDHCI_INT_DMA_END) {
2355 u32 dmastart, dmanow;
2356 dmastart = sg_dma_address(host->data->sg);
2357 dmanow = dmastart + host->data->bytes_xfered;
2358 /*
2359 * Force update to the next DMA block boundary.
2360 */
2361 dmanow = (dmanow &
2362 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2363 SDHCI_DEFAULT_BOUNDARY_SIZE;
2364 host->data->bytes_xfered = dmanow - dmastart;
2365 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2366 " next 0x%08x\n",
2367 mmc_hostname(host->mmc), dmastart,
2368 host->data->bytes_xfered, dmanow);
2369 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2370 }
2371
2372 if (intmask & SDHCI_INT_DATA_END) {
2373 if (host->cmd) {
2374 /*
2375 * Data managed to finish before the
2376 * command completed. Make sure we do
2377 * things in the proper order.
2378 */
2379 host->data_early = 1;
2380 } else {
2381 sdhci_finish_data(host);
2382 }
2383 }
2384 }
2385 }
2386
2387 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2388 {
2389 irqreturn_t result;
2390 struct sdhci_host *host = dev_id;
2391 u32 intmask, unexpected = 0;
2392 int cardint = 0, max_loops = 16;
2393
2394 spin_lock(&host->lock);
2395
2396 if (host->runtime_suspended) {
2397 spin_unlock(&host->lock);
2398 pr_warning("%s: got irq while runtime suspended\n",
2399 mmc_hostname(host->mmc));
2400 return IRQ_HANDLED;
2401 }
2402
2403 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2404
2405 if (!intmask || intmask == 0xffffffff) {
2406 result = IRQ_NONE;
2407 goto out;
2408 }
2409
2410 again:
2411 DBG("*** %s got interrupt: 0x%08x\n",
2412 mmc_hostname(host->mmc), intmask);
2413
2414 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2415 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2416 SDHCI_CARD_PRESENT;
2417
2418 /*
2419 * There is a observation on i.mx esdhc. INSERT bit will be
2420 * immediately set again when it gets cleared, if a card is
2421 * inserted. We have to mask the irq to prevent interrupt
2422 * storm which will freeze the system. And the REMOVE gets
2423 * the same situation.
2424 *
2425 * More testing are needed here to ensure it works for other
2426 * platforms though.
2427 */
2428 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2429 SDHCI_INT_CARD_REMOVE);
2430 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2431 SDHCI_INT_CARD_INSERT);
2432
2433 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2434 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2435 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2436 tasklet_schedule(&host->card_tasklet);
2437 }
2438
2439 if (intmask & SDHCI_INT_CMD_MASK) {
2440 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2441 SDHCI_INT_STATUS);
2442 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2443 }
2444
2445 if (intmask & SDHCI_INT_DATA_MASK) {
2446 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2447 SDHCI_INT_STATUS);
2448 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2449 }
2450
2451 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2452
2453 intmask &= ~SDHCI_INT_ERROR;
2454
2455 if (intmask & SDHCI_INT_BUS_POWER) {
2456 pr_err("%s: Card is consuming too much power!\n",
2457 mmc_hostname(host->mmc));
2458 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2459 }
2460
2461 intmask &= ~SDHCI_INT_BUS_POWER;
2462
2463 if (intmask & SDHCI_INT_CARD_INT)
2464 cardint = 1;
2465
2466 intmask &= ~SDHCI_INT_CARD_INT;
2467
2468 if (intmask) {
2469 unexpected |= intmask;
2470 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2471 }
2472
2473 result = IRQ_HANDLED;
2474
2475 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2476 if (intmask && --max_loops)
2477 goto again;
2478 out:
2479 spin_unlock(&host->lock);
2480
2481 if (unexpected) {
2482 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2483 mmc_hostname(host->mmc), unexpected);
2484 sdhci_dumpregs(host);
2485 }
2486 /*
2487 * We have to delay this as it calls back into the driver.
2488 */
2489 if (cardint)
2490 mmc_signal_sdio_irq(host->mmc);
2491
2492 return result;
2493 }
2494
2495 /*****************************************************************************\
2496 * *
2497 * Suspend/resume *
2498 * *
2499 \*****************************************************************************/
2500
2501 #ifdef CONFIG_PM
2502 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2503 {
2504 u8 val;
2505 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2506 | SDHCI_WAKE_ON_INT;
2507
2508 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2509 val |= mask ;
2510 /* Avoid fake wake up */
2511 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2512 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2513 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2514 }
2515 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2516
2517 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2518 {
2519 u8 val;
2520 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2521 | SDHCI_WAKE_ON_INT;
2522
2523 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2524 val &= ~mask;
2525 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2526 }
2527 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2528
2529 int sdhci_suspend_host(struct sdhci_host *host)
2530 {
2531 int ret;
2532
2533 if (host->ops->platform_suspend)
2534 host->ops->platform_suspend(host);
2535
2536 sdhci_disable_card_detection(host);
2537
2538 /* Disable tuning since we are suspending */
2539 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2540 del_timer_sync(&host->tuning_timer);
2541 host->flags &= ~SDHCI_NEEDS_RETUNING;
2542 }
2543
2544 ret = mmc_suspend_host(host->mmc);
2545 if (ret) {
2546 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2547 host->flags |= SDHCI_NEEDS_RETUNING;
2548 mod_timer(&host->tuning_timer, jiffies +
2549 host->tuning_count * HZ);
2550 }
2551
2552 sdhci_enable_card_detection(host);
2553
2554 return ret;
2555 }
2556
2557 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2558 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2559 free_irq(host->irq, host);
2560 } else {
2561 sdhci_enable_irq_wakeups(host);
2562 enable_irq_wake(host->irq);
2563 }
2564 return ret;
2565 }
2566
2567 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2568
2569 int sdhci_resume_host(struct sdhci_host *host)
2570 {
2571 int ret;
2572
2573 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2574 if (host->ops->enable_dma)
2575 host->ops->enable_dma(host);
2576 }
2577
2578 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2579 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2580 mmc_hostname(host->mmc), host);
2581 if (ret)
2582 return ret;
2583 } else {
2584 sdhci_disable_irq_wakeups(host);
2585 disable_irq_wake(host->irq);
2586 }
2587
2588 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2589 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2590 /* Card keeps power but host controller does not */
2591 sdhci_init(host, 0);
2592 host->pwr = 0;
2593 host->clock = 0;
2594 sdhci_do_set_ios(host, &host->mmc->ios);
2595 } else {
2596 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2597 mmiowb();
2598 }
2599
2600 ret = mmc_resume_host(host->mmc);
2601 sdhci_enable_card_detection(host);
2602
2603 if (host->ops->platform_resume)
2604 host->ops->platform_resume(host);
2605
2606 /* Set the re-tuning expiration flag */
2607 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2608 host->flags |= SDHCI_NEEDS_RETUNING;
2609
2610 return ret;
2611 }
2612
2613 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2614 #endif /* CONFIG_PM */
2615
2616 #ifdef CONFIG_PM_RUNTIME
2617
2618 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2619 {
2620 return pm_runtime_get_sync(host->mmc->parent);
2621 }
2622
2623 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2624 {
2625 pm_runtime_mark_last_busy(host->mmc->parent);
2626 return pm_runtime_put_autosuspend(host->mmc->parent);
2627 }
2628
2629 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2630 {
2631 unsigned long flags;
2632 int ret = 0;
2633
2634 /* Disable tuning since we are suspending */
2635 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2636 del_timer_sync(&host->tuning_timer);
2637 host->flags &= ~SDHCI_NEEDS_RETUNING;
2638 }
2639
2640 spin_lock_irqsave(&host->lock, flags);
2641 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2642 spin_unlock_irqrestore(&host->lock, flags);
2643
2644 synchronize_irq(host->irq);
2645
2646 spin_lock_irqsave(&host->lock, flags);
2647 host->runtime_suspended = true;
2648 spin_unlock_irqrestore(&host->lock, flags);
2649
2650 return ret;
2651 }
2652 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2653
2654 int sdhci_runtime_resume_host(struct sdhci_host *host)
2655 {
2656 unsigned long flags;
2657 int ret = 0, host_flags = host->flags;
2658
2659 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2660 if (host->ops->enable_dma)
2661 host->ops->enable_dma(host);
2662 }
2663
2664 sdhci_init(host, 0);
2665
2666 /* Force clock and power re-program */
2667 host->pwr = 0;
2668 host->clock = 0;
2669 sdhci_do_set_ios(host, &host->mmc->ios);
2670
2671 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2672 if ((host_flags & SDHCI_PV_ENABLED) &&
2673 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2674 spin_lock_irqsave(&host->lock, flags);
2675 sdhci_enable_preset_value(host, true);
2676 spin_unlock_irqrestore(&host->lock, flags);
2677 }
2678
2679 /* Set the re-tuning expiration flag */
2680 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2681 host->flags |= SDHCI_NEEDS_RETUNING;
2682
2683 spin_lock_irqsave(&host->lock, flags);
2684
2685 host->runtime_suspended = false;
2686
2687 /* Enable SDIO IRQ */
2688 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2689 sdhci_enable_sdio_irq_nolock(host, true);
2690
2691 /* Enable Card Detection */
2692 sdhci_enable_card_detection(host);
2693
2694 spin_unlock_irqrestore(&host->lock, flags);
2695
2696 return ret;
2697 }
2698 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2699
2700 #endif
2701
2702 /*****************************************************************************\
2703 * *
2704 * Device allocation/registration *
2705 * *
2706 \*****************************************************************************/
2707
2708 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2709 size_t priv_size)
2710 {
2711 struct mmc_host *mmc;
2712 struct sdhci_host *host;
2713
2714 WARN_ON(dev == NULL);
2715
2716 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2717 if (!mmc)
2718 return ERR_PTR(-ENOMEM);
2719
2720 host = mmc_priv(mmc);
2721 host->mmc = mmc;
2722
2723 return host;
2724 }
2725
2726 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2727
2728 int sdhci_add_host(struct sdhci_host *host)
2729 {
2730 struct mmc_host *mmc;
2731 u32 caps[2] = {0, 0};
2732 u32 max_current_caps;
2733 unsigned int ocr_avail;
2734 int ret;
2735
2736 WARN_ON(host == NULL);
2737 if (host == NULL)
2738 return -EINVAL;
2739
2740 mmc = host->mmc;
2741
2742 if (debug_quirks)
2743 host->quirks = debug_quirks;
2744 if (debug_quirks2)
2745 host->quirks2 = debug_quirks2;
2746
2747 sdhci_reset(host, SDHCI_RESET_ALL);
2748
2749 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2750 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2751 >> SDHCI_SPEC_VER_SHIFT;
2752 if (host->version > SDHCI_SPEC_300) {
2753 pr_err("%s: Unknown controller version (%d). "
2754 "You may experience problems.\n", mmc_hostname(mmc),
2755 host->version);
2756 }
2757
2758 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2759 sdhci_readl(host, SDHCI_CAPABILITIES);
2760
2761 if (host->version >= SDHCI_SPEC_300)
2762 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2763 host->caps1 :
2764 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2765
2766 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2767 host->flags |= SDHCI_USE_SDMA;
2768 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2769 DBG("Controller doesn't have SDMA capability\n");
2770 else
2771 host->flags |= SDHCI_USE_SDMA;
2772
2773 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2774 (host->flags & SDHCI_USE_SDMA)) {
2775 DBG("Disabling DMA as it is marked broken\n");
2776 host->flags &= ~SDHCI_USE_SDMA;
2777 }
2778
2779 if ((host->version >= SDHCI_SPEC_200) &&
2780 (caps[0] & SDHCI_CAN_DO_ADMA2))
2781 host->flags |= SDHCI_USE_ADMA;
2782
2783 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2784 (host->flags & SDHCI_USE_ADMA)) {
2785 DBG("Disabling ADMA as it is marked broken\n");
2786 host->flags &= ~SDHCI_USE_ADMA;
2787 }
2788
2789 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2790 if (host->ops->enable_dma) {
2791 if (host->ops->enable_dma(host)) {
2792 pr_warning("%s: No suitable DMA "
2793 "available. Falling back to PIO.\n",
2794 mmc_hostname(mmc));
2795 host->flags &=
2796 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2797 }
2798 }
2799 }
2800
2801 if (host->flags & SDHCI_USE_ADMA) {
2802 /*
2803 * We need to allocate descriptors for all sg entries
2804 * (128) and potentially one alignment transfer for
2805 * each of those entries.
2806 */
2807 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2808 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2809 if (!host->adma_desc || !host->align_buffer) {
2810 kfree(host->adma_desc);
2811 kfree(host->align_buffer);
2812 pr_warning("%s: Unable to allocate ADMA "
2813 "buffers. Falling back to standard DMA.\n",
2814 mmc_hostname(mmc));
2815 host->flags &= ~SDHCI_USE_ADMA;
2816 }
2817 }
2818
2819 /*
2820 * If we use DMA, then it's up to the caller to set the DMA
2821 * mask, but PIO does not need the hw shim so we set a new
2822 * mask here in that case.
2823 */
2824 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2825 host->dma_mask = DMA_BIT_MASK(64);
2826 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2827 }
2828
2829 if (host->version >= SDHCI_SPEC_300)
2830 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2831 >> SDHCI_CLOCK_BASE_SHIFT;
2832 else
2833 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2834 >> SDHCI_CLOCK_BASE_SHIFT;
2835
2836 host->max_clk *= 1000000;
2837 if (host->max_clk == 0 || host->quirks &
2838 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2839 if (!host->ops->get_max_clock) {
2840 pr_err("%s: Hardware doesn't specify base clock "
2841 "frequency.\n", mmc_hostname(mmc));
2842 return -ENODEV;
2843 }
2844 host->max_clk = host->ops->get_max_clock(host);
2845 }
2846
2847 /*
2848 * In case of Host Controller v3.00, find out whether clock
2849 * multiplier is supported.
2850 */
2851 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2852 SDHCI_CLOCK_MUL_SHIFT;
2853
2854 /*
2855 * In case the value in Clock Multiplier is 0, then programmable
2856 * clock mode is not supported, otherwise the actual clock
2857 * multiplier is one more than the value of Clock Multiplier
2858 * in the Capabilities Register.
2859 */
2860 if (host->clk_mul)
2861 host->clk_mul += 1;
2862
2863 /*
2864 * Set host parameters.
2865 */
2866 mmc->ops = &sdhci_ops;
2867 mmc->f_max = host->max_clk;
2868 if (host->ops->get_min_clock)
2869 mmc->f_min = host->ops->get_min_clock(host);
2870 else if (host->version >= SDHCI_SPEC_300) {
2871 if (host->clk_mul) {
2872 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2873 mmc->f_max = host->max_clk * host->clk_mul;
2874 } else
2875 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2876 } else
2877 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2878
2879 host->timeout_clk =
2880 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2881 if (host->timeout_clk == 0) {
2882 if (host->ops->get_timeout_clock) {
2883 host->timeout_clk = host->ops->get_timeout_clock(host);
2884 } else if (!(host->quirks &
2885 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2886 pr_err("%s: Hardware doesn't specify timeout clock "
2887 "frequency.\n", mmc_hostname(mmc));
2888 return -ENODEV;
2889 }
2890 }
2891 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2892 host->timeout_clk *= 1000;
2893
2894 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2895 host->timeout_clk = mmc->f_max / 1000;
2896
2897 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2898
2899 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2900
2901 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2902 host->flags |= SDHCI_AUTO_CMD12;
2903
2904 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2905 if ((host->version >= SDHCI_SPEC_300) &&
2906 ((host->flags & SDHCI_USE_ADMA) ||
2907 !(host->flags & SDHCI_USE_SDMA))) {
2908 host->flags |= SDHCI_AUTO_CMD23;
2909 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2910 } else {
2911 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2912 }
2913
2914 /*
2915 * A controller may support 8-bit width, but the board itself
2916 * might not have the pins brought out. Boards that support
2917 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2918 * their platform code before calling sdhci_add_host(), and we
2919 * won't assume 8-bit width for hosts without that CAP.
2920 */
2921 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2922 mmc->caps |= MMC_CAP_4_BIT_DATA;
2923
2924 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2925 mmc->caps &= ~MMC_CAP_CMD23;
2926
2927 if (caps[0] & SDHCI_CAN_DO_HISPD)
2928 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2929
2930 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2931 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2932 mmc->caps |= MMC_CAP_NEEDS_POLL;
2933
2934 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2935 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2936 if (IS_ERR_OR_NULL(host->vqmmc)) {
2937 if (PTR_ERR(host->vqmmc) < 0) {
2938 pr_info("%s: no vqmmc regulator found\n",
2939 mmc_hostname(mmc));
2940 host->vqmmc = NULL;
2941 }
2942 } else {
2943 ret = regulator_enable(host->vqmmc);
2944 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2945 1950000))
2946 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2947 SDHCI_SUPPORT_SDR50 |
2948 SDHCI_SUPPORT_DDR50);
2949 if (ret) {
2950 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2951 mmc_hostname(mmc), ret);
2952 host->vqmmc = NULL;
2953 }
2954 }
2955
2956 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2957 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2958 SDHCI_SUPPORT_DDR50);
2959
2960 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2961 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2962 SDHCI_SUPPORT_DDR50))
2963 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2964
2965 /* SDR104 supports also implies SDR50 support */
2966 if (caps[1] & SDHCI_SUPPORT_SDR104)
2967 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2968 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2969 mmc->caps |= MMC_CAP_UHS_SDR50;
2970
2971 if (caps[1] & SDHCI_SUPPORT_DDR50)
2972 mmc->caps |= MMC_CAP_UHS_DDR50;
2973
2974 /* Does the host need tuning for SDR50? */
2975 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2976 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2977
2978 /* Does the host need tuning for HS200? */
2979 if (mmc->caps2 & MMC_CAP2_HS200)
2980 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2981
2982 /* Driver Type(s) (A, C, D) supported by the host */
2983 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2984 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2985 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2986 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2987 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2988 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2989
2990 /* Initial value for re-tuning timer count */
2991 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2992 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2993
2994 /*
2995 * In case Re-tuning Timer is not disabled, the actual value of
2996 * re-tuning timer will be 2 ^ (n - 1).
2997 */
2998 if (host->tuning_count)
2999 host->tuning_count = 1 << (host->tuning_count - 1);
3000
3001 /* Re-tuning mode supported by the Host Controller */
3002 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3003 SDHCI_RETUNING_MODE_SHIFT;
3004
3005 ocr_avail = 0;
3006
3007 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3008 if (IS_ERR_OR_NULL(host->vmmc)) {
3009 if (PTR_ERR(host->vmmc) < 0) {
3010 pr_info("%s: no vmmc regulator found\n",
3011 mmc_hostname(mmc));
3012 host->vmmc = NULL;
3013 }
3014 }
3015
3016 #ifdef CONFIG_REGULATOR
3017 /*
3018 * Voltage range check makes sense only if regulator reports
3019 * any voltage value.
3020 */
3021 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3022 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3023 3600000);
3024 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3025 caps[0] &= ~SDHCI_CAN_VDD_330;
3026 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3027 caps[0] &= ~SDHCI_CAN_VDD_300;
3028 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3029 1950000);
3030 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3031 caps[0] &= ~SDHCI_CAN_VDD_180;
3032 }
3033 #endif /* CONFIG_REGULATOR */
3034
3035 /*
3036 * According to SD Host Controller spec v3.00, if the Host System
3037 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3038 * the value is meaningful only if Voltage Support in the Capabilities
3039 * register is set. The actual current value is 4 times the register
3040 * value.
3041 */
3042 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3043 if (!max_current_caps && host->vmmc) {
3044 u32 curr = regulator_get_current_limit(host->vmmc);
3045 if (curr > 0) {
3046
3047 /* convert to SDHCI_MAX_CURRENT format */
3048 curr = curr/1000; /* convert to mA */
3049 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3050
3051 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3052 max_current_caps =
3053 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3054 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3055 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3056 }
3057 }
3058
3059 if (caps[0] & SDHCI_CAN_VDD_330) {
3060 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3061
3062 mmc->max_current_330 = ((max_current_caps &
3063 SDHCI_MAX_CURRENT_330_MASK) >>
3064 SDHCI_MAX_CURRENT_330_SHIFT) *
3065 SDHCI_MAX_CURRENT_MULTIPLIER;
3066 }
3067 if (caps[0] & SDHCI_CAN_VDD_300) {
3068 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3069
3070 mmc->max_current_300 = ((max_current_caps &
3071 SDHCI_MAX_CURRENT_300_MASK) >>
3072 SDHCI_MAX_CURRENT_300_SHIFT) *
3073 SDHCI_MAX_CURRENT_MULTIPLIER;
3074 }
3075 if (caps[0] & SDHCI_CAN_VDD_180) {
3076 ocr_avail |= MMC_VDD_165_195;
3077
3078 mmc->max_current_180 = ((max_current_caps &
3079 SDHCI_MAX_CURRENT_180_MASK) >>
3080 SDHCI_MAX_CURRENT_180_SHIFT) *
3081 SDHCI_MAX_CURRENT_MULTIPLIER;
3082 }
3083
3084 mmc->ocr_avail = ocr_avail;
3085 mmc->ocr_avail_sdio = ocr_avail;
3086 if (host->ocr_avail_sdio)
3087 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3088 mmc->ocr_avail_sd = ocr_avail;
3089 if (host->ocr_avail_sd)
3090 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3091 else /* normal SD controllers don't support 1.8V */
3092 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3093 mmc->ocr_avail_mmc = ocr_avail;
3094 if (host->ocr_avail_mmc)
3095 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3096
3097 if (mmc->ocr_avail == 0) {
3098 pr_err("%s: Hardware doesn't report any "
3099 "support voltages.\n", mmc_hostname(mmc));
3100 return -ENODEV;
3101 }
3102
3103 spin_lock_init(&host->lock);
3104
3105 /*
3106 * Maximum number of segments. Depends on if the hardware
3107 * can do scatter/gather or not.
3108 */
3109 if (host->flags & SDHCI_USE_ADMA)
3110 mmc->max_segs = 128;
3111 else if (host->flags & SDHCI_USE_SDMA)
3112 mmc->max_segs = 1;
3113 else /* PIO */
3114 mmc->max_segs = 128;
3115
3116 /*
3117 * Maximum number of sectors in one transfer. Limited by DMA boundary
3118 * size (512KiB).
3119 */
3120 mmc->max_req_size = 524288;
3121
3122 /*
3123 * Maximum segment size. Could be one segment with the maximum number
3124 * of bytes. When doing hardware scatter/gather, each entry cannot
3125 * be larger than 64 KiB though.
3126 */
3127 if (host->flags & SDHCI_USE_ADMA) {
3128 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3129 mmc->max_seg_size = 65535;
3130 else
3131 mmc->max_seg_size = 65536;
3132 } else {
3133 mmc->max_seg_size = mmc->max_req_size;
3134 }
3135
3136 /*
3137 * Maximum block size. This varies from controller to controller and
3138 * is specified in the capabilities register.
3139 */
3140 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3141 mmc->max_blk_size = 2;
3142 } else {
3143 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3144 SDHCI_MAX_BLOCK_SHIFT;
3145 if (mmc->max_blk_size >= 3) {
3146 pr_warning("%s: Invalid maximum block size, "
3147 "assuming 512 bytes\n", mmc_hostname(mmc));
3148 mmc->max_blk_size = 0;
3149 }
3150 }
3151
3152 mmc->max_blk_size = 512 << mmc->max_blk_size;
3153
3154 /*
3155 * Maximum block count.
3156 */
3157 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3158
3159 /*
3160 * Init tasklets.
3161 */
3162 tasklet_init(&host->card_tasklet,
3163 sdhci_tasklet_card, (unsigned long)host);
3164 tasklet_init(&host->finish_tasklet,
3165 sdhci_tasklet_finish, (unsigned long)host);
3166
3167 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3168
3169 if (host->version >= SDHCI_SPEC_300) {
3170 init_waitqueue_head(&host->buf_ready_int);
3171
3172 /* Initialize re-tuning timer */
3173 init_timer(&host->tuning_timer);
3174 host->tuning_timer.data = (unsigned long)host;
3175 host->tuning_timer.function = sdhci_tuning_timer;
3176 }
3177
3178 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3179 mmc_hostname(mmc), host);
3180 if (ret) {
3181 pr_err("%s: Failed to request IRQ %d: %d\n",
3182 mmc_hostname(mmc), host->irq, ret);
3183 goto untasklet;
3184 }
3185
3186 sdhci_init(host, 0);
3187
3188 #ifdef CONFIG_MMC_DEBUG
3189 sdhci_dumpregs(host);
3190 #endif
3191
3192 #ifdef SDHCI_USE_LEDS_CLASS
3193 snprintf(host->led_name, sizeof(host->led_name),
3194 "%s::", mmc_hostname(mmc));
3195 host->led.name = host->led_name;
3196 host->led.brightness = LED_OFF;
3197 host->led.default_trigger = mmc_hostname(mmc);
3198 host->led.brightness_set = sdhci_led_control;
3199
3200 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3201 if (ret) {
3202 pr_err("%s: Failed to register LED device: %d\n",
3203 mmc_hostname(mmc), ret);
3204 goto reset;
3205 }
3206 #endif
3207
3208 mmiowb();
3209
3210 mmc_add_host(mmc);
3211
3212 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3213 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3214 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3215 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3216
3217 sdhci_enable_card_detection(host);
3218
3219 return 0;
3220
3221 #ifdef SDHCI_USE_LEDS_CLASS
3222 reset:
3223 sdhci_reset(host, SDHCI_RESET_ALL);
3224 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3225 free_irq(host->irq, host);
3226 #endif
3227 untasklet:
3228 tasklet_kill(&host->card_tasklet);
3229 tasklet_kill(&host->finish_tasklet);
3230
3231 return ret;
3232 }
3233
3234 EXPORT_SYMBOL_GPL(sdhci_add_host);
3235
3236 void sdhci_remove_host(struct sdhci_host *host, int dead)
3237 {
3238 unsigned long flags;
3239
3240 if (dead) {
3241 spin_lock_irqsave(&host->lock, flags);
3242
3243 host->flags |= SDHCI_DEVICE_DEAD;
3244
3245 if (host->mrq) {
3246 pr_err("%s: Controller removed during "
3247 " transfer!\n", mmc_hostname(host->mmc));
3248
3249 host->mrq->cmd->error = -ENOMEDIUM;
3250 tasklet_schedule(&host->finish_tasklet);
3251 }
3252
3253 spin_unlock_irqrestore(&host->lock, flags);
3254 }
3255
3256 sdhci_disable_card_detection(host);
3257
3258 mmc_remove_host(host->mmc);
3259
3260 #ifdef SDHCI_USE_LEDS_CLASS
3261 led_classdev_unregister(&host->led);
3262 #endif
3263
3264 if (!dead)
3265 sdhci_reset(host, SDHCI_RESET_ALL);
3266
3267 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3268 free_irq(host->irq, host);
3269
3270 del_timer_sync(&host->timer);
3271
3272 tasklet_kill(&host->card_tasklet);
3273 tasklet_kill(&host->finish_tasklet);
3274
3275 if (host->vmmc) {
3276 regulator_disable(host->vmmc);
3277 regulator_put(host->vmmc);
3278 }
3279
3280 if (host->vqmmc) {
3281 regulator_disable(host->vqmmc);
3282 regulator_put(host->vqmmc);
3283 }
3284
3285 kfree(host->adma_desc);
3286 kfree(host->align_buffer);
3287
3288 host->adma_desc = NULL;
3289 host->align_buffer = NULL;
3290 }
3291
3292 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3293
3294 void sdhci_free_host(struct sdhci_host *host)
3295 {
3296 mmc_free_host(host->mmc);
3297 }
3298
3299 EXPORT_SYMBOL_GPL(sdhci_free_host);
3300
3301 /*****************************************************************************\
3302 * *
3303 * Driver init/exit *
3304 * *
3305 \*****************************************************************************/
3306
3307 static int __init sdhci_drv_init(void)
3308 {
3309 pr_info(DRIVER_NAME
3310 ": Secure Digital Host Controller Interface driver\n");
3311 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3312
3313 return 0;
3314 }
3315
3316 static void __exit sdhci_drv_exit(void)
3317 {
3318 }
3319
3320 module_init(sdhci_drv_init);
3321 module_exit(sdhci_drv_exit);
3322
3323 module_param(debug_quirks, uint, 0444);
3324 module_param(debug_quirks2, uint, 0444);
3325
3326 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3327 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3328 MODULE_LICENSE("GPL");
3329
3330 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3331 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
kernel source for telekom puls (alcatel/mediatek)