projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:


16d7f939a747a9e636c159f2c7f81c9491edadaf
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
32
33 #include "sdhci.h"
34
35 #define DRIVER_NAME "sdhci"
36
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
43 #endif
44
45 #define MAX_TUNING_LOOP 40
46
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
49
50 static void sdhci_finish_data(struct sdhci_host *);
51
52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_tuning_timer(unsigned long data);
56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57
58 #ifdef CONFIG_PM_RUNTIME
59 static int sdhci_runtime_pm_get(struct sdhci_host *host);
60 static int sdhci_runtime_pm_put(struct sdhci_host *host);
61 #else
62 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
63 {
64 return 0;
65 }
66 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
67 {
68 return 0;
69 }
70 #endif
71
72 static void sdhci_dumpregs(struct sdhci_host *host)
73 {
74 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
75 mmc_hostname(host->mmc));
76
77 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
78 sdhci_readl(host, SDHCI_DMA_ADDRESS),
79 sdhci_readw(host, SDHCI_HOST_VERSION));
80 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
81 sdhci_readw(host, SDHCI_BLOCK_SIZE),
82 sdhci_readw(host, SDHCI_BLOCK_COUNT));
83 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
84 sdhci_readl(host, SDHCI_ARGUMENT),
85 sdhci_readw(host, SDHCI_TRANSFER_MODE));
86 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
87 sdhci_readl(host, SDHCI_PRESENT_STATE),
88 sdhci_readb(host, SDHCI_HOST_CONTROL));
89 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
90 sdhci_readb(host, SDHCI_POWER_CONTROL),
91 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
92 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
93 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
94 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
95 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
96 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
97 sdhci_readl(host, SDHCI_INT_STATUS));
98 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
99 sdhci_readl(host, SDHCI_INT_ENABLE),
100 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
101 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
102 sdhci_readw(host, SDHCI_ACMD12_ERR),
103 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
104 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
105 sdhci_readl(host, SDHCI_CAPABILITIES),
106 sdhci_readl(host, SDHCI_CAPABILITIES_1));
107 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
108 sdhci_readw(host, SDHCI_COMMAND),
109 sdhci_readl(host, SDHCI_MAX_CURRENT));
110 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
111 sdhci_readw(host, SDHCI_HOST_CONTROL2));
112
113 if (host->flags & SDHCI_USE_ADMA)
114 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
115 readl(host->ioaddr + SDHCI_ADMA_ERROR),
116 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
117
118 pr_debug(DRIVER_NAME ": ===========================================\n");
119 }
120
121 /*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125 \*****************************************************************************/
126
127 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
128 {
129 u32 ier;
130
131 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
132 ier &= ~clear;
133 ier |= set;
134 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
135 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
136 }
137
138 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
139 {
140 sdhci_clear_set_irqs(host, 0, irqs);
141 }
142
143 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
144 {
145 sdhci_clear_set_irqs(host, irqs, 0);
146 }
147
148 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
149 {
150 u32 present, irqs;
151
152 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
153 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
154 return;
155
156 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
157 SDHCI_CARD_PRESENT;
158 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
159
160 if (enable)
161 sdhci_unmask_irqs(host, irqs);
162 else
163 sdhci_mask_irqs(host, irqs);
164 }
165
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 {
168 sdhci_set_card_detection(host, true);
169 }
170
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 {
173 sdhci_set_card_detection(host, false);
174 }
175
176 static void sdhci_reset(struct sdhci_host *host, u8 mask)
177 {
178 unsigned long timeout;
179 u32 uninitialized_var(ier);
180
181 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
182 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
183 SDHCI_CARD_PRESENT))
184 return;
185 }
186
187 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
188 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
189
190 if (host->ops->platform_reset_enter)
191 host->ops->platform_reset_enter(host, mask);
192
193 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
194
195 if (mask & SDHCI_RESET_ALL)
196 host->clock = 0;
197
198 /* Wait max 100 ms */
199 timeout = 100;
200
201 /* hw clears the bit when it's done */
202 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
203 if (timeout == 0) {
204 pr_err("%s: Reset 0x%x never completed.\n",
205 mmc_hostname(host->mmc), (int)mask);
206 sdhci_dumpregs(host);
207 return;
208 }
209 timeout--;
210 mdelay(1);
211 }
212
213 if (host->ops->platform_reset_exit)
214 host->ops->platform_reset_exit(host, mask);
215
216 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
217 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
218
219 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
221 host->ops->enable_dma(host);
222 }
223 }
224
225 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
226
227 static void sdhci_init(struct sdhci_host *host, int soft)
228 {
229 if (soft)
230 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
231 else
232 sdhci_reset(host, SDHCI_RESET_ALL);
233
234 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
235 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
237 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
238 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
243 sdhci_set_ios(host->mmc, &host->mmc->ios);
244 }
245 }
246
247 static void sdhci_reinit(struct sdhci_host *host)
248 {
249 sdhci_init(host, 0);
250 /*
251 * Retuning stuffs are affected by different cards inserted and only
252 * applicable to UHS-I cards. So reset these fields to their initial
253 * value when card is removed.
254 */
255 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
256 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
257
258 del_timer_sync(&host->tuning_timer);
259 host->flags &= ~SDHCI_NEEDS_RETUNING;
260 host->mmc->max_blk_count =
261 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
262 }
263 sdhci_enable_card_detection(host);
264 }
265
266 static void sdhci_activate_led(struct sdhci_host *host)
267 {
268 u8 ctrl;
269
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl |= SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 }
274
275 static void sdhci_deactivate_led(struct sdhci_host *host)
276 {
277 u8 ctrl;
278
279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
280 ctrl &= ~SDHCI_CTRL_LED;
281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
282 }
283
284 #ifdef SDHCI_USE_LEDS_CLASS
285 static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
287 {
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 unsigned long flags;
290
291 spin_lock_irqsave(&host->lock, flags);
292
293 if (host->runtime_suspended)
294 goto out;
295
296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
298 else
299 sdhci_activate_led(host);
300 out:
301 spin_unlock_irqrestore(&host->lock, flags);
302 }
303 #endif
304
305 /*****************************************************************************\
306 * *
307 * Core functions *
308 * *
309 \*****************************************************************************/
310
311 static void sdhci_read_block_pio(struct sdhci_host *host)
312 {
313 unsigned long flags;
314 size_t blksize, len, chunk;
315 u32 uninitialized_var(scratch);
316 u8 *buf;
317
318 DBG("PIO reading\n");
319
320 blksize = host->data->blksz;
321 chunk = 0;
322
323 local_irq_save(flags);
324
325 while (blksize) {
326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
328
329 len = min(host->sg_miter.length, blksize);
330
331 blksize -= len;
332 host->sg_miter.consumed = len;
333
334 buf = host->sg_miter.addr;
335
336 while (len) {
337 if (chunk == 0) {
338 scratch = sdhci_readl(host, SDHCI_BUFFER);
339 chunk = 4;
340 }
341
342 *buf = scratch & 0xFF;
343
344 buf++;
345 scratch >>= 8;
346 chunk--;
347 len--;
348 }
349 }
350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
354 }
355
356 static void sdhci_write_block_pio(struct sdhci_host *host)
357 {
358 unsigned long flags;
359 size_t blksize, len, chunk;
360 u32 scratch;
361 u8 *buf;
362
363 DBG("PIO writing\n");
364
365 blksize = host->data->blksz;
366 chunk = 0;
367 scratch = 0;
368
369 local_irq_save(flags);
370
371 while (blksize) {
372 if (!sg_miter_next(&host->sg_miter))
373 BUG();
374
375 len = min(host->sg_miter.length, blksize);
376
377 blksize -= len;
378 host->sg_miter.consumed = len;
379
380 buf = host->sg_miter.addr;
381
382 while (len) {
383 scratch |= (u32)*buf << (chunk * 8);
384
385 buf++;
386 chunk++;
387 len--;
388
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
390 sdhci_writel(host, scratch, SDHCI_BUFFER);
391 chunk = 0;
392 scratch = 0;
393 }
394 }
395 }
396
397 sg_miter_stop(&host->sg_miter);
398
399 local_irq_restore(flags);
400 }
401
402 static void sdhci_transfer_pio(struct sdhci_host *host)
403 {
404 u32 mask;
405
406 BUG_ON(!host->data);
407
408 if (host->blocks == 0)
409 return;
410
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
413 else
414 mask = SDHCI_SPACE_AVAILABLE;
415
416 /*
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
420 */
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
423 mask = ~0;
424
425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 udelay(100);
428
429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
431 else
432 sdhci_write_block_pio(host);
433
434 host->blocks--;
435 if (host->blocks == 0)
436 break;
437 }
438
439 DBG("PIO transfer complete.\n");
440 }
441
442 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443 {
444 local_irq_save(*flags);
445 return kmap_atomic(sg_page(sg)) + sg->offset;
446 }
447
448 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449 {
450 kunmap_atomic(buffer);
451 local_irq_restore(*flags);
452 }
453
454 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
455 {
456 __le32 *dataddr = (__le32 __force *)(desc + 4);
457 __le16 *cmdlen = (__le16 __force *)desc;
458
459 /* SDHCI specification says ADMA descriptors should be 4 byte
460 * aligned, so using 16 or 32bit operations should be safe. */
461
462 cmdlen[0] = cpu_to_le16(cmd);
463 cmdlen[1] = cpu_to_le16(len);
464
465 dataddr[0] = cpu_to_le32(addr);
466 }
467
468 static int sdhci_adma_table_pre(struct sdhci_host *host,
469 struct mmc_data *data)
470 {
471 int direction;
472
473 u8 *desc;
474 u8 *align;
475 dma_addr_t addr;
476 dma_addr_t align_addr;
477 int len, offset;
478
479 struct scatterlist *sg;
480 int i;
481 char *buffer;
482 unsigned long flags;
483
484 /*
485 * The spec does not specify endianness of descriptor table.
486 * We currently guess that it is LE.
487 */
488
489 if (data->flags & MMC_DATA_READ)
490 direction = DMA_FROM_DEVICE;
491 else
492 direction = DMA_TO_DEVICE;
493
494 /*
495 * The ADMA descriptor table is mapped further down as we
496 * need to fill it with data first.
497 */
498
499 host->align_addr = dma_map_single(mmc_dev(host->mmc),
500 host->align_buffer, 128 * 4, direction);
501 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
502 goto fail;
503 BUG_ON(host->align_addr & 0x3);
504
505 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
506 data->sg, data->sg_len, direction);
507 if (host->sg_count == 0)
508 goto unmap_align;
509
510 desc = host->adma_desc;
511 align = host->align_buffer;
512
513 align_addr = host->align_addr;
514
515 for_each_sg(data->sg, sg, host->sg_count, i) {
516 addr = sg_dma_address(sg);
517 len = sg_dma_len(sg);
518
519 /*
520 * The SDHCI specification states that ADMA
521 * addresses must be 32-bit aligned. If they
522 * aren't, then we use a bounce buffer for
523 * the (up to three) bytes that screw up the
524 * alignment.
525 */
526 offset = (4 - (addr & 0x3)) & 0x3;
527 if (offset) {
528 if (data->flags & MMC_DATA_WRITE) {
529 buffer = sdhci_kmap_atomic(sg, &flags);
530 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
531 memcpy(align, buffer, offset);
532 sdhci_kunmap_atomic(buffer, &flags);
533 }
534
535 /* tran, valid */
536 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
537
538 BUG_ON(offset > 65536);
539
540 align += 4;
541 align_addr += 4;
542
543 desc += 8;
544
545 addr += offset;
546 len -= offset;
547 }
548
549 BUG_ON(len > 65536);
550
551 /* tran, valid */
552 sdhci_set_adma_desc(desc, addr, len, 0x21);
553 desc += 8;
554
555 /*
556 * If this triggers then we have a calculation bug
557 * somewhere. :/
558 */
559 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
560 }
561
562 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
563 /*
564 * Mark the last descriptor as the terminating descriptor
565 */
566 if (desc != host->adma_desc) {
567 desc -= 8;
568 desc[0] |= 0x2; /* end */
569 }
570 } else {
571 /*
572 * Add a terminating entry.
573 */
574
575 /* nop, end, valid */
576 sdhci_set_adma_desc(desc, 0, 0, 0x3);
577 }
578
579 /*
580 * Resync align buffer as we might have changed it.
581 */
582 if (data->flags & MMC_DATA_WRITE) {
583 dma_sync_single_for_device(mmc_dev(host->mmc),
584 host->align_addr, 128 * 4, direction);
585 }
586
587 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
588 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
589 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
590 goto unmap_entries;
591 BUG_ON(host->adma_addr & 0x3);
592
593 return 0;
594
595 unmap_entries:
596 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
597 data->sg_len, direction);
598 unmap_align:
599 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
600 128 * 4, direction);
601 fail:
602 return -EINVAL;
603 }
604
605 static void sdhci_adma_table_post(struct sdhci_host *host,
606 struct mmc_data *data)
607 {
608 int direction;
609
610 struct scatterlist *sg;
611 int i, size;
612 u8 *align;
613 char *buffer;
614 unsigned long flags;
615
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
618 else
619 direction = DMA_TO_DEVICE;
620
621 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
622 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
623
624 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
625 128 * 4, direction);
626
627 if (data->flags & MMC_DATA_READ) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
629 data->sg_len, direction);
630
631 align = host->align_buffer;
632
633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & 0x3) {
635 size = 4 - (sg_dma_address(sg) & 0x3);
636
637 buffer = sdhci_kmap_atomic(sg, &flags);
638 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
641
642 align += 4;
643 }
644 }
645 }
646
647 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
648 data->sg_len, direction);
649 }
650
651 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
652 {
653 u8 count;
654 struct mmc_data *data = cmd->data;
655 unsigned target_timeout, current_timeout;
656
657 /*
658 * If the host controller provides us with an incorrect timeout
659 * value, just skip the check and use 0xE. The hardware may take
660 * longer to time out, but that's much better than having a too-short
661 * timeout value.
662 */
663 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
664 return 0xE;
665
666 /* Unspecified timeout, assume max */
667 if (!data && !cmd->cmd_timeout_ms)
668 return 0xE;
669
670 /* timeout in us */
671 if (!data)
672 target_timeout = cmd->cmd_timeout_ms * 1000;
673 else {
674 target_timeout = data->timeout_ns / 1000;
675 if (host->clock)
676 target_timeout += data->timeout_clks / host->clock;
677 }
678
679 /*
680 * Figure out needed cycles.
681 * We do this in steps in order to fit inside a 32 bit int.
682 * The first step is the minimum timeout, which will have a
683 * minimum resolution of 6 bits:
684 * (1) 2^13*1000 > 2^22,
685 * (2) host->timeout_clk < 2^16
686 * =>
687 * (1) / (2) > 2^6
688 */
689 count = 0;
690 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
691 while (current_timeout < target_timeout) {
692 count++;
693 current_timeout <<= 1;
694 if (count >= 0xF)
695 break;
696 }
697
698 if (count >= 0xF) {
699 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
700 mmc_hostname(host->mmc), count, cmd->opcode);
701 count = 0xE;
702 }
703
704 return count;
705 }
706
707 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708 {
709 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
710 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711
712 if (host->flags & SDHCI_REQ_USE_DMA)
713 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
714 else
715 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
716 }
717
718 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
719 {
720 u8 count;
721 u8 ctrl;
722 struct mmc_data *data = cmd->data;
723 int ret;
724
725 WARN_ON(host->data);
726
727 if (data || (cmd->flags & MMC_RSP_BUSY)) {
728 count = sdhci_calc_timeout(host, cmd);
729 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
730 }
731
732 if (!data)
733 return;
734
735 /* Sanity checks */
736 BUG_ON(data->blksz * data->blocks > 524288);
737 BUG_ON(data->blksz > host->mmc->max_blk_size);
738 BUG_ON(data->blocks > 65535);
739
740 host->data = data;
741 host->data_early = 0;
742 host->data->bytes_xfered = 0;
743
744 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
745 host->flags |= SDHCI_REQ_USE_DMA;
746
747 /*
748 * FIXME: This doesn't account for merging when mapping the
749 * scatterlist.
750 */
751 if (host->flags & SDHCI_REQ_USE_DMA) {
752 int broken, i;
753 struct scatterlist *sg;
754
755 broken = 0;
756 if (host->flags & SDHCI_USE_ADMA) {
757 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
758 broken = 1;
759 } else {
760 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
761 broken = 1;
762 }
763
764 if (unlikely(broken)) {
765 for_each_sg(data->sg, sg, data->sg_len, i) {
766 if (sg->length & 0x3) {
767 DBG("Reverting to PIO because of "
768 "transfer size (%d)\n",
769 sg->length);
770 host->flags &= ~SDHCI_REQ_USE_DMA;
771 break;
772 }
773 }
774 }
775 }
776
777 /*
778 * The assumption here being that alignment is the same after
779 * translation to device address space.
780 */
781 if (host->flags & SDHCI_REQ_USE_DMA) {
782 int broken, i;
783 struct scatterlist *sg;
784
785 broken = 0;
786 if (host->flags & SDHCI_USE_ADMA) {
787 /*
788 * As we use 3 byte chunks to work around
789 * alignment problems, we need to check this
790 * quirk.
791 */
792 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
793 broken = 1;
794 } else {
795 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
796 broken = 1;
797 }
798
799 if (unlikely(broken)) {
800 for_each_sg(data->sg, sg, data->sg_len, i) {
801 if (sg->offset & 0x3) {
802 DBG("Reverting to PIO because of "
803 "bad alignment\n");
804 host->flags &= ~SDHCI_REQ_USE_DMA;
805 break;
806 }
807 }
808 }
809 }
810
811 if (host->flags & SDHCI_REQ_USE_DMA) {
812 if (host->flags & SDHCI_USE_ADMA) {
813 ret = sdhci_adma_table_pre(host, data);
814 if (ret) {
815 /*
816 * This only happens when someone fed
817 * us an invalid request.
818 */
819 WARN_ON(1);
820 host->flags &= ~SDHCI_REQ_USE_DMA;
821 } else {
822 sdhci_writel(host, host->adma_addr,
823 SDHCI_ADMA_ADDRESS);
824 }
825 } else {
826 int sg_cnt;
827
828 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
829 data->sg, data->sg_len,
830 (data->flags & MMC_DATA_READ) ?
831 DMA_FROM_DEVICE :
832 DMA_TO_DEVICE);
833 if (sg_cnt == 0) {
834 /*
835 * This only happens when someone fed
836 * us an invalid request.
837 */
838 WARN_ON(1);
839 host->flags &= ~SDHCI_REQ_USE_DMA;
840 } else {
841 WARN_ON(sg_cnt != 1);
842 sdhci_writel(host, sg_dma_address(data->sg),
843 SDHCI_DMA_ADDRESS);
844 }
845 }
846 }
847
848 /*
849 * Always adjust the DMA selection as some controllers
850 * (e.g. JMicron) can't do PIO properly when the selection
851 * is ADMA.
852 */
853 if (host->version >= SDHCI_SPEC_200) {
854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
855 ctrl &= ~SDHCI_CTRL_DMA_MASK;
856 if ((host->flags & SDHCI_REQ_USE_DMA) &&
857 (host->flags & SDHCI_USE_ADMA))
858 ctrl |= SDHCI_CTRL_ADMA32;
859 else
860 ctrl |= SDHCI_CTRL_SDMA;
861 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
862 }
863
864 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
865 int flags;
866
867 flags = SG_MITER_ATOMIC;
868 if (host->data->flags & MMC_DATA_READ)
869 flags |= SG_MITER_TO_SG;
870 else
871 flags |= SG_MITER_FROM_SG;
872 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
873 host->blocks = data->blocks;
874 }
875
876 sdhci_set_transfer_irqs(host);
877
878 /* Set the DMA boundary value and block size */
879 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
880 data->blksz), SDHCI_BLOCK_SIZE);
881 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
882 }
883
884 static void sdhci_set_transfer_mode(struct sdhci_host *host,
885 struct mmc_command *cmd)
886 {
887 u16 mode;
888 struct mmc_data *data = cmd->data;
889
890 if (data == NULL)
891 return;
892
893 WARN_ON(!host->data);
894
895 mode = SDHCI_TRNS_BLK_CNT_EN;
896 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
897 mode |= SDHCI_TRNS_MULTI;
898 /*
899 * If we are sending CMD23, CMD12 never gets sent
900 * on successful completion (so no Auto-CMD12).
901 */
902 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
903 mode |= SDHCI_TRNS_AUTO_CMD12;
904 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
905 mode |= SDHCI_TRNS_AUTO_CMD23;
906 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
907 }
908 }
909
910 if (data->flags & MMC_DATA_READ)
911 mode |= SDHCI_TRNS_READ;
912 if (host->flags & SDHCI_REQ_USE_DMA)
913 mode |= SDHCI_TRNS_DMA;
914
915 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
916 }
917
918 static void sdhci_finish_data(struct sdhci_host *host)
919 {
920 struct mmc_data *data;
921
922 BUG_ON(!host->data);
923
924 data = host->data;
925 host->data = NULL;
926
927 if (host->flags & SDHCI_REQ_USE_DMA) {
928 if (host->flags & SDHCI_USE_ADMA)
929 sdhci_adma_table_post(host, data);
930 else {
931 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
932 data->sg_len, (data->flags & MMC_DATA_READ) ?
933 DMA_FROM_DEVICE : DMA_TO_DEVICE);
934 }
935 }
936
937 /*
938 * The specification states that the block count register must
939 * be updated, but it does not specify at what point in the
940 * data flow. That makes the register entirely useless to read
941 * back so we have to assume that nothing made it to the card
942 * in the event of an error.
943 */
944 if (data->error)
945 data->bytes_xfered = 0;
946 else
947 data->bytes_xfered = data->blksz * data->blocks;
948
949 /*
950 * Need to send CMD12 if -
951 * a) open-ended multiblock transfer (no CMD23)
952 * b) error in multiblock transfer
953 */
954 if (data->stop &&
955 (data->error ||
956 !host->mrq->sbc)) {
957
958 /*
959 * The controller needs a reset of internal state machines
960 * upon error conditions.
961 */
962 if (data->error) {
963 sdhci_reset(host, SDHCI_RESET_CMD);
964 sdhci_reset(host, SDHCI_RESET_DATA);
965 }
966
967 sdhci_send_command(host, data->stop);
968 } else
969 tasklet_schedule(&host->finish_tasklet);
970 }
971
972 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
973 {
974 int flags;
975 u32 mask;
976 unsigned long timeout;
977
978 WARN_ON(host->cmd);
979
980 /* Wait max 10 ms */
981 timeout = 10;
982
983 mask = SDHCI_CMD_INHIBIT;
984 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
985 mask |= SDHCI_DATA_INHIBIT;
986
987 /* We shouldn't wait for data inihibit for stop commands, even
988 though they might use busy signaling */
989 if (host->mrq->data && (cmd == host->mrq->data->stop))
990 mask &= ~SDHCI_DATA_INHIBIT;
991
992 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
993 if (timeout == 0) {
994 pr_err("%s: Controller never released "
995 "inhibit bit(s).\n", mmc_hostname(host->mmc));
996 sdhci_dumpregs(host);
997 cmd->error = -EIO;
998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
1001 timeout--;
1002 mdelay(1);
1003 }
1004
1005 mod_timer(&host->timer, jiffies + 10 * HZ);
1006
1007 host->cmd = cmd;
1008
1009 sdhci_prepare_data(host, cmd);
1010
1011 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1012
1013 sdhci_set_transfer_mode(host, cmd);
1014
1015 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1016 pr_err("%s: Unsupported response type!\n",
1017 mmc_hostname(host->mmc));
1018 cmd->error = -EINVAL;
1019 tasklet_schedule(&host->finish_tasklet);
1020 return;
1021 }
1022
1023 if (!(cmd->flags & MMC_RSP_PRESENT))
1024 flags = SDHCI_CMD_RESP_NONE;
1025 else if (cmd->flags & MMC_RSP_136)
1026 flags = SDHCI_CMD_RESP_LONG;
1027 else if (cmd->flags & MMC_RSP_BUSY)
1028 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1029 else
1030 flags = SDHCI_CMD_RESP_SHORT;
1031
1032 if (cmd->flags & MMC_RSP_CRC)
1033 flags |= SDHCI_CMD_CRC;
1034 if (cmd->flags & MMC_RSP_OPCODE)
1035 flags |= SDHCI_CMD_INDEX;
1036
1037 /* CMD19 is special in that the Data Present Select should be set */
1038 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1039 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1040 flags |= SDHCI_CMD_DATA;
1041
1042 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1043 }
1044
1045 static void sdhci_finish_command(struct sdhci_host *host)
1046 {
1047 int i;
1048
1049 BUG_ON(host->cmd == NULL);
1050
1051 if (host->cmd->flags & MMC_RSP_PRESENT) {
1052 if (host->cmd->flags & MMC_RSP_136) {
1053 /* CRC is stripped so we need to do some shifting. */
1054 for (i = 0;i < 4;i++) {
1055 host->cmd->resp[i] = sdhci_readl(host,
1056 SDHCI_RESPONSE + (3-i)*4) << 8;
1057 if (i != 3)
1058 host->cmd->resp[i] |=
1059 sdhci_readb(host,
1060 SDHCI_RESPONSE + (3-i)*4-1);
1061 }
1062 } else {
1063 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1064 }
1065 }
1066
1067 host->cmd->error = 0;
1068
1069 /* Finished CMD23, now send actual command. */
1070 if (host->cmd == host->mrq->sbc) {
1071 host->cmd = NULL;
1072 sdhci_send_command(host, host->mrq->cmd);
1073 } else {
1074
1075 /* Processed actual command. */
1076 if (host->data && host->data_early)
1077 sdhci_finish_data(host);
1078
1079 if (!host->cmd->data)
1080 tasklet_schedule(&host->finish_tasklet);
1081
1082 host->cmd = NULL;
1083 }
1084 }
1085
1086 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1087 {
1088 u16 ctrl, preset = 0;
1089
1090 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1091
1092 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1093 case SDHCI_CTRL_UHS_SDR12:
1094 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1095 break;
1096 case SDHCI_CTRL_UHS_SDR25:
1097 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1098 break;
1099 case SDHCI_CTRL_UHS_SDR50:
1100 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1101 break;
1102 case SDHCI_CTRL_UHS_SDR104:
1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1104 break;
1105 case SDHCI_CTRL_UHS_DDR50:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1107 break;
1108 default:
1109 pr_warn("%s: Invalid UHS-I mode selected\n",
1110 mmc_hostname(host->mmc));
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1112 break;
1113 }
1114 return preset;
1115 }
1116
1117 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1118 {
1119 int div = 0; /* Initialized for compiler warning */
1120 int real_div = div, clk_mul = 1;
1121 u16 clk = 0;
1122 unsigned long timeout;
1123
1124 if (clock && clock == host->clock)
1125 return;
1126
1127 host->mmc->actual_clock = 0;
1128
1129 if (host->ops->set_clock) {
1130 host->ops->set_clock(host, clock);
1131 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1132 return;
1133 }
1134
1135 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1136
1137 if (clock == 0)
1138 goto out;
1139
1140 if (host->version >= SDHCI_SPEC_300) {
1141 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1142 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1143 u16 pre_val;
1144
1145 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1146 pre_val = sdhci_get_preset_value(host);
1147 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1148 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1149 if (host->clk_mul &&
1150 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1151 clk = SDHCI_PROG_CLOCK_MODE;
1152 real_div = div + 1;
1153 clk_mul = host->clk_mul;
1154 } else {
1155 real_div = max_t(int, 1, div << 1);
1156 }
1157 goto clock_set;
1158 }
1159
1160 /*
1161 * Check if the Host Controller supports Programmable Clock
1162 * Mode.
1163 */
1164 if (host->clk_mul) {
1165 for (div = 1; div <= 1024; div++) {
1166 if ((host->max_clk * host->clk_mul / div)
1167 <= clock)
1168 break;
1169 }
1170 /*
1171 * Set Programmable Clock Mode in the Clock
1172 * Control register.
1173 */
1174 clk = SDHCI_PROG_CLOCK_MODE;
1175 real_div = div;
1176 clk_mul = host->clk_mul;
1177 div--;
1178 } else {
1179 /* Version 3.00 divisors must be a multiple of 2. */
1180 if (host->max_clk <= clock)
1181 div = 1;
1182 else {
1183 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1184 div += 2) {
1185 if ((host->max_clk / div) <= clock)
1186 break;
1187 }
1188 }
1189 real_div = div;
1190 div >>= 1;
1191 }
1192 } else {
1193 /* Version 2.00 divisors must be a power of 2. */
1194 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1195 if ((host->max_clk / div) <= clock)
1196 break;
1197 }
1198 real_div = div;
1199 div >>= 1;
1200 }
1201
1202 clock_set:
1203 if (real_div)
1204 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1205
1206 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1207 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1208 << SDHCI_DIVIDER_HI_SHIFT;
1209 clk |= SDHCI_CLOCK_INT_EN;
1210 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1211
1212 /* Wait max 20 ms */
1213 timeout = 20;
1214 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1215 & SDHCI_CLOCK_INT_STABLE)) {
1216 if (timeout == 0) {
1217 pr_err("%s: Internal clock never "
1218 "stabilised.\n", mmc_hostname(host->mmc));
1219 sdhci_dumpregs(host);
1220 return;
1221 }
1222 timeout--;
1223 spin_unlock_irq(&host->lock);
1224 usleep_range(900, 1100);
1225 spin_lock_irq(&host->lock);
1226 }
1227
1228 clk |= SDHCI_CLOCK_CARD_EN;
1229 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1230
1231 out:
1232 host->clock = clock;
1233 }
1234
1235 static inline void sdhci_update_clock(struct sdhci_host *host)
1236 {
1237 unsigned int clock;
1238
1239 clock = host->clock;
1240 host->clock = 0;
1241 sdhci_set_clock(host, clock);
1242 }
1243
1244 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1245 {
1246 u8 pwr = 0;
1247
1248 if (power != (unsigned short)-1) {
1249 switch (1 << power) {
1250 case MMC_VDD_165_195:
1251 pwr = SDHCI_POWER_180;
1252 break;
1253 case MMC_VDD_29_30:
1254 case MMC_VDD_30_31:
1255 pwr = SDHCI_POWER_300;
1256 break;
1257 case MMC_VDD_32_33:
1258 case MMC_VDD_33_34:
1259 pwr = SDHCI_POWER_330;
1260 break;
1261 default:
1262 BUG();
1263 }
1264 }
1265
1266 if (host->pwr == pwr)
1267 return -1;
1268
1269 host->pwr = pwr;
1270
1271 if (pwr == 0) {
1272 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1273 return 0;
1274 }
1275
1276 /*
1277 * Spec says that we should clear the power reg before setting
1278 * a new value. Some controllers don't seem to like this though.
1279 */
1280 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1281 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1282
1283 /*
1284 * At least the Marvell CaFe chip gets confused if we set the voltage
1285 * and set turn on power at the same time, so set the voltage first.
1286 */
1287 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1288 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1289
1290 pwr |= SDHCI_POWER_ON;
1291
1292 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1293
1294 /*
1295 * Some controllers need an extra 10ms delay of 10ms before they
1296 * can apply clock after applying power
1297 */
1298 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1299 mdelay(10);
1300
1301 return power;
1302 }
1303
1304 /*****************************************************************************\
1305 * *
1306 * MMC callbacks *
1307 * *
1308 \*****************************************************************************/
1309
1310 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1311 {
1312 struct sdhci_host *host;
1313 int present;
1314 unsigned long flags;
1315 u32 tuning_opcode;
1316
1317 host = mmc_priv(mmc);
1318
1319 sdhci_runtime_pm_get(host);
1320
1321 present = mmc_gpio_get_cd(host->mmc);
1322
1323 spin_lock_irqsave(&host->lock, flags);
1324
1325 WARN_ON(host->mrq != NULL);
1326
1327 #ifndef SDHCI_USE_LEDS_CLASS
1328 sdhci_activate_led(host);
1329 #endif
1330
1331 /*
1332 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1333 * requests if Auto-CMD12 is enabled.
1334 */
1335 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1336 if (mrq->stop) {
1337 mrq->data->stop = NULL;
1338 mrq->stop = NULL;
1339 }
1340 }
1341
1342 host->mrq = mrq;
1343
1344 /*
1345 * Firstly check card presence from cd-gpio. The return could
1346 * be one of the following possibilities:
1347 * negative: cd-gpio is not available
1348 * zero: cd-gpio is used, and card is removed
1349 * one: cd-gpio is used, and card is present
1350 */
1351 if (present < 0) {
1352 /* If polling, assume that the card is always present. */
1353 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1354 present = 1;
1355 else
1356 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1357 SDHCI_CARD_PRESENT;
1358 }
1359
1360 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1361 host->mrq->cmd->error = -ENOMEDIUM;
1362 tasklet_schedule(&host->finish_tasklet);
1363 } else {
1364 u32 present_state;
1365
1366 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1367 /*
1368 * Check if the re-tuning timer has already expired and there
1369 * is no on-going data transfer. If so, we need to execute
1370 * tuning procedure before sending command.
1371 */
1372 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1373 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1374 if (mmc->card) {
1375 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1376 tuning_opcode =
1377 mmc->card->type == MMC_TYPE_MMC ?
1378 MMC_SEND_TUNING_BLOCK_HS200 :
1379 MMC_SEND_TUNING_BLOCK;
1380 spin_unlock_irqrestore(&host->lock, flags);
1381 sdhci_execute_tuning(mmc, tuning_opcode);
1382 spin_lock_irqsave(&host->lock, flags);
1383
1384 /* Restore original mmc_request structure */
1385 host->mrq = mrq;
1386 }
1387 }
1388
1389 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1390 sdhci_send_command(host, mrq->sbc);
1391 else
1392 sdhci_send_command(host, mrq->cmd);
1393 }
1394
1395 mmiowb();
1396 spin_unlock_irqrestore(&host->lock, flags);
1397 }
1398
1399 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1400 {
1401 unsigned long flags;
1402 int vdd_bit = -1;
1403 u8 ctrl;
1404
1405 spin_lock_irqsave(&host->lock, flags);
1406
1407 if (host->flags & SDHCI_DEVICE_DEAD) {
1408 spin_unlock_irqrestore(&host->lock, flags);
1409 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1410 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1411 return;
1412 }
1413
1414 /*
1415 * Reset the chip on each power off.
1416 * Should clear out any weird states.
1417 */
1418 if (ios->power_mode == MMC_POWER_OFF) {
1419 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1420 sdhci_reinit(host);
1421 }
1422
1423 if (host->version >= SDHCI_SPEC_300 &&
1424 (ios->power_mode == MMC_POWER_UP))
1425 sdhci_enable_preset_value(host, false);
1426
1427 sdhci_set_clock(host, ios->clock);
1428
1429 if (ios->power_mode == MMC_POWER_OFF)
1430 vdd_bit = sdhci_set_power(host, -1);
1431 else
1432 vdd_bit = sdhci_set_power(host, ios->vdd);
1433
1434 if (host->vmmc && vdd_bit != -1) {
1435 spin_unlock_irqrestore(&host->lock, flags);
1436 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1437 spin_lock_irqsave(&host->lock, flags);
1438 }
1439
1440 if (host->ops->platform_send_init_74_clocks)
1441 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1442
1443 /*
1444 * If your platform has 8-bit width support but is not a v3 controller,
1445 * or if it requires special setup code, you should implement that in
1446 * platform_bus_width().
1447 */
1448 if (host->ops->platform_bus_width) {
1449 host->ops->platform_bus_width(host, ios->bus_width);
1450 } else {
1451 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1452 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1453 ctrl &= ~SDHCI_CTRL_4BITBUS;
1454 if (host->version >= SDHCI_SPEC_300)
1455 ctrl |= SDHCI_CTRL_8BITBUS;
1456 } else {
1457 if (host->version >= SDHCI_SPEC_300)
1458 ctrl &= ~SDHCI_CTRL_8BITBUS;
1459 if (ios->bus_width == MMC_BUS_WIDTH_4)
1460 ctrl |= SDHCI_CTRL_4BITBUS;
1461 else
1462 ctrl &= ~SDHCI_CTRL_4BITBUS;
1463 }
1464 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1465 }
1466
1467 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1468
1469 if ((ios->timing == MMC_TIMING_SD_HS ||
1470 ios->timing == MMC_TIMING_MMC_HS)
1471 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1472 ctrl |= SDHCI_CTRL_HISPD;
1473 else
1474 ctrl &= ~SDHCI_CTRL_HISPD;
1475
1476 if (host->version >= SDHCI_SPEC_300) {
1477 u16 clk, ctrl_2;
1478
1479 /* In case of UHS-I modes, set High Speed Enable */
1480 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1481 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1482 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1483 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1484 (ios->timing == MMC_TIMING_UHS_SDR25))
1485 ctrl |= SDHCI_CTRL_HISPD;
1486
1487 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1488 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1489 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1490 /*
1491 * We only need to set Driver Strength if the
1492 * preset value enable is not set.
1493 */
1494 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1495 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1496 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1497 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1498 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1499
1500 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1501 } else {
1502 /*
1503 * According to SDHC Spec v3.00, if the Preset Value
1504 * Enable in the Host Control 2 register is set, we
1505 * need to reset SD Clock Enable before changing High
1506 * Speed Enable to avoid generating clock gliches.
1507 */
1508
1509 /* Reset SD Clock Enable */
1510 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1511 clk &= ~SDHCI_CLOCK_CARD_EN;
1512 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1513
1514 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1515
1516 /* Re-enable SD Clock */
1517 sdhci_update_clock(host);
1518 }
1519
1520
1521 /* Reset SD Clock Enable */
1522 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1523 clk &= ~SDHCI_CLOCK_CARD_EN;
1524 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1525
1526 if (host->ops->set_uhs_signaling)
1527 host->ops->set_uhs_signaling(host, ios->timing);
1528 else {
1529 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1530 /* Select Bus Speed Mode for host */
1531 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1532 if (ios->timing == MMC_TIMING_MMC_HS200)
1533 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1534 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1535 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1536 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1537 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1538 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1539 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1540 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1541 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1542 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1543 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1544 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1545 }
1546
1547 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1548 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1549 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1550 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1551 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1552 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1553 u16 preset;
1554
1555 sdhci_enable_preset_value(host, true);
1556 preset = sdhci_get_preset_value(host);
1557 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1558 >> SDHCI_PRESET_DRV_SHIFT;
1559 }
1560
1561 /* Re-enable SD Clock */
1562 sdhci_update_clock(host);
1563 } else
1564 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1565
1566 /*
1567 * Some (ENE) controllers go apeshit on some ios operation,
1568 * signalling timeout and CRC errors even on CMD0. Resetting
1569 * it on each ios seems to solve the problem.
1570 */
1571 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1572 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1573
1574 mmiowb();
1575 spin_unlock_irqrestore(&host->lock, flags);
1576 }
1577
1578 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1579 {
1580 struct sdhci_host *host = mmc_priv(mmc);
1581
1582 sdhci_runtime_pm_get(host);
1583 sdhci_do_set_ios(host, ios);
1584 sdhci_runtime_pm_put(host);
1585 }
1586
1587 static int sdhci_do_get_cd(struct sdhci_host *host)
1588 {
1589 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1590
1591 if (host->flags & SDHCI_DEVICE_DEAD)
1592 return 0;
1593
1594 /* If polling/nonremovable, assume that the card is always present. */
1595 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1596 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1597 return 1;
1598
1599 /* Try slot gpio detect */
1600 if (!IS_ERR_VALUE(gpio_cd))
1601 return !!gpio_cd;
1602
1603 /* Host native card detect */
1604 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1605 }
1606
1607 static int sdhci_get_cd(struct mmc_host *mmc)
1608 {
1609 struct sdhci_host *host = mmc_priv(mmc);
1610 int ret;
1611
1612 sdhci_runtime_pm_get(host);
1613 ret = sdhci_do_get_cd(host);
1614 sdhci_runtime_pm_put(host);
1615 return ret;
1616 }
1617
1618 static int sdhci_check_ro(struct sdhci_host *host)
1619 {
1620 unsigned long flags;
1621 int is_readonly;
1622
1623 spin_lock_irqsave(&host->lock, flags);
1624
1625 if (host->flags & SDHCI_DEVICE_DEAD)
1626 is_readonly = 0;
1627 else if (host->ops->get_ro)
1628 is_readonly = host->ops->get_ro(host);
1629 else
1630 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1631 & SDHCI_WRITE_PROTECT);
1632
1633 spin_unlock_irqrestore(&host->lock, flags);
1634
1635 /* This quirk needs to be replaced by a callback-function later */
1636 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1637 !is_readonly : is_readonly;
1638 }
1639
1640 #define SAMPLE_COUNT 5
1641
1642 static int sdhci_do_get_ro(struct sdhci_host *host)
1643 {
1644 int i, ro_count;
1645
1646 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1647 return sdhci_check_ro(host);
1648
1649 ro_count = 0;
1650 for (i = 0; i < SAMPLE_COUNT; i++) {
1651 if (sdhci_check_ro(host)) {
1652 if (++ro_count > SAMPLE_COUNT / 2)
1653 return 1;
1654 }
1655 msleep(30);
1656 }
1657 return 0;
1658 }
1659
1660 static void sdhci_hw_reset(struct mmc_host *mmc)
1661 {
1662 struct sdhci_host *host = mmc_priv(mmc);
1663
1664 if (host->ops && host->ops->hw_reset)
1665 host->ops->hw_reset(host);
1666 }
1667
1668 static int sdhci_get_ro(struct mmc_host *mmc)
1669 {
1670 struct sdhci_host *host = mmc_priv(mmc);
1671 int ret;
1672
1673 sdhci_runtime_pm_get(host);
1674 ret = sdhci_do_get_ro(host);
1675 sdhci_runtime_pm_put(host);
1676 return ret;
1677 }
1678
1679 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1680 {
1681 if (host->flags & SDHCI_DEVICE_DEAD)
1682 goto out;
1683
1684 if (enable)
1685 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1686 else
1687 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1688
1689 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1690 if (host->runtime_suspended)
1691 goto out;
1692
1693 if (enable)
1694 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1695 else
1696 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1697 out:
1698 mmiowb();
1699 }
1700
1701 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1702 {
1703 struct sdhci_host *host = mmc_priv(mmc);
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&host->lock, flags);
1707 sdhci_enable_sdio_irq_nolock(host, enable);
1708 spin_unlock_irqrestore(&host->lock, flags);
1709 }
1710
1711 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1712 struct mmc_ios *ios)
1713 {
1714 u16 ctrl;
1715 int ret;
1716
1717 /*
1718 * Signal Voltage Switching is only applicable for Host Controllers
1719 * v3.00 and above.
1720 */
1721 if (host->version < SDHCI_SPEC_300)
1722 return 0;
1723
1724 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1725
1726 switch (ios->signal_voltage) {
1727 case MMC_SIGNAL_VOLTAGE_330:
1728 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1729 ctrl &= ~SDHCI_CTRL_VDD_180;
1730 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1731
1732 if (host->vqmmc) {
1733 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1734 if (ret) {
1735 pr_warning("%s: Switching to 3.3V signalling voltage "
1736 " failed\n", mmc_hostname(host->mmc));
1737 return -EIO;
1738 }
1739 }
1740 /* Wait for 5ms */
1741 usleep_range(5000, 5500);
1742
1743 /* 3.3V regulator output should be stable within 5 ms */
1744 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1745 if (!(ctrl & SDHCI_CTRL_VDD_180))
1746 return 0;
1747
1748 pr_warning("%s: 3.3V regulator output did not became stable\n",
1749 mmc_hostname(host->mmc));
1750
1751 return -EAGAIN;
1752 case MMC_SIGNAL_VOLTAGE_180:
1753 if (host->vqmmc) {
1754 ret = regulator_set_voltage(host->vqmmc,
1755 1700000, 1950000);
1756 if (ret) {
1757 pr_warning("%s: Switching to 1.8V signalling voltage "
1758 " failed\n", mmc_hostname(host->mmc));
1759 return -EIO;
1760 }
1761 }
1762
1763 /*
1764 * Enable 1.8V Signal Enable in the Host Control2
1765 * register
1766 */
1767 ctrl |= SDHCI_CTRL_VDD_180;
1768 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1769
1770 /* Wait for 5ms */
1771 usleep_range(5000, 5500);
1772
1773 /* 1.8V regulator output should be stable within 5 ms */
1774 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1775 if (ctrl & SDHCI_CTRL_VDD_180)
1776 return 0;
1777
1778 pr_warning("%s: 1.8V regulator output did not became stable\n",
1779 mmc_hostname(host->mmc));
1780
1781 return -EAGAIN;
1782 case MMC_SIGNAL_VOLTAGE_120:
1783 if (host->vqmmc) {
1784 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1785 if (ret) {
1786 pr_warning("%s: Switching to 1.2V signalling voltage "
1787 " failed\n", mmc_hostname(host->mmc));
1788 return -EIO;
1789 }
1790 }
1791 return 0;
1792 default:
1793 /* No signal voltage switch required */
1794 return 0;
1795 }
1796 }
1797
1798 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1799 struct mmc_ios *ios)
1800 {
1801 struct sdhci_host *host = mmc_priv(mmc);
1802 int err;
1803
1804 if (host->version < SDHCI_SPEC_300)
1805 return 0;
1806 sdhci_runtime_pm_get(host);
1807 err = sdhci_do_start_signal_voltage_switch(host, ios);
1808 sdhci_runtime_pm_put(host);
1809 return err;
1810 }
1811
1812 static int sdhci_card_busy(struct mmc_host *mmc)
1813 {
1814 struct sdhci_host *host = mmc_priv(mmc);
1815 u32 present_state;
1816
1817 sdhci_runtime_pm_get(host);
1818 /* Check whether DAT[3:0] is 0000 */
1819 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1820 sdhci_runtime_pm_put(host);
1821
1822 return !(present_state & SDHCI_DATA_LVL_MASK);
1823 }
1824
1825 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1826 {
1827 struct sdhci_host *host;
1828 u16 ctrl;
1829 u32 ier;
1830 int tuning_loop_counter = MAX_TUNING_LOOP;
1831 unsigned long timeout;
1832 int err = 0;
1833 bool requires_tuning_nonuhs = false;
1834
1835 host = mmc_priv(mmc);
1836
1837 sdhci_runtime_pm_get(host);
1838 disable_irq(host->irq);
1839 spin_lock(&host->lock);
1840
1841 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1842
1843 /*
1844 * The Host Controller needs tuning only in case of SDR104 mode
1845 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1846 * Capabilities register.
1847 * If the Host Controller supports the HS200 mode then the
1848 * tuning function has to be executed.
1849 */
1850 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1851 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1852 host->flags & SDHCI_HS200_NEEDS_TUNING))
1853 requires_tuning_nonuhs = true;
1854
1855 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1856 requires_tuning_nonuhs)
1857 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1858 else {
1859 spin_unlock(&host->lock);
1860 enable_irq(host->irq);
1861 sdhci_runtime_pm_put(host);
1862 return 0;
1863 }
1864
1865 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1866
1867 /*
1868 * As per the Host Controller spec v3.00, tuning command
1869 * generates Buffer Read Ready interrupt, so enable that.
1870 *
1871 * Note: The spec clearly says that when tuning sequence
1872 * is being performed, the controller does not generate
1873 * interrupts other than Buffer Read Ready interrupt. But
1874 * to make sure we don't hit a controller bug, we _only_
1875 * enable Buffer Read Ready interrupt here.
1876 */
1877 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1878 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1879
1880 /*
1881 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1882 * of loops reaches 40 times or a timeout of 150ms occurs.
1883 */
1884 timeout = 150;
1885 do {
1886 struct mmc_command cmd = {0};
1887 struct mmc_request mrq = {NULL};
1888
1889 if (!tuning_loop_counter && !timeout)
1890 break;
1891
1892 cmd.opcode = opcode;
1893 cmd.arg = 0;
1894 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1895 cmd.retries = 0;
1896 cmd.data = NULL;
1897 cmd.error = 0;
1898
1899 mrq.cmd = &cmd;
1900 host->mrq = &mrq;
1901
1902 /*
1903 * In response to CMD19, the card sends 64 bytes of tuning
1904 * block to the Host Controller. So we set the block size
1905 * to 64 here.
1906 */
1907 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1908 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1909 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1910 SDHCI_BLOCK_SIZE);
1911 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1912 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1913 SDHCI_BLOCK_SIZE);
1914 } else {
1915 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1916 SDHCI_BLOCK_SIZE);
1917 }
1918
1919 /*
1920 * The tuning block is sent by the card to the host controller.
1921 * So we set the TRNS_READ bit in the Transfer Mode register.
1922 * This also takes care of setting DMA Enable and Multi Block
1923 * Select in the same register to 0.
1924 */
1925 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1926
1927 sdhci_send_command(host, &cmd);
1928
1929 host->cmd = NULL;
1930 host->mrq = NULL;
1931
1932 spin_unlock(&host->lock);
1933 enable_irq(host->irq);
1934
1935 /* Wait for Buffer Read Ready interrupt */
1936 wait_event_interruptible_timeout(host->buf_ready_int,
1937 (host->tuning_done == 1),
1938 msecs_to_jiffies(50));
1939 disable_irq(host->irq);
1940 spin_lock(&host->lock);
1941
1942 if (!host->tuning_done) {
1943 pr_info(DRIVER_NAME ": Timeout waiting for "
1944 "Buffer Read Ready interrupt during tuning "
1945 "procedure, falling back to fixed sampling "
1946 "clock\n");
1947 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1948 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1949 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1950 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1951
1952 err = -EIO;
1953 goto out;
1954 }
1955
1956 host->tuning_done = 0;
1957
1958 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1959 tuning_loop_counter--;
1960 timeout--;
1961 mdelay(1);
1962 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1963
1964 /*
1965 * The Host Driver has exhausted the maximum number of loops allowed,
1966 * so use fixed sampling frequency.
1967 */
1968 if (!tuning_loop_counter || !timeout) {
1969 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1970 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1971 } else {
1972 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1973 pr_info(DRIVER_NAME ": Tuning procedure"
1974 " failed, falling back to fixed sampling"
1975 " clock\n");
1976 err = -EIO;
1977 }
1978 }
1979
1980 out:
1981 /*
1982 * If this is the very first time we are here, we start the retuning
1983 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1984 * flag won't be set, we check this condition before actually starting
1985 * the timer.
1986 */
1987 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1988 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1989 host->flags |= SDHCI_USING_RETUNING_TIMER;
1990 mod_timer(&host->tuning_timer, jiffies +
1991 host->tuning_count * HZ);
1992 /* Tuning mode 1 limits the maximum data length to 4MB */
1993 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1994 } else {
1995 host->flags &= ~SDHCI_NEEDS_RETUNING;
1996 /* Reload the new initial value for timer */
1997 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1998 mod_timer(&host->tuning_timer, jiffies +
1999 host->tuning_count * HZ);
2000 }
2001
2002 /*
2003 * In case tuning fails, host controllers which support re-tuning can
2004 * try tuning again at a later time, when the re-tuning timer expires.
2005 * So for these controllers, we return 0. Since there might be other
2006 * controllers who do not have this capability, we return error for
2007 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2008 * a retuning timer to do the retuning for the card.
2009 */
2010 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2011 err = 0;
2012
2013 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2014 spin_unlock(&host->lock);
2015 enable_irq(host->irq);
2016 sdhci_runtime_pm_put(host);
2017
2018 return err;
2019 }
2020
2021
2022 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2023 {
2024 u16 ctrl;
2025
2026 /* Host Controller v3.00 defines preset value registers */
2027 if (host->version < SDHCI_SPEC_300)
2028 return;
2029
2030 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2031
2032 /*
2033 * We only enable or disable Preset Value if they are not already
2034 * enabled or disabled respectively. Otherwise, we bail out.
2035 */
2036 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2037 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039 host->flags |= SDHCI_PV_ENABLED;
2040 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2041 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2042 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2043 host->flags &= ~SDHCI_PV_ENABLED;
2044 }
2045 }
2046
2047 static void sdhci_card_event(struct mmc_host *mmc)
2048 {
2049 struct sdhci_host *host = mmc_priv(mmc);
2050 unsigned long flags;
2051
2052 spin_lock_irqsave(&host->lock, flags);
2053
2054 /* Check host->mrq first in case we are runtime suspended */
2055 if (host->mrq &&
2056 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2057 pr_err("%s: Card removed during transfer!\n",
2058 mmc_hostname(host->mmc));
2059 pr_err("%s: Resetting controller.\n",
2060 mmc_hostname(host->mmc));
2061
2062 sdhci_reset(host, SDHCI_RESET_CMD);
2063 sdhci_reset(host, SDHCI_RESET_DATA);
2064
2065 host->mrq->cmd->error = -ENOMEDIUM;
2066 tasklet_schedule(&host->finish_tasklet);
2067 }
2068
2069 spin_unlock_irqrestore(&host->lock, flags);
2070 }
2071
2072 static const struct mmc_host_ops sdhci_ops = {
2073 .request = sdhci_request,
2074 .set_ios = sdhci_set_ios,
2075 .get_cd = sdhci_get_cd,
2076 .get_ro = sdhci_get_ro,
2077 .hw_reset = sdhci_hw_reset,
2078 .enable_sdio_irq = sdhci_enable_sdio_irq,
2079 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2080 .execute_tuning = sdhci_execute_tuning,
2081 .card_event = sdhci_card_event,
2082 .card_busy = sdhci_card_busy,
2083 };
2084
2085 /*****************************************************************************\
2086 * *
2087 * Tasklets *
2088 * *
2089 \*****************************************************************************/
2090
2091 static void sdhci_tasklet_card(unsigned long param)
2092 {
2093 struct sdhci_host *host = (struct sdhci_host*)param;
2094
2095 sdhci_card_event(host->mmc);
2096
2097 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2098 }
2099
2100 static void sdhci_tasklet_finish(unsigned long param)
2101 {
2102 struct sdhci_host *host;
2103 unsigned long flags;
2104 struct mmc_request *mrq;
2105
2106 host = (struct sdhci_host*)param;
2107
2108 spin_lock_irqsave(&host->lock, flags);
2109
2110 /*
2111 * If this tasklet gets rescheduled while running, it will
2112 * be run again afterwards but without any active request.
2113 */
2114 if (!host->mrq) {
2115 spin_unlock_irqrestore(&host->lock, flags);
2116 return;
2117 }
2118
2119 del_timer(&host->timer);
2120
2121 mrq = host->mrq;
2122
2123 /*
2124 * The controller needs a reset of internal state machines
2125 * upon error conditions.
2126 */
2127 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2128 ((mrq->cmd && mrq->cmd->error) ||
2129 (mrq->data && (mrq->data->error ||
2130 (mrq->data->stop && mrq->data->stop->error))) ||
2131 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2132
2133 /* Some controllers need this kick or reset won't work here */
2134 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2135 /* This is to force an update */
2136 sdhci_update_clock(host);
2137
2138 /* Spec says we should do both at the same time, but Ricoh
2139 controllers do not like that. */
2140 sdhci_reset(host, SDHCI_RESET_CMD);
2141 sdhci_reset(host, SDHCI_RESET_DATA);
2142 }
2143
2144 host->mrq = NULL;
2145 host->cmd = NULL;
2146 host->data = NULL;
2147
2148 #ifndef SDHCI_USE_LEDS_CLASS
2149 sdhci_deactivate_led(host);
2150 #endif
2151
2152 mmiowb();
2153 spin_unlock_irqrestore(&host->lock, flags);
2154
2155 mmc_request_done(host->mmc, mrq);
2156 sdhci_runtime_pm_put(host);
2157 }
2158
2159 static void sdhci_timeout_timer(unsigned long data)
2160 {
2161 struct sdhci_host *host;
2162 unsigned long flags;
2163
2164 host = (struct sdhci_host*)data;
2165
2166 spin_lock_irqsave(&host->lock, flags);
2167
2168 if (host->mrq) {
2169 pr_err("%s: Timeout waiting for hardware "
2170 "interrupt.\n", mmc_hostname(host->mmc));
2171 sdhci_dumpregs(host);
2172
2173 if (host->data) {
2174 host->data->error = -ETIMEDOUT;
2175 sdhci_finish_data(host);
2176 } else {
2177 if (host->cmd)
2178 host->cmd->error = -ETIMEDOUT;
2179 else
2180 host->mrq->cmd->error = -ETIMEDOUT;
2181
2182 tasklet_schedule(&host->finish_tasklet);
2183 }
2184 }
2185
2186 mmiowb();
2187 spin_unlock_irqrestore(&host->lock, flags);
2188 }
2189
2190 static void sdhci_tuning_timer(unsigned long data)
2191 {
2192 struct sdhci_host *host;
2193 unsigned long flags;
2194
2195 host = (struct sdhci_host *)data;
2196
2197 spin_lock_irqsave(&host->lock, flags);
2198
2199 host->flags |= SDHCI_NEEDS_RETUNING;
2200
2201 spin_unlock_irqrestore(&host->lock, flags);
2202 }
2203
2204 /*****************************************************************************\
2205 * *
2206 * Interrupt handling *
2207 * *
2208 \*****************************************************************************/
2209
2210 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2211 {
2212 BUG_ON(intmask == 0);
2213
2214 if (!host->cmd) {
2215 pr_err("%s: Got command interrupt 0x%08x even "
2216 "though no command operation was in progress.\n",
2217 mmc_hostname(host->mmc), (unsigned)intmask);
2218 sdhci_dumpregs(host);
2219 return;
2220 }
2221
2222 if (intmask & SDHCI_INT_TIMEOUT)
2223 host->cmd->error = -ETIMEDOUT;
2224 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2225 SDHCI_INT_INDEX))
2226 host->cmd->error = -EILSEQ;
2227
2228 if (host->cmd->error) {
2229 tasklet_schedule(&host->finish_tasklet);
2230 return;
2231 }
2232
2233 /*
2234 * The host can send and interrupt when the busy state has
2235 * ended, allowing us to wait without wasting CPU cycles.
2236 * Unfortunately this is overloaded on the "data complete"
2237 * interrupt, so we need to take some care when handling
2238 * it.
2239 *
2240 * Note: The 1.0 specification is a bit ambiguous about this
2241 * feature so there might be some problems with older
2242 * controllers.
2243 */
2244 if (host->cmd->flags & MMC_RSP_BUSY) {
2245 if (host->cmd->data)
2246 DBG("Cannot wait for busy signal when also "
2247 "doing a data transfer");
2248 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2249 return;
2250
2251 /* The controller does not support the end-of-busy IRQ,
2252 * fall through and take the SDHCI_INT_RESPONSE */
2253 }
2254
2255 if (intmask & SDHCI_INT_RESPONSE)
2256 sdhci_finish_command(host);
2257 }
2258
2259 #ifdef CONFIG_MMC_DEBUG
2260 static void sdhci_show_adma_error(struct sdhci_host *host)
2261 {
2262 const char *name = mmc_hostname(host->mmc);
2263 u8 *desc = host->adma_desc;
2264 __le32 *dma;
2265 __le16 *len;
2266 u8 attr;
2267
2268 sdhci_dumpregs(host);
2269
2270 while (true) {
2271 dma = (__le32 *)(desc + 4);
2272 len = (__le16 *)(desc + 2);
2273 attr = *desc;
2274
2275 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2276 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2277
2278 desc += 8;
2279
2280 if (attr & 2)
2281 break;
2282 }
2283 }
2284 #else
2285 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2286 #endif
2287
2288 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2289 {
2290 u32 command;
2291 BUG_ON(intmask == 0);
2292
2293 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2294 if (intmask & SDHCI_INT_DATA_AVAIL) {
2295 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2296 if (command == MMC_SEND_TUNING_BLOCK ||
2297 command == MMC_SEND_TUNING_BLOCK_HS200) {
2298 host->tuning_done = 1;
2299 wake_up(&host->buf_ready_int);
2300 return;
2301 }
2302 }
2303
2304 if (!host->data) {
2305 /*
2306 * The "data complete" interrupt is also used to
2307 * indicate that a busy state has ended. See comment
2308 * above in sdhci_cmd_irq().
2309 */
2310 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2311 if (intmask & SDHCI_INT_DATA_END) {
2312 sdhci_finish_command(host);
2313 return;
2314 }
2315 }
2316
2317 pr_err("%s: Got data interrupt 0x%08x even "
2318 "though no data operation was in progress.\n",
2319 mmc_hostname(host->mmc), (unsigned)intmask);
2320 sdhci_dumpregs(host);
2321
2322 return;
2323 }
2324
2325 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2326 host->data->error = -ETIMEDOUT;
2327 else if (intmask & SDHCI_INT_DATA_END_BIT)
2328 host->data->error = -EILSEQ;
2329 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2330 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2331 != MMC_BUS_TEST_R)
2332 host->data->error = -EILSEQ;
2333 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2334 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2335 sdhci_show_adma_error(host);
2336 host->data->error = -EIO;
2337 if (host->ops->adma_workaround)
2338 host->ops->adma_workaround(host, intmask);
2339 }
2340
2341 if (host->data->error)
2342 sdhci_finish_data(host);
2343 else {
2344 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2345 sdhci_transfer_pio(host);
2346
2347 /*
2348 * We currently don't do anything fancy with DMA
2349 * boundaries, but as we can't disable the feature
2350 * we need to at least restart the transfer.
2351 *
2352 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2353 * should return a valid address to continue from, but as
2354 * some controllers are faulty, don't trust them.
2355 */
2356 if (intmask & SDHCI_INT_DMA_END) {
2357 u32 dmastart, dmanow;
2358 dmastart = sg_dma_address(host->data->sg);
2359 dmanow = dmastart + host->data->bytes_xfered;
2360 /*
2361 * Force update to the next DMA block boundary.
2362 */
2363 dmanow = (dmanow &
2364 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2365 SDHCI_DEFAULT_BOUNDARY_SIZE;
2366 host->data->bytes_xfered = dmanow - dmastart;
2367 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2368 " next 0x%08x\n",
2369 mmc_hostname(host->mmc), dmastart,
2370 host->data->bytes_xfered, dmanow);
2371 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2372 }
2373
2374 if (intmask & SDHCI_INT_DATA_END) {
2375 if (host->cmd) {
2376 /*
2377 * Data managed to finish before the
2378 * command completed. Make sure we do
2379 * things in the proper order.
2380 */
2381 host->data_early = 1;
2382 } else {
2383 sdhci_finish_data(host);
2384 }
2385 }
2386 }
2387 }
2388
2389 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2390 {
2391 irqreturn_t result;
2392 struct sdhci_host *host = dev_id;
2393 u32 intmask, unexpected = 0;
2394 int cardint = 0, max_loops = 16;
2395
2396 spin_lock(&host->lock);
2397
2398 if (host->runtime_suspended) {
2399 spin_unlock(&host->lock);
2400 pr_warning("%s: got irq while runtime suspended\n",
2401 mmc_hostname(host->mmc));
2402 return IRQ_HANDLED;
2403 }
2404
2405 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2406
2407 if (!intmask || intmask == 0xffffffff) {
2408 result = IRQ_NONE;
2409 goto out;
2410 }
2411
2412 again:
2413 DBG("*** %s got interrupt: 0x%08x\n",
2414 mmc_hostname(host->mmc), intmask);
2415
2416 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2417 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2418 SDHCI_CARD_PRESENT;
2419
2420 /*
2421 * There is a observation on i.mx esdhc. INSERT bit will be
2422 * immediately set again when it gets cleared, if a card is
2423 * inserted. We have to mask the irq to prevent interrupt
2424 * storm which will freeze the system. And the REMOVE gets
2425 * the same situation.
2426 *
2427 * More testing are needed here to ensure it works for other
2428 * platforms though.
2429 */
2430 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2431 SDHCI_INT_CARD_REMOVE);
2432 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2433 SDHCI_INT_CARD_INSERT);
2434
2435 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2436 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2437 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2438 tasklet_schedule(&host->card_tasklet);
2439 }
2440
2441 if (intmask & SDHCI_INT_CMD_MASK) {
2442 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2443 SDHCI_INT_STATUS);
2444 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2445 }
2446
2447 if (intmask & SDHCI_INT_DATA_MASK) {
2448 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2449 SDHCI_INT_STATUS);
2450 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2451 }
2452
2453 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2454
2455 intmask &= ~SDHCI_INT_ERROR;
2456
2457 if (intmask & SDHCI_INT_BUS_POWER) {
2458 pr_err("%s: Card is consuming too much power!\n",
2459 mmc_hostname(host->mmc));
2460 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2461 }
2462
2463 intmask &= ~SDHCI_INT_BUS_POWER;
2464
2465 if (intmask & SDHCI_INT_CARD_INT)
2466 cardint = 1;
2467
2468 intmask &= ~SDHCI_INT_CARD_INT;
2469
2470 if (intmask) {
2471 unexpected |= intmask;
2472 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2473 }
2474
2475 result = IRQ_HANDLED;
2476
2477 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2478 if (intmask && --max_loops)
2479 goto again;
2480 out:
2481 spin_unlock(&host->lock);
2482
2483 if (unexpected) {
2484 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2485 mmc_hostname(host->mmc), unexpected);
2486 sdhci_dumpregs(host);
2487 }
2488 /*
2489 * We have to delay this as it calls back into the driver.
2490 */
2491 if (cardint)
2492 mmc_signal_sdio_irq(host->mmc);
2493
2494 return result;
2495 }
2496
2497 /*****************************************************************************\
2498 * *
2499 * Suspend/resume *
2500 * *
2501 \*****************************************************************************/
2502
2503 #ifdef CONFIG_PM
2504 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2505 {
2506 u8 val;
2507 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2508 | SDHCI_WAKE_ON_INT;
2509
2510 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2511 val |= mask ;
2512 /* Avoid fake wake up */
2513 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2514 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2515 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2516 }
2517 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2518
2519 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2520 {
2521 u8 val;
2522 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2523 | SDHCI_WAKE_ON_INT;
2524
2525 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2526 val &= ~mask;
2527 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2528 }
2529 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2530
2531 int sdhci_suspend_host(struct sdhci_host *host)
2532 {
2533 int ret;
2534
2535 if (host->ops->platform_suspend)
2536 host->ops->platform_suspend(host);
2537
2538 sdhci_disable_card_detection(host);
2539
2540 /* Disable tuning since we are suspending */
2541 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2542 del_timer_sync(&host->tuning_timer);
2543 host->flags &= ~SDHCI_NEEDS_RETUNING;
2544 }
2545
2546 ret = mmc_suspend_host(host->mmc);
2547 if (ret) {
2548 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2549 host->flags |= SDHCI_NEEDS_RETUNING;
2550 mod_timer(&host->tuning_timer, jiffies +
2551 host->tuning_count * HZ);
2552 }
2553
2554 sdhci_enable_card_detection(host);
2555
2556 return ret;
2557 }
2558
2559 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2560 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2561 free_irq(host->irq, host);
2562 } else {
2563 sdhci_enable_irq_wakeups(host);
2564 enable_irq_wake(host->irq);
2565 }
2566 return ret;
2567 }
2568
2569 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2570
2571 int sdhci_resume_host(struct sdhci_host *host)
2572 {
2573 int ret;
2574
2575 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2576 if (host->ops->enable_dma)
2577 host->ops->enable_dma(host);
2578 }
2579
2580 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2581 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2582 mmc_hostname(host->mmc), host);
2583 if (ret)
2584 return ret;
2585 } else {
2586 sdhci_disable_irq_wakeups(host);
2587 disable_irq_wake(host->irq);
2588 }
2589
2590 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2591 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2592 /* Card keeps power but host controller does not */
2593 sdhci_init(host, 0);
2594 host->pwr = 0;
2595 host->clock = 0;
2596 sdhci_do_set_ios(host, &host->mmc->ios);
2597 } else {
2598 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2599 mmiowb();
2600 }
2601
2602 ret = mmc_resume_host(host->mmc);
2603 sdhci_enable_card_detection(host);
2604
2605 if (host->ops->platform_resume)
2606 host->ops->platform_resume(host);
2607
2608 /* Set the re-tuning expiration flag */
2609 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2610 host->flags |= SDHCI_NEEDS_RETUNING;
2611
2612 return ret;
2613 }
2614
2615 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2616 #endif /* CONFIG_PM */
2617
2618 #ifdef CONFIG_PM_RUNTIME
2619
2620 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2621 {
2622 return pm_runtime_get_sync(host->mmc->parent);
2623 }
2624
2625 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2626 {
2627 pm_runtime_mark_last_busy(host->mmc->parent);
2628 return pm_runtime_put_autosuspend(host->mmc->parent);
2629 }
2630
2631 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2632 {
2633 unsigned long flags;
2634 int ret = 0;
2635
2636 /* Disable tuning since we are suspending */
2637 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2638 del_timer_sync(&host->tuning_timer);
2639 host->flags &= ~SDHCI_NEEDS_RETUNING;
2640 }
2641
2642 spin_lock_irqsave(&host->lock, flags);
2643 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2644 spin_unlock_irqrestore(&host->lock, flags);
2645
2646 synchronize_irq(host->irq);
2647
2648 spin_lock_irqsave(&host->lock, flags);
2649 host->runtime_suspended = true;
2650 spin_unlock_irqrestore(&host->lock, flags);
2651
2652 return ret;
2653 }
2654 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2655
2656 int sdhci_runtime_resume_host(struct sdhci_host *host)
2657 {
2658 unsigned long flags;
2659 int ret = 0, host_flags = host->flags;
2660
2661 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2662 if (host->ops->enable_dma)
2663 host->ops->enable_dma(host);
2664 }
2665
2666 sdhci_init(host, 0);
2667
2668 /* Force clock and power re-program */
2669 host->pwr = 0;
2670 host->clock = 0;
2671 sdhci_do_set_ios(host, &host->mmc->ios);
2672
2673 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2674 if ((host_flags & SDHCI_PV_ENABLED) &&
2675 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2676 spin_lock_irqsave(&host->lock, flags);
2677 sdhci_enable_preset_value(host, true);
2678 spin_unlock_irqrestore(&host->lock, flags);
2679 }
2680
2681 /* Set the re-tuning expiration flag */
2682 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2683 host->flags |= SDHCI_NEEDS_RETUNING;
2684
2685 spin_lock_irqsave(&host->lock, flags);
2686
2687 host->runtime_suspended = false;
2688
2689 /* Enable SDIO IRQ */
2690 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2691 sdhci_enable_sdio_irq_nolock(host, true);
2692
2693 /* Enable Card Detection */
2694 sdhci_enable_card_detection(host);
2695
2696 spin_unlock_irqrestore(&host->lock, flags);
2697
2698 return ret;
2699 }
2700 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2701
2702 #endif
2703
2704 /*****************************************************************************\
2705 * *
2706 * Device allocation/registration *
2707 * *
2708 \*****************************************************************************/
2709
2710 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2711 size_t priv_size)
2712 {
2713 struct mmc_host *mmc;
2714 struct sdhci_host *host;
2715
2716 WARN_ON(dev == NULL);
2717
2718 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2719 if (!mmc)
2720 return ERR_PTR(-ENOMEM);
2721
2722 host = mmc_priv(mmc);
2723 host->mmc = mmc;
2724
2725 return host;
2726 }
2727
2728 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2729
2730 int sdhci_add_host(struct sdhci_host *host)
2731 {
2732 struct mmc_host *mmc;
2733 u32 caps[2] = {0, 0};
2734 u32 max_current_caps;
2735 unsigned int ocr_avail;
2736 int ret;
2737
2738 WARN_ON(host == NULL);
2739 if (host == NULL)
2740 return -EINVAL;
2741
2742 mmc = host->mmc;
2743
2744 if (debug_quirks)
2745 host->quirks = debug_quirks;
2746 if (debug_quirks2)
2747 host->quirks2 = debug_quirks2;
2748
2749 sdhci_reset(host, SDHCI_RESET_ALL);
2750
2751 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2752 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2753 >> SDHCI_SPEC_VER_SHIFT;
2754 if (host->version > SDHCI_SPEC_300) {
2755 pr_err("%s: Unknown controller version (%d). "
2756 "You may experience problems.\n", mmc_hostname(mmc),
2757 host->version);
2758 }
2759
2760 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2761 sdhci_readl(host, SDHCI_CAPABILITIES);
2762
2763 if (host->version >= SDHCI_SPEC_300)
2764 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2765 host->caps1 :
2766 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2767
2768 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2769 host->flags |= SDHCI_USE_SDMA;
2770 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2771 DBG("Controller doesn't have SDMA capability\n");
2772 else
2773 host->flags |= SDHCI_USE_SDMA;
2774
2775 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2776 (host->flags & SDHCI_USE_SDMA)) {
2777 DBG("Disabling DMA as it is marked broken\n");
2778 host->flags &= ~SDHCI_USE_SDMA;
2779 }
2780
2781 if ((host->version >= SDHCI_SPEC_200) &&
2782 (caps[0] & SDHCI_CAN_DO_ADMA2))
2783 host->flags |= SDHCI_USE_ADMA;
2784
2785 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2786 (host->flags & SDHCI_USE_ADMA)) {
2787 DBG("Disabling ADMA as it is marked broken\n");
2788 host->flags &= ~SDHCI_USE_ADMA;
2789 }
2790
2791 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2792 if (host->ops->enable_dma) {
2793 if (host->ops->enable_dma(host)) {
2794 pr_warning("%s: No suitable DMA "
2795 "available. Falling back to PIO.\n",
2796 mmc_hostname(mmc));
2797 host->flags &=
2798 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2799 }
2800 }
2801 }
2802
2803 if (host->flags & SDHCI_USE_ADMA) {
2804 /*
2805 * We need to allocate descriptors for all sg entries
2806 * (128) and potentially one alignment transfer for
2807 * each of those entries.
2808 */
2809 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2810 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2811 if (!host->adma_desc || !host->align_buffer) {
2812 kfree(host->adma_desc);
2813 kfree(host->align_buffer);
2814 pr_warning("%s: Unable to allocate ADMA "
2815 "buffers. Falling back to standard DMA.\n",
2816 mmc_hostname(mmc));
2817 host->flags &= ~SDHCI_USE_ADMA;
2818 }
2819 }
2820
2821 /*
2822 * If we use DMA, then it's up to the caller to set the DMA
2823 * mask, but PIO does not need the hw shim so we set a new
2824 * mask here in that case.
2825 */
2826 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2827 host->dma_mask = DMA_BIT_MASK(64);
2828 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2829 }
2830
2831 if (host->version >= SDHCI_SPEC_300)
2832 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2833 >> SDHCI_CLOCK_BASE_SHIFT;
2834 else
2835 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2836 >> SDHCI_CLOCK_BASE_SHIFT;
2837
2838 host->max_clk *= 1000000;
2839 if (host->max_clk == 0 || host->quirks &
2840 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2841 if (!host->ops->get_max_clock) {
2842 pr_err("%s: Hardware doesn't specify base clock "
2843 "frequency.\n", mmc_hostname(mmc));
2844 return -ENODEV;
2845 }
2846 host->max_clk = host->ops->get_max_clock(host);
2847 }
2848
2849 /*
2850 * In case of Host Controller v3.00, find out whether clock
2851 * multiplier is supported.
2852 */
2853 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2854 SDHCI_CLOCK_MUL_SHIFT;
2855
2856 /*
2857 * In case the value in Clock Multiplier is 0, then programmable
2858 * clock mode is not supported, otherwise the actual clock
2859 * multiplier is one more than the value of Clock Multiplier
2860 * in the Capabilities Register.
2861 */
2862 if (host->clk_mul)
2863 host->clk_mul += 1;
2864
2865 /*
2866 * Set host parameters.
2867 */
2868 mmc->ops = &sdhci_ops;
2869 mmc->f_max = host->max_clk;
2870 if (host->ops->get_min_clock)
2871 mmc->f_min = host->ops->get_min_clock(host);
2872 else if (host->version >= SDHCI_SPEC_300) {
2873 if (host->clk_mul) {
2874 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2875 mmc->f_max = host->max_clk * host->clk_mul;
2876 } else
2877 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2878 } else
2879 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2880
2881 host->timeout_clk =
2882 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2883 if (host->timeout_clk == 0) {
2884 if (host->ops->get_timeout_clock) {
2885 host->timeout_clk = host->ops->get_timeout_clock(host);
2886 } else if (!(host->quirks &
2887 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2888 pr_err("%s: Hardware doesn't specify timeout clock "
2889 "frequency.\n", mmc_hostname(mmc));
2890 return -ENODEV;
2891 }
2892 }
2893 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2894 host->timeout_clk *= 1000;
2895
2896 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2897 host->timeout_clk = mmc->f_max / 1000;
2898
2899 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2900
2901 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2902
2903 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2904 host->flags |= SDHCI_AUTO_CMD12;
2905
2906 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2907 if ((host->version >= SDHCI_SPEC_300) &&
2908 ((host->flags & SDHCI_USE_ADMA) ||
2909 !(host->flags & SDHCI_USE_SDMA))) {
2910 host->flags |= SDHCI_AUTO_CMD23;
2911 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2912 } else {
2913 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2914 }
2915
2916 /*
2917 * A controller may support 8-bit width, but the board itself
2918 * might not have the pins brought out. Boards that support
2919 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2920 * their platform code before calling sdhci_add_host(), and we
2921 * won't assume 8-bit width for hosts without that CAP.
2922 */
2923 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2924 mmc->caps |= MMC_CAP_4_BIT_DATA;
2925
2926 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2927 mmc->caps &= ~MMC_CAP_CMD23;
2928
2929 if (caps[0] & SDHCI_CAN_DO_HISPD)
2930 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2931
2932 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2933 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2934 mmc->caps |= MMC_CAP_NEEDS_POLL;
2935
2936 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2937 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2938 if (IS_ERR_OR_NULL(host->vqmmc)) {
2939 if (PTR_ERR(host->vqmmc) < 0) {
2940 pr_info("%s: no vqmmc regulator found\n",
2941 mmc_hostname(mmc));
2942 host->vqmmc = NULL;
2943 }
2944 } else {
2945 ret = regulator_enable(host->vqmmc);
2946 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2947 1950000))
2948 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2949 SDHCI_SUPPORT_SDR50 |
2950 SDHCI_SUPPORT_DDR50);
2951 if (ret) {
2952 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2953 mmc_hostname(mmc), ret);
2954 host->vqmmc = NULL;
2955 }
2956 }
2957
2958 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2959 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2960 SDHCI_SUPPORT_DDR50);
2961
2962 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2963 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2964 SDHCI_SUPPORT_DDR50))
2965 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2966
2967 /* SDR104 supports also implies SDR50 support */
2968 if (caps[1] & SDHCI_SUPPORT_SDR104)
2969 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2970 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2971 mmc->caps |= MMC_CAP_UHS_SDR50;
2972
2973 if (caps[1] & SDHCI_SUPPORT_DDR50)
2974 mmc->caps |= MMC_CAP_UHS_DDR50;
2975
2976 /* Does the host need tuning for SDR50? */
2977 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2978 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2979
2980 /* Does the host need tuning for HS200? */
2981 if (mmc->caps2 & MMC_CAP2_HS200)
2982 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2983
2984 /* Driver Type(s) (A, C, D) supported by the host */
2985 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2986 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2987 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2988 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2989 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2990 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2991
2992 /* Initial value for re-tuning timer count */
2993 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2994 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2995
2996 /*
2997 * In case Re-tuning Timer is not disabled, the actual value of
2998 * re-tuning timer will be 2 ^ (n - 1).
2999 */
3000 if (host->tuning_count)
3001 host->tuning_count = 1 << (host->tuning_count - 1);
3002
3003 /* Re-tuning mode supported by the Host Controller */
3004 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3005 SDHCI_RETUNING_MODE_SHIFT;
3006
3007 ocr_avail = 0;
3008
3009 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3010 if (IS_ERR_OR_NULL(host->vmmc)) {
3011 if (PTR_ERR(host->vmmc) < 0) {
3012 pr_info("%s: no vmmc regulator found\n",
3013 mmc_hostname(mmc));
3014 host->vmmc = NULL;
3015 }
3016 }
3017
3018 #ifdef CONFIG_REGULATOR
3019 /*
3020 * Voltage range check makes sense only if regulator reports
3021 * any voltage value.
3022 */
3023 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3024 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3025 3600000);
3026 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3027 caps[0] &= ~SDHCI_CAN_VDD_330;
3028 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3029 caps[0] &= ~SDHCI_CAN_VDD_300;
3030 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3031 1950000);
3032 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3033 caps[0] &= ~SDHCI_CAN_VDD_180;
3034 }
3035 #endif /* CONFIG_REGULATOR */
3036
3037 /*
3038 * According to SD Host Controller spec v3.00, if the Host System
3039 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3040 * the value is meaningful only if Voltage Support in the Capabilities
3041 * register is set. The actual current value is 4 times the register
3042 * value.
3043 */
3044 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3045 if (!max_current_caps && host->vmmc) {
3046 u32 curr = regulator_get_current_limit(host->vmmc);
3047 if (curr > 0) {
3048
3049 /* convert to SDHCI_MAX_CURRENT format */
3050 curr = curr/1000; /* convert to mA */
3051 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3052
3053 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3054 max_current_caps =
3055 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3056 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3057 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3058 }
3059 }
3060
3061 if (caps[0] & SDHCI_CAN_VDD_330) {
3062 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3063
3064 mmc->max_current_330 = ((max_current_caps &
3065 SDHCI_MAX_CURRENT_330_MASK) >>
3066 SDHCI_MAX_CURRENT_330_SHIFT) *
3067 SDHCI_MAX_CURRENT_MULTIPLIER;
3068 }
3069 if (caps[0] & SDHCI_CAN_VDD_300) {
3070 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3071
3072 mmc->max_current_300 = ((max_current_caps &
3073 SDHCI_MAX_CURRENT_300_MASK) >>
3074 SDHCI_MAX_CURRENT_300_SHIFT) *
3075 SDHCI_MAX_CURRENT_MULTIPLIER;
3076 }
3077 if (caps[0] & SDHCI_CAN_VDD_180) {
3078 ocr_avail |= MMC_VDD_165_195;
3079
3080 mmc->max_current_180 = ((max_current_caps &
3081 SDHCI_MAX_CURRENT_180_MASK) >>
3082 SDHCI_MAX_CURRENT_180_SHIFT) *
3083 SDHCI_MAX_CURRENT_MULTIPLIER;
3084 }
3085
3086 mmc->ocr_avail = ocr_avail;
3087 mmc->ocr_avail_sdio = ocr_avail;
3088 if (host->ocr_avail_sdio)
3089 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3090 mmc->ocr_avail_sd = ocr_avail;
3091 if (host->ocr_avail_sd)
3092 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3093 else /* normal SD controllers don't support 1.8V */
3094 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3095 mmc->ocr_avail_mmc = ocr_avail;
3096 if (host->ocr_avail_mmc)
3097 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3098
3099 if (mmc->ocr_avail == 0) {
3100 pr_err("%s: Hardware doesn't report any "
3101 "support voltages.\n", mmc_hostname(mmc));
3102 return -ENODEV;
3103 }
3104
3105 spin_lock_init(&host->lock);
3106
3107 /*
3108 * Maximum number of segments. Depends on if the hardware
3109 * can do scatter/gather or not.
3110 */
3111 if (host->flags & SDHCI_USE_ADMA)
3112 mmc->max_segs = 128;
3113 else if (host->flags & SDHCI_USE_SDMA)
3114 mmc->max_segs = 1;
3115 else /* PIO */
3116 mmc->max_segs = 128;
3117
3118 /*
3119 * Maximum number of sectors in one transfer. Limited by DMA boundary
3120 * size (512KiB).
3121 */
3122 mmc->max_req_size = 524288;
3123
3124 /*
3125 * Maximum segment size. Could be one segment with the maximum number
3126 * of bytes. When doing hardware scatter/gather, each entry cannot
3127 * be larger than 64 KiB though.
3128 */
3129 if (host->flags & SDHCI_USE_ADMA) {
3130 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3131 mmc->max_seg_size = 65535;
3132 else
3133 mmc->max_seg_size = 65536;
3134 } else {
3135 mmc->max_seg_size = mmc->max_req_size;
3136 }
3137
3138 /*
3139 * Maximum block size. This varies from controller to controller and
3140 * is specified in the capabilities register.
3141 */
3142 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3143 mmc->max_blk_size = 2;
3144 } else {
3145 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3146 SDHCI_MAX_BLOCK_SHIFT;
3147 if (mmc->max_blk_size >= 3) {
3148 pr_warning("%s: Invalid maximum block size, "
3149 "assuming 512 bytes\n", mmc_hostname(mmc));
3150 mmc->max_blk_size = 0;
3151 }
3152 }
3153
3154 mmc->max_blk_size = 512 << mmc->max_blk_size;
3155
3156 /*
3157 * Maximum block count.
3158 */
3159 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3160
3161 /*
3162 * Init tasklets.
3163 */
3164 tasklet_init(&host->card_tasklet,
3165 sdhci_tasklet_card, (unsigned long)host);
3166 tasklet_init(&host->finish_tasklet,
3167 sdhci_tasklet_finish, (unsigned long)host);
3168
3169 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3170
3171 if (host->version >= SDHCI_SPEC_300) {
3172 init_waitqueue_head(&host->buf_ready_int);
3173
3174 /* Initialize re-tuning timer */
3175 init_timer(&host->tuning_timer);
3176 host->tuning_timer.data = (unsigned long)host;
3177 host->tuning_timer.function = sdhci_tuning_timer;
3178 }
3179
3180 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3181 mmc_hostname(mmc), host);
3182 if (ret) {
3183 pr_err("%s: Failed to request IRQ %d: %d\n",
3184 mmc_hostname(mmc), host->irq, ret);
3185 goto untasklet;
3186 }
3187
3188 sdhci_init(host, 0);
3189
3190 #ifdef CONFIG_MMC_DEBUG
3191 sdhci_dumpregs(host);
3192 #endif
3193
3194 #ifdef SDHCI_USE_LEDS_CLASS
3195 snprintf(host->led_name, sizeof(host->led_name),
3196 "%s::", mmc_hostname(mmc));
3197 host->led.name = host->led_name;
3198 host->led.brightness = LED_OFF;
3199 host->led.default_trigger = mmc_hostname(mmc);
3200 host->led.brightness_set = sdhci_led_control;
3201
3202 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3203 if (ret) {
3204 pr_err("%s: Failed to register LED device: %d\n",
3205 mmc_hostname(mmc), ret);
3206 goto reset;
3207 }
3208 #endif
3209
3210 mmiowb();
3211
3212 mmc_add_host(mmc);
3213
3214 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3215 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3216 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3217 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3218
3219 sdhci_enable_card_detection(host);
3220
3221 return 0;
3222
3223 #ifdef SDHCI_USE_LEDS_CLASS
3224 reset:
3225 sdhci_reset(host, SDHCI_RESET_ALL);
3226 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3227 free_irq(host->irq, host);
3228 #endif
3229 untasklet:
3230 tasklet_kill(&host->card_tasklet);
3231 tasklet_kill(&host->finish_tasklet);
3232
3233 return ret;
3234 }
3235
3236 EXPORT_SYMBOL_GPL(sdhci_add_host);
3237
3238 void sdhci_remove_host(struct sdhci_host *host, int dead)
3239 {
3240 unsigned long flags;
3241
3242 if (dead) {
3243 spin_lock_irqsave(&host->lock, flags);
3244
3245 host->flags |= SDHCI_DEVICE_DEAD;
3246
3247 if (host->mrq) {
3248 pr_err("%s: Controller removed during "
3249 " transfer!\n", mmc_hostname(host->mmc));
3250
3251 host->mrq->cmd->error = -ENOMEDIUM;
3252 tasklet_schedule(&host->finish_tasklet);
3253 }
3254
3255 spin_unlock_irqrestore(&host->lock, flags);
3256 }
3257
3258 sdhci_disable_card_detection(host);
3259
3260 mmc_remove_host(host->mmc);
3261
3262 #ifdef SDHCI_USE_LEDS_CLASS
3263 led_classdev_unregister(&host->led);
3264 #endif
3265
3266 if (!dead)
3267 sdhci_reset(host, SDHCI_RESET_ALL);
3268
3269 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3270 free_irq(host->irq, host);
3271
3272 del_timer_sync(&host->timer);
3273
3274 tasklet_kill(&host->card_tasklet);
3275 tasklet_kill(&host->finish_tasklet);
3276
3277 if (host->vmmc) {
3278 regulator_disable(host->vmmc);
3279 regulator_put(host->vmmc);
3280 }
3281
3282 if (host->vqmmc) {
3283 regulator_disable(host->vqmmc);
3284 regulator_put(host->vqmmc);
3285 }
3286
3287 kfree(host->adma_desc);
3288 kfree(host->align_buffer);
3289
3290 host->adma_desc = NULL;
3291 host->align_buffer = NULL;
3292 }
3293
3294 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3295
3296 void sdhci_free_host(struct sdhci_host *host)
3297 {
3298 mmc_free_host(host->mmc);
3299 }
3300
3301 EXPORT_SYMBOL_GPL(sdhci_free_host);
3302
3303 /*****************************************************************************\
3304 * *
3305 * Driver init/exit *
3306 * *
3307 \*****************************************************************************/
3308
3309 static int __init sdhci_drv_init(void)
3310 {
3311 pr_info(DRIVER_NAME
3312 ": Secure Digital Host Controller Interface driver\n");
3313 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3314
3315 return 0;
3316 }
3317
3318 static void __exit sdhci_drv_exit(void)
3319 {
3320 }
3321
3322 module_init(sdhci_drv_init);
3323 module_exit(sdhci_drv_exit);
3324
3325 module_param(debug_quirks, uint, 0444);
3326 module_param(debug_quirks2, uint, 0444);
3327
3328 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3329 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3330 MODULE_LICENSE("GPL");
3331
3332 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3333 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
kernel source for telekom puls (alcatel/mediatek)