projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
import PULS_20180308
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / video / mt8127 / mt8127 / dsi_drv.c
1 #ifdef BUILD_UBOOT
2 #define ENABLE_DSI_INTERRUPT 0
3
4 #include <asm/arch/disp_drv_platform.h>
5 #else
6
7 #define ENABLE_DSI_INTERRUPT 1
8
9 #include <linux/delay.h>
10 #include <disp_drv_log.h>
11 #include <linux/time.h>
12 #include <linux/string.h>
13 #include <linux/mutex.h>
14 #include "disp_drv_platform.h"
15
16 #include "lcd_reg.h"
17 #include "lcd_drv.h"
18
19 #include "dsi_reg.h"
20 #include "dsi_drv.h"
21 #include "mach/mt_spm_idle.h"
22 #endif
23
24 extern unsigned int EnableVSyncLog;
25
26 #if ENABLE_DSI_INTERRUPT
27 #include <linux/sched.h>
28 #include <linux/interrupt.h>
29 #include <linux/wait.h>
30 #include <mach/irqs.h>
31 #include "mtkfb.h"
32 #include "fbconfig_kdebug.h"
33 static wait_queue_head_t _dsi_wait_queue;
34 static wait_queue_head_t _dsi_dcs_read_wait_queue;
35 static wait_queue_head_t _dsi_wait_bta_te;
36 static wait_queue_head_t _dsi_wait_ext_te;
37 /* [PLATFORM]-Mod-BEGIN by TCTSZ.yaohui.zeng, 2015/04/15,MTK patch,fix FB suspend/resume DSI issue*/
38 wait_queue_head_t _dsi_wait_vm_done_queue;
39 /* [PLATFORM]-Mod-END by TCTSZ.yaohui.zeng, 2015/04/15*/
40
41 #endif
42 //static unsigned int _dsi_reg_update_wq_flag = 0;
43 static DECLARE_WAIT_QUEUE_HEAD(_dsi_reg_update_wq);
44
45 #include "debug.h"
46
47 //#define ENABLE_DSI_ERROR_REPORT
48
49 /*
50 #define PLL_BASE (0xF0060000)
51 #define DSI_PHY_BASE (0xF0060B00)
52 #define DSI_BASE (0xF0140000)
53 */
54
55
56 #include <mach/sync_write.h>
57 #ifdef OUTREG32
58 #undef OUTREG32
59 #define OUTREG32(x, y) mt65xx_reg_sync_writel(y, x)
60 #endif
61
62 #ifndef OUTREGBIT
63 #define OUTREGBIT(TYPE,REG,bit,value) \
64 do { \
65 TYPE r = *((TYPE*)&INREG32(&REG)); \
66 r.bit = value; \
67 OUTREG32(&REG, AS_UINT32(&r)); \
68 } while (0)
69 #endif
70
71 static PDSI_REGS const DSI_REG = (PDSI_REGS)(DSI_BASE);
72 static PDSI_VM_CMDQ_REGS const DSI_VM_CMD_REG = (PDSI_VM_CMDQ_REGS)(DSI_BASE + 0x134);
73 static PDSI_PHY_REGS const DSI_PHY_REG = (PDSI_PHY_REGS)(MIPI_CONFIG_BASE);
74 static PDSI_CMDQ_REGS const DSI_CMDQ_REG = (PDSI_CMDQ_REGS)(DSI_BASE+0x180);
75 //static PLCD_REGS const LCD_REG = (PLCD_REGS)(LCD_BASE);
76
77
78
79 extern LCM_DRIVER *lcm_drv;
80 static bool dsi_log_on = false;
81 static bool glitch_log_on = false;
82 static bool force_transfer = false;
83 extern BOOL is_early_suspended;
84
85 typedef struct
86 {
87 DSI_REGS regBackup;
88 unsigned int cmdq_size;
89 DSI_CMDQ_REGS cmdqBackup;
90 unsigned int bit_time_ns;
91 unsigned int vfp_period_us;
92 unsigned int vsa_vs_period_us;
93 unsigned int vsa_hs_period_us;
94 unsigned int vsa_ve_period_us;
95 unsigned int vbp_period_us;
96 void (*pIntCallback)(DISP_INTERRUPT_EVENTS);
97 } DSI_CONTEXT;
98
99 static bool s_isDsiPowerOn = FALSE;
100 static DSI_CONTEXT _dsiContext;
101 extern LCM_PARAMS *lcm_params;
102
103 // PLL_clock * 10
104 #define PLL_TABLE_NUM (26)
105 int LCM_DSI_6582_PLL_CLOCK_List[PLL_TABLE_NUM+1]={0,1000,1040,1250,1300,1500,1560,1750,1820,2000,2080,2250,
106 2340,2500,2600,2750,2860,3000,3120,3250,3500,3750,4000,4250,4500,4750,5000};
107
108 DSI_PLL_CONFIG pll_config[PLL_TABLE_NUM+1] =
109 {{0,0,0,0,0,0,0},
110 {2,0,0x3D89D89D,1,0x1B1,0x745,0x745},
111 {2,0,0x40000000,1,0x1B1,0x790,0x790},
112 {1,0,0x26762762,1,0x1B1,0x48B,0x48B},
113 {1,0,0x28000000,1,0x1B1,0x4BA,0x4BA},
114 {1,0,0x2E276276,1,0x1B1,0x574,0x574},
115 {1,0,0x30000000,1,0x1B1,0x5AC,0x5AC},
116 {1,0,0x35D89D89,1,0x1B1,0x65D,0x65D},
117 {1,0,0x38000000,1,0x1B1,0x69E,0x69E},
118 {1,0,0x3D89D89D,1,0x1B1,0x745,0x745},
119 {1,0,0x40000000,1,0x1B1,0x790,0x790},
120 {1,0,0x453B13B1,1,0x1B1,0x82E,0x82E},
121 {1,0,0x48000000,1,0x1B1,0x882,0x882},
122 {0,0,0x26762762,1,0x1B1,0x48B,0x48B},
123 {0,0,0x28000000,1,0x1B1,0x4BA,0x4BA},
124 {0,0,0x2A4EC4EC,1,0x1B1,0x500,0x500},
125 {0,0,0x2C000000,1,0x1B1,0x533,0x533},
126 {0,0,0x2E276276,1,0x1B1,0x574,0x574},
127 {0,0,0x30000000,1,0x1B1,0x5AC,0x5AC},
128 {0,0,0x32000000,1,0x1B1,0x5E8,0x5E8},
129 {0,0,0x35D89D89,1,0x1B1,0x65D,0x65D},
130 {0,0,0x39B13B13,1,0x1B1,0x6D1,0x6D1},
131 {0,0,0x3D89D89D,1,0x1B1,0x745,0x745},
132 {0,0,0x41627627,1,0x1B1,0x7BA,0x7BA},
133 {0,0,0x453B13B1,1,0x1B1,0x82E,0x82E},
134 {0,0,0x4913B13B,1,0x1B1,0x8A2,0x8A2},
135 {0,0,0x4CEC4EC4,1,0x1B1,0x917,0x917},
136 };
137
138 #ifndef BUILD_UBOOT
139
140 #ifndef MT65XX_NEW_DISP
141 static bool dsi_esd_recovery = false;
142 static bool dsi_int_te_enabled = false;
143 static unsigned int dsi_int_te_period = 1;
144 static unsigned int dsi_dpi_isr_count = 0;
145 #endif
146 //static unsigned int dsi_noncont_clk_period = 1;
147 static bool dsi_noncont_clk_enabled = true;
148 static bool dsi_glitch_enable = false;
149 unsigned long g_handle_esd_flag;
150
151 static volatile bool lcdStartTransfer = false;
152 static volatile bool isTeSetting = false;
153 static volatile bool dsiTeEnable = false;
154 static volatile bool dsiTeExtEnable = false;
155
156 #endif
157
158 #ifdef BUILD_UBOOT
159 static long int get_current_time_us(void)
160 {
161 return 0; ///TODO: fix me
162 }
163 #else
164 static long int get_current_time_us(void)
165 {
166 struct timeval t;
167 do_gettimeofday(&t);
168 return (t.tv_sec & 0xFFF) * 1000000 + t.tv_usec;
169 }
170 #endif
171 #if 0
172 unsigned int custom_pll_clock_remap(int input_mipi_clock)
173 {
174 int i;
175 unsigned int ret = 0;
176 int mipi_clock=10*input_mipi_clock;
177 printk("DSI: custom_pll_clock_remap,mipi clock should be %d!!!\n", mipi_clock);
178
179 if(mipi_clock == 0)return 0;
180
181 if((mipi_clock>0)&&(mipi_clock<LCM_DSI_6582_PLL_CLOCK_List[1]))
182 // lcm_params->dsi.PLL_CLOCK=1;
183 return 1;
184
185 if(mipi_clock>LCM_DSI_6582_PLL_CLOCK_List[PLL_TABLE_NUM])
186 // lcm_params->dsi.PLL_CLOCK=50;
187 return PLL_TABLE_NUM;
188
189 for(i=1;i<PLL_TABLE_NUM+1;i++)
190 {
191 ASSERT(LCM_DSI_6582_PLL_CLOCK_List[i] < LCM_DSI_6582_PLL_CLOCK_List[i+1]);
192 if((mipi_clock>=LCM_DSI_6582_PLL_CLOCK_List[i])&&(mipi_clock<=LCM_DSI_6582_PLL_CLOCK_List[i+1]))
193 {
194 if((mipi_clock-LCM_DSI_6582_PLL_CLOCK_List[i])<=(LCM_DSI_6582_PLL_CLOCK_List[i+1]-mipi_clock))
195 {
196 // lcm_params->dsi.PLL_CLOCK=i+1;
197 ret = i;
198 break;
199 }
200 else
201 {
202 // lcm_params->dsi.PLL_CLOCK=i+2;
203 ret = i+1;
204 break;
205 }
206 }
207 }
208 printk("custom_pll_clock_remap,remap clock is %d!!!\n", ret);
209 return ret;
210 }
211 #endif
212 static void lcm_mdelay(UINT32 ms)
213 {
214 udelay(1000 * ms);
215 }
216 void DSI_Enable_Log(bool enable)
217 {
218 dsi_log_on = enable;
219 }
220
221 unsigned int try_times = 30;
222
223 static wait_queue_head_t _vsync_wait_queue;
224 static bool dsi_vsync = false;
225 static bool wait_dsi_vsync = false;
226 static struct hrtimer hrtimer_vsync;
227 #define VSYNC_US_TO_NS(x) (x * 1000)
228 static unsigned int vsync_timer = 0;
229 static bool wait_vm_done_irq = false;
230 #if ENABLE_DSI_INTERRUPT
231 static irqreturn_t _DSI_InterruptHandler(int irq, void *dev_id)
232 {
233 DSI_INT_STATUS_REG status = DSI_REG->DSI_INTSTA;
234 #ifdef ENABLE_DSI_ERROR_REPORT
235 static unsigned int prev_error = 0;
236 #endif
237
238 MMProfileLogEx(MTKFB_MMP_Events.DSIIRQ, MMProfileFlagPulse, *(unsigned int*)&status, lcdStartTransfer);
239 if(dsi_log_on)
240 printk("DSI IRQ, value = 0x%x!!\n", INREG32(0xF400C00C));
241
242 if (status.RD_RDY)
243 {
244 ///write clear RD_RDY interrupt
245
246 /// write clear RD_RDY interrupt must be before DSI_RACK
247 /// because CMD_DONE will raise after DSI_RACK,
248 /// so write clear RD_RDY after that will clear CMD_DONE too
249 #ifdef ENABLE_DSI_ERROR_REPORT
250 {
251 unsigned int read_data[4];
252 OUTREG32(&read_data[0], AS_UINT32(&DSI_REG->DSI_RX_DATA0));
253 OUTREG32(&read_data[1], AS_UINT32(&DSI_REG->DSI_RX_DATA1));
254 OUTREG32(&read_data[2], AS_UINT32(&DSI_REG->DSI_RX_DATA2));
255 OUTREG32(&read_data[3], AS_UINT32(&DSI_REG->DSI_TRIG_STA));
256 if (dsi_log_on)
257 {
258 if ((read_data[0] & 0x3) == 0x02)
259 {
260 if (read_data[0] & (~prev_error))
261 printk("[DSI] Detect DSI error. prev:0x%08X new:0x%08X\n", prev_error, read_data[0]);
262 }
263 else if ((read_data[1] & 0x3) == 0x02)
264 {
265 if (read_data[1] & (~prev_error))
266 printk("[DSI] Detect DSI error. prev:0x%08X new:0x%08X\n", prev_error, read_data[1]);
267 }
268 }
269 MMProfileLogEx(MTKFB_MMP_Events.DSIRead, MMProfileFlagStart, read_data[0], read_data[1]);
270 MMProfileLogEx(MTKFB_MMP_Events.DSIRead, MMProfileFlagEnd, read_data[2], read_data[3]);
271 }
272 #endif
273 do
274 {
275 ///send read ACK
276 //DSI_REG->DSI_RACK.DSI_RACK = 1;
277 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
278 } while(DSI_REG->DSI_INTSTA.BUSY);
279
280 MASKREG32(&DSI_REG->DSI_INTSTA, 0x1, 0x0);
281 wake_up_interruptible(&_dsi_dcs_read_wait_queue);
282 if(_dsiContext.pIntCallback)
283 _dsiContext.pIntCallback(DISP_DSI_READ_RDY_INT);
284 }
285
286 if (status.CMD_DONE)
287 {
288 if (lcdStartTransfer)
289 {
290 // The last screen update has finished.
291 if(_dsiContext.pIntCallback)
292 _dsiContext.pIntCallback(DISP_DSI_CMD_DONE_INT);
293 #ifdef SPM_SODI_ENABLED
294 spm_enable_sodi();
295 #endif
296 DBG_OnLcdDone();
297 if(dsi_glitch_enable){
298 DSI_clk_HS_mode(0);
299 }
300 }
301
302 // clear flag & wait for next trigger
303 lcdStartTransfer = false;
304
305 //DSI_REG->DSI_INTSTA.CMD_DONE = 0;
306 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,0);
307
308 wake_up_interruptible(&_dsi_wait_queue);
309 //if(_dsiContext.pIntCallback)
310 // _dsiContext.pIntCallback(DISP_DSI_CMD_DONE_INT);
311 //MASKREG32(&DSI_REG->DSI_INTSTA, 0x2, 0x0);
312 }
313
314 if (status.TE_RDY)
315 {
316 DBG_OnTeDelayDone();
317
318 // Write clear RD_RDY
319 //DSI_REG->DSI_INTSTA.TE_RDY = 0;
320 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,TE_RDY,0);
321
322 // Set DSI_RACK to let DSI idle
323 //DSI_REG->DSI_RACK.DSI_RACK = 1;
324 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
325
326 wake_up_interruptible(&_dsi_wait_bta_te);
327
328
329 #ifndef BUILD_UBOOT
330 if(wait_dsi_vsync)//judge if wait vsync
331 {
332 if (EnableVSyncLog)
333 printk("[DSI] VSync2\n");
334 if(-1 != hrtimer_try_to_cancel(&hrtimer_vsync))
335 {
336 dsi_vsync = true;
337 //hrtimer_try_to_cancel(&hrtimer_vsync);
338 if (EnableVSyncLog)
339 printk("[DSI] VSync3\n");
340 wake_up_interruptible(&_vsync_wait_queue);
341 }
342 //printk("TE signal, and wake up\n");
343 }
344 #endif
345 }
346 if (status.EXT_TE)
347 {
348 DBG_OnTeDelayDone();
349
350 // Write clear RD_RDY
351 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,EXT_TE,0);
352
353 wake_up_interruptible(&_dsi_wait_ext_te);
354
355 #ifndef BUILD_UBOOT
356 if(wait_dsi_vsync)//judge if wait vsync
357 {
358 if (EnableVSyncLog)
359 printk("[DSI] VSync2\n");
360
361 if(-1 != hrtimer_try_to_cancel(&hrtimer_vsync))
362 {
363 dsi_vsync = true;
364 //hrtimer_try_to_cancel(&hrtimer_vsync);
365 if (EnableVSyncLog)
366 printk("[DSI] VSync3\n");
367
368 wake_up_interruptible(&_vsync_wait_queue);
369 }
370 //printk("TE signal, and wake up\n");
371 }
372 #endif
373 }
374
375
376 if (status.VM_DONE)
377 {
378 // DBG_OnTeDelayDone();
379 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,VM_DONE,0);
380 if(_dsiContext.pIntCallback)
381 _dsiContext.pIntCallback(DISP_DSI_VMDONE_INT);
382 if(dsi_log_on)
383 printk("DSI VM done IRQ!!\n");
384 // Write clear VM_Done
385 //DSI_REG->DSI_INTSTA.VM_DONE= 0;
386 wake_up_interruptible(&_dsi_wait_vm_done_queue);
387 if(dsi_glitch_enable){
388 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 1, 22);
389 if(!is_early_suspended && !wait_vm_done_irq){
390 if(1 == DSI_Detect_CLK_Glitch()){
391 printk("VM Done detect glitch fail!!,%d\n",__LINE__);
392 }
393 // DSI_EnableClk();
394 DSI_Start();
395 }
396 }
397 }
398
399 return IRQ_HANDLED;
400
401 }
402 #endif
403 #ifndef BUILD_UBOOT
404 void DSI_GetVsyncCnt(void)
405 {
406 }
407 enum hrtimer_restart dsi_te_hrtimer_func(struct hrtimer *timer)
408 {
409 // long long ret;
410 if (EnableVSyncLog)
411 printk("[DSI] VSync0\n");
412 if(wait_dsi_vsync)
413 {
414 dsi_vsync = true;
415
416 if (EnableVSyncLog)
417 printk("[DSI] VSync1\n");
418 wake_up_interruptible(&_vsync_wait_queue);
419 }
420 // ret = hrtimer_forward_now(timer, ktime_set(0, VSYNC_US_TO_NS(vsync_timer)));
421 // printk("hrtimer callback\n");
422 return HRTIMER_NORESTART;
423 }
424 #endif
425
426
427 //static unsigned int vsync_wait_time = 0;
428 void DSI_WaitTE(void)
429 {
430 #ifndef BUILD_UBOOT
431 wait_dsi_vsync = true;
432
433 hrtimer_start(&hrtimer_vsync, ktime_set(0, VSYNC_US_TO_NS(vsync_timer)), HRTIMER_MODE_REL);
434 if (EnableVSyncLog)
435 printk("[DSI] +VSync\n");
436 wait_event_interruptible(_vsync_wait_queue, dsi_vsync);
437 if (EnableVSyncLog)
438 printk("[DSI] -VSync\n");
439 dsi_vsync = false;
440 wait_dsi_vsync = false;
441 #endif
442 }
443 void DSI_InitVSYNC(unsigned int vsync_interval)
444 {
445 #ifndef BUILD_UBOOT
446 ktime_t ktime;
447 vsync_timer = vsync_interval;
448 ktime = ktime_set(0, VSYNC_US_TO_NS(vsync_timer));
449 hrtimer_init(&hrtimer_vsync, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
450 hrtimer_vsync.function = dsi_te_hrtimer_func;
451 // hrtimer_start(&hrtimer_vsync, ktime, HRTIMER_MODE_REL);
452 #endif
453 }
454
455 /* [PLATFORM]-Mod-BEGIN by TCTSZ.yaohui.zeng, 2015/04/15,MTK patch,fix FB suspend/resume DSI issue*/
456 BOOL _IsEngineBusy(void)
457 {
458 DSI_INT_STATUS_REG status;
459
460 status = DSI_REG->DSI_INTSTA;
461
462 if (status.BUSY)
463 return TRUE;
464 return FALSE;
465 }
466 /* [PLATFORM]-Mod-END by TCTSZ.yaohui.zeng, 2015/04/15*/
467
468
469 static void _WaitForEngineNotBusy(void)
470 {
471 int timeOut;
472 #if ENABLE_DSI_INTERRUPT
473
474 long int time;
475 static const long WAIT_TIMEOUT = 2 * HZ; // 2 sec
476 #endif
477
478 if (DSI_REG->DSI_MODE_CTRL.MODE)
479 return ;
480
481 timeOut = 200;
482
483 #if ENABLE_DSI_INTERRUPT
484 time = get_current_time_us();
485
486 if (in_interrupt())
487 {
488 // perform busy waiting if in interrupt context
489 while(_IsEngineBusy()) {
490 msleep(1);
491 if (--timeOut < 0) {
492
493 DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", " Wait for DSI engine not busy timeout!!!(Wait %d us)\n", get_current_time_us() - time);
494 DSI_DumpRegisters();
495 DSI_Reset();
496
497 break;
498 }
499 }
500 }
501 else
502 {
503 while (DSI_REG->DSI_INTSTA.BUSY || DSI_REG->DSI_INTSTA.CMD_DONE)
504 {
505 long ret = wait_event_interruptible_timeout(_dsi_wait_queue,
506 !_IsEngineBusy() && !(DSI_REG->DSI_INTSTA.CMD_DONE),
507 WAIT_TIMEOUT);
508 if (0 == ret) {
509 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine not busy timeout!!!\n");
510 DSI_DumpRegisters();
511 DSI_Reset();
512 //dsiTeEnable = false;
513 }
514 }
515 }
516 #else
517
518 while(_IsEngineBusy()) {
519 mdelay(10);
520 /*printk("xuecheng, dsi wait\n");*/
521 if (--timeOut < 0) {
522 DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", " Wait for DSI engine not busy timeout!!!\n");
523 DSI_DumpRegisters();
524 DSI_Reset();
525 dsiTeEnable = false;
526 dsiTeExtEnable = false;
527 break;
528 }
529 }
530 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
531 #endif
532 }
533 void hdmi_dsi_waitnotbusy(void)
534 {
535 _WaitForEngineNotBusy();
536 }
537
538
539
540 DSI_STATUS DSI_BackupRegisters(void)
541 {
542 DSI_REGS *regs = &(_dsiContext.regBackup);
543
544 //memcpy((void*)&(_dsiContext.regBackup), (void*)DSI_BASE, sizeof(DSI_REGS));
545
546 OUTREG32(&regs->DSI_INTEN, AS_UINT32(&DSI_REG->DSI_INTEN));
547 OUTREG32(&regs->DSI_MODE_CTRL, AS_UINT32(&DSI_REG->DSI_MODE_CTRL));
548 OUTREG32(&regs->DSI_TXRX_CTRL, AS_UINT32(&DSI_REG->DSI_TXRX_CTRL));
549 OUTREG32(&regs->DSI_PSCTRL, AS_UINT32(&DSI_REG->DSI_PSCTRL));
550
551 OUTREG32(&regs->DSI_VSA_NL, AS_UINT32(&DSI_REG->DSI_VSA_NL));
552 OUTREG32(&regs->DSI_VBP_NL, AS_UINT32(&DSI_REG->DSI_VBP_NL));
553 OUTREG32(&regs->DSI_VFP_NL, AS_UINT32(&DSI_REG->DSI_VFP_NL));
554 OUTREG32(&regs->DSI_VACT_NL, AS_UINT32(&DSI_REG->DSI_VACT_NL));
555
556 OUTREG32(&regs->DSI_HSA_WC, AS_UINT32(&DSI_REG->DSI_HSA_WC));
557 OUTREG32(&regs->DSI_HBP_WC, AS_UINT32(&DSI_REG->DSI_HBP_WC));
558 OUTREG32(&regs->DSI_HFP_WC, AS_UINT32(&DSI_REG->DSI_HFP_WC));
559 OUTREG32(&regs->DSI_BLLP_WC, AS_UINT32(&DSI_REG->DSI_BLLP_WC));
560
561 OUTREG32(&regs->DSI_HSTX_CKL_WC, AS_UINT32(&DSI_REG->DSI_HSTX_CKL_WC));
562 OUTREG32(&regs->DSI_MEM_CONTI, AS_UINT32(&DSI_REG->DSI_MEM_CONTI));
563
564 OUTREG32(&regs->DSI_PHY_TIMECON0, AS_UINT32(&DSI_REG->DSI_PHY_TIMECON0));
565 OUTREG32(&regs->DSI_PHY_TIMECON1, AS_UINT32(&DSI_REG->DSI_PHY_TIMECON1));
566 OUTREG32(&regs->DSI_PHY_TIMECON2, AS_UINT32(&DSI_REG->DSI_PHY_TIMECON2));
567 OUTREG32(&regs->DSI_PHY_TIMECON3, AS_UINT32(&DSI_REG->DSI_PHY_TIMECON3));
568 OUTREG32(&regs->DSI_VM_CMD_CON, AS_UINT32(&DSI_REG->DSI_VM_CMD_CON));
569 return DSI_STATUS_OK;
570 }
571
572
573 DSI_STATUS DSI_RestoreRegisters(void)
574 {
575 DSI_REGS *regs = &(_dsiContext.regBackup);
576
577 OUTREG32(&DSI_REG->DSI_INTEN, AS_UINT32(&regs->DSI_INTEN));
578 OUTREG32(&DSI_REG->DSI_MODE_CTRL, AS_UINT32(&regs->DSI_MODE_CTRL));
579 OUTREG32(&DSI_REG->DSI_TXRX_CTRL, AS_UINT32(&regs->DSI_TXRX_CTRL));
580 OUTREG32(&DSI_REG->DSI_PSCTRL, AS_UINT32(&regs->DSI_PSCTRL));
581
582 OUTREG32(&DSI_REG->DSI_VSA_NL, AS_UINT32(&regs->DSI_VSA_NL));
583 OUTREG32(&DSI_REG->DSI_VBP_NL, AS_UINT32(&regs->DSI_VBP_NL));
584 OUTREG32(&DSI_REG->DSI_VFP_NL, AS_UINT32(&regs->DSI_VFP_NL));
585 OUTREG32(&DSI_REG->DSI_VACT_NL, AS_UINT32(&regs->DSI_VACT_NL));
586
587 OUTREG32(&DSI_REG->DSI_HSA_WC, AS_UINT32(&regs->DSI_HSA_WC));
588 OUTREG32(&DSI_REG->DSI_HBP_WC, AS_UINT32(&regs->DSI_HBP_WC));
589 OUTREG32(&DSI_REG->DSI_HFP_WC, AS_UINT32(&regs->DSI_HFP_WC));
590 OUTREG32(&DSI_REG->DSI_BLLP_WC, AS_UINT32(&regs->DSI_BLLP_WC));
591
592 OUTREG32(&DSI_REG->DSI_HSTX_CKL_WC, AS_UINT32(&regs->DSI_HSTX_CKL_WC));
593 OUTREG32(&DSI_REG->DSI_MEM_CONTI, AS_UINT32(&regs->DSI_MEM_CONTI));
594
595 OUTREG32(&DSI_REG->DSI_PHY_TIMECON0, AS_UINT32(&regs->DSI_PHY_TIMECON0));
596 OUTREG32(&DSI_REG->DSI_PHY_TIMECON1, AS_UINT32(&regs->DSI_PHY_TIMECON1));
597 OUTREG32(&DSI_REG->DSI_PHY_TIMECON2, AS_UINT32(&regs->DSI_PHY_TIMECON2));
598 OUTREG32(&DSI_REG->DSI_PHY_TIMECON3, AS_UINT32(&regs->DSI_PHY_TIMECON3));
599 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&regs->DSI_VM_CMD_CON));
600 return DSI_STATUS_OK;
601 }
602
603 static void _ResetBackupedDSIRegisterValues(void)
604 {
605 DSI_REGS *regs = &_dsiContext.regBackup;
606 memset((void*)regs, 0, sizeof(DSI_REGS));
607 }
608
609
610 static void DSI_BackUpCmdQ(void)
611 {
612 unsigned int i;
613 DSI_CMDQ_REGS *regs = &(_dsiContext.cmdqBackup);
614
615 _dsiContext.cmdq_size = AS_UINT32(&DSI_REG->DSI_CMDQ_SIZE);
616
617 for (i=0; i<_dsiContext.cmdq_size; i++)
618 OUTREG32(&regs->data[i], AS_UINT32(&DSI_CMDQ_REG->data[i]));
619 }
620
621
622 static void DSI_RestoreCmdQ(void)
623 {
624 unsigned int i;
625 DSI_CMDQ_REGS *regs = &(_dsiContext.cmdqBackup);
626
627 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, AS_UINT32(&_dsiContext.cmdq_size));
628
629 for (i=0; i<_dsiContext.cmdq_size; i++)
630 OUTREG32(&DSI_CMDQ_REG->data[i], AS_UINT32(&regs->data[i]));
631 }
632
633 static void _DSI_RDMA0_IRQ_Handler(unsigned int param);
634 spinlock_t dsi_glitch_detect_lock;
635 static DSI_STATUS DSI_TE_Setting(void)
636 {
637 //return DSI_STATUS_OK;
638 if(isTeSetting)
639 {
640 return DSI_STATUS_OK;
641 }
642
643 if(lcm_params->dsi.mode == CMD_MODE && lcm_params->dsi.lcm_ext_te_enable == TRUE)
644 {
645 //Enable EXT TE
646 dsiTeEnable = false;
647 dsiTeExtEnable = true;
648 }
649 else
650 {
651 //Enable BTA TE
652 dsiTeEnable = true;
653 dsiTeExtEnable = false;
654 }
655
656 isTeSetting = true;
657
658 return DSI_STATUS_OK;
659 }
660
661 DSI_STATUS DSI_Init(BOOL isDsiPoweredOn)
662 {
663 DSI_STATUS ret = DSI_STATUS_OK;
664
665 memset(&_dsiContext, 0, sizeof(_dsiContext));
666 OUTREG32(DISPSYS_BASE + 0x4C, 0x0);
667 if (isDsiPoweredOn) {
668 DSI_BackupRegisters();
669 } else {
670 _ResetBackupedDSIRegisterValues();
671 }
672 ret = DSI_PowerOn();
673
674 DSI_TE_Setting();
675 OUTREG32(&DSI_REG->DSI_MEM_CONTI, DSI_WMEM_CONTI);
676
677 ASSERT(ret == DSI_STATUS_OK);
678
679 #if ENABLE_DSI_INTERRUPT
680 init_waitqueue_head(&_dsi_wait_queue);
681 init_waitqueue_head(&_dsi_dcs_read_wait_queue);
682 init_waitqueue_head(&_dsi_wait_bta_te);
683 init_waitqueue_head(&_dsi_wait_ext_te);
684 init_waitqueue_head(&_dsi_wait_vm_done_queue);
685 if (request_irq(MT6582_DISP_DSI_IRQ_ID,
686 _DSI_InterruptHandler, IRQF_TRIGGER_LOW, MTKFB_DRIVER, NULL) < 0)
687 {
688 DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", "fail to request DSI irq\n");
689 return DSI_STATUS_ERROR;
690 }
691 //mt65xx_irq_unmask(MT6577_DSI_IRQ_ID);
692 //DSI_REG->DSI_INTEN.CMD_DONE=1;
693 //DSI_REG->DSI_INTEN.RD_RDY=1;
694 //DSI_REG->DSI_INTEN.TE_RDY = 1;
695 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,1);
696 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
697 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,TE_RDY,1);
698 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,EXT_TE,1);
699
700 init_waitqueue_head(&_vsync_wait_queue);
701 //DSI_REG->DSI_INTEN.VM_DONE = 1;
702 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,VM_DONE,1);
703 init_waitqueue_head(&_vsync_wait_queue);
704
705
706 #endif
707 if (lcm_params->dsi.mode == (LCM_DSI_MODE_CON)DSI_CMD_MODE)
708 disp_register_irq(DISP_MODULE_RDMA0, _DSI_RDMA0_IRQ_Handler);
709 spin_lock_init(&dsi_glitch_detect_lock);
710 return DSI_STATUS_OK;
711 }
712
713
714 DSI_STATUS DSI_Deinit(void)
715 {
716 DSI_STATUS ret = DSI_PowerOff();
717
718 ASSERT(ret == DSI_STATUS_OK);
719
720 return DSI_STATUS_OK;
721 }
722
723 #ifdef BUILD_UBOOT
724 DSI_STATUS DSI_PowerOn(void)
725 {
726 if (!s_isDsiPowerOn)
727 {
728 MASKREG32(0x14000110, 0x3, 0x0);
729 printf("[DISP] - uboot - DSI_PowerOn. 0x%8x,0x%8x,0x%8x\n", INREG32(0x14000110), INREG32(0x14000114), INREG32(0x14000118));
730
731 DSI_RestoreRegisters();
732 //DSI_WaitForEngineNotBusy();
733 s_isDsiPowerOn = TRUE;
734 }
735
736 return DSI_STATUS_OK;
737 }
738
739
740 DSI_STATUS DSI_PowerOff(void)
741 {
742 if (s_isDsiPowerOn)
743 {
744 BOOL ret = TRUE;
745 //DSI_WaitForEngineNotBusy();
746 DSI_BackupRegisters();
747
748 OUTREG32(&DSI_REG->DSI_INTSTA, 0);
749 MASKREG32(0x14000110, 0x3, 0x3);
750 printf("[DISP] - uboot - DSI_PowerOff. 0x%8x,0x%8x,0x%8x\n", INREG32(0x14000110), INREG32(0x14000114), INREG32(0x14000118));
751
752 s_isDsiPowerOn = FALSE;
753 }
754
755 return DSI_STATUS_OK;
756 }
757
758 #else
759 DSI_STATUS DSI_PowerOn(void)
760 {
761 int ret = 0;
762 #if 1
763 if (!s_isDsiPowerOn)
764 {
765 ret += enable_clock(MT_CG_DISP1_DSI_ENGINE, "DSI");
766 ret += enable_clock(MT_CG_DISP1_DSI_DIGITAL, "DSI");
767 ret += enable_clock(MT_CG_DISP0_DISP_UFOE, "UFOE");
768 if(ret > 0)
769 {
770 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "DSI power manager API return FALSE\n");
771 }
772
773 s_isDsiPowerOn = TRUE;
774 }
775 #endif
776 // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
777 return DSI_STATUS_OK;
778 }
779
780
781 DSI_STATUS DSI_PowerOff(void)
782 {
783 int ret = 0;
784
785 #if 1
786 if (s_isDsiPowerOn)
787 {
788 ret += disable_clock(MT_CG_DISP1_DSI_ENGINE, "DSI");
789 ret += disable_clock(MT_CG_DISP1_DSI_DIGITAL, "DSI");
790 ret += disable_clock(MT_CG_DISP0_DISP_UFOE, "UFOE");
791
792 if(ret > 0)
793 {
794 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "DSI power manager API return FALSE\n");
795 }
796
797 s_isDsiPowerOn = FALSE;
798 }
799 #endif
800
801 return DSI_STATUS_OK;
802 }
803 #endif
804
805 DSI_STATUS DSI_WaitForNotBusy(void)
806 {
807 _WaitForEngineNotBusy();
808
809 return DSI_STATUS_OK;
810 }
811
812
813 static void DSI_WaitBtaTE(void)
814 {
815 DSI_T0_INS t0;
816 #if ENABLE_DSI_INTERRUPT
817 long ret;
818 static const long WAIT_TIMEOUT = 2 * HZ; // 2 sec
819 #else
820 long int dsi_current_time;
821 #endif
822
823 if(DSI_REG->DSI_MODE_CTRL.MODE != CMD_MODE)
824 return;
825
826 _WaitForEngineNotBusy();
827
828 DSI_clk_HS_mode(0);
829 // backup command queue setting.
830 DSI_BackUpCmdQ();
831
832 t0.CONFG = 0x20; ///TE
833 t0.Data0 = 0;
834 t0.Data_ID = 0;
835 t0.Data1 = 0;
836
837 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
838 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
839
840 //DSI_REG->DSI_START.DSI_START=0;
841 //DSI_REG->DSI_START.DSI_START=1;
842 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
843 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
844
845 // wait BTA TE command complete.
846 _WaitForEngineNotBusy();
847
848 // restore command queue setting.
849 DSI_RestoreCmdQ();
850
851 #if ENABLE_DSI_INTERRUPT
852
853 ret = wait_event_interruptible_timeout(_dsi_wait_bta_te,
854 !_IsEngineBusy(),
855 WAIT_TIMEOUT);
856
857 if (0 == ret) {
858 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "Wait for _dsi_wait_bta_te(DSI_INTSTA.TE_RDY) ready timeout!!!\n");
859
860 // Set DSI_RACK to let DSI idle
861 //DSI_REG->DSI_RACK.DSI_RACK = 1;
862 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
863
864 DSI_DumpRegisters();
865 ///do necessary reset here
866 DSI_Reset();
867 dsiTeEnable = false;//disable TE
868 return;
869 }
870
871 // After setting DSI_RACK, it needs to wait for CMD_DONE interrupt.
872 _WaitForEngineNotBusy();
873
874 #else
875
876 dsi_current_time = get_current_time_us();
877
878 while(DSI_REG->DSI_INTSTA.TE_RDY == 0) // polling TE_RDY
879 {
880 if(get_current_time_us() - dsi_current_time > 100*1000)
881 {
882 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "Wait for TE_RDY timeout!!!\n");
883
884 // Set DSI_RACK to let DSI idle
885 //DSI_REG->DSI_RACK.DSI_RACK = 1;
886 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
887
888 DSI_DumpRegisters();
889
890 //do necessary reset here
891 DSI_Reset();
892 dsiTeEnable = false;//disable TE
893 break;
894 }
895 }
896
897 // Write clear RD_RDY
898 //DSI_REG->DSI_INTSTA.TE_RDY = 0;
899 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,TE_RDY,0);
900
901 // Set DSI_RACK to let DSI idle
902 //DSI_REG->DSI_RACK.DSI_RACK = 1;
903 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
904 if(!dsiTeEnable){
905 DSI_LP_Reset();
906 return;
907 }
908 dsi_current_time = get_current_time_us();
909
910 while(DSI_REG->DSI_INTSTA.CMD_DONE == 0) // polling CMD_DONE
911 {
912 if(get_current_time_us() - dsi_current_time > 100*1000)
913 {
914 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "Wait for CMD_DONE timeout!!!\n");
915
916 // Set DSI_RACK to let DSI idle
917 //DSI_REG->DSI_RACK.DSI_RACK = 1;
918 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
919
920 DSI_DumpRegisters();
921
922 ///do necessary reset here
923 DSI_Reset();
924 dsiTeEnable = false;//disable TE
925 break;
926 }
927 }
928
929 // Write clear CMD_DONE
930 //DSI_REG->DSI_INTSTA.CMD_DONE = 0;
931 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,0);
932
933 #endif
934 DSI_LP_Reset();
935 }
936
937 static void DSI_WaitExternalTE(void)
938 {
939 #if ENABLE_DSI_INTERRUPT
940 long ret;
941 static const long WAIT_TIMEOUT = 2 * HZ; // 2 sec
942 #else
943 long int dsi_current_time;
944 #endif
945
946
947 if(DSI_REG->DSI_MODE_CTRL.MODE != CMD_MODE)
948 return;
949
950
951 OUTREGBIT(DSI_TXRX_CTRL_REG,DSI_REG->DSI_TXRX_CTRL,EXT_TE_EN,1);
952 OUTREGBIT(DSI_TXRX_CTRL_REG,DSI_REG->DSI_TXRX_CTRL,EXT_TE_EDGE,0);
953
954 #if ENABLE_DSI_INTERRUPT
955 ret = wait_event_interruptible_timeout(_dsi_wait_ext_te,
956 !_IsEngineBusy(),
957 WAIT_TIMEOUT);
958
959 if (0 == ret) {
960 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "Wait for _dsi_wait_ext_te(DSI_INTSTA.EXT_TE) ready timeout!!!\n");
961
962 OUTREGBIT(DSI_TXRX_CTRL_REG,DSI_REG->DSI_TXRX_CTRL,EXT_TE_EN,0);
963 DSI_DumpRegisters();
964 ///do necessary reset here
965 DSI_Reset();
966 dsiTeExtEnable = false;//disable TE
967
968 return;
969 }
970
971 #else
972 dsi_current_time = get_current_time_us();
973
974 while(DSI_REG->DSI_INTSTA.EXT_TE == 0) // polling EXT_TE
975 {
976 if(get_current_time_us() - dsi_current_time > 100*1000)
977 {
978 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", "Wait for EXT_TE timeout!!!\n");
979
980 DSI_DumpRegisters();
981
982 //do necessary reset here
983 DSI_Reset();
984 dsiTeExtEnable = false;//disable TE
985
986 break;
987 }
988 }
989
990 // Write clear EXT_TE
991 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,EXT_TE,0);
992
993 if(!dsiTeExtEnable){
994 DSI_LP_Reset();
995 return;
996 }
997
998 #endif
999
1000 DSI_LP_Reset();
1001 }
1002
1003 DSI_STATUS DSI_EnableClk(void)
1004 {
1005 //_WaitForEngineNotBusy();
1006
1007 //DSI_REG->DSI_START.DSI_START=0;
1008 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_EN,1);
1009
1010 return DSI_STATUS_OK;
1011 }
1012 DSI_STATUS DSI_Start(void)
1013 {
1014 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1015 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1016 return DSI_STATUS_OK;
1017 }
1018 DSI_STATUS DSI_EnableVM_CMD(void)
1019 {
1020 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,VM_CMD_START,0);
1021 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,VM_CMD_START,1);
1022 return DSI_STATUS_OK;
1023 }
1024 DSI_STATUS DSI_StartTransfer(bool isMutexLocked)
1025 {
1026 // needStartDSI = 1: For command mode or the first time of video mode.
1027 // After the first time of video mode. Configuration is applied in ConfigurationUpdateTask.
1028 extern struct mutex OverlaySettingMutex;
1029 #ifdef SPM_SODI_ENABLED
1030 if(DSI_REG->DSI_MODE_CTRL.MODE == CMD_MODE)
1031 {
1032 spm_disable_sodi();
1033 }
1034 #endif
1035 if (!isMutexLocked) {
1036 disp_path_get_mutex();
1037 mutex_lock(&OverlaySettingMutex);
1038 LCD_ConfigOVL();
1039 }
1040 // Insert log for trigger point.
1041 DBG_OnTriggerLcd();
1042
1043 if (dsiTeEnable)
1044 DSI_WaitBtaTE();
1045 if(dsiTeExtEnable)
1046 {
1047 DSI_WaitExternalTE();
1048 }
1049
1050 if(dsi_glitch_enable){
1051 spin_lock_irq(&dsi_glitch_detect_lock);
1052 if(1 == DSI_Detect_CLK_Glitch()){
1053 if(!force_transfer){
1054 spin_unlock_irq(&dsi_glitch_detect_lock);
1055 if (!isMutexLocked) {
1056 mutex_unlock(&OverlaySettingMutex);
1057 disp_path_release_mutex();
1058 }
1059 if(_dsiContext.pIntCallback)
1060 _dsiContext.pIntCallback(DISP_DSI_CMD_DONE_INT);
1061 return DSI_STATUS_OK;
1062 }
1063 }
1064 spin_unlock_irq(&dsi_glitch_detect_lock);
1065 }
1066 _WaitForEngineNotBusy();
1067 lcdStartTransfer = true;
1068 // To trigger frame update.
1069 DSI_clk_HS_mode(1);
1070 DSI_Start();
1071 if (!isMutexLocked) {
1072 mutex_unlock(&OverlaySettingMutex);
1073 disp_path_release_mutex();
1074 }
1075 return DSI_STATUS_OK;
1076 }
1077
1078 unsigned int glitch_detect_fail_cnt = 0;
1079
1080 static unsigned int DSI_Detect_CLK_Glitch_Default(void)
1081 {
1082 DSI_T0_INS t0;
1083 char i;
1084 int read_timeout_cnt=10000;
1085 int read_timeout_ret = 0;
1086 unsigned long long start_time,end_time;
1087 DSI_RX_DATA_REG read_data0;
1088 DSI_RX_DATA_REG read_data1;
1089
1090 if(glitch_detect_fail_cnt>2){
1091 return 0;
1092 }
1093
1094 while(DSI_REG->DSI_INTSTA.BUSY);
1095 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
1096
1097 DSI_BackUpCmdQ();
1098 DSI_SetMode(CMD_MODE);
1099 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,0);
1100 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,0);
1101
1102 OUTREG32(&DSI_CMDQ_REG->data[0], 0x00340500);//turn off TE
1103 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1104
1105 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1106 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1107 while(DSI_REG->DSI_INTSTA.CMD_DONE == 0);
1108 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,0);
1109
1110 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 0);
1111 #if 1
1112 OUTREG32(&DSI_CMDQ_REG->data[0], 0x00ff1500);
1113 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1114
1115 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1116 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1117 while(DSI_REG->DSI_INTSTA.CMD_DONE == 0);
1118 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,0);
1119 #endif
1120 for(i=0;i<try_times;i++)
1121 {
1122 DSI_clk_HS_mode(0);
1123
1124 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 9);
1125 while((INREG32(&DSI_REG->DSI_STATE_DBG0)&0x1) == 0); // polling bit0
1126
1127 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
1128 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,1);//reset
1129 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
1130
1131 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 10);
1132 if(i>0)
1133 {
1134 MASKREG32(MIPI_CONFIG_BASE + 0x04, 0x20, 0x0);
1135 }
1136 DSI_clk_HS_mode(1);
1137 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 1);
1138 while((INREG32(&DSI_REG->DSI_STATE_DBG0)&0x40000) == 0); // polling bit18 start
1139 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 2);
1140 if(i>0)
1141 {
1142 MASKREG32(MIPI_CONFIG_BASE + 0x04, 0x20, 0x20);
1143 }
1144 // OUTREG32(&DSI_CMDQ_REG->data[0], 0x00290508);
1145 OUTREG32(&DSI_CMDQ_REG->data[0], 0x00351508);
1146 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1147
1148 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1149 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1150 read_timeout_cnt=1000000;
1151 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 3);
1152 start_time = sched_clock();
1153 while(DSI_REG->DSI_INTSTA.BUSY) {
1154 end_time = sched_clock();
1155 if(((unsigned int)sched_clock() - (unsigned int)start_time) > 50000){
1156 DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", " Wait for DSI engine not busy timeout!!!:%d\n",__LINE__);
1157 DSI_Reset();
1158 break;
1159 }
1160 }
1161 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
1162 // spin_unlock_irq(&dsi_glitch_detect_lock);
1163 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 4);
1164
1165 t0.CONFG = 0x04;
1166 t0.Data0 = 0;
1167 t0.Data_ID = 0;
1168 t0.Data1 = 0;
1169
1170 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
1171 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1172
1173 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1174 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1175
1176
1177
1178 read_timeout_cnt=1000;
1179 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 5);
1180 start_time = sched_clock();
1181 while(DSI_REG->DSI_INTSTA.RD_RDY == 0) ///read clear
1182 {
1183 end_time = sched_clock();
1184 if(((unsigned int)sched_clock() - (unsigned int)start_time) > 50000)
1185 {
1186 if(glitch_log_on)
1187 printk("Test log 4:Polling DSI read ready timeout,%d us\n", (unsigned int)sched_clock() - (unsigned int)start_time);
1188
1189 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 13);
1190 #if 1
1191 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
1192 DSI_Reset();
1193 #endif
1194 read_timeout_ret = 1;
1195 break;
1196 }
1197 }
1198 if(1 == read_timeout_ret){
1199 read_timeout_ret = 0;
1200 // return 1;
1201 continue;
1202 }
1203 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 6);
1204 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
1205 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,RD_RDY,0);
1206
1207 if(((DSI_REG->DSI_TRIG_STA.TRIG2) )==1)
1208 {
1209 break;
1210 // continue;
1211 }
1212 else
1213 {
1214 //read error report
1215 OUTREG32(&read_data0, AS_UINT32(&DSI_REG->DSI_RX_DATA0));
1216 OUTREG32(&read_data1, AS_UINT32(&DSI_REG->DSI_RX_DATA1));
1217 if(glitch_log_on)
1218 {
1219 printk("read_data0, %x,%x,%x,%x\n", read_data0.byte0, read_data0.byte1, read_data0.byte2, read_data0.byte3);
1220 printk("read_data1, %x,%x,%x,%x\n", read_data1.byte0, read_data1.byte1, read_data1.byte2, read_data1.byte3);
1221 }
1222 if(((read_data0.byte1&0x7) != 0)||((read_data0.byte2&0x3)!=0)) //bit 0-3 bit 8-9
1223 {
1224 continue;
1225 }
1226 else
1227 {
1228 // continue;
1229 break;// jump out the for loop ,go to refresh
1230 }
1231
1232 }
1233 }
1234 #if 1
1235 if(i>0)
1236 printk("detect times:%d\n",i);
1237 #endif
1238
1239 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 7);
1240 #if 1
1241 switch(lcm_params->dsi.LANE_NUM)
1242 {
1243 case LCM_FOUR_LANE:
1244 OUTREG32(MIPI_CONFIG_BASE + 0x84, 0x3CF3C7B1);
1245 break;
1246 case LCM_THREE_LANE:
1247 OUTREG32(MIPI_CONFIG_BASE + 0x84, 0x00F3C7B1);
1248 break;
1249 default:
1250 OUTREG32(MIPI_CONFIG_BASE + 0x84, 0x0003C7B1);
1251 }
1252
1253 OUTREG32(MIPI_CONFIG_BASE + 0x88, 0x0);
1254 OUTREG32(MIPI_CONFIG_BASE + 0x80, 0x1);
1255
1256 DSI_REG->DSI_COM_CTRL.DSI_RESET = 0;
1257 DSI_REG->DSI_COM_CTRL.DSI_RESET = 1;
1258 DSI_REG->DSI_COM_CTRL.DSI_RESET = 0;
1259
1260 DSI_clk_HS_mode(1);
1261
1262 while((INREG32(&DSI_REG->DSI_STATE_DBG0)&0x40000) == 0); // polling bit18
1263
1264 OUTREG32(MIPI_CONFIG_BASE + 0x80, 0x0);
1265 #endif
1266 start_time = sched_clock();
1267 while(DSI_REG->DSI_INTSTA.BUSY) {
1268 end_time = sched_clock();
1269 if(((unsigned int)sched_clock() - (unsigned int)start_time) > 50000)
1270 {
1271 DSI_Reset();
1272 break;
1273 }
1274 }
1275 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
1276
1277 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
1278 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,1);
1279 DSI_RestoreCmdQ();
1280 DSI_SetMode(lcm_params->dsi.mode);
1281 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 8);
1282 #if 1
1283 // if(glitch_log_on)
1284 if(i == try_times){
1285 glitch_detect_fail_cnt++;
1286 return 1;
1287 }
1288 #endif
1289 glitch_detect_fail_cnt = 0;
1290 return 0;
1291 }
1292
1293 static unsigned int DSI_Detect_CLK_Glitch_Parallel(void)
1294 {
1295 DSI_T0_INS t0;
1296 char i;
1297 int read_timeout_cnt=10000;
1298 int read_timeout_ret = 0;
1299 int read_IC_ID = 0;
1300 unsigned long long start_time,end_time;
1301 DSI_RX_DATA_REG read_data0;
1302 DSI_RX_DATA_REG read_data1;
1303
1304 if(glitch_detect_fail_cnt>2){
1305 return 0;
1306 }
1307
1308 while(DSI_REG->DSI_INTSTA.BUSY);
1309 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
1310
1311 DSI_BackUpCmdQ();
1312 DSI_SetMode(CMD_MODE);
1313 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,0);
1314 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,0);
1315 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 0);
1316 for(i=0;i<try_times*4;i++)
1317 {
1318 if(read_IC_ID == 0) // slave
1319 {
1320
1321 DSI_clk_HS_mode(0);
1322
1323 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 9);
1324 while((INREG32(&DSI_REG->DSI_STATE_DBG0)&0x1) == 0); // polling bit0
1325
1326 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
1327 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,1);//reset
1328 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
1329
1330 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 10);
1331 if(i>0)
1332 {
1333 MASKREG32(MIPI_CONFIG_BASE + 0x04, 0x20, 0x0);
1334 }
1335 DSI_clk_HS_mode(1);
1336
1337 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 1);
1338 while((INREG32(&DSI_REG->DSI_STATE_DBG0)&0x40000) == 0); // polling bit18 start
1339 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 2);
1340 if(i>0)
1341 {
1342 MASKREG32(MIPI_CONFIG_BASE + 0x04, 0x20, 0x20);
1343 }
1344 // OUTREG32(&DSI_CMDQ_REG->data[0], 0x00290508);
1345
1346 }
1347
1348 #if 1 // HS command
1349 OUTREG32(&DSI_CMDQ_REG->data[0], 0xAA801508);
1350 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1351
1352 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1353 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1354
1355 read_timeout_cnt=1000000;
1356 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 3);
1357 start_time = sched_clock();
1358 while(DSI_REG->DSI_INTSTA.BUSY) {
1359 end_time = sched_clock();
1360 if(((unsigned int)sched_clock() - (unsigned int)start_time) > 50000){
1361 DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DSI", " Wait for DSI engine not busy timeout!!!:%d\n",__LINE__);
1362 DSI_Reset();
1363 break;
1364 }
1365 }
1366 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
1367 // spin_unlock_irq(&dsi_glitch_detect_lock);
1368 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 4);
1369
1370 #endif
1371 // LP command
1372 if(read_IC_ID == 0) // slave
1373 {
1374 //OUTREG32(&DSI_CMDQ_REG->data[0], 0x00023902);
1375 //OUTREG32(&DSI_CMDQ_REG->data[1], 0x000010B5);
1376 OUTREG32(&DSI_CMDQ_REG->data[0], 0x10B51500);
1377 }
1378 else // read_IC_ID == 1, master
1379 {
1380 //OUTREG32(&DSI_CMDQ_REG->data[0], 0x00023902);
1381 //OUTREG32(&DSI_CMDQ_REG->data[1], 0x000090B5);
1382 OUTREG32(&DSI_CMDQ_REG->data[0], 0x90B51500);
1383 }
1384
1385 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1386 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1387 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1388 while(DSI_REG->DSI_INTSTA.CMD_DONE == 0);
1389 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,0);
1390
1391 t0.CONFG = 0x04;
1392 t0.Data0 = 0;
1393 t0.Data_ID = 0;
1394 t0.Data1 = 0;
1395
1396 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
1397 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
1398
1399 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1400 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1401
1402
1403 read_timeout_cnt=1000;
1404 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 5);
1405 start_time = sched_clock();
1406 while(DSI_REG->DSI_INTSTA.RD_RDY == 0) ///read clear
1407 {
1408 end_time = sched_clock();
1409 if(((unsigned int)sched_clock() - (unsigned int)start_time) > 50000)
1410 {
1411 if(glitch_log_on)
1412 printk("Test log 4:Polling DSI read ready timeout,%d us\n", (unsigned int)sched_clock() - (unsigned int)start_time);
1413
1414 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 13);
1415 #if 1
1416 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
1417 DSI_Reset();
1418 #endif
1419 read_timeout_ret = 1;
1420 break;
1421 }
1422 }
1423 if(1 == read_timeout_ret){
1424 read_timeout_ret = 0;
1425 printk("iii detect timeout ID:%d\n",read_IC_ID);
1426 read_IC_ID = 0;
1427 continue;
1428 }
1429 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 6);
1430 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
1431 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,RD_RDY,0);
1432
1433 if(((DSI_REG->DSI_TRIG_STA.TRIG2) )==1)
1434 {
1435 if(read_IC_ID == 0)
1436 {
1437 read_IC_ID = 1;
1438 continue;
1439 }
1440 break;
1441 }
1442 else
1443 {
1444 //read error report
1445 OUTREG32(&read_data0, AS_UINT32(&DSI_REG->DSI_RX_DATA0));
1446 OUTREG32(&read_data1, AS_UINT32(&DSI_REG->DSI_RX_DATA1));
1447 if(glitch_log_on)
1448 {
1449 printk("read_data0, %x,%x,%x,%x\n", read_data0.byte0, read_data0.byte1, read_data0.byte2, read_data0.byte3);
1450 printk("read_data1, %x,%x,%x,%x\n", read_data1.byte0, read_data1.byte1, read_data1.byte2, read_data1.byte3);
1451
1452 if(((read_data0.byte1&0x4) != 0)||((read_data0.byte2&0x3)!=0)) //bit 3 bit 8-9
1453 {
1454 printk("111 ID:%d ECC err read_data0, %x,%x,%x,%x\n", read_IC_ID, read_data0.byte0, read_data0.byte1, read_data0.byte2, read_data0.byte3);
1455 }
1456 }
1457 if(((read_data0.byte1&0x7) != 0)||((read_data0.byte2&0x3)!=0)) //bit 0-3 bit 8-9
1458 {
1459 printk("read_data0, %x,%x,%x,%x\n", read_data0.byte0, read_data0.byte1, read_data0.byte2, read_data0.byte3);
1460 printk("iii detect error ID:%d\n",read_IC_ID);
1461 read_IC_ID = 0;
1462 continue;
1463 }
1464 else
1465 {
1466 if(read_IC_ID == 0)
1467 {
1468 read_IC_ID = 1;
1469 continue;
1470 }
1471 break;// jump out the for loop ,go to refresh
1472 }
1473
1474 }
1475 }
1476 #if 1
1477 if(i>1)
1478 printk("detect times:%d\n",i);
1479 #endif
1480
1481 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 7);
1482 #if 1
1483 switch(lcm_params->dsi.LANE_NUM)
1484 {
1485 case LCM_FOUR_LANE:
1486 OUTREG32(MIPI_CONFIG_BASE + 0x84, 0x3CF3C7B1);
1487 break;
1488 case LCM_THREE_LANE:
1489 OUTREG32(MIPI_CONFIG_BASE + 0x84, 0x00F3C7B1);
1490 break;
1491 default:
1492 OUTREG32(MIPI_CONFIG_BASE + 0x84, 0x0003C7B1);
1493 }
1494
1495 OUTREG32(MIPI_CONFIG_BASE + 0x88, 0x0);
1496 OUTREG32(MIPI_CONFIG_BASE + 0x80, 0x1);
1497
1498 DSI_REG->DSI_COM_CTRL.DSI_RESET = 0;
1499 DSI_REG->DSI_COM_CTRL.DSI_RESET = 1;
1500 DSI_REG->DSI_COM_CTRL.DSI_RESET = 0;
1501
1502 DSI_clk_HS_mode(1);
1503
1504 while((INREG32(&DSI_REG->DSI_STATE_DBG0)&0x40000) == 0); // polling bit18
1505
1506 OUTREG32(MIPI_CONFIG_BASE + 0x80, 0x0);
1507 #endif
1508 start_time = sched_clock();
1509 while(DSI_REG->DSI_INTSTA.BUSY) {
1510 end_time = sched_clock();
1511 if(((unsigned int)sched_clock() - (unsigned int)start_time) > 50000)
1512 {
1513 DSI_Reset();
1514 break;
1515 }
1516 }
1517 OUTREG32(&DSI_REG->DSI_INTSTA, 0x0);
1518
1519 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
1520 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,1);
1521 DSI_RestoreCmdQ();
1522 DSI_SetMode(lcm_params->dsi.mode);
1523 MMProfileLogEx(MTKFB_MMP_Events.Debug, MMProfileFlagPulse, 0, 8);
1524 #if 1
1525 // if(glitch_log_on)
1526 if(i == try_times*4){
1527 glitch_detect_fail_cnt++;
1528 return 1;
1529 }
1530 #endif
1531 glitch_detect_fail_cnt = 0;
1532 return 0;
1533 }
1534
1535 unsigned int DSI_Detect_CLK_Glitch(void)
1536 {
1537 if (lcm_params->dsi.compatibility_for_nvk == 1)
1538 {
1539 return DSI_Detect_CLK_Glitch_Default();
1540 }
1541 else if (lcm_params->dsi.compatibility_for_nvk == 2)
1542 {
1543 return DSI_Detect_CLK_Glitch_Parallel();
1544 }
1545 else
1546 {
1547 return DSI_Detect_CLK_Glitch_Default();
1548 }
1549 }
1550
1551
1552 DSI_STATUS DSI_Config_VDO_FRM_Mode(void)
1553 {
1554 try_times = 30;
1555 force_transfer = true;
1556 OUTREGBIT(DSI_MODE_CTRL_REG,DSI_REG->DSI_MODE_CTRL,FRM_MODE,1);
1557 return DSI_STATUS_OK;
1558 }
1559
1560 DSI_STATUS DSI_DisableClk(void)
1561 {
1562 //DSI_REG->DSI_START.DSI_START=0;
1563 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_EN,0);
1564
1565 return DSI_STATUS_OK;
1566 }
1567
1568
1569 DSI_STATUS DSI_Reset(void)
1570 {
1571 //DSI_REG->DSI_COM_CTRL.DSI_RESET = 1;
1572 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,1);
1573 // lcm_mdelay(5);
1574 //DSI_REG->DSI_COM_CTRL.DSI_RESET = 0;
1575 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
1576
1577
1578 return DSI_STATUS_OK;
1579 }
1580
1581 DSI_STATUS DSI_LP_Reset(void)
1582 {
1583 #if 0
1584 _WaitForEngineNotBusy();
1585 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,1);
1586 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
1587 #endif
1588 return DSI_STATUS_OK;
1589 }
1590
1591 DSI_STATUS DSI_SetMode(unsigned int mode)
1592 {
1593
1594 //DSI_REG->DSI_MODE_CTRL.MODE = mode;
1595 OUTREGBIT(DSI_MODE_CTRL_REG,DSI_REG->DSI_MODE_CTRL,MODE,mode);
1596 return DSI_STATUS_OK;
1597 }
1598
1599 static void _DSI_RDMA0_IRQ_Handler(unsigned int param)
1600 {
1601 if(_dsiContext.pIntCallback)
1602 {
1603 if (param & 4)
1604 {
1605 MMProfileLogEx(MTKFB_MMP_Events.ScreenUpdate, MMProfileFlagEnd, param, 0);
1606 _dsiContext.pIntCallback(DISP_DSI_SCREEN_UPDATE_END_INT);
1607 }
1608 if (param & 8)
1609 {
1610 MMProfileLogEx(MTKFB_MMP_Events.ScreenUpdate, MMProfileFlagEnd, param, 0);
1611 }
1612 if (param & 2)
1613 {
1614 MMProfileLogEx(MTKFB_MMP_Events.ScreenUpdate, MMProfileFlagStart, param, 0);
1615 _dsiContext.pIntCallback(DISP_DSI_SCREEN_UPDATE_START_INT);
1616 }
1617 if (param & 0x20)
1618 {
1619 _dsiContext.pIntCallback(DISP_DSI_TARGET_LINE_INT);
1620 _dsiContext.pIntCallback(DISP_DSI_VSYNC_INT);
1621 }
1622 }
1623 }
1624
1625 static void _DSI_MUTEX_IRQ_Handler(unsigned int param)
1626 {
1627 if(_dsiContext.pIntCallback)
1628 {
1629 #ifndef MTK_OVERLAY_ENGINE_SUPPORT
1630 if (param & 1)
1631 #endif
1632 {
1633 _dsiContext.pIntCallback(DISP_DSI_REG_UPDATE_INT);
1634 }
1635 }
1636 }
1637
1638 DSI_STATUS DSI_SleepOut(void)
1639 {
1640 OUTREGBIT(DSI_MODE_CTRL_REG,DSI_REG->DSI_MODE_CTRL,SLEEP_MODE,1);
1641 OUTREGBIT(DSI_PHY_TIMCON4_REG,DSI_REG->DSI_PHY_TIMECON4,ULPS_WAKEUP,0x22E09); // cycle to 1ms for 520MHz
1642
1643 return DSI_STATUS_OK;
1644 }
1645
1646
1647 DSI_STATUS DSI_Wakeup(void)
1648 {
1649 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,SLEEPOUT_START,0);
1650 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,SLEEPOUT_START,1);
1651 mdelay(1);
1652
1653 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,SLEEPOUT_START,0);
1654 OUTREGBIT(DSI_MODE_CTRL_REG,DSI_REG->DSI_MODE_CTRL,SLEEP_MODE,0);
1655
1656 return DSI_STATUS_OK;
1657 }
1658
1659 DSI_STATUS DSI_EnableInterrupt(DISP_INTERRUPT_EVENTS eventID)
1660 {
1661 #if ENABLE_DSI_INTERRUPT
1662 switch(eventID)
1663 {
1664 case DISP_DSI_READ_RDY_INT:
1665 //DSI_REG->DSI_INTEN.RD_RDY = 1;
1666 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
1667 break;
1668 case DISP_DSI_CMD_DONE_INT:
1669 //DSI_REG->DSI_INTEN.CMD_DONE = 1;
1670 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,1);
1671 break;
1672 case DISP_DSI_VMDONE_INT:
1673 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,VM_DONE,1);
1674 break;
1675 case DISP_DSI_VSYNC_INT:
1676 disp_register_irq(DISP_MODULE_RDMA0, _DSI_RDMA0_IRQ_Handler);
1677 break;
1678 case DISP_DSI_TARGET_LINE_INT:
1679 disp_register_irq(DISP_MODULE_RDMA0, _DSI_RDMA0_IRQ_Handler);
1680 break;
1681 case DISP_DSI_SCREEN_UPDATE_START_INT:
1682 disp_register_irq(DISP_MODULE_RDMA0, _DSI_RDMA0_IRQ_Handler);
1683 break;
1684 case DISP_DSI_SCREEN_UPDATE_END_INT:
1685 disp_register_irq(DISP_MODULE_RDMA0, _DSI_RDMA0_IRQ_Handler);
1686 break;
1687 case DISP_DSI_REG_UPDATE_INT:
1688 //wake_up_interruptible(&_dsi_reg_update_wq);
1689 disp_register_irq(DISP_MODULE_MUTEX, _DSI_MUTEX_IRQ_Handler);
1690 break;
1691 default:
1692 return DSI_STATUS_ERROR;
1693 }
1694
1695 return DSI_STATUS_OK;
1696 #else
1697 ///TODO: warning log here
1698 return DSI_STATUS_OK;
1699 #endif
1700 }
1701
1702
1703 DSI_STATUS DSI_SetInterruptCallback(void (*pCB)(DISP_INTERRUPT_EVENTS))
1704 {
1705 _dsiContext.pIntCallback = pCB;
1706
1707 return DSI_STATUS_OK;
1708 }
1709
1710 DSI_STATUS DSI_handle_TE(void)
1711 {
1712
1713 unsigned int data_array;
1714
1715 //data_array=0x00351504;
1716 //DSI_set_cmdq(&data_array, 1, 1);
1717
1718 //lcm_mdelay(10);
1719
1720 // RACT
1721 //data_array=1;
1722 //OUTREG32(&DSI_REG->DSI_RACK, data_array);
1723
1724 // TE + BTA
1725 data_array=0x24;
1726 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI_handle_TE TE + BTA !! \n");
1727 OUTREG32(&DSI_CMDQ_REG->data, data_array);
1728
1729 //DSI_CMDQ_REG->data.byte0=0x24;
1730 //DSI_CMDQ_REG->data.byte1=0;
1731 //DSI_CMDQ_REG->data.byte2=0;
1732 //DSI_CMDQ_REG->data.byte3=0;
1733
1734 //DSI_REG->DSI_CMDQ_SIZE.CMDQ_SIZE=1;
1735 OUTREGBIT(DSI_CMDQ_CTRL_REG,DSI_REG->DSI_CMDQ_SIZE,CMDQ_SIZE,1);
1736
1737 //DSI_REG->DSI_START.DSI_START=0;
1738 //DSI_REG->DSI_START.DSI_START=1;
1739 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,0);
1740 OUTREGBIT(DSI_START_REG,DSI_REG->DSI_START,DSI_START,1);
1741
1742
1743 // wait TE Trigger status
1744 // do
1745 // {
1746 lcm_mdelay(10);
1747
1748 data_array=INREG32(&DSI_REG->DSI_INTSTA);
1749 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI INT state : %x !! \n", data_array);
1750
1751 data_array=INREG32(&DSI_REG->DSI_TRIG_STA);
1752 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI TRIG TE status check : %x !! \n", data_array);
1753 // } while(!(data_array&0x4));
1754
1755 // RACT
1756 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI Set RACT !! \n");
1757 data_array=1;
1758 OUTREG32(&DSI_REG->DSI_RACK, data_array);
1759
1760 return DSI_STATUS_OK;
1761
1762 }
1763
1764
1765
1766
1767
1768 void DSI_PHY_clk_setting(LCM_PARAMS *lcm_params)
1769 {
1770 unsigned int data_Rate = lcm_params->dsi.PLL_CLOCK*2;
1771 unsigned int txdiv,pcw;
1772 // unsigned int fmod = 30;//Fmod = 30KHz by default
1773 unsigned int delta1 = 5;//Delta1 is SSC range, default is 0%~-5%
1774 unsigned int pdelta1;
1775
1776 OUTREGBIT(MIPITX_DSI_TOP_CON_REG,DSI_PHY_REG->MIPITX_DSI_TOP_CON,RG_DSI_LNT_IMP_CAL_CODE,8);
1777 OUTREGBIT(MIPITX_DSI_TOP_CON_REG,DSI_PHY_REG->MIPITX_DSI_TOP_CON,RG_DSI_LNT_HS_BIAS_EN,1);
1778
1779 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_V032_SEL,4);
1780 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_V04_SEL,4);
1781 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_V072_SEL,4);
1782 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_V10_SEL,4);
1783 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_V12_SEL,4);
1784 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_BG_CKEN,1);
1785 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_BG_CORE_EN,1);
1786 mdelay(10);
1787
1788 OUTREGBIT(MIPITX_DSI0_CON_REG,DSI_PHY_REG->MIPITX_DSI0_CON,RG_DSI0_CKG_LDOOUT_EN,1);
1789 OUTREGBIT(MIPITX_DSI0_CON_REG,DSI_PHY_REG->MIPITX_DSI0_CON,RG_DSI0_LDOCORE_EN,1);
1790
1791 OUTREGBIT(MIPITX_DSI_PLL_PWR_REG,DSI_PHY_REG->MIPITX_DSI_PLL_PWR,DA_DSI0_MPPLL_SDM_PWR_ON,1);
1792 OUTREGBIT(MIPITX_DSI_PLL_PWR_REG,DSI_PHY_REG->MIPITX_DSI_PLL_PWR,DA_DSI0_MPPLL_SDM_ISO_EN,1);
1793 mdelay(10);
1794
1795 OUTREGBIT(MIPITX_DSI_PLL_PWR_REG,DSI_PHY_REG->MIPITX_DSI_PLL_PWR,DA_DSI0_MPPLL_SDM_ISO_EN,0);
1796
1797 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_PREDIV,0);
1798 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_POSDIV,0);
1799
1800 if(0!=data_Rate){//if lcm_params->dsi.PLL_CLOCK=0, use other method
1801 if(data_Rate > 1250){
1802 printk("[dsi_drv.c error]Data Rate exceed limitation\n");
1803 ASSERT(0);
1804 }
1805 else if(data_Rate >= 500)
1806 txdiv = 1;
1807 else if(data_Rate >= 250)
1808 txdiv = 2;
1809 else if(data_Rate >= 125)
1810 txdiv = 4;
1811 else if(data_Rate > 62)
1812 txdiv = 8;
1813 else if(data_Rate >= 50)
1814 txdiv = 16;
1815 else{
1816 printk("[dsi_drv.c Error]: dataRate is too low,%d!!!\n", __LINE__);
1817 ASSERT(0);
1818 }
1819 //PLL txdiv config
1820 switch(txdiv)
1821 {
1822 case 1:
1823 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV0,0);
1824 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV1,0);
1825 break;
1826 case 2:
1827 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV0,1);
1828 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV1,0);
1829 break;
1830 case 4:
1831 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV0,2);
1832 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV1,0);
1833 break;
1834 case 8:
1835 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV0,2);
1836 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV1,1);
1837 break;
1838 case 16:
1839 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV0,2);
1840 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV1,2);
1841 break;
1842 default:
1843 break;
1844 }
1845
1846 // PLL PCW config
1847 /*
1848 PCW bit 24~30 = floor(pcw)
1849 PCW bit 16~23 = (pcw - floor(pcw))*256
1850 PCW bit 8~15 = (pcw*256 - floor(pcw)*256)*256
1851 PCW bit 8~15 = (pcw*256*256 - floor(pcw)*256*256)*256
1852 */
1853 // pcw = data_Rate*4*txdiv/(26*2);//Post DIV =4, so need data_Rate*4
1854 pcw = data_Rate*txdiv/13;
1855
1856 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_H,(pcw & 0x7F));
1857 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_16_23,((256*(data_Rate*txdiv%13)/13) & 0xFF));
1858 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_8_15,((256*(256*(data_Rate*txdiv%13)%13)/13) & 0xFF));
1859 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_0_7,((256*(256*(256*(data_Rate*txdiv%13)%13)%13)/13) & 0xFF));
1860
1861 //SSC config
1862 // pmod = ROUND(1000*26MHz/fmod/2);fmod default is 30Khz, and this value not be changed
1863 // pmod = 433.33;
1864 if(1 != lcm_params->dsi.ssc_disable){
1865 OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_SSC_PH_INIT,1);
1866 OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_SSC_PRD,0x1B1);//PRD=ROUND(pmod) = 433;
1867 if(0 != lcm_params->dsi.ssc_range){
1868 delta1 = lcm_params->dsi.ssc_range;
1869 }
1870 ASSERT(delta1<=8);
1871 pdelta1 = (delta1*data_Rate*txdiv*262144+281664)/563329;
1872 OUTREGBIT(MIPITX_DSI_PLL_CON3_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON3,RG_DSI0_MPPLL_SDM_SSC_DELTA,pdelta1);
1873 OUTREGBIT(MIPITX_DSI_PLL_CON3_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON3,RG_DSI0_MPPLL_SDM_SSC_DELTA1,pdelta1);
1874 //OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_FRA_EN,1);
1875 printk("[dsi_drv.c] PLL config:data_rate=%d,txdiv=%d,pcw=%d,delta1=%d,pdelta1=0x%x\n",
1876 data_Rate,txdiv,INREG32(&DSI_PHY_REG->MIPITX_DSI_PLL_CON2),delta1,pdelta1);
1877 }
1878 }
1879 else{
1880 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV0,lcm_params->dsi.pll_div1);
1881 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_TXDIV1,lcm_params->dsi.pll_div2);
1882
1883 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_H,((lcm_params->dsi.fbk_div)<< 2));
1884 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_16_23,0);
1885 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_8_15,0);
1886 OUTREGBIT(MIPITX_DSI_PLL_CON2_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON2,RG_DSI0_MPPLL_SDM_PCW_0_7,0);
1887
1888 //OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_FRA_EN,0);
1889 }
1890 OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_FRA_EN,1);
1891
1892 OUTREGBIT(MIPITX_DSI0_CLOCK_LANE_REG,DSI_PHY_REG->MIPITX_DSI0_CLOCK_LANE,RG_DSI0_LNTC_RT_CODE,0x8);
1893 OUTREGBIT(MIPITX_DSI0_CLOCK_LANE_REG,DSI_PHY_REG->MIPITX_DSI0_CLOCK_LANE,RG_DSI0_LNTC_PHI_SEL,0x1);
1894 OUTREGBIT(MIPITX_DSI0_CLOCK_LANE_REG,DSI_PHY_REG->MIPITX_DSI0_CLOCK_LANE,RG_DSI0_LNTC_LDOOUT_EN,1);
1895 if(lcm_params->dsi.LANE_NUM > 0)
1896 {
1897 OUTREGBIT(MIPITX_DSI0_DATA_LANE0_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE0,RG_DSI0_LNT0_RT_CODE,0x8);
1898 OUTREGBIT(MIPITX_DSI0_DATA_LANE0_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE0,RG_DSI0_LNT0_LDOOUT_EN,1);
1899 }
1900
1901 if(lcm_params->dsi.LANE_NUM > 1)
1902 {
1903 OUTREGBIT(MIPITX_DSI0_DATA_LANE1_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE1,RG_DSI0_LNT1_RT_CODE,0x8);
1904 OUTREGBIT(MIPITX_DSI0_DATA_LANE1_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE1,RG_DSI0_LNT1_LDOOUT_EN,1);
1905 }
1906
1907 if(lcm_params->dsi.LANE_NUM > 2)
1908 {
1909 OUTREGBIT(MIPITX_DSI0_DATA_LANE2_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE2,RG_DSI0_LNT2_RT_CODE,0x8);
1910 OUTREGBIT(MIPITX_DSI0_DATA_LANE2_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE2,RG_DSI0_LNT2_LDOOUT_EN,1);
1911 }
1912
1913 if(lcm_params->dsi.LANE_NUM > 3)
1914 {
1915 OUTREGBIT(MIPITX_DSI0_DATA_LANE3_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE3,RG_DSI0_LNT3_RT_CODE,0x8);
1916 OUTREGBIT(MIPITX_DSI0_DATA_LANE3_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE3,RG_DSI0_LNT3_LDOOUT_EN,1);
1917 }
1918
1919 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_PLL_EN,1);
1920 mdelay(1);
1921 if((0 != data_Rate) && (1 != lcm_params->dsi.ssc_disable))
1922 OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_SSC_EN,1);
1923 else
1924 OUTREGBIT(MIPITX_DSI_PLL_CON1_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON1,RG_DSI0_MPPLL_SDM_SSC_EN,0);
1925
1926 // default POSDIV by 4
1927 OUTREGBIT(MIPITX_DSI_PLL_TOP_REG,DSI_PHY_REG->MIPITX_DSI_PLL_TOP,RG_MPPLL_PRESERVE_L,3);
1928 OUTREGBIT(MIPITX_DSI_TOP_CON_REG,DSI_PHY_REG->MIPITX_DSI_TOP_CON,RG_DSI_PAD_TIE_LOW_EN, 0);
1929 }
1930
1931
1932 void DSI_PHY_clk_switch(bool on)
1933 {
1934 if(on){//workaround: do nothing
1935 DSI_PHY_clk_setting(lcm_params);
1936 }
1937 else
1938 {
1939 // pre_oe/oe = 1
1940 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNTC_LPTX_PRE_OE,1);
1941 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNTC_LPTX_OE,1);
1942 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT0_LPTX_PRE_OE,1);
1943 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT0_LPTX_OE,1);
1944 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT1_LPTX_PRE_OE,1);
1945 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT1_LPTX_OE,1);
1946 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT2_LPTX_PRE_OE,1);
1947 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT2_LPTX_OE,1);
1948 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT3_LPTX_PRE_OE,1);
1949 OUTREGBIT(MIPITX_DSI_SW_CTRL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL_CON0,SW_LNT3_LPTX_OE,1);
1950
1951 // switch to mipi tx sw mode
1952 OUTREGBIT(MIPITX_DSI_SW_CTRL_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL,SW_CTRL_EN,1);
1953
1954 // disable mipi clock
1955 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0,RG_DSI0_MPPLL_PLL_EN,0);
1956 mdelay(1);
1957 OUTREGBIT(MIPITX_DSI_PLL_TOP_REG, DSI_PHY_REG->MIPITX_DSI_PLL_TOP, RG_MPPLL_PRESERVE_L, 0);
1958
1959 OUTREGBIT(MIPITX_DSI_TOP_CON_REG,DSI_PHY_REG->MIPITX_DSI_TOP_CON,RG_DSI_PAD_TIE_LOW_EN, 1);
1960 OUTREGBIT(MIPITX_DSI0_CLOCK_LANE_REG,DSI_PHY_REG->MIPITX_DSI0_CLOCK_LANE,RG_DSI0_LNTC_LDOOUT_EN,0);
1961 OUTREGBIT(MIPITX_DSI0_DATA_LANE0_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE0,RG_DSI0_LNT0_LDOOUT_EN,0);
1962 OUTREGBIT(MIPITX_DSI0_DATA_LANE1_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE1,RG_DSI0_LNT1_LDOOUT_EN,0);
1963 OUTREGBIT(MIPITX_DSI0_DATA_LANE2_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE2,RG_DSI0_LNT2_LDOOUT_EN,0);
1964 OUTREGBIT(MIPITX_DSI0_DATA_LANE3_REG,DSI_PHY_REG->MIPITX_DSI0_DATA_LANE3,RG_DSI0_LNT3_LDOOUT_EN,0);
1965 mdelay(1);
1966
1967 OUTREGBIT(MIPITX_DSI_PLL_PWR_REG, DSI_PHY_REG->MIPITX_DSI_PLL_PWR, DA_DSI0_MPPLL_SDM_ISO_EN, 1);
1968 OUTREGBIT(MIPITX_DSI_PLL_PWR_REG, DSI_PHY_REG->MIPITX_DSI_PLL_PWR, DA_DSI0_MPPLL_SDM_PWR_ON, 0);
1969 OUTREGBIT(MIPITX_DSI_TOP_CON_REG,DSI_PHY_REG->MIPITX_DSI_TOP_CON,RG_DSI_LNT_HS_BIAS_EN, 0);
1970
1971 OUTREGBIT(MIPITX_DSI0_CON_REG,DSI_PHY_REG->MIPITX_DSI0_CON,RG_DSI0_CKG_LDOOUT_EN,0);
1972 OUTREGBIT(MIPITX_DSI0_CON_REG,DSI_PHY_REG->MIPITX_DSI0_CON,RG_DSI0_LDOCORE_EN,0);
1973
1974 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_BG_CKEN,0);
1975 OUTREGBIT(MIPITX_DSI_BG_CON_REG,DSI_PHY_REG->MIPITX_DSI_BG_CON,RG_DSI_BG_CORE_EN,0);
1976
1977 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0, RG_DSI0_MPPLL_PREDIV,0);
1978 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0, RG_DSI0_MPPLL_TXDIV0,0);
1979 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0, RG_DSI0_MPPLL_TXDIV1,0);
1980 OUTREGBIT(MIPITX_DSI_PLL_CON0_REG,DSI_PHY_REG->MIPITX_DSI_PLL_CON0, RG_DSI0_MPPLL_POSDIV,0);
1981
1982
1983 OUTREG32(&DSI_PHY_REG->MIPITX_DSI_PLL_CON1, 0x00000000);
1984 OUTREG32(&DSI_PHY_REG->MIPITX_DSI_PLL_CON2, 0x50000000);
1985
1986 OUTREGBIT(MIPITX_DSI_SW_CTRL_REG,DSI_PHY_REG->MIPITX_DSI_SW_CTRL,SW_CTRL_EN,0);
1987 mdelay(1);
1988 }
1989 }
1990
1991 void DSI_Set_VM_CMD(LCM_PARAMS *lcm_params)
1992 {
1993 OUTREGBIT(DSI_VM_CMD_CON_REG,DSI_REG->DSI_VM_CMD_CON,TS_VFP_EN,1);
1994 OUTREGBIT(DSI_VM_CMD_CON_REG,DSI_REG->DSI_VM_CMD_CON,VM_CMD_EN,1);
1995 return;
1996 }
1997
1998 void DSI_PHY_TIMCONFIG(LCM_PARAMS *lcm_params)
1999 {
2000 DSI_PHY_TIMCON0_REG timcon0;
2001 DSI_PHY_TIMCON1_REG timcon1;
2002 DSI_PHY_TIMCON2_REG timcon2;
2003 DSI_PHY_TIMCON3_REG timcon3;
2004 unsigned int div1 = 0;
2005 unsigned int div2 = 0;
2006 unsigned int pre_div = 0;
2007 unsigned int post_div = 0;
2008 unsigned int fbk_sel = 0;
2009 unsigned int fbk_div = 0;
2010 unsigned int lane_no = lcm_params->dsi.LANE_NUM;
2011
2012 // unsigned int div2_real;
2013 unsigned int cycle_time;
2014 unsigned int ui;
2015 unsigned int hs_trail_m, hs_trail_n;
2016
2017 if(0 != lcm_params->dsi.PLL_CLOCK){
2018 ui= 1000/(lcm_params->dsi.PLL_CLOCK*2)+0x01;
2019 cycle_time=8000/(lcm_params->dsi.PLL_CLOCK*2)+0x01;
2020 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = %d(ns), Unit Interval = %d(ns). , lane# = %d \n", cycle_time, ui, lane_no);
2021 }
2022 else{
2023 div1 = lcm_params->dsi.pll_div1;
2024 div2 = lcm_params->dsi.pll_div2;
2025 fbk_div = lcm_params->dsi.fbk_div;
2026 switch(div1)
2027 {
2028 case 0:
2029 div1 = 1;
2030 break;
2031
2032 case 1:
2033 div1 = 2;
2034 break;
2035
2036 case 2:
2037 case 3:
2038 div1 = 4;
2039 break;
2040
2041 default:
2042 printk("div1 should be less than 4!!\n");
2043 div1 = 4;
2044 break;
2045 }
2046
2047 switch(div2)
2048 {
2049 case 0:
2050 div2 = 1;
2051 break;
2052 case 1:
2053 div2 = 2;
2054 break;
2055 case 2:
2056 case 3:
2057 div2 = 4;
2058 break;
2059 default:
2060 printk("div2 should be less than 4!!\n");
2061 div2 = 4;
2062 break;
2063 }
2064
2065 switch(pre_div)
2066 {
2067 case 0:
2068 pre_div = 1;
2069 break;
2070
2071 case 1:
2072 pre_div = 2;
2073 break;
2074
2075 case 2:
2076 case 3:
2077 pre_div = 4;
2078 break;
2079
2080 default:
2081 printk("pre_div should be less than 4!!\n");
2082 pre_div = 4;
2083 break;
2084 }
2085
2086 switch(post_div)
2087 {
2088 case 0:
2089 post_div = 1;
2090 break;
2091
2092 case 1:
2093 post_div = 2;
2094 break;
2095
2096 case 2:
2097 case 3:
2098 post_div = 4;
2099 break;
2100
2101 default:
2102 printk("post_div should be less than 4!!\n");
2103 post_div = 4;
2104 break;
2105 }
2106
2107 switch(fbk_sel)
2108 {
2109 case 0:
2110 fbk_sel = 1;
2111 break;
2112
2113 case 1:
2114 fbk_sel = 2;
2115 break;
2116
2117 case 2:
2118 case 3:
2119 fbk_sel = 4;
2120 break;
2121
2122 default:
2123 printk("fbk_sel should be less than 4!!\n");
2124 fbk_sel = 4;
2125 break;
2126 }
2127 cycle_time=(1000*4*div2*div1)/(fbk_div*26)+0x01;
2128
2129 ui=(1000*div2*div1)/(fbk_div*26*0x2)+0x01;
2130 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = %d(ns), Unit Interval = %d(ns). div1 = %d, div2 = %d, fbk_div = %d, lane# = %d \n", cycle_time, ui, div1, div2, fbk_div, lane_no);
2131 }
2132
2133 // div2_real=div2 ? div2*0x02 : 0x1;
2134 //cycle_time = (1000 * div2 * div1 * pre_div * post_div)/ (fbk_sel * (fbk_div+0x01) * 26) + 1;
2135 //ui = (1000 * div2 * div1 * pre_div * post_div)/ (fbk_sel * (fbk_div+0x01) * 26 * 2) + 1;
2136 #define NS_TO_CYCLE(n, c) ((n) / (c))
2137
2138 hs_trail_m=1;
2139 hs_trail_n= (lcm_params->dsi.HS_TRAIL == 0) ? NS_TO_CYCLE(((hs_trail_m * 0x4) + 0x60), cycle_time) : lcm_params->dsi.HS_TRAIL;
2140 // +3 is recommended from designer becauase of HW latency
2141 timcon0.HS_TRAIL = ((hs_trail_m > hs_trail_n) ? hs_trail_m : hs_trail_n) + 0x0a;
2142
2143 timcon0.HS_PRPR = (lcm_params->dsi.HS_PRPR == 0) ? NS_TO_CYCLE((0x40 + 0x5 * ui), cycle_time) : lcm_params->dsi.HS_PRPR;
2144 // HS_PRPR can't be 1.
2145 if (timcon0.HS_PRPR == 0)
2146 timcon0.HS_PRPR = 1;
2147
2148 timcon0.HS_ZERO = (lcm_params->dsi.HS_ZERO == 0) ? NS_TO_CYCLE((0xC8 + 0x0a * ui), cycle_time) : lcm_params->dsi.HS_ZERO;
2149 if (timcon0.HS_ZERO > timcon0.HS_PRPR)
2150 timcon0.HS_ZERO -= timcon0.HS_PRPR;
2151
2152 timcon0.LPX = (lcm_params->dsi.LPX == 0) ? NS_TO_CYCLE(0x50, cycle_time) : lcm_params->dsi.LPX;
2153 if(timcon0.LPX == 0)
2154 timcon0.LPX = 1;
2155
2156 // timcon1.TA_SACK = (lcm_params->dsi.TA_SACK == 0) ? 1 : lcm_params->dsi.TA_SACK;
2157 timcon1.TA_GET = (lcm_params->dsi.TA_GET == 0) ? (0x5 * timcon0.LPX) : lcm_params->dsi.TA_GET;
2158 timcon1.TA_SURE = (lcm_params->dsi.TA_SURE == 0) ? (0x3 * timcon0.LPX / 0x2) : lcm_params->dsi.TA_SURE;
2159 timcon1.TA_GO = (lcm_params->dsi.TA_GO == 0) ? (0x4 * timcon0.LPX) : lcm_params->dsi.TA_GO;
2160 // --------------------------------------------------------------
2161 // NT35510 need fine tune timing
2162 // Data_hs_exit = 60 ns + 128UI
2163 // Clk_post = 60 ns + 128 UI.
2164 // --------------------------------------------------------------
2165 timcon1.DA_HS_EXIT = (lcm_params->dsi.DA_HS_EXIT == 0) ? NS_TO_CYCLE((0x3c + 0x80 * ui), cycle_time) : lcm_params->dsi.DA_HS_EXIT;
2166
2167 timcon2.CLK_TRAIL = ((lcm_params->dsi.CLK_TRAIL == 0) ? NS_TO_CYCLE(0x64, cycle_time) : lcm_params->dsi.CLK_TRAIL) + 0x0a;
2168 // CLK_TRAIL can't be 1.
2169 if (timcon2.CLK_TRAIL < 2)
2170 timcon2.CLK_TRAIL = 2;
2171
2172 // timcon2.LPX_WAIT = (lcm_params->dsi.LPX_WAIT == 0) ? 1 : lcm_params->dsi.LPX_WAIT;
2173 timcon2.CONT_DET = lcm_params->dsi.CONT_DET;
2174 timcon2.CLK_ZERO = (lcm_params->dsi.CLK_ZERO == 0) ? NS_TO_CYCLE(0x190, cycle_time) : lcm_params->dsi.CLK_ZERO;
2175
2176 timcon3.CLK_HS_PRPR = (lcm_params->dsi.CLK_HS_PRPR == 0) ? NS_TO_CYCLE(0x40, cycle_time) : lcm_params->dsi.CLK_HS_PRPR;
2177 if(timcon3.CLK_HS_PRPR == 0)
2178 timcon3.CLK_HS_PRPR = 1;
2179 timcon3.CLK_HS_EXIT= (lcm_params->dsi.CLK_HS_EXIT == 0) ? (2 * timcon0.LPX) : lcm_params->dsi.CLK_HS_EXIT;
2180 timcon3.CLK_HS_POST= (lcm_params->dsi.CLK_HS_POST == 0) ? NS_TO_CYCLE((0x3c + 0x80 * ui), cycle_time) : lcm_params->dsi.CLK_HS_POST;
2181
2182 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = %d, HS_ZERO = %d, HS_PRPR = %d, LPX = %d, TA_GET = %d, TA_SURE = %d, TA_GO = %d, CLK_TRAIL = %d, CLK_ZERO = %d, CLK_HS_PRPR = %d \n", \
2183 timcon0.HS_TRAIL, timcon0.HS_ZERO, timcon0.HS_PRPR, timcon0.LPX, timcon1.TA_GET, timcon1.TA_SURE, timcon1.TA_GO, timcon2.CLK_TRAIL, timcon2.CLK_ZERO, timcon3.CLK_HS_PRPR);
2184
2185 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,LPX,timcon0.LPX);
2186 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,HS_PRPR,timcon0.HS_PRPR);
2187 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,HS_ZERO,timcon0.HS_ZERO);
2188 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,HS_TRAIL,timcon0.HS_TRAIL);
2189
2190 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,TA_GO,timcon1.TA_GO);
2191 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,TA_SURE,timcon1.TA_SURE);
2192 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,TA_GET,timcon1.TA_GET);
2193 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,DA_HS_EXIT,timcon1.DA_HS_EXIT);
2194
2195 OUTREGBIT(DSI_PHY_TIMCON2_REG,DSI_REG->DSI_PHY_TIMECON2,CONT_DET,timcon2.CONT_DET);
2196 OUTREGBIT(DSI_PHY_TIMCON2_REG,DSI_REG->DSI_PHY_TIMECON2,CLK_ZERO,timcon2.CLK_ZERO);
2197 OUTREGBIT(DSI_PHY_TIMCON2_REG,DSI_REG->DSI_PHY_TIMECON2,CLK_TRAIL,timcon2.CLK_TRAIL);
2198
2199 OUTREGBIT(DSI_PHY_TIMCON3_REG,DSI_REG->DSI_PHY_TIMECON3,CLK_HS_PRPR,timcon3.CLK_HS_PRPR);
2200 OUTREGBIT(DSI_PHY_TIMCON3_REG,DSI_REG->DSI_PHY_TIMECON3,CLK_HS_POST,timcon3.CLK_HS_POST);
2201 OUTREGBIT(DSI_PHY_TIMCON3_REG,DSI_REG->DSI_PHY_TIMECON3,CLK_HS_EXIT,timcon3.CLK_HS_EXIT);
2202 printk("%s, 0x%08x,0x%08x,0x%08x,0x%08x\n", __func__, INREG32(DSI_BASE+0x110),INREG32(DSI_BASE+0x114),INREG32(DSI_BASE+0x118),INREG32(DSI_BASE+0x11c));
2203 }
2204
2205
2206
2207 void DSI_clk_ULP_mode(bool enter)
2208 {
2209 if(enter) {
2210 OUTREGBIT(DSI_PHY_LCCON_REG, DSI_REG->DSI_PHY_LCCON, LC_HS_TX_EN, 0);
2211 mdelay(1);
2212
2213 OUTREGBIT(DSI_PHY_LCCON_REG, DSI_REG->DSI_PHY_LCCON, LC_ULPM_EN, 1);
2214 mdelay(1);
2215 }
2216 else {
2217 OUTREGBIT(DSI_PHY_LCCON_REG, DSI_REG->DSI_PHY_LCCON, LC_ULPM_EN, 0);
2218 mdelay(1);
2219
2220 OUTREGBIT(DSI_PHY_LCCON_REG, DSI_REG->DSI_PHY_LCCON, LC_WAKEUP_EN, 1);
2221 mdelay(1);
2222
2223 OUTREGBIT(DSI_PHY_LCCON_REG, DSI_REG->DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
2224 mdelay(1);
2225 }
2226 }
2227
2228
2229 void DSI_clk_HS_mode(bool enter)
2230 {
2231 DSI_PHY_LCCON_REG tmp_reg1 = DSI_REG->DSI_PHY_LCCON;
2232
2233
2234 if(enter && !DSI_clk_HS_state()) {
2235 tmp_reg1.LC_HS_TX_EN=1;
2236 OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&tmp_reg1));
2237 }
2238 else if (!enter && DSI_clk_HS_state()) {
2239 tmp_reg1.LC_HS_TX_EN=0;
2240 OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&tmp_reg1));
2241
2242 }
2243 }
2244
2245
2246 void DSI_Continuous_HS(void)
2247 {
2248 DSI_TXRX_CTRL_REG tmp_reg = DSI_REG->DSI_TXRX_CTRL;
2249
2250 tmp_reg.HSTX_CKLP_EN = 0;
2251 OUTREG32(&DSI_REG->DSI_TXRX_CTRL, AS_UINT32(&tmp_reg));
2252 }
2253
2254
2255 bool DSI_clk_HS_state(void)
2256 {
2257 return DSI_REG->DSI_PHY_LCCON.LC_HS_TX_EN ? TRUE : FALSE;
2258 }
2259
2260
2261 void DSI_lane0_ULP_mode(bool enter)
2262 {
2263 DSI_PHY_LD0CON_REG tmp_reg1;
2264
2265 tmp_reg1=DSI_REG->DSI_PHY_LD0CON;
2266
2267 if(enter) {
2268 // suspend
2269 tmp_reg1.L0_HS_TX_EN=0;
2270 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&tmp_reg1));
2271 lcm_mdelay(1);
2272 tmp_reg1.L0_ULPM_EN=1;
2273 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&tmp_reg1));
2274 lcm_mdelay(1);
2275 }
2276 else {
2277 // resume
2278 tmp_reg1.L0_ULPM_EN=0;
2279 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&tmp_reg1));
2280 lcm_mdelay(1);
2281 tmp_reg1.L0_WAKEUP_EN=1;
2282 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&tmp_reg1));
2283 lcm_mdelay(1);
2284 tmp_reg1.L0_WAKEUP_EN=0;
2285 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&tmp_reg1));
2286 lcm_mdelay(1);
2287 }
2288 }
2289
2290 // called by DPI ISR
2291 void DSI_handle_esd_recovery(void)
2292 {
2293 }
2294
2295
2296 // called by "esd_recovery_kthread"
2297 bool DSI_esd_check(void)
2298 {
2299 #ifndef MT65XX_NEW_DISP
2300 bool result = false;
2301
2302 if(dsi_esd_recovery)
2303 result = true;
2304 else
2305 result = false;
2306
2307 dsi_esd_recovery = false;
2308 #else
2309 DSI_MODE_CTRL_REG mode_ctl, mode_ctl_backup;
2310 bool result = false;
2311 #if ENABLE_DSI_INTERRUPT //wait video mode done
2312 static const long WAIT_TIMEOUT = HZ/2; // 2 sec//modified to 500ms
2313 long ret;
2314 #endif
2315 //backup video mode
2316 OUTREG32(&mode_ctl_backup, AS_UINT32(&DSI_REG->DSI_MODE_CTRL));
2317 OUTREG32(&mode_ctl, AS_UINT32(&DSI_REG->DSI_MODE_CTRL));
2318 //set to cmd mode
2319 mode_ctl.MODE = 0;
2320 OUTREG32(&DSI_REG->DSI_MODE_CTRL, AS_UINT32(&mode_ctl));
2321 #if ENABLE_DSI_INTERRUPT //wait video mode done
2322
2323 wait_vm_done_irq = true;
2324 ret = wait_event_interruptible_timeout(_dsi_wait_vm_done_queue,
2325 !_IsEngineBusy(),
2326 WAIT_TIMEOUT);
2327 if (0 == ret) {
2328 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine read ready timeout!!!\n");
2329
2330 DSI_DumpRegisters();
2331 ///do necessary reset here
2332 DSI_Reset();
2333 wait_vm_done_irq = false;
2334 return 0;
2335 }
2336
2337 #else
2338 unsigned int read_timeout_ms = 100;
2339 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
2340 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " Start polling VM done ready!!!\n");
2341 #endif
2342 while(DSI_REG->DSI_INTSTA.VM_DONE== 0) //clear
2343 {
2344 ///keep polling
2345 msleep(1);
2346 read_timeout_ms --;
2347
2348 if(read_timeout_ms == 0)
2349 {
2350 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " Polling DSI VM done timeout!!!\n");
2351 DSI_DumpRegisters();
2352
2353 DSI_Reset();
2354 return 0;
2355 }
2356 }
2357 //DSI_REG->DSI_INTSTA.VM_DONE = 0;
2358 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,VM_DONE,0);
2359 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
2360 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " End polling DSI VM done ready!!!\n");
2361 #endif
2362 #endif
2363 //read DriverIC and check ESD
2364 result = lcm_drv->esd_check();
2365 //restore video mode
2366 if(!result)
2367 OUTREG32(&DSI_REG->DSI_MODE_CTRL, AS_UINT32(&mode_ctl_backup));
2368 #endif
2369 wait_vm_done_irq = false;
2370 return result;
2371 }
2372
2373
2374 void DSI_set_int_TE(bool enable, unsigned int period)
2375 {
2376 #ifndef MT65XX_NEW_DISP
2377 dsi_int_te_enabled = enable;
2378 if(period<1)
2379 period = 1;
2380 dsi_int_te_period = period;
2381 dsi_dpi_isr_count = 0;
2382 #endif
2383 }
2384
2385
2386 // called by DPI ISR.
2387 bool DSI_handle_int_TE(void)
2388 {
2389 #ifndef CONFIG_ARCH_MT8127
2390 #ifndef MT65XX_NEW_DISP
2391 DSI_T0_INS t0;
2392 long int dsi_current_time;
2393
2394 if (!DSI_REG->DSI_MODE_CTRL.MODE)
2395 return false;
2396
2397 dsi_current_time = get_current_time_us();
2398
2399 if(DSI_REG->DSI_STATE_DBG3.TCON_STATE == DSI_VDO_VFP_STATE)
2400 {
2401 udelay(_dsiContext.vfp_period_us / 2);
2402
2403 if ((DSI_REG->DSI_STATE_DBG3.TCON_STATE == DSI_VDO_VFP_STATE) && DSI_REG->DSI_STATE_DBG0.CTL_STATE_0 == 0x1)
2404 {
2405 // Can't do int. TE check while INUSE FB number is not 0 because later disable/enable DPI will set INUSE FB to number 0.
2406 if(DPI_REG->STATUS.FB_INUSE != 0)
2407 return false;
2408
2409 DSI_clk_HS_mode(0);
2410
2411 //DSI_REG->DSI_COM_CTRL.DSI_RESET = 1;
2412 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,1);
2413 DPI_DisableClk();
2414 DSI_SetMode(CMD_MODE);
2415 //DSI_REG->DSI_COM_CTRL.DSI_RESET = 0;
2416 OUTREGBIT(DSI_COM_CTRL_REG,DSI_REG->DSI_COM_CTRL,DSI_RESET,0);
2417 //DSI_Reset();
2418
2419 t0.CONFG = 0x20; ///TE
2420 t0.Data0 = 0;
2421 t0.Data_ID = 0;
2422 t0.Data1 = 0;
2423
2424 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
2425 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
2426
2427 // Enable RD_RDY INT for polling it's status later
2428 //DSI_REG->DSI_INTEN.RD_RDY = 1;
2429 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
2430
2431 DSI_Start();
2432
2433 while(DSI_REG->DSI_INTSTA.RD_RDY == 0) // polling RD_RDY
2434 {
2435 if(get_current_time_us() - dsi_current_time > _dsiContext.vfp_period_us)
2436 {
2437 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for internal TE time-out for %d (us)!!!\n", _dsiContext.vfp_period_us);
2438
2439 ///do necessary reset here
2440 //DSI_REG->DSI_RACK.DSI_RACK = 1;
2441 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
2442 DSI_Reset();
2443
2444 return true;
2445 }
2446 }
2447
2448 // Write clear RD_RDY
2449 //DSI_REG->DSI_INTSTA.RD_RDY = 1;
2450 //DSI_REG->DSI_RACK.DSI_RACK = 1;
2451 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,RD_RDY,1);
2452 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
2453 // Write clear CMD_DONE
2454 //DSI_REG->DSI_INTSTA.CMD_DONE = 1;
2455 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,1);
2456
2457 // Restart video mode. (with VSA ahead)
2458 DSI_SetMode(SYNC_PULSE_VDO_MODE);
2459 DSI_clk_HS_mode(1);
2460 DPI_EnableClk();
2461 DSI_Start();
2462 }
2463
2464 }
2465 #endif
2466 #endif
2467 return false;
2468
2469 }
2470
2471
2472 void DSI_set_noncont_clk(bool enable, unsigned int period)
2473 {
2474 dsi_noncont_clk_enabled = enable;
2475 // dsi_noncont_clk_period = period;
2476 }
2477
2478 void DSI_Detect_glitch_enable(bool enable)
2479 {
2480 dsi_glitch_enable = enable;
2481 }
2482 // called by DPI ISR.
2483 void DSI_handle_noncont_clk(void)
2484 {
2485 #ifndef CONFIG_ARCH_MT8127
2486 #ifndef MT65XX_NEW_DISP
2487 unsigned int state;
2488 long int dsi_current_time;
2489
2490 if (!DSI_REG->DSI_MODE_CTRL.MODE)
2491 return ;
2492
2493 state = DSI_REG->DSI_STATE_DBG3.TCON_STATE;
2494
2495 dsi_current_time = get_current_time_us();
2496
2497 switch(state)
2498 {
2499 case DSI_VDO_VSA_VS_STATE:
2500 while(DSI_REG->DSI_STATE_DBG3.TCON_STATE != DSI_VDO_VSA_HS_STATE)
2501 {
2502 if(get_current_time_us() - dsi_current_time > _dsiContext.vsa_vs_period_us)
2503 {
2504 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for %x state timeout %d (us)!!!\n", DSI_VDO_VSA_HS_STATE, _dsiContext.vsa_vs_period_us);
2505 return ;
2506 }
2507 }
2508 break;
2509
2510 case DSI_VDO_VSA_HS_STATE:
2511 while(DSI_REG->DSI_STATE_DBG3.TCON_STATE != DSI_VDO_VSA_VE_STATE)
2512 {
2513 if(get_current_time_us() - dsi_current_time > _dsiContext.vsa_hs_period_us)
2514 {
2515 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for %x state timeout %d (us)!!!\n", DSI_VDO_VSA_VE_STATE, _dsiContext.vsa_hs_period_us);
2516 return ;
2517 }
2518 }
2519 break;
2520
2521 case DSI_VDO_VSA_VE_STATE:
2522 while(DSI_REG->DSI_STATE_DBG3.TCON_STATE != DSI_VDO_VBP_STATE)
2523 {
2524 if(get_current_time_us() - dsi_current_time > _dsiContext.vsa_ve_period_us)
2525 {
2526 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for %x state timeout %d (us)!!!\n", DSI_VDO_VBP_STATE, _dsiContext.vsa_ve_period_us);
2527 return ;
2528 }
2529 }
2530 break;
2531
2532 case DSI_VDO_VBP_STATE:
2533 xlog_printk(ANDROID_LOG_WARN, "DSI", "Can't do clock switch in DSI_VDO_VBP_STATE !!!\n");
2534 break;
2535
2536 case DSI_VDO_VACT_STATE:
2537 while(DSI_REG->DSI_STATE_DBG3.TCON_STATE != DSI_VDO_VFP_STATE)
2538 {
2539 if(get_current_time_us() - dsi_current_time > _dsiContext.vfp_period_us )
2540 {
2541 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for %x state timeout %d (us)!!!\n", DSI_VDO_VFP_STATE, _dsiContext.vfp_period_us );
2542 return ;
2543 }
2544 }
2545 break;
2546
2547 case DSI_VDO_VFP_STATE:
2548 while(DSI_REG->DSI_STATE_DBG3.TCON_STATE != DSI_VDO_VSA_VS_STATE)
2549 {
2550 if(get_current_time_us() - dsi_current_time > _dsiContext.vfp_period_us )
2551 {
2552 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for %x state timeout %d (us)!!!\n", DSI_VDO_VSA_VS_STATE, _dsiContext.vfp_period_us );
2553 return ;
2554 }
2555 }
2556 break;
2557
2558 default :
2559 xlog_printk(ANDROID_LOG_ERROR, "DSI", "invalid state = %x \n", state);
2560 return ;
2561 }
2562
2563 // Clock switch HS->LP->HS
2564 DSI_clk_HS_mode(0);
2565 udelay(1);
2566 DSI_clk_HS_mode(1);
2567 #endif
2568 #endif
2569 }
2570
2571 #ifdef ENABLE_DSI_ERROR_REPORT
2572 static unsigned int _dsi_cmd_queue[32];
2573 #endif
2574 void DSI_set_cmdq_V2(unsigned cmd, unsigned char count, unsigned char *para_list, unsigned char force_update)
2575 {
2576 UINT32 i;
2577 UINT32 goto_addr, mask_para, set_para;
2578 //UINT32 fbPhysAddr, fbVirAddr;
2579 DSI_T0_INS t0;
2580 DSI_T2_INS t2;
2581 if (0 != DSI_REG->DSI_MODE_CTRL.MODE){//not in cmd mode
2582 DSI_VM_CMD_CON_REG vm_cmdq;
2583 OUTREG32(&vm_cmdq, AS_UINT32(&DSI_REG->DSI_VM_CMD_CON));
2584 printk("set cmdq in VDO mode in set_cmdq_V2\n");
2585 if (cmd < 0xB0)
2586 {
2587 if (count > 1)
2588 {
2589 vm_cmdq.LONG_PKT = 1;
2590 vm_cmdq.CM_DATA_ID = DSI_DCS_LONG_PACKET_ID;
2591 vm_cmdq.CM_DATA_0 = count+1;
2592 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2593
2594 goto_addr = (UINT32)(&DSI_VM_CMD_REG->data[0].byte0);
2595 mask_para = (0xFF<<((goto_addr&0x3)*8));
2596 set_para = (cmd<<((goto_addr&0x3)*8));
2597 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2598
2599 for(i=0; i<count; i++)
2600 {
2601 goto_addr = (UINT32)(&DSI_VM_CMD_REG->data[0].byte1) + i;
2602 mask_para = (0xFF<<((goto_addr&0x3)*8));
2603 set_para = (para_list[i]<<((goto_addr&0x3)*8));
2604 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2605 }
2606 }
2607 else
2608 {
2609 vm_cmdq.LONG_PKT = 0;
2610 vm_cmdq.CM_DATA_0 = cmd;
2611 if (count)
2612 {
2613 vm_cmdq.CM_DATA_ID = DSI_DCS_SHORT_PACKET_ID_1;
2614 vm_cmdq.CM_DATA_1 = para_list[0];
2615 }
2616 else
2617 {
2618 vm_cmdq.CM_DATA_ID = DSI_DCS_SHORT_PACKET_ID_0;
2619 vm_cmdq.CM_DATA_1 = 0;
2620 }
2621 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2622 }
2623 }
2624 else{
2625 if (count > 1)
2626 {
2627 vm_cmdq.LONG_PKT = 1;
2628 vm_cmdq.CM_DATA_ID = DSI_GERNERIC_LONG_PACKET_ID;
2629 vm_cmdq.CM_DATA_0 = count+1;
2630 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2631
2632 goto_addr = (UINT32)(&DSI_VM_CMD_REG->data[0].byte0);
2633 mask_para = (0xFF<<((goto_addr&0x3)*8));
2634 set_para = (cmd<<((goto_addr&0x3)*8));
2635 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2636
2637 for(i=0; i<count; i++)
2638 {
2639 goto_addr = (UINT32)(&DSI_VM_CMD_REG->data[0].byte1) + i;
2640 mask_para = (0xFF<<((goto_addr&0x3)*8));
2641 set_para = (para_list[i]<<((goto_addr&0x3)*8));
2642 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2643 }
2644 }
2645 else
2646 {
2647 vm_cmdq.LONG_PKT = 0;
2648 vm_cmdq.CM_DATA_0 = cmd;
2649 if (count)
2650 {
2651 vm_cmdq.CM_DATA_ID = DSI_GERNERIC_SHORT_PACKET_ID_2;
2652 vm_cmdq.CM_DATA_1 = para_list[0];
2653 }
2654 else
2655 {
2656 vm_cmdq.CM_DATA_ID = DSI_GERNERIC_SHORT_PACKET_ID_1;
2657 vm_cmdq.CM_DATA_1 = 0;
2658 }
2659 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2660 }
2661 }
2662 //start DSI VM CMDQ
2663 if(force_update){
2664 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagStart, *(unsigned int*)(&DSI_VM_CMD_REG->data[0]), *(unsigned int*)(&DSI_VM_CMD_REG->data[1]));
2665 DSI_EnableVM_CMD();
2666
2667 //must wait VM CMD done?
2668 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagEnd, *(unsigned int*)(&DSI_VM_CMD_REG->data[2]), *(unsigned int*)(&DSI_VM_CMD_REG->data[3]));
2669 }
2670 }
2671 else{
2672 #ifdef ENABLE_DSI_ERROR_REPORT
2673 if ((para_list[0] & 1))
2674 {
2675 memset(_dsi_cmd_queue, 0, sizeof(_dsi_cmd_queue));
2676 memcpy(_dsi_cmd_queue, para_list, count);
2677 _dsi_cmd_queue[(count+3)/4*4] = 0x4;
2678 count = (count+3)/4*4 + 4;
2679 para_list = (unsigned char*) _dsi_cmd_queue;
2680 }
2681 else
2682 {
2683 para_list[0] |= 4;
2684 }
2685 #endif
2686 _WaitForEngineNotBusy();
2687 if (cmd < 0xB0)
2688 {
2689 if (count > 1)
2690 {
2691 t2.CONFG = 2;
2692 t2.Data_ID = DSI_DCS_LONG_PACKET_ID;
2693 t2.WC16 = count+1;
2694
2695 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t2));
2696
2697 goto_addr = (UINT32)(&DSI_CMDQ_REG->data[1].byte0);
2698 mask_para = (0xFF<<((goto_addr&0x3)*8));
2699 set_para = (cmd<<((goto_addr&0x3)*8));
2700 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2701
2702 for(i=0; i<count; i++)
2703 {
2704 goto_addr = (UINT32)(&DSI_CMDQ_REG->data[1].byte1) + i;
2705 mask_para = (0xFF<<((goto_addr&0x3)*8));
2706 set_para = (para_list[i]<<((goto_addr&0x3)*8));
2707 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2708 }
2709
2710 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 2+(count)/4);
2711 }
2712 else
2713 {
2714 t0.CONFG = 0;
2715 t0.Data0 = cmd;
2716 if (count)
2717 {
2718 t0.Data_ID = DSI_DCS_SHORT_PACKET_ID_1;
2719 t0.Data1 = para_list[0];
2720 }
2721 else
2722 {
2723 t0.Data_ID = DSI_DCS_SHORT_PACKET_ID_0;
2724 t0.Data1 = 0;
2725 }
2726 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
2727 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
2728 }
2729 }
2730 else
2731 {
2732 if (count > 1)
2733 {
2734 t2.CONFG = 2;
2735 t2.Data_ID = DSI_GERNERIC_LONG_PACKET_ID;
2736 t2.WC16 = count+1;
2737
2738 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t2));
2739
2740 goto_addr = (UINT32)(&DSI_CMDQ_REG->data[1].byte0);
2741 mask_para = (0xFF<<((goto_addr&0x3)*8));
2742 set_para = (cmd<<((goto_addr&0x3)*8));
2743 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2744
2745 for(i=0; i<count; i++)
2746 {
2747 goto_addr = (UINT32)(&DSI_CMDQ_REG->data[1].byte1) + i;
2748 mask_para = (0xFF<<((goto_addr&0x3)*8));
2749 set_para = (para_list[i]<<((goto_addr&0x3)*8));
2750 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2751 }
2752
2753 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 2+(count)/4);
2754
2755 }
2756 else
2757 {
2758 t0.CONFG = 0;
2759 t0.Data0 = cmd;
2760 if (count)
2761 {
2762 t0.Data_ID = DSI_GERNERIC_SHORT_PACKET_ID_2;
2763 t0.Data1 = para_list[0];
2764 }
2765 else
2766 {
2767 t0.Data_ID = DSI_GERNERIC_SHORT_PACKET_ID_1;
2768 t0.Data1 = 0;
2769 }
2770 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
2771 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
2772 }
2773 }
2774
2775 // for (i = 0; i < AS_UINT32(&DSI_REG->DSI_CMDQ_SIZE); i++)
2776 // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI_set_cmdq_V2. DSI_CMDQ+%04x : 0x%08x\n", i*4, INREG32(DSI_BASE + 0x180 + i*4));
2777
2778 if(force_update)
2779 {
2780 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagStart, *(unsigned int*)(&DSI_CMDQ_REG->data[0]), *(unsigned int*)(&DSI_CMDQ_REG->data[1]));
2781 DSI_Start();
2782 for(i=0; i<10; i++) ;
2783 _WaitForEngineNotBusy();
2784 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagEnd, *(unsigned int*)(&DSI_CMDQ_REG->data[2]), *(unsigned int*)(&DSI_CMDQ_REG->data[3]));
2785 }
2786 }
2787
2788 }
2789
2790 void DSI_set_cmdq_V3(LCM_setting_table_V3 *para_tbl, unsigned int size, unsigned char force_update)
2791 {
2792 UINT32 i;
2793 UINT32 goto_addr, mask_para, set_para;
2794 //UINT32 fbPhysAddr, fbVirAddr;
2795 DSI_T0_INS t0;
2796 //DSI_T1_INS t1;
2797 DSI_T2_INS t2;
2798
2799 UINT32 index = 0;
2800
2801 unsigned char data_id, cmd, count;
2802 unsigned char *para_list;
2803
2804 do {
2805 data_id = para_tbl[index].id;
2806 cmd = para_tbl[index].cmd;
2807 count = para_tbl[index].count;
2808 para_list = para_tbl[index].para_list;
2809
2810 if (data_id == REGFLAG_ESCAPE_ID && cmd == REGFLAG_DELAY_MS_V3)
2811 {
2812 udelay(1000*count);
2813 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI_set_cmdq_V3[%d]. Delay %d (ms) \n", index, count);
2814
2815 continue;
2816 }
2817
2818 if (0 != DSI_REG->DSI_MODE_CTRL.MODE){//not in cmd mode
2819 DSI_VM_CMD_CON_REG vm_cmdq;
2820 OUTREG32(&vm_cmdq, AS_UINT32(&DSI_REG->DSI_VM_CMD_CON));
2821 printk("set cmdq in VDO mode\n");
2822 if (count > 1)
2823 {
2824 vm_cmdq.LONG_PKT = 1;
2825 vm_cmdq.CM_DATA_ID = data_id;
2826 vm_cmdq.CM_DATA_0 = count+1;
2827 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2828
2829 goto_addr = (UINT32)(&DSI_VM_CMD_REG->data[0].byte0);
2830 mask_para = (0xFF<<((goto_addr&0x3)*8));
2831 set_para = (cmd<<((goto_addr&0x3)*8));
2832 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2833
2834 for(i=0; i<count; i++)
2835 {
2836 goto_addr = (UINT32)(&DSI_VM_CMD_REG->data[0].byte1) + i;
2837 mask_para = (0xFF<<((goto_addr&0x3)*8));
2838 set_para = (para_list[i]<<((goto_addr&0x3)*8));
2839 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2840 }
2841 }
2842 else
2843 {
2844 vm_cmdq.LONG_PKT = 0;
2845 vm_cmdq.CM_DATA_0 = cmd;
2846 if (count)
2847 {
2848 vm_cmdq.CM_DATA_ID = data_id;
2849 vm_cmdq.CM_DATA_1 = para_list[0];
2850 }
2851 else
2852 {
2853 vm_cmdq.CM_DATA_ID = data_id;
2854 vm_cmdq.CM_DATA_1 = 0;
2855 }
2856 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2857 }
2858 //start DSI VM CMDQ
2859 if(force_update){
2860 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagStart, *(unsigned int*)(&DSI_VM_CMD_REG->data[0]), *(unsigned int*)(&DSI_VM_CMD_REG->data[1]));
2861 DSI_EnableVM_CMD();
2862
2863 //must wait VM CMD done?
2864 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagEnd, *(unsigned int*)(&DSI_VM_CMD_REG->data[2]), *(unsigned int*)(&DSI_VM_CMD_REG->data[3]));
2865 }
2866 }
2867 else{
2868 _WaitForEngineNotBusy();
2869 {
2870 //for(i = 0; i < sizeof(DSI_CMDQ_REG->data0) / sizeof(DSI_CMDQ); i++)
2871 // OUTREG32(&DSI_CMDQ_REG->data0[i], 0);
2872 //memset(&DSI_CMDQ_REG->data[0], 0, sizeof(DSI_CMDQ_REG->data[0]));
2873 OUTREG32(&DSI_CMDQ_REG->data[0], 0);
2874
2875 if (count > 1)
2876 {
2877 t2.CONFG = 2;
2878 t2.Data_ID = data_id;
2879 t2.WC16 = count+1;
2880
2881 OUTREG32(&DSI_CMDQ_REG->data[0].byte0, AS_UINT32(&t2));
2882
2883 goto_addr = (UINT32)(&DSI_CMDQ_REG->data[1].byte0);
2884 mask_para = (0xFF<<((goto_addr&0x3)*8));
2885 set_para = (cmd<<((goto_addr&0x3)*8));
2886 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2887
2888 for(i=0; i<count; i++)
2889 {
2890 goto_addr = (UINT32)(&DSI_CMDQ_REG->data[1].byte1) + i;
2891 mask_para = (0xFF<<((goto_addr&0x3)*8));
2892 set_para = (para_list[i]<<((goto_addr&0x3)*8));
2893 MASKREG32(goto_addr&(~0x3), mask_para, set_para);
2894 }
2895
2896 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 2+(count)/4);
2897 }
2898 else
2899 {
2900 t0.CONFG = 0;
2901 t0.Data0 = cmd;
2902 if (count)
2903 {
2904 t0.Data_ID = data_id;
2905 t0.Data1 = para_list[0];
2906 }
2907 else
2908 {
2909 t0.Data_ID = data_id;
2910 t0.Data1 = 0;
2911 }
2912 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
2913 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
2914 }
2915
2916 for (i = 0; i < AS_UINT32(&DSI_REG->DSI_CMDQ_SIZE); i++)
2917 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI_set_cmdq_V3[%d]. DSI_CMDQ+%04x : 0x%08x\n", index, i*4, INREG32(DSI_BASE + 0x180 + i*4));
2918
2919 if(force_update)
2920 {
2921 MMProfileLog(MTKFB_MMP_Events.DSICmd, MMProfileFlagStart);
2922 DSI_Start();
2923 for(i=0; i<10; i++) ;
2924 _WaitForEngineNotBusy();
2925 MMProfileLog(MTKFB_MMP_Events.DSICmd, MMProfileFlagEnd);
2926 }
2927 }
2928 }
2929 } while (++index < size);
2930
2931 }
2932
2933 void DSI_set_cmdq(unsigned int *pdata, unsigned int queue_size, unsigned char force_update)
2934 {
2935 UINT32 i;
2936
2937 // _WaitForEngineNotBusy();
2938
2939 if (0 != DSI_REG->DSI_MODE_CTRL.MODE){//not in cmd mode
2940 DSI_VM_CMD_CON_REG vm_cmdq;
2941 OUTREG32(&vm_cmdq, AS_UINT32(&DSI_REG->DSI_VM_CMD_CON));
2942 printk("set cmdq in VDO mode\n");
2943 if(queue_size > 1){//long packet
2944 unsigned int i = 0;
2945 vm_cmdq.LONG_PKT = 1;
2946 vm_cmdq.CM_DATA_ID = ((pdata[0] >> 8) & 0xFF);
2947 vm_cmdq.CM_DATA_0 = ((pdata[0] >> 16) & 0xFF);
2948 vm_cmdq.CM_DATA_1 = 0;
2949 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2950 for(i=0;i<queue_size-1;i++)
2951 OUTREG32(&DSI_VM_CMD_REG->data[i], AS_UINT32((pdata+i+1)));
2952 }
2953 else{
2954 vm_cmdq.LONG_PKT = 0;
2955 vm_cmdq.CM_DATA_ID = ((pdata[0] >> 8) & 0xFF);
2956 vm_cmdq.CM_DATA_0 = ((pdata[0] >> 16) & 0xFF);
2957 vm_cmdq.CM_DATA_1 = ((pdata[0] >> 24) & 0xFF);
2958 OUTREG32(&DSI_REG->DSI_VM_CMD_CON, AS_UINT32(&vm_cmdq));
2959 }
2960 //start DSI VM CMDQ
2961 if(force_update){
2962 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagStart, *(unsigned int*)(&DSI_VM_CMD_REG->data[0]), *(unsigned int*)(&DSI_VM_CMD_REG->data[1]));
2963 DSI_EnableVM_CMD();
2964
2965 //must wait VM CMD done?
2966 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagEnd, *(unsigned int*)(&DSI_VM_CMD_REG->data[2]), *(unsigned int*)(&DSI_VM_CMD_REG->data[3]));
2967 }
2968 }
2969 else{
2970 ASSERT(queue_size<=32);
2971 _WaitForEngineNotBusy();
2972 #ifdef ENABLE_DSI_ERROR_REPORT
2973 if ((pdata[0] & 1))
2974 {
2975 memcpy(_dsi_cmd_queue, pdata, queue_size*4);
2976 _dsi_cmd_queue[queue_size++] = 0x4;
2977 pdata = (unsigned int*) _dsi_cmd_queue;
2978 }
2979 else
2980 {
2981 pdata[0] |= 4;
2982 }
2983 #endif
2984
2985 for(i=0; i<queue_size; i++)
2986 OUTREG32(&DSI_CMDQ_REG->data[i], AS_UINT32((pdata+i)));
2987
2988 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, queue_size);
2989
2990 // for (i = 0; i < queue_size; i++)
2991 // printk("[DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+%04x : 0x%08x\n", i*4, INREG32(DSI_BASE + 0x180 + i*4));
2992
2993 if(force_update)
2994 {
2995 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagStart, *(unsigned int*)(&DSI_CMDQ_REG->data[0]), *(unsigned int*)(&DSI_CMDQ_REG->data[1]));
2996 DSI_Start();
2997 for(i=0; i<10; i++) ;
2998 _WaitForEngineNotBusy();
2999 MMProfileLogEx(MTKFB_MMP_Events.DSICmd, MMProfileFlagEnd, *(unsigned int*)(&DSI_CMDQ_REG->data[2]), *(unsigned int*)(&DSI_CMDQ_REG->data[3]));
3000 }
3001 }
3002 }
3003
3004
3005 DSI_STATUS DSI_Write_T0_INS(DSI_T0_INS *t0)
3006 {
3007 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(t0));
3008
3009 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
3010 OUTREG32(&DSI_REG->DSI_START, 0);
3011 OUTREG32(&DSI_REG->DSI_START, 1);
3012
3013 return DSI_STATUS_OK;
3014 }
3015
3016
3017 DSI_STATUS DSI_Write_T1_INS(DSI_T1_INS *t1)
3018 {
3019 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(t1));
3020
3021 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
3022 OUTREG32(&DSI_REG->DSI_START, 0);
3023 OUTREG32(&DSI_REG->DSI_START, 1);
3024
3025 return DSI_STATUS_OK;
3026 }
3027
3028
3029 DSI_STATUS DSI_Write_T2_INS(DSI_T2_INS *t2)
3030 {
3031 unsigned int i;
3032
3033 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(t2));
3034
3035 for(i=0;i<((t2->WC16-1)>>2)+1;i++)
3036 OUTREG32(&DSI_CMDQ_REG->data[1+i], AS_UINT32((t2->pdata+i)));
3037
3038 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, (((t2->WC16-1)>>2)+2));
3039 OUTREG32(&DSI_REG->DSI_START, 0);
3040 OUTREG32(&DSI_REG->DSI_START, 1);
3041
3042 return DSI_STATUS_OK;
3043 }
3044
3045
3046 DSI_STATUS DSI_Write_T3_INS(DSI_T3_INS *t3)
3047 {
3048 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(t3));
3049
3050 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
3051 OUTREG32(&DSI_REG->DSI_START, 0);
3052 OUTREG32(&DSI_REG->DSI_START, 1);
3053
3054 return DSI_STATUS_OK;
3055 }
3056
3057 DSI_STATUS DSI_TXRX_Control(bool cksm_en,
3058 bool ecc_en,
3059 unsigned char lane_num,
3060 unsigned char vc_num,
3061 bool null_packet_en,
3062 bool err_correction_en,
3063 bool dis_eotp_en,
3064 bool hstx_cklp_en,
3065 unsigned int max_return_size)
3066 {
3067 DSI_TXRX_CTRL_REG tmp_reg;
3068 tmp_reg=DSI_REG->DSI_TXRX_CTRL;
3069
3070 ///TODO: parameter checking
3071 // tmp_reg.CKSM_EN=cksm_en;
3072 // tmp_reg.ECC_EN=ecc_en;
3073 switch(lane_num)
3074 {
3075 case LCM_ONE_LANE:tmp_reg.LANE_NUM = 1;break;
3076 case LCM_TWO_LANE:tmp_reg.LANE_NUM = 3;break;
3077 case LCM_THREE_LANE:tmp_reg.LANE_NUM = 0x7;break;
3078 case LCM_FOUR_LANE:tmp_reg.LANE_NUM = 0xF;break;
3079 }
3080 tmp_reg.VC_NUM=vc_num;
3081 // tmp_reg.CORR_EN = err_correction_en;
3082 tmp_reg.DIS_EOT = dis_eotp_en;
3083 tmp_reg.NULL_EN = null_packet_en;
3084 tmp_reg.MAX_RTN_SIZE = max_return_size;
3085 tmp_reg.HSTX_CKLP_EN = hstx_cklp_en;
3086 OUTREG32(&DSI_REG->DSI_TXRX_CTRL, AS_UINT32(&tmp_reg));
3087
3088 return DSI_STATUS_OK;
3089 }
3090
3091
3092 DSI_STATUS DSI_PS_Control(unsigned int ps_type, unsigned int vact_line, unsigned int ps_wc)
3093 {
3094 DSI_PSCTRL_REG tmp_reg;
3095 UINT32 tmp_hstx_cklp_wc;
3096 tmp_reg=DSI_REG->DSI_PSCTRL;
3097
3098 ///TODO: parameter checking
3099 ASSERT(ps_type <= PACKED_PS_18BIT_RGB666);
3100 if(ps_type>LOOSELY_PS_18BIT_RGB666)
3101 tmp_reg.DSI_PS_SEL=(5 - ps_type);
3102 else
3103 tmp_reg.DSI_PS_SEL=ps_type;
3104 tmp_reg.DSI_PS_WC=ps_wc;
3105 tmp_hstx_cklp_wc = ps_wc;
3106
3107 OUTREG32(&DSI_REG->DSI_VACT_NL, AS_UINT32(&vact_line));
3108 OUTREG32(&DSI_REG->DSI_PSCTRL, AS_UINT32(&tmp_reg));
3109 OUTREG32(&DSI_REG->DSI_HSTX_CKL_WC, tmp_hstx_cklp_wc);
3110 return DSI_STATUS_OK;
3111 }
3112
3113
3114 #define ALIGN_TO(x, n) \
3115 (((x) + ((n) - 1)) & ~((n) - 1))
3116 //unsigned int dsi_cycle_time;
3117
3118 void DSI_Config_VDO_Timing(LCM_PARAMS *lcm_params)
3119 {
3120 unsigned int line_byte;
3121 unsigned int horizontal_sync_active_byte = 0;
3122 unsigned int horizontal_backporch_byte;
3123 unsigned int horizontal_frontporch_byte;
3124 unsigned int horizontal_bllp_byte;
3125 unsigned int dsiTmpBufBpp;
3126
3127 #define LINE_PERIOD_US (8 * line_byte * _dsiContext.bit_time_ns / 1000)
3128
3129 if(lcm_params->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
3130 dsiTmpBufBpp = 2;
3131 else
3132 dsiTmpBufBpp = 3;
3133
3134 OUTREG32(&DSI_REG->DSI_VSA_NL, lcm_params->dsi.vertical_sync_active);
3135 OUTREG32(&DSI_REG->DSI_VBP_NL, lcm_params->dsi.vertical_backporch);
3136 OUTREG32(&DSI_REG->DSI_VFP_NL, lcm_params->dsi.vertical_frontporch);
3137 OUTREG32(&DSI_REG->DSI_VACT_NL, lcm_params->dsi.vertical_active_line);
3138
3139 line_byte = (lcm_params->dsi.horizontal_sync_active \
3140 + lcm_params->dsi.horizontal_backporch \
3141 + lcm_params->dsi.horizontal_frontporch \
3142 + lcm_params->dsi.horizontal_active_pixel) * dsiTmpBufBpp;
3143
3144 if (lcm_params->dsi.mode == SYNC_EVENT_VDO_MODE || lcm_params->dsi.mode == BURST_VDO_MODE ){
3145 ASSERT((lcm_params->dsi.horizontal_backporch + lcm_params->dsi.horizontal_sync_active) * dsiTmpBufBpp> 9);
3146 horizontal_backporch_byte = ((lcm_params->dsi.horizontal_backporch + lcm_params->dsi.horizontal_sync_active)* dsiTmpBufBpp - 10);
3147 }
3148 else{
3149 ASSERT(lcm_params->dsi.horizontal_sync_active * dsiTmpBufBpp > 9);
3150 horizontal_sync_active_byte = (lcm_params->dsi.horizontal_sync_active * dsiTmpBufBpp - 10);
3151
3152 ASSERT(lcm_params->dsi.horizontal_backporch * dsiTmpBufBpp > 9);
3153 horizontal_backporch_byte = (lcm_params->dsi.horizontal_backporch * dsiTmpBufBpp - 10);
3154 }
3155
3156 ASSERT(lcm_params->dsi.horizontal_frontporch * dsiTmpBufBpp > 11);
3157 horizontal_frontporch_byte = (lcm_params->dsi.horizontal_frontporch * dsiTmpBufBpp - 12);
3158 horizontal_bllp_byte = (lcm_params->dsi.horizontal_bllp * dsiTmpBufBpp);
3159 // ASSERT(lcm_params->dsi.horizontal_frontporch * dsiTmpBufBpp > ((300/dsi_cycle_time) * lcm_params->dsi.LANE_NUM));
3160 // horizontal_frontporch_byte -= ((300/dsi_cycle_time) * lcm_params->dsi.LANE_NUM);
3161
3162 OUTREG32(&DSI_REG->DSI_HSA_WC, ALIGN_TO((horizontal_sync_active_byte), 4));
3163 OUTREG32(&DSI_REG->DSI_HBP_WC, ALIGN_TO((horizontal_backporch_byte), 4));
3164 OUTREG32(&DSI_REG->DSI_HFP_WC, ALIGN_TO((horizontal_frontporch_byte), 4));
3165 OUTREG32(&DSI_REG->DSI_BLLP_WC, ALIGN_TO((horizontal_bllp_byte), 4));
3166
3167 _dsiContext.vfp_period_us = LINE_PERIOD_US * lcm_params->dsi.vertical_frontporch / 1000;
3168 _dsiContext.vsa_vs_period_us = LINE_PERIOD_US * 1 / 1000;
3169 _dsiContext.vsa_hs_period_us = LINE_PERIOD_US * (lcm_params->dsi.vertical_sync_active - 2) / 1000;
3170 _dsiContext.vsa_ve_period_us = LINE_PERIOD_US * 1 / 1000;
3171 _dsiContext.vbp_period_us = LINE_PERIOD_US * lcm_params->dsi.vertical_backporch / 1000;
3172
3173 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - video timing, mode = %d \n", lcm_params->dsi.mode);
3174 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - VSA : %d %d(us)\n", DSI_REG->DSI_VSA_NL, (_dsiContext.vsa_vs_period_us+_dsiContext.vsa_hs_period_us+_dsiContext.vsa_ve_period_us));
3175 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - VBP : %d %d(us)\n", DSI_REG->DSI_VBP_NL, _dsiContext.vbp_period_us);
3176 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - VFP : %d %d(us)\n", DSI_REG->DSI_VFP_NL, _dsiContext.vfp_period_us);
3177 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - VACT: %d \n", DSI_REG->DSI_VACT_NL);
3178 }
3179
3180 void DSI_write_lcm_cmd(unsigned int cmd)
3181 {
3182 DSI_T0_INS t0_tmp;
3183 DSI_CMDQ_CONFG CONFG_tmp;
3184
3185 CONFG_tmp.type=SHORT_PACKET_RW;
3186 CONFG_tmp.BTA=DISABLE_BTA;
3187 CONFG_tmp.HS=LOW_POWER;
3188 CONFG_tmp.CL=CL_8BITS;
3189 CONFG_tmp.TE=DISABLE_TE;
3190 CONFG_tmp.RPT=DISABLE_RPT;
3191
3192 t0_tmp.CONFG = *((unsigned char *)(&CONFG_tmp));
3193 t0_tmp.Data_ID= (cmd&0xFF);
3194 t0_tmp.Data0 = 0x0;
3195 t0_tmp.Data1 = 0x0;
3196
3197 DSI_Write_T0_INS(&t0_tmp);
3198 }
3199
3200
3201 void DSI_write_lcm_regs(unsigned int addr, unsigned int *para, unsigned int nums)
3202 {
3203 DSI_T2_INS *t2_tmp=0;
3204 DSI_CMDQ_CONFG CONFG_tmp;
3205
3206 CONFG_tmp.type=LONG_PACKET_W;
3207 CONFG_tmp.BTA=DISABLE_BTA;
3208 CONFG_tmp.HS=LOW_POWER;
3209 CONFG_tmp.CL=CL_8BITS;
3210 CONFG_tmp.TE=DISABLE_TE;
3211 CONFG_tmp.RPT=DISABLE_RPT;
3212
3213 t2_tmp->CONFG = *((unsigned char *)(&CONFG_tmp));
3214 t2_tmp->Data_ID = (addr&0xFF);
3215 t2_tmp->WC16 = nums;
3216 t2_tmp->pdata = para;
3217
3218 DSI_Write_T2_INS(t2_tmp);
3219
3220 }
3221
3222 UINT32 DSI_dcs_read_lcm_reg(UINT8 cmd)
3223 {
3224 //UINT32 max_try_count = 5;
3225 UINT32 recv_data = 0;
3226 //UINT32 recv_data_cnt;
3227 //unsigned int read_timeout_ms;
3228 //unsigned char packet_type;
3229 #if 0
3230 DSI_T0_INS t0;
3231 #if ENABLE_DSI_INTERRUPT
3232 static const long WAIT_TIMEOUT = 2 * HZ; // 2 sec
3233 long ret;
3234 #endif
3235
3236 if (DSI_REG->DSI_MODE_CTRL.MODE)
3237 return 0;
3238
3239 do
3240 {
3241 if(max_try_count == 0)
3242 return 0;
3243
3244 max_try_count--;
3245 recv_data = 0;
3246 recv_data_cnt = 0;
3247 read_timeout_ms = 20;
3248
3249 _WaitForEngineNotBusy();
3250
3251 t0.CONFG = 0x04; ///BTA
3252 t0.Data0 = cmd;
3253 t0.Data_ID = DSI_DCS_READ_PACKET_ID;
3254 t0.Data1 = 0;
3255
3256 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
3257 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
3258
3259 ///clear read ACK
3260 DSI_REG->DSI_RACK.DSI_RACK = 1;
3261 DSI_REG->DSI_INTSTA.RD_RDY = 1;
3262 DSI_REG->DSI_INTSTA.CMD_DONE = 1;
3263 DSI_REG->DSI_INTEN.RD_RDY = 1;
3264 DSI_REG->DSI_INTEN.CMD_DONE= 1;
3265
3266 OUTREG32(&DSI_REG->DSI_START, 0);
3267 OUTREG32(&DSI_REG->DSI_START, 1);
3268
3269 /// the following code is to
3270 /// 1: wait read ready
3271 /// 2: ack read ready
3272 /// 3: wait for CMDQ_DONE
3273 /// 3: read data
3274 #if ENABLE_DSI_INTERRUPT
3275 ret = wait_event_interruptible_timeout(_dsi_dcs_read_wait_queue,
3276 !_IsEngineBusy(),
3277 WAIT_TIMEOUT);
3278 if (0 == ret) {
3279 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine read ready timeout!!!\n");
3280
3281 DSI_DumpRegisters();
3282
3283 ///do necessary reset here
3284 DSI_REG->DSI_RACK.DSI_RACK = 1;
3285 DSI_Reset();
3286
3287 return 0;
3288 }
3289 #else
3290 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3291 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " Start polling DSI read ready!!!\n");
3292 #endif
3293 while(DSI_REG->DSI_INTSTA.RD_RDY == 0) ///read clear
3294 {
3295 ///keep polling
3296 msleep(1);
3297 read_timeout_ms --;
3298
3299 if(read_timeout_ms == 0)
3300 {
3301 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " Polling DSI read ready timeout!!!\n");
3302 DSI_DumpRegisters();
3303
3304 ///do necessary reset here
3305 DSI_REG->DSI_RACK.DSI_RACK = 1;
3306 DSI_Reset();
3307 return 0;
3308 }
3309 }
3310 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3311 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " End polling DSI read ready!!!\n");
3312 #endif
3313
3314 DSI_REG->DSI_RACK.DSI_RACK = 1;
3315
3316 while(DSI_REG->DSI_STA.BUF_UNDERRUN || DSI_REG->DSI_STA.ESC_ENTRY_ERR || DSI_REG->DSI_STA.LPDT_SYNC_ERR || DSI_REG->DSI_STA.CTRL_ERR || DSI_REG->DSI_STA.CONTENT_ERR)
3317 {
3318 ///DSI READ ACK HW bug workaround
3319 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3320 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI is busy: 0x%x !!!\n", DSI_REG->DSI_STA.BUSY);
3321 #endif
3322 DSI_REG->DSI_RACK.DSI_RACK = 1;
3323 }
3324
3325
3326 ///clear interrupt status
3327 DSI_REG->DSI_INTSTA.RD_RDY = 1;
3328 ///STOP DSI
3329 OUTREG32(&DSI_REG->DSI_START, 0);
3330
3331 #endif
3332
3333 DSI_REG->DSI_INTEN.RD_RDY = 0;
3334
3335 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3336 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_STA : 0x%x \n", DSI_REG->DSI_RX_STA);
3337 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_SIZE : 0x%x \n", DSI_REG->DSI_CMDQ_SIZE.CMDQ_SIZE);
3338 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA0 : 0x%x \n", DSI_CMDQ_REG->data[0].byte0);
3339 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA1 : 0x%x \n", DSI_CMDQ_REG->data[0].byte1);
3340 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA2 : 0x%x \n", DSI_CMDQ_REG->data[0].byte2);
3341 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA3 : 0x%x \n", DSI_CMDQ_REG->data[0].byte3);
3342 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE0 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE0);
3343 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE1 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE1);
3344 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE2 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE2);
3345 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE3 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE3);
3346 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE4 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE4);
3347 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE5 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE5);
3348 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE6 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE6);
3349 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA.BYTE7 : 0x%x \n", DSI_REG->DSI_RX_DATA.BYTE7);
3350 #endif
3351 packet_type = DSI_REG->DSI_RX_DATA.BYTE0;
3352
3353 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3354 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI read packet_type is 0x%x \n",packet_type);
3355 #endif
3356 if(DSI_REG->DSI_RX_STA.LONG == 1)
3357 {
3358 recv_data_cnt = DSI_REG->DSI_RX_DATA.BYTE1 + DSI_REG->DSI_RX_DATA.BYTE2 * 16;
3359 if(recv_data_cnt > 4)
3360 {
3361 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3362 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " DSI read long packet data exceeds 4 bytes \n");
3363 #endif
3364 recv_data_cnt = 4;
3365 }
3366 memcpy((void*)&recv_data, (void*)&DSI_REG->DSI_RX_DATA.BYTE4, recv_data_cnt);
3367 }
3368 else
3369 {
3370 memcpy((void*)&recv_data, (void*)&DSI_REG->DSI_RX_DATA.BYTE1, 2);
3371 }
3372
3373 #ifdef DSI_DRV_DEBUG_LOG_ENABLE
3374 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI read 0x%x data is 0x%x \n",cmd, recv_data);
3375 #endif
3376 }while(packet_type != 0x1C && packet_type != 0x21 && packet_type != 0x22);
3377 /// here: we may receive a ACK packet which packet type is 0x02 (incdicates some error happened)
3378 /// therefore we try re-read again until no ACK packet
3379 /// But: if it is a good way to keep re-trying ???
3380 #endif
3381 return recv_data;
3382 }
3383
3384 /// return value: the data length we got
3385 UINT32 DSI_dcs_read_lcm_reg_v2(UINT8 cmd, UINT8 *buffer, UINT8 buffer_size)
3386 {
3387 UINT32 max_try_count = 5;
3388 UINT32 recv_data_cnt;
3389 unsigned int read_timeout_ms;
3390 unsigned char packet_type;
3391 DSI_RX_DATA_REG read_data0;
3392 DSI_RX_DATA_REG read_data1;
3393 DSI_RX_DATA_REG read_data2;
3394 DSI_RX_DATA_REG read_data3;
3395 #if 1
3396 DSI_T0_INS t0;
3397
3398 #if ENABLE_DSI_INTERRUPT
3399 static const long WAIT_TIMEOUT = HZ/2; // 2 sec//Yifan Modified for ESD Check with out LCM
3400 long ret;
3401 #endif
3402 if (DSI_REG->DSI_MODE_CTRL.MODE)
3403 return 0;
3404
3405 if (buffer == NULL || buffer_size == 0)
3406 return 0;
3407
3408 do
3409 {
3410 if(max_try_count == 0)
3411 return 0;
3412 max_try_count--;
3413 recv_data_cnt = 0;
3414 read_timeout_ms = 20;
3415
3416 _WaitForEngineNotBusy();
3417
3418 t0.CONFG = 0x04; ///BTA
3419 t0.Data0 = cmd;
3420 if (buffer_size < 0x3)
3421 t0.Data_ID = DSI_DCS_READ_PACKET_ID;
3422 else
3423 t0.Data_ID = DSI_GERNERIC_READ_LONG_PACKET_ID;
3424 t0.Data1 = 0;
3425
3426 OUTREG32(&DSI_CMDQ_REG->data[0], AS_UINT32(&t0));
3427 OUTREG32(&DSI_REG->DSI_CMDQ_SIZE, 1);
3428
3429 ///clear read ACK
3430 //DSI_REG->DSI_RACK.DSI_RACK = 1;
3431 //DSI_REG->DSI_INTSTA.RD_RDY = 1;
3432 //DSI_REG->DSI_INTSTA.CMD_DONE = 1;
3433 //DSI_REG->DSI_INTEN.RD_RDY = 1;
3434 //DSI_REG->DSI_INTEN.CMD_DONE= 1;
3435 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
3436 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,RD_RDY,1);
3437 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,CMD_DONE,1);
3438 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
3439 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,CMD_DONE,1);
3440
3441
3442
3443 OUTREG32(&DSI_REG->DSI_START, 0);
3444 OUTREG32(&DSI_REG->DSI_START, 1);
3445
3446 /// the following code is to
3447 /// 1: wait read ready
3448 /// 2: ack read ready
3449 /// 3: wait for CMDQ_DONE
3450 /// 3: read data
3451 #if ENABLE_DSI_INTERRUPT
3452 ret = wait_event_interruptible_timeout(_dsi_dcs_read_wait_queue,
3453 !_IsEngineBusy(),
3454 WAIT_TIMEOUT);
3455 if (0 == ret) {
3456 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine read ready timeout!!!\n");
3457
3458 DSI_DumpRegisters();
3459
3460 ///do necessary reset here
3461 //DSI_REG->DSI_RACK.DSI_RACK = 1;
3462 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
3463 DSI_Reset();
3464
3465 return 0;
3466 }
3467 #else
3468 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3469 if(dsi_log_on)
3470 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " Start polling DSI read ready!!!\n");
3471 #endif
3472 while(DSI_REG->DSI_INTSTA.RD_RDY == 0) ///read clear
3473 {
3474 ///keep polling
3475 msleep(1);
3476 read_timeout_ms --;
3477
3478 if(read_timeout_ms == 0)
3479 {
3480 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " Polling DSI read ready timeout!!!\n");
3481 DSI_DumpRegisters();
3482
3483 ///do necessary reset here
3484 //DSI_REG->DSI_RACK.DSI_RACK = 1;
3485 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
3486 DSI_Reset();
3487 return 0;
3488 }
3489 }
3490 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3491 if(dsi_log_on)
3492 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " End polling DSI read ready!!!\n");
3493 #endif
3494
3495 //DSI_REG->DSI_RACK.DSI_RACK = 1;
3496 OUTREGBIT(DSI_RACK_REG,DSI_REG->DSI_RACK,DSI_RACK,1);
3497
3498 ///clear interrupt status
3499 //DSI_REG->DSI_INTSTA.RD_RDY = 1;
3500 OUTREGBIT(DSI_INT_STATUS_REG,DSI_REG->DSI_INTSTA,RD_RDY,1);
3501 ///STOP DSI
3502 OUTREG32(&DSI_REG->DSI_START, 0);
3503
3504 #endif
3505
3506 //DSI_REG->DSI_INTEN.RD_RDY = 0;
3507 OUTREGBIT(DSI_INT_ENABLE_REG,DSI_REG->DSI_INTEN,RD_RDY,1);
3508
3509 OUTREG32(&read_data0, AS_UINT32(&DSI_REG->DSI_RX_DATA0));
3510 OUTREG32(&read_data1, AS_UINT32(&DSI_REG->DSI_RX_DATA1));
3511 OUTREG32(&read_data2, AS_UINT32(&DSI_REG->DSI_RX_DATA2));
3512 OUTREG32(&read_data3, AS_UINT32(&DSI_REG->DSI_RX_DATA3));
3513 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3514 if(dsi_log_on)
3515 {
3516 unsigned int i;
3517 // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_STA : 0x%x \n", DSI_REG->DSI_RX_STA);
3518 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_SIZE : 0x%x \n", DSI_REG->DSI_CMDQ_SIZE.CMDQ_SIZE);
3519 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA0 : 0x%x \n", DSI_CMDQ_REG->data[0].byte0);
3520 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA1 : 0x%x \n", DSI_CMDQ_REG->data[0].byte1);
3521 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA2 : 0x%x \n", DSI_CMDQ_REG->data[0].byte2);
3522 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_CMDQ_DATA3 : 0x%x \n", DSI_CMDQ_REG->data[0].byte3);
3523 #if 1
3524 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA0 : 0x%x \n", DSI_REG->DSI_RX_DATA0);
3525 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA1 : 0x%x \n", DSI_REG->DSI_RX_DATA1);
3526 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA2 : 0x%x \n", DSI_REG->DSI_RX_DATA2);
3527 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI_RX_DATA3 : 0x%x \n", DSI_REG->DSI_RX_DATA3);
3528
3529 printk("read_data0, %x,%x,%x,%x\n", read_data0.byte0, read_data0.byte1, read_data0.byte2, read_data0.byte3);
3530 printk("read_data1, %x,%x,%x,%x\n", read_data1.byte0, read_data1.byte1, read_data1.byte2, read_data1.byte3);
3531 printk("read_data2, %x,%x,%x,%x\n", read_data2.byte0, read_data2.byte1, read_data2.byte2, read_data2.byte3);
3532 printk("read_data3, %x,%x,%x,%x\n", read_data3.byte0, read_data3.byte1, read_data3.byte2, read_data3.byte3);
3533 #endif
3534 }
3535 #endif
3536
3537 #if 1
3538 packet_type = read_data0.byte0;
3539
3540 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3541 if(dsi_log_on)
3542 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", " DSI read packet_type is 0x%x \n",packet_type);
3543 #endif
3544
3545
3546
3547 if(packet_type == 0x1A || packet_type == 0x1C)
3548 {
3549 recv_data_cnt = read_data0.byte1 + read_data0.byte2 * 16;
3550 if(recv_data_cnt > 10)
3551 {
3552 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3553 if(dsi_log_on)
3554 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " DSI read long packet data exceeds 4 bytes \n");
3555 #endif
3556 recv_data_cnt = 10;
3557 }
3558
3559 if(recv_data_cnt > buffer_size)
3560 {
3561 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3562 if(dsi_log_on)
3563 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " DSI read long packet data exceeds buffer size: %d\n", buffer_size);
3564 #endif
3565 recv_data_cnt = buffer_size;
3566 }
3567 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3568 if(dsi_log_on)
3569 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " DSI read long packet size: %d\n", recv_data_cnt);
3570 #endif
3571 memcpy((void*)buffer, (void*)&read_data1, recv_data_cnt);
3572 }
3573 else
3574 {
3575 if(recv_data_cnt > buffer_size)
3576 {
3577 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3578 if(dsi_log_on)
3579 DISP_LOG_PRINT(ANDROID_LOG_WARN, "DSI", " DSI read short packet data exceeds buffer size: %d\n", buffer_size);
3580 #endif
3581 recv_data_cnt = buffer_size;
3582 }
3583 memcpy((void*)buffer,(void*)&read_data0.byte1, 2);
3584 }
3585 #endif
3586 }while(packet_type != 0x1C && packet_type != 0x21 && packet_type != 0x22 && packet_type != 0x1A);
3587 /// here: we may receive a ACK packet which packet type is 0x02 (incdicates some error happened)
3588 /// therefore we try re-read again until no ACK packet
3589 /// But: if it is a good way to keep re-trying ???
3590 #endif
3591 return recv_data_cnt;
3592 }
3593
3594 UINT32 DSI_read_lcm_reg()
3595 {
3596 return 0;
3597 }
3598
3599
3600 DSI_STATUS DSI_write_lcm_fb(unsigned int addr, bool long_length)
3601 {
3602 DSI_T1_INS t1_tmp;
3603 DSI_CMDQ_CONFG CONFG_tmp;
3604
3605 CONFG_tmp.type=FB_WRITE;
3606 CONFG_tmp.BTA=DISABLE_BTA;
3607 CONFG_tmp.HS=HIGH_SPEED;
3608
3609 if(long_length)
3610 CONFG_tmp.CL=CL_16BITS;
3611 else
3612 CONFG_tmp.CL=CL_8BITS;
3613
3614 CONFG_tmp.TE=DISABLE_TE;
3615 CONFG_tmp.RPT=DISABLE_RPT;
3616
3617
3618 t1_tmp.CONFG = *((unsigned char *)(&CONFG_tmp));
3619 t1_tmp.Data_ID= 0x39;
3620 t1_tmp.mem_start0 = (addr&0xFF);
3621
3622 if(long_length)
3623 t1_tmp.mem_start1 = ((addr>>8)&0xFF);
3624
3625 return DSI_Write_T1_INS(&t1_tmp);
3626
3627
3628 }
3629
3630
3631 DSI_STATUS DSI_read_lcm_fb(unsigned char *buffer)
3632 {
3633 //unsigned int array[2];
3634
3635 _WaitForEngineNotBusy();
3636 #if 0
3637 array[0] = 0x000A3700;// read size
3638 DSI_set_cmdq(array, 1, 1);
3639
3640 DSI_dcs_read_lcm_reg_v2(0x2E,buffer,10);
3641 DSI_dcs_read_lcm_reg_v2(0x2E,buffer+10,10);
3642 DSI_dcs_read_lcm_reg_v2(0x2E,buffer+10*2,10);
3643 DSI_dcs_read_lcm_reg_v2(0x2E,buffer+10*3,10);
3644 DSI_dcs_read_lcm_reg_v2(0x2E,buffer+10*4,10);
3645 DSI_dcs_read_lcm_reg_v2(0x2E,buffer+10*5,10);
3646 #else
3647 // if read_fb not impl, should return info
3648 if(lcm_drv->read_fb)
3649 lcm_drv->read_fb(buffer);
3650 #endif
3651 return DSI_STATUS_OK;
3652 }
3653
3654 unsigned int DSI_Check_LCM(UINT32 color)
3655 {
3656 unsigned int ret = 1;
3657 unsigned char buffer[60];
3658 unsigned int i=0;
3659 OUTREG32(&DSI_REG->DSI_MEM_CONTI, DSI_RMEM_CONTI);
3660 DSI_read_lcm_fb(buffer);
3661 for(i=0;i<60;i++)
3662 printk("%d\n",buffer[i]);
3663 OUTREG32(&DSI_REG->DSI_MEM_CONTI, DSI_WMEM_CONTI);
3664
3665 for(i=0;i<60;i+=3){
3666 printk("read pixel = 0x%x,",(buffer[i]<<16)|(buffer[i+1]<<8)|(buffer[i+2]));
3667 if(((buffer[i]<<16)|(buffer[i+1]<<8)|(buffer[i+2])) != (color&0xFFFFFF)){
3668 ret = 0;
3669 break;
3670 }
3671 }
3672 return ret;
3673 }
3674
3675 unsigned int DSI_BLS_Query(void)
3676 {
3677 printk("BLS: 0x%x\n", INREG32(0xF400A000));
3678 return (0x1 == (INREG32(0xF400A000)&0x1));//if 1, BLS enable
3679 }
3680
3681 void DSI_BLS_Enable(bool enable)
3682 {
3683 if(enable){
3684 OUTREG32(0xF400A0B0, 0x3);
3685 OUTREG32(0xF400A000, 0x00010001);
3686 OUTREG32(0xF400A0B0, 0x0);
3687 }
3688 else{
3689 OUTREG32(0xF400A0B0, 0x3);
3690 OUTREG32(0xF400A000, 0x00010000);
3691 OUTREG32(0xF400A0B0, 0x0);
3692 }
3693 }
3694
3695 DSI_STATUS DSI_enable_MIPI_txio(bool en)
3696 {
3697 #if 0
3698 if(en)
3699 {
3700 *(volatile unsigned int *) (INFRACFG_BASE+0x890) |= 0x00000100; // enable MIPI TX IO
3701 }
3702 else
3703 {
3704 *(volatile unsigned int *) (INFRACFG_BASE+0x890) &= ~0x00000100; // disable MIPI TX IO
3705 }
3706 #endif
3707 return DSI_STATUS_OK;
3708 }
3709
3710
3711 bool Need_Wait_ULPS(void)
3712 {
3713 #ifndef MT65XX_NEW_DISP
3714 if(((INREG32(DSI_BASE + 0x14C)>> 24) & 0xFF) != 0x04) {
3715
3716 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3717 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[%s]:true \n", __func__);
3718 #endif
3719 return TRUE;
3720
3721 } else {
3722
3723 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3724 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[%s]:false \n", __func__);
3725 #endif
3726 return FALSE;
3727
3728 }
3729 #else
3730 return FALSE;
3731 #endif
3732 }
3733
3734
3735 DSI_STATUS Wait_ULPS_Mode(void)
3736 {
3737 #ifndef MT65XX_NEW_DISP
3738 DSI_PHY_LCCON_REG lccon_reg=DSI_REG->DSI_PHY_LCCON;
3739 DSI_PHY_LD0CON_REG ld0con=DSI_REG->DSI_PHY_LD0CON;
3740
3741 lccon_reg.LC_ULPM_EN =1;
3742 ld0con.L0_ULPM_EN=1;
3743 OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&lccon_reg));
3744 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&ld0con));
3745
3746 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3747 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[%s]:enter \n", __func__);
3748 #endif
3749
3750 while(((INREG32(DSI_BASE + 0x14C)>> 24) & 0xFF) != 0x04)
3751 {
3752 lcm_mdelay(5);
3753 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3754 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI+%04x : 0x%08x \n", DSI_BASE, INREG32(DSI_BASE + 0x14C));
3755 #endif
3756 }
3757
3758 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3759 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[%s]:exit \n", __func__);
3760 #endif
3761 #endif
3762 return DSI_STATUS_OK;
3763
3764 }
3765
3766
3767 DSI_STATUS Wait_WakeUp(void)
3768 {
3769 #ifndef MT65XX_NEW_DISP
3770 DSI_PHY_LCCON_REG lccon_reg=DSI_REG->DSI_PHY_LCCON;
3771 DSI_PHY_LD0CON_REG ld0con=DSI_REG->DSI_PHY_LD0CON;
3772
3773 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3774 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[%s]:enter \n", __func__);
3775 #endif
3776
3777 lccon_reg.LC_ULPM_EN =0;
3778 ld0con.L0_ULPM_EN=0;
3779 OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&lccon_reg));
3780 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&ld0con));
3781
3782 lcm_mdelay(1);//Wait 1ms for LCM Spec
3783
3784 lccon_reg.LC_WAKEUP_EN =1;
3785 ld0con.L0_WAKEUP_EN=1;
3786 OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&lccon_reg));
3787 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&ld0con));
3788
3789 while(((INREG32(DSI_BASE + 0x148)>> 8) & 0xFF) != 0x01)
3790 {
3791 lcm_mdelay(5);
3792 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3793 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[soso]DSI+%04x : 0x%08x \n", DSI_BASE, INREG32(DSI_BASE + 0x148));
3794 #endif
3795 }
3796
3797 #ifdef DDI_DRV_DEBUG_LOG_ENABLE
3798 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[%s]:exit \n", __func__);
3799 #endif
3800
3801 lccon_reg.LC_WAKEUP_EN =0;
3802 ld0con.L0_WAKEUP_EN=0;
3803 OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&lccon_reg));
3804 OUTREG32(&DSI_REG->DSI_PHY_LD0CON, AS_UINT32(&ld0con));
3805 #endif
3806 return DSI_STATUS_OK;
3807
3808 }
3809
3810 // -------------------- Retrieve Information --------------------
3811
3812 DSI_STATUS DSI_DumpRegisters(void)
3813 {
3814 UINT32 i;
3815 /*
3816 description of dsi status
3817 Bit Value Description
3818 [0] 0x0001 Idle (wait for command)
3819 [1] 0x0002 Reading command queue for header
3820 [2] 0x0004 Sending type-0 command
3821 [3] 0x0008 Waiting frame data from RDMA for type-1 command
3822 [4] 0x0010 Sending type-1 command
3823 [5] 0x0020 Sending type-2 command
3824 [6] 0x0040 Reading command queue for data
3825 [7] 0x0080 Sending type-3 command
3826 [8] 0x0100 Sending BTA
3827 [9] 0x0200 Waiting RX-read data
3828 [10] 0x0400 Waiting SW RACK for RX-read data
3829 [11] 0x0800 Waiting TE
3830 [12] 0x1000 Get TE
3831 [13] 0x2000 Waiting external TE
3832 [14] 0x4000 Waiting SW RACK for TE
3833
3834 */
3835 static const char* DSI_DBG_STATUS_DESCRIPTION[] =
3836 {
3837 "null",
3838 "Idle (wait for command)",
3839 "Reading command queue for header",
3840 "Sending type-0 command",
3841 "Waiting frame data from RDMA for type-1 command",
3842 "Sending type-1 command",
3843 "Sending type-2 command",
3844 "Reading command queue for data",
3845 "Sending type-3 command",
3846 "Sending BTA",
3847 "Waiting RX-read data ",
3848 "Waiting SW RACK for RX-read data",
3849 "Waiting TE",
3850 "Get TE ",
3851 "Waiting external TE",
3852 "Waiting SW RACK for TE",
3853 };
3854 unsigned int DSI_DBG6_Status = (INREG32(DSI_BASE+0x160))&0xffff;
3855 //unsigned int DSI_DBG6_Status_bak = DSI_DBG6_Status;
3856 int count=0;
3857 while(DSI_DBG6_Status){DSI_DBG6_Status>>=1; count++;}
3858 //while((1<<count) != DSI_DBG6_Status) count++;
3859 //count++;
3860 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "---------- Start dump DSI registers ----------\n");
3861 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI_STATE_DBG6=0x%08x, count=%d, means: [%s]\n", DSI_DBG6_Status, count, DSI_DBG_STATUS_DESCRIPTION[count]);
3862
3863 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "---------- Start dump DSI registers ----------\n");
3864
3865 for (i = 0; i < sizeof(DSI_REGS); i += 16)
3866 {
3867 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI+%04x : 0x%08x 0x%08x 0x%08x 0x%08x\n", i, INREG32(DSI_BASE + i), INREG32(DSI_BASE + i + 0x4), INREG32(DSI_BASE + i + 0x8), INREG32(DSI_BASE + i + 0xc));
3868 }
3869
3870 for (i = 0; i < sizeof(DSI_CMDQ_REGS); i += 16)
3871 {
3872 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI_CMD+%04x : 0x%08x 0x%08x 0x%08x 0x%08x\n", i, INREG32((DSI_BASE+0x180+i)), INREG32((DSI_BASE+0x180+i+0x4)), INREG32((DSI_BASE+0x180+i+0x8)), INREG32((DSI_BASE+0x180+i+0xc)));
3873 }
3874
3875 for (i = 0; i < sizeof(DSI_PHY_REGS); i += 16)
3876 {
3877 DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "DSI_PHY+%04x : 0x%08x 0x%08x 0x%08x 0x%08x\n", i, INREG32((MIPI_CONFIG_BASE+i)), INREG32((MIPI_CONFIG_BASE+i+0x4)), INREG32((MIPI_CONFIG_BASE+i+0x8)), INREG32((MIPI_CONFIG_BASE+i+0xc)));
3878 }
3879
3880 return DSI_STATUS_OK;
3881 }
3882
3883
3884 static LCM_PARAMS lcm_params_for_clk_setting;
3885
3886
3887 DSI_STATUS DSI_FMDesense_Query(void)
3888 {
3889 return DSI_STATUS_OK;
3890 }
3891
3892 DSI_STATUS DSI_FM_Desense(unsigned long freq)
3893 {
3894 ///need check
3895 DSI_Change_CLK(freq);
3896 return DSI_STATUS_OK;
3897 }
3898
3899 DSI_STATUS DSI_Reset_CLK(void)
3900 {
3901 extern LCM_PARAMS *lcm_params;
3902
3903 _WaitForEngineNotBusy();
3904 DSI_PHY_clk_setting(lcm_params);
3905 DSI_PHY_TIMCONFIG(lcm_params);
3906 return DSI_STATUS_OK;
3907 }
3908
3909 DSI_STATUS DSI_Get_Default_CLK(unsigned int *clk)
3910 {
3911 extern LCM_PARAMS *lcm_params;
3912 unsigned int div2_real = lcm_params->dsi.pll_div2 ? lcm_params->dsi.pll_div2 : 0x1;
3913
3914 *clk = 13 * (lcm_params->dsi.pll_div1 + 1) / div2_real;
3915 return DSI_STATUS_OK;
3916 }
3917
3918 DSI_STATUS DSI_Get_Current_CLK(unsigned int *clk)
3919 {
3920 #if 0
3921 if(mipitx_con1.RG_PLL_DIV2 == 0)
3922 *clk = 26 * (mipitx_con1.RG_PLL_DIV1 + 1);
3923 else
3924 *clk = 13 * (mipitx_con1.RG_PLL_DIV1 + 1) / mipitx_con1.RG_PLL_DIV2;
3925 #endif
3926 return DSI_STATUS_OK;
3927 }
3928
3929 DSI_STATUS DSI_Change_CLK(unsigned int clk)
3930 {
3931 extern LCM_PARAMS *lcm_params;
3932
3933 if(clk > 1000)
3934 return DSI_STATUS_ERROR;
3935 memcpy((void *)&lcm_params_for_clk_setting, (void *)lcm_params, sizeof(LCM_PARAMS));
3936
3937 for(lcm_params_for_clk_setting.dsi.pll_div2 = 15; lcm_params_for_clk_setting.dsi.pll_div2 > 0; lcm_params_for_clk_setting.dsi.pll_div2--)
3938 {
3939 for(lcm_params_for_clk_setting.dsi.pll_div1 = 0; lcm_params_for_clk_setting.dsi.pll_div1 < 39; lcm_params_for_clk_setting.dsi.pll_div1++)
3940 {
3941 if((13 * (lcm_params_for_clk_setting.dsi.pll_div1 + 1) / lcm_params_for_clk_setting.dsi.pll_div2) >= clk)
3942 goto end;
3943 }
3944 }
3945
3946 if(lcm_params_for_clk_setting.dsi.pll_div2 == 0)
3947 {
3948 for(lcm_params_for_clk_setting.dsi.pll_div1 = 0; lcm_params_for_clk_setting.dsi.pll_div1 < 39; lcm_params_for_clk_setting.dsi.pll_div1++)
3949 {
3950 if((26 * (lcm_params_for_clk_setting.dsi.pll_div1 + 1)) >= clk)
3951 goto end;
3952 }
3953 }
3954
3955 end:
3956 _WaitForEngineNotBusy();
3957 DSI_PHY_clk_setting(&lcm_params_for_clk_setting);
3958 DSI_PHY_TIMCONFIG(&lcm_params_for_clk_setting);
3959 return DSI_STATUS_OK;
3960 }
3961 /*fbconfig ulitity to set dsi clock ;
3962 ioctl : MIPI_SET_CLK
3963 */
3964 DSI_STATUS fbconfig_DSI_set_CLK(unsigned int clk)
3965 {
3966 extern LCM_PARAMS *lcm_params;
3967 LCM_PARAMS fb_lcm_params ;
3968 printk("sxk==>fbconfig_DSI_set_CLK:%d\n",clk);
3969
3970 if(clk > 1000)
3971 return DSI_STATUS_ERROR;
3972 memcpy((void *)&fb_lcm_params, (void *)lcm_params, sizeof(LCM_PARAMS));
3973 fb_lcm_params.dsi.PLL_CLOCK = clk;
3974 printk("sxk==>fbconfig_DSI_set_CLK:will wait!!\n");
3975
3976 _WaitForEngineNotBusy();//cmd mode
3977 printk("sxk==>will fbconfig_DSI_set_CLK:%d\n",clk);
3978
3979 DSI_PHY_clk_setting(&fb_lcm_params);
3980 //DSI_PHY_TIMCONFIG(&lcm_params_for_clk_setting);
3981 DSI_DumpRegisters();
3982 return DSI_STATUS_OK;
3983 }
3984
3985 void fbconfig_DSI_set_lane_num(unsigned int lane_num)
3986 {
3987 DSI_TXRX_CTRL_REG tmp_reg;
3988 tmp_reg=DSI_REG->DSI_TXRX_CTRL;
3989 switch(lane_num)
3990 {
3991 case LCM_ONE_LANE:tmp_reg.LANE_NUM = 1;break;
3992 case LCM_TWO_LANE:tmp_reg.LANE_NUM = 3;break;
3993 case LCM_THREE_LANE:tmp_reg.LANE_NUM = 0x7;break;
3994 case LCM_FOUR_LANE:tmp_reg.LANE_NUM = 0xF;break;
3995 }
3996 OUTREG32(&DSI_REG->DSI_TXRX_CTRL, AS_UINT32(&tmp_reg));
3997 //DSI Clock setting for accroding lane num ;
3998 if(lane_num > 0)
3999 {
4000 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE0.RG_DSI0_LNT0_RT_CODE = 0x8;
4001 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE0.RG_DSI0_LNT0_LDOOUT_EN = 1;
4002 }
4003
4004 if(lane_num > 1)
4005 {
4006 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE1.RG_DSI0_LNT1_RT_CODE = 0x8;
4007 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE1.RG_DSI0_LNT1_LDOOUT_EN = 1;
4008 }
4009
4010 if(lane_num > 2)
4011 {
4012 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE2.RG_DSI0_LNT2_RT_CODE = 0x8;
4013 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE2.RG_DSI0_LNT2_LDOOUT_EN = 1;
4014 }
4015
4016 if(lane_num > 3)
4017 {
4018 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE3.RG_DSI0_LNT3_RT_CODE = 0x8;
4019 DSI_PHY_REG->MIPITX_DSI0_DATA_LANE3.RG_DSI0_LNT3_LDOOUT_EN = 1;
4020 }
4021
4022 }
4023 //"TIMCON0_REG:" "HS_PRPR" "HS_ZERO" "HS_TRAIL\n"
4024 // "TIMCON1_REG:" "TA_GO" "TA_SURE" "TA_GET" "DA_HS_EXIT\n"
4025 // "TIMCON2_REG:" "CLK_ZERO" "CLK_TRAIL" "CONT_DET\n"
4026 // "TIMCON3_REG:" "CLK_HS_PRPR" "CLK_HS_POST" "CLK_HS_EXIT\n"
4027
4028 void fbconfig_DSI_set_timing(MIPI_TIMING timing)
4029 {
4030 switch(timing.type)
4031 {
4032 case HS_PRPR:
4033 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,HS_PRPR,timing.value);
4034 break;
4035 case HS_ZERO:
4036 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,HS_ZERO,timing.value);
4037 break;
4038 case HS_TRAIL:
4039 OUTREGBIT(DSI_PHY_TIMCON0_REG,DSI_REG->DSI_PHY_TIMECON0,HS_TRAIL,timing.value);
4040 break;
4041 case TA_GO:
4042 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,TA_GO,timing.value);
4043 break;
4044 case TA_SURE:
4045 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,TA_SURE,timing.value);
4046 break;
4047 case TA_GET:
4048 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,TA_GET,timing.value);
4049 break;
4050 case DA_HS_EXIT:
4051 OUTREGBIT(DSI_PHY_TIMCON1_REG,DSI_REG->DSI_PHY_TIMECON1,DA_HS_EXIT,timing.value);
4052 break;
4053 case CONT_DET:
4054 OUTREGBIT(DSI_PHY_TIMCON2_REG,DSI_REG->DSI_PHY_TIMECON2,CONT_DET,timing.value);
4055 break;
4056 case CLK_ZERO:
4057 OUTREGBIT(DSI_PHY_TIMCON2_REG,DSI_REG->DSI_PHY_TIMECON2,CLK_ZERO,timing.value);
4058 break;
4059 case CLK_TRAIL:
4060 OUTREGBIT(DSI_PHY_TIMCON2_REG,DSI_REG->DSI_PHY_TIMECON2,CLK_TRAIL,timing.value);
4061 break;
4062 case CLK_HS_PRPR:
4063 OUTREGBIT(DSI_PHY_TIMCON3_REG,DSI_REG->DSI_PHY_TIMECON3,CLK_HS_PRPR,timing.value);
4064 break;
4065 case CLK_HS_POST:
4066 OUTREGBIT(DSI_PHY_TIMCON3_REG,DSI_REG->DSI_PHY_TIMECON3,CLK_HS_POST,timing.value);
4067 break;
4068 case CLK_HS_EXIT:
4069 OUTREGBIT(DSI_PHY_TIMCON3_REG,DSI_REG->DSI_PHY_TIMECON3,CLK_HS_EXIT,timing.value);
4070 break;
4071 case HPW:
4072 OUTREG32(&DSI_REG->DSI_HSA_WC, ALIGN_TO((timing.value), 4));
4073 break;
4074 case HFP:
4075 OUTREG32(&DSI_REG->DSI_HFP_WC, ALIGN_TO((timing.value), 4));
4076 break;
4077 case HBP:
4078 OUTREG32(&DSI_REG->DSI_HBP_WC, ALIGN_TO((timing.value), 4));
4079 break;
4080 case VPW:
4081 OUTREG32(&DSI_REG->DSI_VACT_NL,timing.value);
4082 break;
4083 case VFP:
4084 OUTREG32(&DSI_REG->DSI_VFP_NL, timing.value);
4085 break;
4086 case VBP:
4087 OUTREG32(&DSI_REG->DSI_VBP_NL, timing.value);
4088 break;
4089 default:
4090 printk("fbconfig dsi set timing :no such type!!\n");
4091 }
4092 DSI_DumpRegisters();
4093 }
4094
4095
4096 DSI_STATUS DSI_Capture_Framebuffer(unsigned int pvbuf, unsigned int bpp, bool cmd_mode)
4097 {
4098 unsigned int mva;
4099 unsigned int ret = 0;
4100 M4U_PORT_STRUCT portStruct;
4101
4102 struct disp_path_config_mem_out_struct mem_out = {0};
4103 printk("enter DSI_Capture_FB!\n");
4104
4105 if(bpp == 32)
4106 mem_out.outFormat = eARGB8888;
4107 else if(bpp == 16)
4108 mem_out.outFormat = eRGB565;
4109 else if(bpp == 24)
4110 mem_out.outFormat = eRGB888;
4111 else
4112 printk("DSI_Capture_FB, fb color format not support\n");
4113
4114 printk("before alloc MVA: va = 0x%x, size = %d\n", pvbuf, lcm_params->height*lcm_params->width*bpp/8);
4115 ret = m4u_alloc_mva(DISP_WDMA,
4116 pvbuf,
4117 lcm_params->height*lcm_params->width*bpp/8,
4118 0,
4119 0,
4120 &mva);
4121 if(ret!=0)
4122 {
4123 printk("m4u_alloc_mva() fail! \n");
4124 return DSI_STATUS_OK;
4125 }
4126 printk("addr=0x%x, format=%d \n", mva, (mem_out.outFormat));
4127
4128 m4u_dma_cache_maint(DISP_WDMA,
4129 (const void *)pvbuf,
4130 lcm_params->height*lcm_params->width*bpp/8,
4131 DMA_BIDIRECTIONAL);
4132
4133 portStruct.ePortID = DISP_WDMA; //hardware port ID, defined in M4U_PORT_ID_ENUM
4134 portStruct.Virtuality = 1;
4135 portStruct.Security = 0;
4136 portStruct.domain = 0; //domain : 0 1 2 3
4137 portStruct.Distance = 1;
4138 portStruct.Direction = 0;
4139 m4u_config_port(&portStruct);
4140
4141 mem_out.enable = 1;
4142 mem_out.dstAddr = mva;
4143 mem_out.srcROI.x = 0;
4144 mem_out.srcROI.y = 0;
4145 mem_out.srcROI.height= lcm_params->height;
4146 mem_out.srcROI.width= lcm_params->width;
4147
4148 _WaitForEngineNotBusy();
4149 disp_path_get_mutex();
4150 disp_path_config_mem_out(&mem_out);
4151 printk("Wait DSI idle \n");
4152
4153 if(cmd_mode)
4154 DSI_Start();
4155
4156 disp_path_release_mutex();
4157
4158 _WaitForEngineNotBusy();
4159 // msleep(20);
4160 disp_path_get_mutex();
4161 mem_out.enable = 0;
4162 disp_path_config_mem_out(&mem_out);
4163
4164 if(cmd_mode)
4165 DSI_Start();
4166
4167 disp_path_release_mutex();
4168
4169 portStruct.ePortID = DISP_WDMA; //hardware port ID, defined in M4U_PORT_ID_ENUM
4170 portStruct.Virtuality = 1;
4171 portStruct.Security = 0;
4172 portStruct.domain = 0; //domain : 0 1 2 3
4173 portStruct.Distance = 1;
4174 portStruct.Direction = 0;
4175 m4u_config_port(&portStruct);
4176
4177 m4u_dealloc_mva(DISP_WDMA,
4178 pvbuf,
4179 lcm_params->height*lcm_params->width*bpp/8,
4180 mva);
4181
4182 return DSI_STATUS_OK;
4183 }
4184
4185
4186 DSI_STATUS DSI_TE_Enable(BOOL enable)
4187 {
4188 printk("sxk==>set TE Enable %d \n",enable);
4189 dsiTeEnable = enable;
4190
4191 return DSI_STATUS_OK;
4192 }
4193 DSI_STATUS DSI_TE_EXT_Enable(BOOL enable)
4194 {
4195
4196 dsiTeExtEnable = enable;
4197
4198 if(dsiTeExtEnable == false)
4199 {
4200 OUTREGBIT(DSI_TXRX_CTRL_REG,DSI_REG->DSI_TXRX_CTRL,EXT_TE_EN,0);
4201 }
4202
4203
4204 return DSI_STATUS_OK;
4205 }
4206
4207 BOOL DSI_Get_EXT_TE(void)
4208 {
4209 return dsiTeExtEnable;
4210 }
4211
4212 BOOL DSI_Get_BTA_TE(void)
4213 {
4214 return dsiTeEnable;
4215 }
4216
4217 DSI_STATUS DSI_Wait_VDO_Idle(void)
4218 {
4219 static const long WAIT_TIMEOUT = 2 * HZ; // 2 sec
4220 long ret;
4221 DSI_SetMode(0);
4222
4223 ret = wait_event_interruptible_timeout(_dsi_wait_vm_done_queue,
4224 !_IsEngineBusy(),
4225 WAIT_TIMEOUT);
4226
4227 if (0 == ret) {
4228 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine read ready timeout!!!\n");
4229
4230 DSI_DumpRegisters();
4231 ///do necessary reset here
4232 DSI_Reset();
4233 }
4234 DSI_SetMode(lcm_params->dsi.mode);
4235
4236 return DSI_STATUS_OK;
4237 }
4238
4239 DSI_MODE_CTRL_REG fb_config_mode_ctl, fb_config_mode_ctl_backup;
4240
4241 void fbconfig_set_cmd_mode(void)
4242 {
4243 //backup video mode
4244 static const long FB_WAIT_TIMEOUT = 2 * HZ; // 2 sec
4245 long ret;
4246
4247 OUTREG32(&fb_config_mode_ctl_backup, AS_UINT32(&DSI_REG->DSI_MODE_CTRL));
4248 OUTREG32(&fb_config_mode_ctl, AS_UINT32(&DSI_REG->DSI_MODE_CTRL));
4249 //set to cmd mode
4250 fb_config_mode_ctl.MODE = 0;
4251 OUTREG32(&DSI_REG->DSI_MODE_CTRL, AS_UINT32(&fb_config_mode_ctl));
4252 //DSI_Reset();
4253
4254 wait_vm_done_irq = true;
4255 ret = wait_event_interruptible_timeout(_dsi_wait_vm_done_queue,
4256 !_IsEngineBusy(),
4257 FB_WAIT_TIMEOUT);
4258 if (0 == ret) {
4259 xlog_printk(ANDROID_LOG_WARN, "DSI", " Wait for DSI engine read ready timeout!!!\n");
4260
4261 DSI_DumpRegisters();
4262 ///do necessary reset here
4263 DSI_Reset();
4264 wait_vm_done_irq = false;
4265 return;
4266 }
4267 }
4268 void fbconfig_set_vdo_mode(void)
4269 {
4270 OUTREG32(&DSI_REG->DSI_MODE_CTRL, AS_UINT32(&fb_config_mode_ctl_backup));
4271 }
4272
4273 void fbconfig_DSI_Continuous_HS(int enable)
4274 {
4275 DSI_TXRX_CTRL_REG tmp_reg = DSI_REG->DSI_TXRX_CTRL;
4276
4277 tmp_reg.HSTX_CKLP_EN = enable;
4278 OUTREG32(&DSI_REG->DSI_TXRX_CTRL, AS_UINT32(&tmp_reg));
4279 }
4280
4281
kernel source for telekom puls (alcatel/mediatek)