drivers/misc/mediatek/usb11/mt8127/musbfsh_mt65xx.h

   1
   2 #ifndef __MUSBFSH_MT65XX_H__
   3 #define __MUSBFSH_MT65XX_H__
   4 #include <mach/mt_reg_base.h>
   5 #include <mach/mt_pm_ldo.h>
   6 #include <mach/mt_gpio.h>
   7 #include <mach/mt_clkmgr.h>
   8
   9 #if defined(MTK_DT_SUPPORT) && !defined(EVDO_DT_SUPPORT)
  10 #include <cust_eint.h>
  11 extern void mt65xx_eint_unmask(unsigned int line);
  12 extern void mt65xx_eint_mask(unsigned int line);
  13 extern void mt65xx_eint_set_polarity(kal_uint8 eintno, kal_bool ACT_Polarity);
  14 extern void mt65xx_eint_set_hw_debounce(kal_uint8 eintno, kal_uint32 ms);
  15 extern kal_uint32 mt65xx_eint_set_sens(kal_uint8 eintno, kal_bool sens);
  16 extern void mt65xx_eint_registration(kal_uint8 eintno, kal_bool Dbounce_En,
  17                                      kal_bool ACT_Polarity, void (EINT_FUNC_PTR)(void),
  18                                      kal_bool auto_umask);
  19 #endif
  20
  21 //#define IC_USB
  22
  23 //Level 1 interrupts:
  24 #define USB11_L1INTS 0xA0
  25 #define USB11_L1INTM 0xA4
  26 #define USB11_L1INTP 0xA8
  27 #define MUSBFSH_HSDMA_BASE              0x200
  28 #define MUSBFSH_HSDMA_INTR              (MUSBFSH_HSDMA_BASE + 0)
  29 #define MUSBFSH_DMA_INTR_UNMASK_CLR_OFFSET (16)
  30 #define MUSBFSH_DMA_INTR_UNMASK_SET_OFFSET (24)
  31 #define USB11_BASE USB1_BASE
  32 //USB11 PHY registers:
  33 #define USB11_PHY_ADDR USB_SIF_BASE + 0x900
  34
  35 #define U1PHYCR0 0xC0
  36 #define RG_USB11_FSLS_ENBGRI 0x08 // @U1PHYCR0+1, 1:power on or recovery; 0:save current
  37
  38 #define U1PHYCR1 0xC4
  39 #define force_usb11_en_fs_ls_rcv 0x04 // @U1PHYCR1+2
  40 #define force_usb11_en_fs_ls_tx 0x02 // @U1PHYCR1+2
  41 #define RG_USB11_EN_FS_LS_RCV 0x04 // @U1PHYCR1+3
  42 #define RG_USB11_EN_FS_LS_TX 0x02 // @U1PHYCR1+3
  43
  44 #define U1PHTCR2 0xC8
  45 #define force_usb11_dm_rpu 0x01
  46 #define force_usb11_dp_rpu 0x02
  47 #define force_usb11_dm_rpd 0x04
  48 #define force_usb11_dp_rpd 0x08
  49 #define RG_USB11_DM_RPU 0x10
  50 #define RG_USB11_DP_RPU 0x20
  51 #define RG_USB11_DM_RPD 0x40
  52 #define RG_USB11_DP_RPD 0x80
  53 #define RG_USB11_AVALID 0x04 // @U1PHYCR2+2
  54 #define RG_USB11_BVALID 0x08 // @U1PHYCR2+2
  55 #define RG_USB11_SESSEND 0x10 // @U1PHYCR2+2
  56 #define RG_USB11_VBUSVALID 0x20 // @U1PHYCR2+2
  57 #define force_usb11_avalid 0x04 // @U1PHYCR2+3
  58 #define force_usb11_bvalid 0x08 // @U1PHYCR2+3
  59 #define force_usb11_sessend 0x10 // @U1PHYCR2+3
  60 #define force_usb11_vbusvalid 0x20 // @U1PHYCR2+3
  61
  62
  63 //USB11 PHY access macro:
  64 #define USB11PHY_READ32(offset)         __raw_readl((void __iomem *)(USB11_PHY_ADDR+(offset)))
  65 #define USB11PHY_READ8(offset)          __raw_readb((void __iomem *)(USB11_PHY_ADDR+(offset)))
  66 #define USB11PHY_WRITE8(offset, value)  __raw_writeb(value, (void __iomem *)(USB11_PHY_ADDR+(offset)))
  67 #define USB11PHY_SET8(offset, mask)     USB11PHY_WRITE8((offset), USB11PHY_READ8(offset) | (mask))
  68 #define USB11PHY_CLR8(offset, mask)     USB11PHY_WRITE8((offset), USB11PHY_READ8(offset) & (~(mask)))
  69
  70
  71 #endif