drivers/misc/mediatek/sound/mt8127/AudDrv_Ana_6397.c

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   AudDrv_Ana.c
  21  *
  22  * Project:
  23  * --------
  24  *   MT8127  Audio Driver ana Register setting
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio register
  29  *
  30  * Author:
  31  * -------
  32  * Luke Liu
  33  * Chipeng Chang
  34  *
  35  *------------------------------------------------------------------------------
  36  * $Revision: #1 $
  37  * $Modtime:$
  38  * $Log:$
  39  *
  40  *
  41  *******************************************************************************/
  42
  43
  44 /*****************************************************************************
  45  *                     C O M P I L E R   F L A G S
  46  *****************************************************************************/
  47
  48
  49 /*****************************************************************************
  50  *                E X T E R N A L   R E F E R E N C E S
  51  *****************************************************************************/
  52
  53 #include "AudDrv_Common.h"
  54 #include "AudDrv_Ana_6397.h"
  55 #include "AudDrv_Clk.h"
  56 #include "AudDrv_ioctl.h"
  57
  58 // define this to use wrapper to control
  59 #define AUDIO_USING_WRAP_DRIVER
  60 #ifdef AUDIO_USING_WRAP_DRIVER
  61 #include <mach/mt_pmic_wrap.h>
  62 #endif
  63
  64 /*****************************************************************************
  65  *                         D A T A   T Y P E S
  66  *****************************************************************************/
  67
  68 void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask)
  69 {
  70     // set pmic register or analog CONTROL_IFACE_PATH
  71     int ret = 0;
  72 #ifdef AUDIO_USING_WRAP_DRIVER
  73     uint32 Reg_Value = Ana_Get_Reg(offset);
  74
  75         if (!(offset <= AUDTOP_MAX_ADDR_OFFSET ||
  76                 (offset >= AFE_ADDR_START && offset <= AFE_ADDR_END)))
  77                 return;
  78
  79     Reg_Value &= (~mask);
  80     Reg_Value |= (value & mask);
  81     ret = pwrap_write(offset, Reg_Value);
  82     Reg_Value = Ana_Get_Reg(offset);
  83     if ((Reg_Value & mask) != (value & mask))
  84     {
  85         printk("Ana_Set_Reg offset= 0x%x , value = 0x%x mask = 0x%x ret = %d Reg_Value = 0x%x\n", offset, value, mask, ret, Reg_Value);
  86     }
  87 #endif
  88 }
  89
  90 uint32 Ana_Get_Reg(uint32 offset)
  91 {
  92     // get pmic register
  93     int ret = 0;
  94     uint32 Rdata = 0;
  95
  96         if (!(offset <= AUDTOP_MAX_ADDR_OFFSET ||
  97                 (offset >= AFE_ADDR_START && offset <= AFE_ADDR_END)))
  98                 return 0;
  99
 100 #ifdef AUDIO_USING_WRAP_DRIVER
 101     ret = pwrap_read(offset, &Rdata);
 102 #endif
 103     //PRINTK_ANA_REG ("Ana_Get_Reg offset= 0x%x  Rdata = 0x%x ret = %d\n",offset,Rdata,ret);
 104     return Rdata;
 105 }
 106
 107 void AudDrv_Store_reg_ANA(AudAna_Suspend_Reg *pBackup_reg)
 108 {
 109     PRINTK_AUDDRV("+AudDrv_Store_reg_ANA \n");
 110
 111     if (pBackup_reg == NULL)
 112     {
 113         PRINTK_AUDDRV("pBackup_reg is null \n");
 114         PRINTK_AUDDRV("-AudDrv_Store_reg_ANA \n");
 115         return;
 116     }
 117
 118     AudDrv_ANA_Clk_On();
 119
 120     //backup digital part registers
 121     pBackup_reg->Suspend_Ana_AFE_UL_DL_CON0 = Ana_Get_Reg(AFE_UL_DL_CON0);
 122     pBackup_reg->Suspend_Ana_AFE_DL_SRC2_CON0_H = Ana_Get_Reg(AFE_DL_SRC2_CON0_H);
 123     pBackup_reg->Suspend_Ana_AFE_DL_SRC2_CON0_L = Ana_Get_Reg(AFE_DL_SRC2_CON0_L);
 124     pBackup_reg->Suspend_Ana_AFE_DL_SDM_CON0 = Ana_Get_Reg(AFE_DL_SDM_CON0);
 125     pBackup_reg->Suspend_Ana_AFE_DL_SDM_CON1 = Ana_Get_Reg(AFE_DL_SDM_CON1);
 126     pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON0_H = Ana_Get_Reg(AFE_UL_SRC_CON0_H);
 127     pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON0_L = Ana_Get_Reg(AFE_UL_SRC_CON0_L);
 128     pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON1_H = Ana_Get_Reg(AFE_UL_SRC_CON1_H);
 129     pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON1_L = Ana_Get_Reg(AFE_UL_SRC_CON1_L);
 130     pBackup_reg->Suspend_Ana_AFE_TOP_CON0 = Ana_Get_Reg(ANA_AFE_TOP_CON0);
 131     pBackup_reg->Suspend_Ana_AUDIO_TOP_CON0 = Ana_Get_Reg(ANA_AUDIO_TOP_CON0);
 132     pBackup_reg->Suspend_Ana_AFUNC_AUD_CON0 = Ana_Get_Reg(AFUNC_AUD_CON0);
 133     pBackup_reg->Suspend_Ana_AFUNC_AUD_CON1 = Ana_Get_Reg(AFUNC_AUD_CON1);
 134     pBackup_reg->Suspend_Ana_AFUNC_AUD_CON2 = Ana_Get_Reg(AFUNC_AUD_CON2);
 135     pBackup_reg->Suspend_Ana_AFUNC_AUD_CON3 = Ana_Get_Reg(AFUNC_AUD_CON3);
 136     pBackup_reg->Suspend_Ana_AFUNC_AUD_CON4 = Ana_Get_Reg(AFUNC_AUD_CON4);
 137     pBackup_reg->Suspend_Ana_AFE_UP8X_FIFO_CFG0 = Ana_Get_Reg(AFE_UP8X_FIFO_CFG0);
 138     pBackup_reg->Suspend_Ana_AFE_DL_DC_COMP_CFG0 = Ana_Get_Reg(AFE_DL_DC_COMP_CFG0);
 139     pBackup_reg->Suspend_Ana_AFE_DL_DC_COMP_CFG1 = Ana_Get_Reg(AFE_DL_DC_COMP_CFG1);
 140     pBackup_reg->Suspend_Ana_AFE_DL_DC_COMP_CFG2 = Ana_Get_Reg(AFE_DL_DC_COMP_CFG2);
 141     pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG0 = Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0);
 142     pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG1 = Ana_Get_Reg(AFE_PMIC_NEWIF_CFG1);
 143     pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG2 = Ana_Get_Reg(AFE_PMIC_NEWIF_CFG2);
 144     pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG3 = Ana_Get_Reg(AFE_PMIC_NEWIF_CFG3);
 145     pBackup_reg->Suspend_Ana_AFE_SGEN_CFG0 = Ana_Get_Reg(AFE_SGEN_CFG0);
 146     pBackup_reg->Suspend_Ana_AFE_SGEN_CFG1 = Ana_Get_Reg(AFE_SGEN_CFG1);
 147
 148
 149     //backup analog part registers
 150     pBackup_reg->Suspend_Ana_TOP_CKPDN = Ana_Get_Reg(TOP_CKPDN);
 151     pBackup_reg->Suspend_Ana_TOP_CKPDN_SET = Ana_Get_Reg(TOP_CKPDN_SET);
 152     pBackup_reg->Suspend_Ana_TOP_CKPDN_CLR = Ana_Get_Reg(TOP_CKPDN_CLR);
 153     pBackup_reg->Suspend_Ana_TOP_CKPDN2 = Ana_Get_Reg(TOP_CKPDN2);
 154     pBackup_reg->Suspend_Ana_TOP_CKPDN2_SET = Ana_Get_Reg(TOP_CKPDN2_SET);
 155     pBackup_reg->Suspend_Ana_TOP_CKPDN2_CLR = Ana_Get_Reg(TOP_CKPDN2_CLR);
 156     pBackup_reg->Suspend_Ana_TOP_CKCON1 = Ana_Get_Reg(TOP_CKCON1);
 157     pBackup_reg->Suspend_Ana_SPK_CON0 = Ana_Get_Reg(SPK_CON0);
 158     pBackup_reg->Suspend_Ana_SPK_CON1 = Ana_Get_Reg(SPK_CON1);
 159     pBackup_reg->Suspend_Ana_SPK_CON2 = Ana_Get_Reg(SPK_CON2);
 160     pBackup_reg->Suspend_Ana_SPK_CON3 = Ana_Get_Reg(SPK_CON3);
 161     pBackup_reg->Suspend_Ana_SPK_CON4 = Ana_Get_Reg(SPK_CON4);
 162     pBackup_reg->Suspend_Ana_SPK_CON5 = Ana_Get_Reg(SPK_CON5);
 163     pBackup_reg->Suspend_Ana_SPK_CON6 = Ana_Get_Reg(SPK_CON6);
 164     pBackup_reg->Suspend_Ana_SPK_CON7 = Ana_Get_Reg(SPK_CON7);
 165     pBackup_reg->Suspend_Ana_SPK_CON8 = Ana_Get_Reg(SPK_CON8);
 166     pBackup_reg->Suspend_Ana_SPK_CON9 = Ana_Get_Reg(SPK_CON9);
 167     pBackup_reg->Suspend_Ana_SPK_CON10 = Ana_Get_Reg(SPK_CON10);
 168     pBackup_reg->Suspend_Ana_SPK_CON11 = Ana_Get_Reg(SPK_CON11);
 169     pBackup_reg->Suspend_Ana_AUDDAC_CON0 = Ana_Get_Reg(AUDDAC_CON0);
 170     pBackup_reg->Suspend_Ana_AUDBUF_CFG0 = Ana_Get_Reg(AUDBUF_CFG0);
 171     pBackup_reg->Suspend_Ana_AUDBUF_CFG1 = Ana_Get_Reg(AUDBUF_CFG1);
 172     pBackup_reg->Suspend_Ana_AUDBUF_CFG2 = Ana_Get_Reg(AUDBUF_CFG2);
 173     pBackup_reg->Suspend_Ana_AUDBUF_CFG3 = Ana_Get_Reg(AUDBUF_CFG3);
 174     pBackup_reg->Suspend_Ana_AUDBUF_CFG4 = Ana_Get_Reg(AUDBUF_CFG4);
 175     pBackup_reg->Suspend_Ana_IBIASDIST_CFG0 = Ana_Get_Reg(IBIASDIST_CFG0);
 176     pBackup_reg->Suspend_Ana_AUDACCDEPOP_CFG0 = Ana_Get_Reg(AUDACCDEPOP_CFG0);
 177     pBackup_reg->Suspend_Ana_AUD_IV_CFG0 = Ana_Get_Reg(AUD_IV_CFG0);
 178     pBackup_reg->Suspend_Ana_AUDCLKGEN_CFG0 = Ana_Get_Reg(AUDCLKGEN_CFG0);
 179     pBackup_reg->Suspend_Ana_AUDLDO_CFG0 = Ana_Get_Reg(AUDLDO_CFG0);
 180     pBackup_reg->Suspend_Ana_AUDLDO_CFG1 = Ana_Get_Reg(AUDLDO_CFG1);
 181     pBackup_reg->Suspend_Ana_AUDNVREGGLB_CFG0 = Ana_Get_Reg(AUDNVREGGLB_CFG0);
 182     pBackup_reg->Suspend_Ana_AUD_NCP0 = Ana_Get_Reg(AUD_NCP0);
 183     pBackup_reg->Suspend_Ana_AUDPREAMP_CON0 = Ana_Get_Reg(AUDPREAMP_CON0);
 184     pBackup_reg->Suspend_Ana_AUDADC_CON0 = Ana_Get_Reg(AUDADC_CON0);
 185     pBackup_reg->Suspend_Ana_AUDADC_CON1 = Ana_Get_Reg(AUDADC_CON1);
 186     pBackup_reg->Suspend_Ana_AUDADC_CON2 = Ana_Get_Reg(AUDADC_CON2);
 187     pBackup_reg->Suspend_Ana_AUDADC_CON3 = Ana_Get_Reg(AUDADC_CON3);
 188     pBackup_reg->Suspend_Ana_AUDADC_CON4 = Ana_Get_Reg(AUDADC_CON4);
 189     pBackup_reg->Suspend_Ana_AUDADC_CON5 = Ana_Get_Reg(AUDADC_CON5);
 190     pBackup_reg->Suspend_Ana_AUDADC_CON6 = Ana_Get_Reg(AUDADC_CON6);
 191     pBackup_reg->Suspend_Ana_AUDDIGMI_CON0 = Ana_Get_Reg(AUDDIGMI_CON0);
 192     pBackup_reg->Suspend_Ana_AUDLSBUF_CON0 = Ana_Get_Reg(AUDLSBUF_CON0);
 193     pBackup_reg->Suspend_Ana_AUDLSBUF_CON1 = Ana_Get_Reg(AUDLSBUF_CON1);
 194     pBackup_reg->Suspend_Ana_AUDENCSPARE_CON0 = Ana_Get_Reg(AUDENCSPARE_CON0);
 195     pBackup_reg->Suspend_Ana_AUDENCCLKSQ_CON0 = Ana_Get_Reg(AUDENCCLKSQ_CON0);
 196     pBackup_reg->Suspend_Ana_AUDPREAMPGAIN_CON0 = Ana_Get_Reg(AUDPREAMPGAIN_CON0);
 197     pBackup_reg->Suspend_Ana_ZCD_CON0 = Ana_Get_Reg(ZCD_CON0);
 198     pBackup_reg->Suspend_Ana_ZCD_CON1 = Ana_Get_Reg(ZCD_CON1);
 199     pBackup_reg->Suspend_Ana_ZCD_CON2 = Ana_Get_Reg(ZCD_CON2);
 200     pBackup_reg->Suspend_Ana_ZCD_CON3 = Ana_Get_Reg(ZCD_CON3);
 201     pBackup_reg->Suspend_Ana_ZCD_CON4 = Ana_Get_Reg(ZCD_CON4);
 202     pBackup_reg->Suspend_Ana_ZCD_CON5 = Ana_Get_Reg(ZCD_CON5);
 203     pBackup_reg->Suspend_Ana_NCP_CLKDIV_CON0 = Ana_Get_Reg(NCP_CLKDIV_CON0);
 204     pBackup_reg->Suspend_Ana_NCP_CLKDIV_CON1 = Ana_Get_Reg(NCP_CLKDIV_CON1);
 205     AudDrv_ANA_Clk_Off();
 206
 207 }
 208
 209 void AudDrv_Recover_reg_ANA(AudAna_Suspend_Reg *pBackup_reg)
 210 {
 211     PRINTK_AUDDRV("+AudDrv_Recover_reg_ANA \n");
 212
 213     if (pBackup_reg == NULL)
 214     {
 215         PRINTK_AUDDRV("pBackup_reg is null \n");
 216         PRINTK_AUDDRV("-AudDrv_Recover_reg_ANA \n");
 217         return;
 218     }
 219
 220     AudDrv_ANA_Clk_On();
 221
 222     Ana_Set_Reg(SPK_CON0, 0x0000, 0xffff); // 1
 223     Ana_Set_Reg(SPK_CON3, 0x0000, 0xffff); // 1
 224     Ana_Set_Reg(SPK_CON11, 0x0000, 0xffff); // 1
 225     Ana_Set_Reg(AUDBUF_CFG0,0x0000,0xffff);
 226     Ana_Set_Reg(IBIASDIST_CFG0,0x1552,0xffff);
 227     Ana_Set_Reg(AUDDAC_CON0,0x0000,0xffff);
 228     Ana_Set_Reg(AUD_IV_CFG0, 0x0000, 0xffff); // 1
 229     Ana_Set_Reg(AUDCLKGEN_CFG0,0x0000,0xffff);
 230     Ana_Set_Reg(AUDNVREGGLB_CFG0,0x0004,0xffff);
 231     Ana_Set_Reg(NCP_CLKDIV_CON1,0x0001,0xffff);
 232     Ana_Set_Reg(AUD_NCP0,0x8000,0xffff);
 233     Ana_Set_Reg(AUDLDO_CFG0,0x0192,0xffff);
 234
 235     Ana_Set_Reg(AFE_UL_DL_CON0, pBackup_reg->Suspend_Ana_AFE_UL_DL_CON0,0xFFFF);
 236     Ana_Set_Reg(AFE_DL_SRC2_CON0_H, pBackup_reg->Suspend_Ana_AFE_DL_SRC2_CON0_H,0xFFFF);
 237     Ana_Set_Reg(AFE_DL_SRC2_CON0_L, pBackup_reg->Suspend_Ana_AFE_DL_SRC2_CON0_L,0xFFFF);
 238     Ana_Set_Reg(AFE_DL_SDM_CON0, pBackup_reg->Suspend_Ana_AFE_DL_SDM_CON0,0xFFFF);
 239     Ana_Set_Reg(AFE_DL_SDM_CON1, pBackup_reg->Suspend_Ana_AFE_DL_SDM_CON1,0xFFFF);
 240     Ana_Set_Reg(AFE_UL_SRC_CON0_H, pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON0_H,0xFFFF);
 241     Ana_Set_Reg(AFE_UL_SRC_CON0_L, pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON0_L,0xFFFF);
 242     Ana_Set_Reg(AFE_UL_SRC_CON1_H, pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON1_H,0xFFFF);
 243     Ana_Set_Reg(AFE_UL_SRC_CON1_L, pBackup_reg->Suspend_Ana_AFE_UL_SRC_CON1_L,0xFFFF);
 244     Ana_Set_Reg(ANA_AFE_TOP_CON0, pBackup_reg->Suspend_Ana_AFE_TOP_CON0,0xFFFF);
 245     Ana_Set_Reg(ANA_AUDIO_TOP_CON0, pBackup_reg->Suspend_Ana_AUDIO_TOP_CON0,0xFFFF);
 246     Ana_Set_Reg(AFUNC_AUD_CON0, pBackup_reg->Suspend_Ana_AFUNC_AUD_CON0,0xFFFF);
 247     Ana_Set_Reg(AFUNC_AUD_CON1, pBackup_reg->Suspend_Ana_AFUNC_AUD_CON1,0xFFFF);
 248     Ana_Set_Reg(AFUNC_AUD_CON2, pBackup_reg->Suspend_Ana_AFUNC_AUD_CON2,0xFFFF);
 249     Ana_Set_Reg(AFUNC_AUD_CON3, pBackup_reg->Suspend_Ana_AFUNC_AUD_CON3,0xFFFF);
 250     Ana_Set_Reg(AFUNC_AUD_CON4, pBackup_reg->Suspend_Ana_AFUNC_AUD_CON4,0xFFFF);
 251     Ana_Set_Reg(AFE_UP8X_FIFO_CFG0, pBackup_reg->Suspend_Ana_AFE_UP8X_FIFO_CFG0,0xFFFF);
 252     Ana_Set_Reg(AFE_DL_DC_COMP_CFG0, pBackup_reg->Suspend_Ana_AFE_DL_DC_COMP_CFG0,0xFFFF);
 253     Ana_Set_Reg(AFE_DL_DC_COMP_CFG1, pBackup_reg->Suspend_Ana_AFE_DL_DC_COMP_CFG1,0xFFFF);
 254     Ana_Set_Reg(AFE_DL_DC_COMP_CFG2, pBackup_reg->Suspend_Ana_AFE_DL_DC_COMP_CFG2,0xFFFF);
 255     Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0, pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG0,0xFFFF);
 256     Ana_Set_Reg(AFE_PMIC_NEWIF_CFG1, pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG1,0xFFFF);
 257     Ana_Set_Reg(AFE_PMIC_NEWIF_CFG2, pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG2,0xFFFF);
 258     Ana_Set_Reg(AFE_PMIC_NEWIF_CFG3, pBackup_reg->Suspend_Ana_AFE_PMIC_NEWIF_CFG3,0xFFFF);
 259     Ana_Set_Reg(AFE_SGEN_CFG0, pBackup_reg->Suspend_Ana_AFE_SGEN_CFG0,0xFFFF);
 260     Ana_Set_Reg(AFE_SGEN_CFG1, pBackup_reg->Suspend_Ana_AFE_SGEN_CFG1,0xFFFF);
 261
 262
 263     //backup analog part registers
 264     //Ana_Set_Reg(TOP_CKPDN, pBackup_reg->Suspend_Ana_TOP_CKPDN,0xFFFF);
 265     //Ana_Set_Reg(TOP_CKPDN2, pBackup_reg->Suspend_Ana_TOP_CKPDN2,0xFFFF);
 266     //Ana_Set_Reg(TOP_CKCON1, pBackup_reg->Suspend_Ana_TOP_CKCON1,0xFFFF);
 267     Ana_Set_Reg(SPK_CON0, pBackup_reg->Suspend_Ana_SPK_CON0, 0xFFFF);
 268     Ana_Set_Reg(SPK_CON1, pBackup_reg->Suspend_Ana_SPK_CON1, 0xFFFF);
 269     Ana_Set_Reg(SPK_CON2, pBackup_reg->Suspend_Ana_SPK_CON2, 0xFFFF);
 270     Ana_Set_Reg(SPK_CON3, pBackup_reg->Suspend_Ana_SPK_CON3,0xFFFF);
 271     Ana_Set_Reg(SPK_CON4, pBackup_reg->Suspend_Ana_SPK_CON4,0xFFFF);
 272     Ana_Set_Reg(SPK_CON5, pBackup_reg->Suspend_Ana_SPK_CON5,0xFFFF);
 273     Ana_Set_Reg(SPK_CON6, pBackup_reg->Suspend_Ana_SPK_CON6, 0xFFFF);
 274     Ana_Set_Reg(SPK_CON7, pBackup_reg->Suspend_Ana_SPK_CON7, 0xFFFF);
 275     Ana_Set_Reg(SPK_CON8, pBackup_reg->Suspend_Ana_SPK_CON8, 0xFFFF);
 276     Ana_Set_Reg(SPK_CON9, pBackup_reg->Suspend_Ana_SPK_CON9, 0xFFFF);
 277     Ana_Set_Reg(SPK_CON10, pBackup_reg->Suspend_Ana_SPK_CON10, 0xFFFF);
 278     Ana_Set_Reg(SPK_CON11, pBackup_reg->Suspend_Ana_SPK_CON11, 0xFFFF);
 279     //Ana_Set_Reg(AUDDAC_CON0, pBackup_reg->Suspend_Ana_AUDDAC_CON0,0xFFFF);
 280     //Ana_Set_Reg(AUDBUF_CFG0, pBackup_reg->Suspend_Ana_AUDBUF_CFG0,0xFFFF);
 281     Ana_Set_Reg(AUDBUF_CFG1, pBackup_reg->Suspend_Ana_AUDBUF_CFG1,0xFFFF);
 282     Ana_Set_Reg(AUDBUF_CFG2, pBackup_reg->Suspend_Ana_AUDBUF_CFG2,0xFFFF);
 283     Ana_Set_Reg(AUDBUF_CFG3, pBackup_reg->Suspend_Ana_AUDBUF_CFG3,0xFFFF);
 284     Ana_Set_Reg(AUDBUF_CFG4, pBackup_reg->Suspend_Ana_AUDBUF_CFG4,0xFFFF);
 285     //Ana_Set_Reg(IBIASDIST_CFG0, pBackup_reg->Suspend_Ana_IBIASDIST_CFG0,0xFFFF);
 286     Ana_Set_Reg(AUDACCDEPOP_CFG0, pBackup_reg->Suspend_Ana_AUDACCDEPOP_CFG0,0xFFFF);
 287     Ana_Set_Reg(AUD_IV_CFG0, pBackup_reg->Suspend_Ana_AUD_IV_CFG0,0xFFFF);
 288     //Ana_Set_Reg(AUDCLKGEN_CFG0, pBackup_reg->Suspend_Ana_AUDCLKGEN_CFG0,0xFFFF);
 289     //Ana_Set_Reg(AUDLDO_CFG0, pBackup_reg->Suspend_Ana_AUDLDO_CFG0,0xFFFF);
 290     Ana_Set_Reg(AUDLDO_CFG1, pBackup_reg->Suspend_Ana_AUDLDO_CFG1,0xFFFF);
 291     //Ana_Set_Reg(AUDNVREGGLB_CFG0, pBackup_reg->Suspend_Ana_AUDNVREGGLB_CFG0,0xFFFF);
 292     //Ana_Set_Reg(AUD_NCP0, pBackup_reg->Suspend_Ana_AUD_NCP0,0xFFFF);
 293     Ana_Set_Reg(AUDPREAMP_CON0, pBackup_reg->Suspend_Ana_AUDPREAMP_CON0,0xFFFF);
 294     Ana_Set_Reg(AUDADC_CON0, pBackup_reg->Suspend_Ana_AUDADC_CON0,0xFFFF);
 295     Ana_Set_Reg(AUDADC_CON1, pBackup_reg->Suspend_Ana_AUDADC_CON1,0xFFFF);
 296     Ana_Set_Reg(AUDADC_CON2, pBackup_reg->Suspend_Ana_AUDADC_CON2,0xFFFF);
 297     Ana_Set_Reg(AUDADC_CON3, pBackup_reg->Suspend_Ana_AUDADC_CON3,0xFFFF);
 298     Ana_Set_Reg(AUDADC_CON4, pBackup_reg->Suspend_Ana_AUDADC_CON4,0xFFFF);
 299     Ana_Set_Reg(AUDADC_CON5, pBackup_reg->Suspend_Ana_AUDADC_CON5,0xFFFF);
 300     Ana_Set_Reg(AUDADC_CON6, pBackup_reg->Suspend_Ana_AUDADC_CON6,0xFFFF);
 301     Ana_Set_Reg(AUDDIGMI_CON0, pBackup_reg->Suspend_Ana_AUDDIGMI_CON0,0xFFFF);
 302     Ana_Set_Reg(AUDLSBUF_CON0, pBackup_reg->Suspend_Ana_AUDLSBUF_CON0,0xFFFF);
 303     Ana_Set_Reg(AUDLSBUF_CON1, pBackup_reg->Suspend_Ana_AUDLSBUF_CON1,0xFFFF);
 304     Ana_Set_Reg(AUDENCSPARE_CON0, pBackup_reg->Suspend_Ana_AUDENCSPARE_CON0,0xFFFF);
 305     Ana_Set_Reg(AUDENCCLKSQ_CON0, pBackup_reg->Suspend_Ana_AUDENCCLKSQ_CON0,0xFFFF);
 306     Ana_Set_Reg(AUDPREAMPGAIN_CON0, pBackup_reg->Suspend_Ana_AUDPREAMPGAIN_CON0,0xFFFF);
 307     Ana_Set_Reg(ZCD_CON0, pBackup_reg->Suspend_Ana_ZCD_CON0,0xFFFF);
 308     Ana_Set_Reg(ZCD_CON1, pBackup_reg->Suspend_Ana_ZCD_CON1,0xFFFF);
 309     Ana_Set_Reg(ZCD_CON2, pBackup_reg->Suspend_Ana_ZCD_CON2,0xFFFF);
 310     Ana_Set_Reg(ZCD_CON3, pBackup_reg->Suspend_Ana_ZCD_CON3,0xFFFF);
 311     Ana_Set_Reg(ZCD_CON4, pBackup_reg->Suspend_Ana_ZCD_CON4,0xFFFF);
 312     Ana_Set_Reg(ZCD_CON5, pBackup_reg->Suspend_Ana_ZCD_CON5,0xFFFF);
 313     Ana_Set_Reg(NCP_CLKDIV_CON0, pBackup_reg->Suspend_Ana_NCP_CLKDIV_CON0,0xFFFF);
 314     //Ana_Set_Reg(NCP_CLKDIV_CON1, pBackup_reg->Suspend_Ana_NCP_CLKDIV_CON1,0xFFFF);
 315
 316     PRINTK_AUDDRV("-AudDrv_Recover_reg_ANA \n");
 317     AudDrv_ANA_Clk_Off();
 318
 319 }
 320
 321 void Ana_Log_Print(void)
 322 {
 323     AudDrv_ANA_Clk_On();
 324     printk("+Ana_Log_Print \n");
 325     printk("AFE_UL_DL_CON0      = 0x%x\n", Ana_Get_Reg(AFE_UL_DL_CON0));
 326     printk("AFE_DL_SRC2_CON0_H  = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC2_CON0_H));
 327     printk("AFE_DL_SRC2_CON0_L  = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC2_CON0_L));
 328     printk("AFE_DL_SDM_CON0  = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_CON0));
 329     printk("AFE_DL_SDM_CON1  = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_CON1));
 330     printk("AFE_UL_SRC_CON0_H  = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC_CON0_H));
 331     printk("AFE_UL_SRC_CON0_L  = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC_CON0_L));
 332     printk("AFE_UL_SRC_CON1_H  = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC_CON1_H));
 333     printk("AFE_UL_SRC_CON1_L  = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC_CON1_L));
 334     printk("ANA_AFE_TOP_CON0  = 0x%x\n", Ana_Get_Reg(ANA_AFE_TOP_CON0));
 335     printk("ANA_AUDIO_TOP_CON0  = 0x%x\n", Ana_Get_Reg(ANA_AUDIO_TOP_CON0));
 336
 337     printk("AFUNC_AUD_CON0      = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON0));
 338     printk("AFUNC_AUD_CON1      = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON1));
 339     printk("AFUNC_AUD_CON2      = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON2));
 340     printk("AFUNC_AUD_CON3      = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON3));
 341     printk("AFUNC_AUD_CON4      = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON4));
 342
 343     printk("AFE_PMIC_NEWIF_CFG0  = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0));
 344     printk("AFE_PMIC_NEWIF_CFG1  = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG1));
 345     printk("AFE_PMIC_NEWIF_CFG2  = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG2));
 346     printk("AFE_PMIC_NEWIF_CFG3  = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG3));
 347     printk("AFE_SGEN_CFG0  = 0x%x\n", Ana_Get_Reg(AFE_SGEN_CFG0));
 348     printk("AFE_SGEN_CFG1  = 0x%x\n", Ana_Get_Reg(AFE_SGEN_CFG1));
 349
 350
 351     printk("TOP_CKPDN  = 0x%x\n", Ana_Get_Reg(TOP_CKPDN));
 352     printk("TOP_CKPDN_SET  = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_SET));
 353     printk("TOP_CKPDN_CLR  = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CLR));
 354     printk("TOP_CKPDN2  = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2));
 355     printk("TOP_CKCON1  = 0x%x\n", Ana_Get_Reg(TOP_CKCON1));
 356     printk("SPK_CON0  = 0x%x\n", Ana_Get_Reg(SPK_CON0));
 357     printk("SPK_CON1  = 0x%x\n", Ana_Get_Reg(SPK_CON1));
 358     printk("SPK_CON2  = 0x%x\n", Ana_Get_Reg(SPK_CON2));
 359     printk("SPK_CON3  = 0x%x\n", Ana_Get_Reg(SPK_CON3));
 360     printk("SPK_CON4  = 0x%x\n", Ana_Get_Reg(SPK_CON4));
 361     printk("SPK_CON5  = 0x%x\n", Ana_Get_Reg(SPK_CON5));
 362     printk("SPK_CON6  = 0x%x\n", Ana_Get_Reg(SPK_CON6));
 363     printk("SPK_CON7  = 0x%x\n", Ana_Get_Reg(SPK_CON7));
 364     printk("SPK_CON8  = 0x%x\n", Ana_Get_Reg(SPK_CON8));
 365     printk("SPK_CON9  = 0x%x\n", Ana_Get_Reg(SPK_CON9));
 366     printk("SPK_CON10  = 0x%x\n", Ana_Get_Reg(SPK_CON10));
 367     printk("SPK_CON11  = 0x%x\n", Ana_Get_Reg(SPK_CON11));
 368
 369     printk("AUDDAC_CON0  = 0x%x\n", Ana_Get_Reg(AUDDAC_CON0));
 370     printk("AUDBUF_CFG0  = 0x%x\n", Ana_Get_Reg(AUDBUF_CFG0));
 371     printk("AUDBUF_CFG1  = 0x%x\n", Ana_Get_Reg(AUDBUF_CFG1));
 372     printk("AUDBUF_CFG2  = 0x%x\n", Ana_Get_Reg(AUDBUF_CFG2));
 373     printk("AUDBUF_CFG3  = 0x%x\n", Ana_Get_Reg(AUDBUF_CFG3));
 374     printk("AUDBUF_CFG4  = 0x%x\n", Ana_Get_Reg(AUDBUF_CFG4));
 375
 376     printk("IBIASDIST_CFG0      = 0x%x\n", Ana_Get_Reg(IBIASDIST_CFG0));
 377     printk("AUDACCDEPOP_CFG0  = 0x%x\n", Ana_Get_Reg(AUDACCDEPOP_CFG0));
 378     printk("AUD_IV_CFG0  = 0x%x\n", Ana_Get_Reg(AUD_IV_CFG0));
 379     printk("AUDCLKGEN_CFG0      = 0x%x\n", Ana_Get_Reg(AUDCLKGEN_CFG0));
 380     printk("AUDLDO_CFG0  = 0x%x\n", Ana_Get_Reg(AUDLDO_CFG0));
 381     printk("AUDLDO_CFG1  = 0x%x\n", Ana_Get_Reg(AUDLDO_CFG1));
 382     printk("AUDNVREGGLB_CFG0  = 0x%x\n", Ana_Get_Reg(AUDNVREGGLB_CFG0));
 383     printk("AUD_NCP0  = 0x%x\n", Ana_Get_Reg(AUD_NCP0));
 384     printk("AUDPREAMP_CON0      = 0x%x\n", Ana_Get_Reg(AUDPREAMP_CON0));
 385     printk("AUDADC_CON0  = 0x%x\n", Ana_Get_Reg(AUDADC_CON0));
 386     printk("AUDADC_CON1  = 0x%x\n", Ana_Get_Reg(AUDADC_CON1));
 387     printk("AUDADC_CON2  = 0x%x\n", Ana_Get_Reg(AUDADC_CON2));
 388     printk("AUDADC_CON3  = 0x%x\n", Ana_Get_Reg(AUDADC_CON3));
 389     printk("AUDADC_CON4  = 0x%x\n", Ana_Get_Reg(AUDADC_CON4));
 390     printk("AUDADC_CON5  = 0x%x\n", Ana_Get_Reg(AUDADC_CON5));
 391     printk("AUDADC_CON6  = 0x%x\n", Ana_Get_Reg(AUDADC_CON6));
 392     printk("AUDDIGMI_CON0  = 0x%x\n", Ana_Get_Reg(AUDDIGMI_CON0));
 393     printk("AUDLSBUF_CON0  = 0x%x\n", Ana_Get_Reg(AUDLSBUF_CON0));
 394     printk("AUDLSBUF_CON1  = 0x%x\n", Ana_Get_Reg(AUDLSBUF_CON1));
 395     printk("AUDENCSPARE_CON0  = 0x%x\n", Ana_Get_Reg(AUDENCSPARE_CON0));
 396     printk("AUDENCCLKSQ_CON0  = 0x%x\n", Ana_Get_Reg(AUDENCCLKSQ_CON0));
 397     printk("AUDPREAMPGAIN_CON0  = 0x%x\n", Ana_Get_Reg(AUDPREAMPGAIN_CON0));
 398     printk("ZCD_CON0  = 0x%x\n", Ana_Get_Reg(ZCD_CON0));
 399     printk("ZCD_CON1  = 0x%x\n", Ana_Get_Reg(ZCD_CON1));
 400     printk("ZCD_CON2  = 0x%x\n", Ana_Get_Reg(ZCD_CON2));
 401     printk("ZCD_CON3  = 0x%x\n", Ana_Get_Reg(ZCD_CON3));
 402     printk("ZCD_CON4  = 0x%x\n", Ana_Get_Reg(ZCD_CON4));
 403     printk("ZCD_CON5  = 0x%x\n", Ana_Get_Reg(ZCD_CON5));
 404     printk("NCP_CLKDIV_CON0  = 0x%x\n", Ana_Get_Reg(NCP_CLKDIV_CON0));
 405     printk("NCP_CLKDIV_CON1  = 0x%x\n", Ana_Get_Reg(NCP_CLKDIV_CON1));
 406     AudDrv_ANA_Clk_Off();
 407     printk("-Ana_Log_Print \n");
 408 }
 409
 410
 411 // export symbols for other module using
 412 EXPORT_SYMBOL(Ana_Log_Print);
 413 EXPORT_SYMBOL(Ana_Set_Reg);
 414 EXPORT_SYMBOL(Ana_Get_Reg);
 415
 416