drivers/misc/mediatek/sound/mt8127/AudDrv_Ana_6323.h

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   AudDrv_Ana.h
  21  *
  22  * Project:
  23  * --------
  24  *   MT6583  Audio Driver Ana
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio register
  29  *
  30  * Author:
  31  * -------
  32  *   Chipeng Chang (mtk02308)
  33  *
  34  *------------------------------------------------------------------------------
  35  * $Revision: #1 $
  36  * $Modtime:$
  37  * $Log:$
  38  *
  39  *
  40  *******************************************************************************/
  41
  42 #ifndef _AUDDRV_ANA_H_
  43 #define _AUDDRV_ANA_H_
  44
  45 /*****************************************************************************
  46  *                     C O M P I L E R   F L A G S
  47  *****************************************************************************/
  48
  49
  50 /*****************************************************************************
  51  *                E X T E R N A L   R E F E R E N C E S
  52  *****************************************************************************/
  53
  54 #include "AudDrv_Common.h"
  55 #include "AudDrv_Def.h"
  56
  57
  58 /*****************************************************************************
  59  *                         D A T A   T Y P E S
  60  *****************************************************************************/
  61
  62
  63 /*****************************************************************************
  64  *                         M A C R O
  65  *****************************************************************************/
  66
  67 /*****************************************************************************
  68  *                  R E G I S T E R       D E F I N I T I O N
  69  *****************************************************************************/
  70
  71 #define PMIC_ABB_AFE_REG_BASE (0x4000)
  72 #define ABB_AFE_CON0    (PMIC_ABB_AFE_REG_BASE+0x0000)
  73 #define ABB_AFE_CON1    (PMIC_ABB_AFE_REG_BASE+0x0002)
  74 #define ABB_AFE_CON2    (PMIC_ABB_AFE_REG_BASE+0x0004)
  75 #define ABB_AFE_CON3    (PMIC_ABB_AFE_REG_BASE+0x0006)
  76 #define ABB_AFE_CON4    (PMIC_ABB_AFE_REG_BASE+0x0008)
  77 #define ABB_AFE_CON5    (PMIC_ABB_AFE_REG_BASE+0x000A)
  78 #define ABB_AFE_CON6    (PMIC_ABB_AFE_REG_BASE+0x000C)
  79 #define ABB_AFE_CON7    (PMIC_ABB_AFE_REG_BASE+0x000E)
  80 #define ABB_AFE_CON8    (PMIC_ABB_AFE_REG_BASE+0x0010)
  81 #define ABB_AFE_CON9    (PMIC_ABB_AFE_REG_BASE+0x0012)
  82 #define ABB_AFE_CON10   (PMIC_ABB_AFE_REG_BASE+0x0014)
  83 #define ABB_AFE_CON11   (PMIC_ABB_AFE_REG_BASE+0x0016)
  84 #define ABB_AFE_STA0    (PMIC_ABB_AFE_REG_BASE+0x0018)
  85 #define ABB_AFE_STA1    (PMIC_ABB_AFE_REG_BASE+0x001A)
  86 #define ABB_AFE_STA2    (PMIC_ABB_AFE_REG_BASE+0x001C)
  87 #define ABB_AFE_UP8X_FIFO_CFG0  (PMIC_ABB_AFE_REG_BASE+0x001E)
  88 #define ABB_AFE_UP8X_FIFO_LOG_MON0  (PMIC_ABB_AFE_REG_BASE+0x0020)
  89 #define ABB_AFE_UP8X_FIFO_LOG_MON1  (PMIC_ABB_AFE_REG_BASE+0x0022)
  90 #define ABB_AFE_PMIC_NEWIF_CFG0 (PMIC_ABB_AFE_REG_BASE+0x0024)
  91 #define ABB_AFE_PMIC_NEWIF_CFG1 (PMIC_ABB_AFE_REG_BASE+0x0026)
  92 #define ABB_AFE_PMIC_NEWIF_CFG2 (PMIC_ABB_AFE_REG_BASE+0x0028)
  93 #define ABB_AFE_PMIC_NEWIF_CFG3 (PMIC_ABB_AFE_REG_BASE+0x002A)
  94 #define ABB_AFE_TOP_CON0    (PMIC_ABB_AFE_REG_BASE+0x002C)
  95 #define ABB_AFE_MON_DEBUG0  (PMIC_ABB_AFE_REG_BASE+0x002E)
  96
  97
  98 /* The valid range of audio digital hardware in PMIC */
  99 #define ABB_AFE_ADDR_START      ABB_AFE_CON0
 100 #define ABB_AFE_ADDR_END                ABB_AFE_MON_DEBUG0
 101
 102 //---------------digital pmic  register define -------------------------------------------
 103 #if 0//
 104 #define AFE_PMICDIG_AUDIO_BASE        (0x4000)
 105 #define AFE_UL_DL_CON0               (AFE_PMICDIG_AUDIO_BASE+0x0000)
 106 #define AFE_DL_SRC2_CON0_H     (AFE_PMICDIG_AUDIO_BASE+0x0002)
 107 #define AFE_DL_SRC2_CON0_L     (AFE_PMICDIG_AUDIO_BASE+0x0004)
 108 #define AFE_DL_SRC2_CON1_H     (AFE_PMICDIG_AUDIO_BASE+0x0006)
 109 #define AFE_DL_SRC2_CON1_L     (AFE_PMICDIG_AUDIO_BASE+0x0008)
 110 #define AFE_DL_SDM_CON0           (AFE_PMICDIG_AUDIO_BASE+0x000A)
 111 #define AFE_DL_SDM_CON1           (AFE_PMICDIG_AUDIO_BASE+0x000C)
 112 #define AFE_UL_SRC_CON0_H       (AFE_PMICDIG_AUDIO_BASE+0x000E)
 113 #define AFE_UL_SRC_CON0_L       (AFE_PMICDIG_AUDIO_BASE+0x0010)
 114 #define AFE_UL_SRC_CON1_H      (AFE_PMICDIG_AUDIO_BASE+0x0012)
 115 #define AFE_UL_SRC_CON1_L       (AFE_PMICDIG_AUDIO_BASE+0x0014)
 116 #define AFE_PREDIS_CON0_H       (AFE_PMICDIG_AUDIO_BASE+0x0016)
 117 #define AFE_PREDIS_CON0_L       (AFE_PMICDIG_AUDIO_BASE+0x0018)
 118 #define AFE_PREDIS_CON1_H       (AFE_PMICDIG_AUDIO_BASE+0x001a)
 119 #define AFE_PREDIS_CON1_L       (AFE_PMICDIG_AUDIO_BASE+0x001c)
 120 #define ANA_AFE_I2S_CON1                  (AFE_PMICDIG_AUDIO_BASE+0x001e)
 121 #define AFE_I2S_FIFO_UL_CFG0  (AFE_PMICDIG_AUDIO_BASE+0x0020)
 122 #define AFE_I2S_FIFO_DL_CFG0  (AFE_PMICDIG_AUDIO_BASE+0x0022)
 123 #define ANA_AFE_TOP_CON0                  (AFE_PMICDIG_AUDIO_BASE+0x0024)
 124 #define ANA_AUDIO_TOP_CON0             (AFE_PMICDIG_AUDIO_BASE+0x0026)
 125 #define AFE_UL_SRC_DEBUG       (AFE_PMICDIG_AUDIO_BASE+0x0028)
 126 #define AFE_DL_SRC_DEBUG       (AFE_PMICDIG_AUDIO_BASE+0x002a)
 127 #define AFE_UL_SRC_MON0        (AFE_PMICDIG_AUDIO_BASE+0x002c)
 128 #define AFE_DL_SRC_MON0        (AFE_PMICDIG_AUDIO_BASE+0x002e)
 129 #define AFE_DL_SDM_TEST0       (AFE_PMICDIG_AUDIO_BASE+0x0030)
 130 #define AFE_MON_DEBUG0         (AFE_PMICDIG_AUDIO_BASE+0x0032)
 131 #define AFUNC_AUD_CON0         (AFE_PMICDIG_AUDIO_BASE+0x0034)
 132 #define AFUNC_AUD_CON1         (AFE_PMICDIG_AUDIO_BASE+0x0036)
 133 #define AFUNC_AUD_CON2         (AFE_PMICDIG_AUDIO_BASE+0x0038)
 134 #define AFUNC_AUD_CON3         (AFE_PMICDIG_AUDIO_BASE+0x003A)
 135 #define AFUNC_AUD_CON4         (AFE_PMICDIG_AUDIO_BASE+0x003C)
 136 #define AFUNC_AUD_MON0         (AFE_PMICDIG_AUDIO_BASE+0x003E)
 137 #define AFUNC_AUD_MON1         (AFE_PMICDIG_AUDIO_BASE+0x0040)
 138 #define AUDRC_TUNE_MON0        (AFE_PMICDIG_AUDIO_BASE+0x0042)
 139 #define AFE_I2S_FIFO_MON0      (AFE_PMICDIG_AUDIO_BASE+0x0044)
 140 #define AFE_DL_DC_COMP_CFG0    (AFE_PMICDIG_AUDIO_BASE+0x0046)
 141 #define AFE_DL_DC_COMP_CFG1    (AFE_PMICDIG_AUDIO_BASE+0x0048)
 142 #define AFE_DL_DC_COMP_CFG2    (AFE_PMICDIG_AUDIO_BASE+0x004a)
 143 #define AFE_MBIST_CFG0                 (AFE_PMICDIG_AUDIO_BASE+0x004c)
 144 #define AFE_MBIST_CFG1                 (AFE_PMICDIG_AUDIO_BASE+0x004e)
 145 #define AFE_MBIST_CFG2                 (AFE_PMICDIG_AUDIO_BASE+0x0050)
 146 #define AFE_I2S_FIFO_CFG0           (AFE_PMICDIG_AUDIO_BASE+0x0052)
 147 #endif
 148 //---------------digital pmic  register define end ---------------------------------------
 149
 150 //---------------analog pmic  register define start --------------------------------------
 151 #if 0
 152 #define AFE_PMICANA_AUDIO_BASE        (0x0)
 153
 154 #define CID                  (AFE_PMICANA_AUDIO_BASE + 0x100)
 155 #define TOP_CKPDN0                  (AFE_PMICANA_AUDIO_BASE + 0x102)
 156 #define TOP_CKPDN0_SET              (AFE_PMICANA_AUDIO_BASE + 0x104)
 157 #define TOP_CKPDN0_CLR              (AFE_PMICANA_AUDIO_BASE + 0x106)
 158 #define TOP_CKPDN1                  (AFE_PMICANA_AUDIO_BASE + 0x108)
 159 #define TOP_CKPDN1_SET              (AFE_PMICANA_AUDIO_BASE + 0x10A)
 160 #define TOP_CKPDN1_CLR              (AFE_PMICANA_AUDIO_BASE + 0x10C)
 161 #define TOP_CKPDN2                  (AFE_PMICANA_AUDIO_BASE + 0x10E)
 162 #define TOP_CKPDN2_SET              (AFE_PMICANA_AUDIO_BASE + 0x110)
 163 #define TOP_CKPDN2_CLR              (AFE_PMICANA_AUDIO_BASE + 0x112)
 164 #define TOP_CKCON1                  (AFE_PMICANA_AUDIO_BASE + 0x126)
 165
 166 #define SPK_CON0                    (AFE_PMICANA_AUDIO_BASE + 0x052)
 167 #define SPK_CON1                    (AFE_PMICANA_AUDIO_BASE + 0x054)
 168 #define SPK_CON2                    (AFE_PMICANA_AUDIO_BASE + 0x056)
 169 #define SPK_CON6                    (AFE_PMICANA_AUDIO_BASE + 0x05E)
 170 #define SPK_CON7                    (AFE_PMICANA_AUDIO_BASE + 0x060)
 171 #define SPK_CON8                    (AFE_PMICANA_AUDIO_BASE + 0x062)
 172 #define SPK_CON9                    (AFE_PMICANA_AUDIO_BASE + 0x064)
 173 #define SPK_CON10                   (AFE_PMICANA_AUDIO_BASE + 0x066)
 174 #define SPK_CON11                   (AFE_PMICANA_AUDIO_BASE + 0x068)
 175 #define SPK_CON12                   (AFE_PMICANA_AUDIO_BASE + 0x06A)
 176
 177 #define AUDTOP_CON0                 (AFE_PMICANA_AUDIO_BASE + 0x700)
 178 #define AUDTOP_CON1                 (AFE_PMICANA_AUDIO_BASE + 0x702)
 179 #define AUDTOP_CON2                 (AFE_PMICANA_AUDIO_BASE + 0x704)
 180 #define AUDTOP_CON3                 (AFE_PMICANA_AUDIO_BASE + 0x706)
 181 #define AUDTOP_CON4                 (AFE_PMICANA_AUDIO_BASE + 0x708)
 182 #define AUDTOP_CON5                 (AFE_PMICANA_AUDIO_BASE + 0x70A)
 183 #define AUDTOP_CON6                 (AFE_PMICANA_AUDIO_BASE + 0x70C)
 184 #define AUDTOP_CON7                 (AFE_PMICANA_AUDIO_BASE + 0x70E)
 185 #define AUDTOP_CON8                 (AFE_PMICANA_AUDIO_BASE + 0x710)
 186 #define AUDTOP_CON9                 (AFE_PMICANA_AUDIO_BASE + 0x712)
 187 #else
 188 #include <mach/upmu_hw.h>
 189 #endif
 190
 191 /* The valid range of audio analog hardware in PMIC */
 192 #define AUDTOP_MAX_ADDR_OFFSET          (0x079A)
 193 typedef struct
 194 {
 195     volatile uint16 Suspend_Ana_ABB_AFE_CON0;
 196     volatile uint16 Suspend_Ana_ABB_AFE_CON1;
 197     volatile uint16 Suspend_Ana_ABB_AFE_CON2;
 198     volatile uint16 Suspend_Ana_ABB_AFE_CON3;
 199     volatile uint16 Suspend_Ana_ABB_AFE_CON4;
 200     volatile uint16 Suspend_Ana_ABB_AFE_CON5;
 201     volatile uint16 Suspend_Ana_ABB_AFE_CON6;
 202     volatile uint16 Suspend_Ana_ABB_AFE_CON7;
 203     volatile uint16 Suspend_Ana_ABB_AFE_CON8;
 204     volatile uint16 Suspend_Ana_ABB_AFE_CON9;
 205     volatile uint16 Suspend_Ana_ABB_AFE_CON10;
 206     volatile uint16 Suspend_Ana_ABB_AFE_CON11;
 207     volatile uint16 Suspend_Ana_ABB_AFE_UP8X_FIFO_CFG0;
 208     volatile uint16 Suspend_Ana_ABB_AFE_PMIC_NEWIF_CFG0;
 209     volatile uint16 Suspend_Ana_ABB_AFE_PMIC_NEWIF_CFG1;
 210     volatile uint16 Suspend_Ana_ABB_AFE_PMIC_NEWIF_CFG2;
 211     volatile uint16 Suspend_Ana_ABB_AFE_PMIC_NEWIF_CFG3;
 212     volatile uint16 Suspend_Ana_ABB_AFE_TOP_CON0;
 213     volatile uint16 Suspend_Ana_ABB_AFE_MON_DEBUG0;
 214
 215     volatile uint16 Suspend_Ana_SPK_CON0;
 216     volatile uint16 Suspend_Ana_SPK_CON1;
 217     volatile uint16 Suspend_Ana_SPK_CON2;
 218     volatile uint16 Suspend_Ana_SPK_CON6;
 219     volatile uint16 Suspend_Ana_SPK_CON7;
 220     volatile uint16 Suspend_Ana_SPK_CON8;
 221     volatile uint16 Suspend_Ana_SPK_CON9;
 222     volatile uint16 Suspend_Ana_SPK_CON10;
 223     volatile uint16 Suspend_Ana_SPK_CON11;
 224     volatile uint16 Suspend_Ana_SPK_CON12;
 225     volatile uint16 Suspend_Ana_TOP_CKPDN0;
 226     volatile uint16 Suspend_Ana_TOP_CKPDN0_SET;
 227     volatile uint16 Suspend_Ana_TOP_CKPDN0_CLR;
 228     volatile uint16 Suspend_Ana_TOP_CKPDN1;
 229     volatile uint16 Suspend_Ana_TOP_CKPDN1_SET;
 230     volatile uint16 Suspend_Ana_TOP_CKPDN1_CLR;
 231     volatile uint16 Suspend_Ana_TOP_CKPDN2;
 232     volatile uint16 Suspend_Ana_TOP_CKPDN2_SET;
 233     volatile uint16 Suspend_Ana_TOP_CKPDN2_CLR;
 234     volatile uint16 Suspend_Ana_TOP_RST_CON;
 235     volatile uint16 Suspend_Ana_TOP_RST_CON_SET;
 236     volatile uint16 Suspend_Ana_TOP_RST_CON_CLR;
 237     volatile uint16 Suspend_Ana_TOP_RST_MISC;
 238     volatile uint16 Suspend_Ana_TOP_RST_MISC_SET;
 239     volatile uint16 Suspend_Ana_TOP_RST_MISC_CLR;
 240     volatile uint16 Suspend_Ana_TOP_CKCON0;
 241     volatile uint16 Suspend_Ana_TOP_CKCON0_SET;
 242     volatile uint16 Suspend_Ana_TOP_CKCON0_CLR;
 243     volatile uint16 Suspend_Ana_TOP_CKCON1;
 244     volatile uint16 Suspend_Ana_TOP_CKCON1_SET;
 245     volatile uint16 Suspend_Ana_TOP_CKCON1_CLR;
 246     volatile uint16 Suspend_Ana_TOP_CKTST0;
 247     volatile uint16 Suspend_Ana_TOP_CKTST1;
 248     volatile uint16 Suspend_Ana_TOP_CKTST2;
 249
 250     volatile uint16 Suspend_Ana_AUDTOP_CON0;
 251     volatile uint16 Suspend_Ana_AUDTOP_CON1;
 252     volatile uint16 Suspend_Ana_AUDTOP_CON2;
 253     volatile uint16 Suspend_Ana_AUDTOP_CON3;
 254     volatile uint16 Suspend_Ana_AUDTOP_CON4;
 255     volatile uint16 Suspend_Ana_AUDTOP_CON5;
 256     volatile uint16 Suspend_Ana_AUDTOP_CON6;
 257     volatile uint16 Suspend_Ana_AUDTOP_CON7;
 258     volatile uint16 Suspend_Ana_AUDTOP_CON8;
 259     volatile uint16 Suspend_Ana_AUDTOP_CON9;
 260 } AudAna_Suspend_Reg;
 261
 262 void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask);
 263 uint32  Ana_Get_Reg(uint32 offset);
 264 void AudDrv_Store_reg_ANA(AudAna_Suspend_Reg *pBackup_reg);
 265 void AudDrv_Recover_reg_ANA(AudAna_Suspend_Reg *pBackup_reg);
 266
 267
 268 // for debug usage
 269 void Ana_Log_Print(void);
 270
 271 #endif
 272