drivers/misc/mediatek/sound/mt8127/AudDrv_Afe.h

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   AudioAfe.h
  21  *
  22  * Project:
  23  * --------
  24  *   MT8127  Audio Driver Afe Register setting
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio register
  29  *
  30  * Author:
  31  * -------
  32  *   Ir Lian (mtk00976)
  33  *   Harvey Huang (mtk03996)
  34  *   Chipeng Chang (mtk02308)
  35  *
  36  *------------------------------------------------------------------------------
  37  * $Revision: #1 $
  38  * $Modtime:$
  39  * $Log:$
  40  *
  41  *
  42  *******************************************************************************/
  43
  44 #ifndef _AUDDRV_AFE_H_
  45 #define _AUDDRV_AFE_H_
  46
  47 #include "AudDrv_Common.h"
  48 #include "AudDrv_Def.h"
  49 #include <mach/mt_clkmgr.h>
  50 /*****************************************************************************
  51  *                     C O M P I L E R   F L A G S
  52  *****************************************************************************/
  53
  54
  55 /*****************************************************************************
  56  *                E X T E R N A L   R E F E R E N C E S
  57  *****************************************************************************/
  58
  59 /*****************************************************************************
  60  *                         D A T A   T Y P E S
  61  *****************************************************************************/
  62
  63 typedef enum
  64 {
  65     AFE_MEM_NONE    = 0,
  66     AFE_MEM_DL1     = 1,
  67     AFE_MEM_DL2     = 2,
  68     AFE_MEM_VUL     = 3,
  69     AFE_MEM_DAI     = 4,
  70     AFE_MEM_I2S     = 5,
  71     AFE_MEM_AWB     = 6,
  72     AFE_MEM_MOD_PCM = 7,
  73 } MEM_INTERFACE_T;
  74
  75 typedef enum
  76 {
  77     AFE_8000HZ  = 0,
  78     AFE_11025HZ = 1,
  79     AFE_12000HZ = 2,
  80     AFE_16000HZ = 3,
  81     AFE_22050HZ = 4,
  82     AFE_24000HZ = 5,
  83     AFE_32000HZ = 6,
  84     AFE_44100HZ = 7,
  85     AFE_48000HZ = 8
  86 }  SAMPLINGRATE_T;
  87
  88 typedef enum
  89 {
  90     AFE_DAIMOD_8000HZ  = 0x0,
  91     AFE_DAIMOD_16000HZ = 0x1,
  92 } DAIMOD_SAMPLINGRATE_T;
  93
  94 typedef enum
  95 {
  96     AFE_STEREO = 0x0,
  97     AFE_MONO   = 0x1
  98 } MEMIF_CH_CFG_T;
  99
 100 typedef enum
 101 {
 102     AFE_MONO_USE_L = 0x0,
 103     AFE_MONO_USE_R = 0x1
 104 } MEMIF_MONO_SEL_T;
 105
 106 typedef enum
 107 {
 108     AFE_DUP_WR_DISABLE = 0x0,
 109     AFE_DUP_WR_ENABLE  = 0x1
 110 } MEMIF_DUP_WRITE_T;
 111
 112 typedef struct
 113 {
 114     uint32 u4AFE_MEMIF_BUF_BASE;
 115     uint32 u4AFE_MEMIF_BUF_END;
 116     uint32 u4AFE_MEMIF_BUF_WP;
 117     uint32 u4AFE_MEMIF_BUF_RP;
 118 } MEMIF_BUF_T;
 119
 120 typedef struct
 121 {
 122     MEM_INTERFACE_T        eMemInterface;
 123     SAMPLINGRATE_T         eSamplingRate;
 124     DAIMOD_SAMPLINGRATE_T  eDaiModSamplingRate;
 125     MEMIF_CH_CFG_T         eChannelConfig;
 126     MEMIF_MONO_SEL_T       eMonoSelect;            //Used when AWB and VUL and data is mono
 127     MEMIF_DUP_WRITE_T      eDupWrite;              //Used when MODPCM and DAI
 128     MEMIF_BUF_T            rBufferSetting;
 129 } MEMIF_CONFIG_T;
 130
 131 // I2S related
 132 typedef enum
 133 {
 134     I2S_EIAJ = 0x0,
 135     I2S_I2S  = 0x1
 136 } I2SFMT_T;
 137
 138 typedef enum
 139 {
 140     I2S_16BIT = 0x0,
 141     I2S_32BIT = 0x1
 142 } I2SWLEN_T;
 143
 144 typedef enum
 145 {
 146     I2S_NOSWAP = 0x0,
 147     I2S_LRSWAP = 0x1
 148 } I2SSWAP_T;
 149
 150 typedef enum
 151 {
 152     I2S_DISABLE = 0x0,
 153     I2S_ENABLE  = 0x1
 154 } I2SEN_T;
 155
 156 typedef enum
 157 {
 158     I2S_MASTER = 0x0,
 159     I2S_SLAVE  = 0x1
 160 } I2SSRC_T;
 161
 162 typedef enum
 163 {
 164     I2S_OUT = 0x0,
 165     I2S_IN  = 0x1
 166 } I2SDIR_T;
 167
 168
 169 // PCM related
 170 typedef enum
 171 {
 172     PCM_1 = 0x0,    // (O7, O8, I9)
 173     PCM_2 = 0x1     // (O17, O18, I14)
 174 } PCM_MODULE;
 175
 176 typedef enum
 177 {
 178     PCM_DISABLE = 0x0,
 179     PCM_ENABLE  = 0x1
 180 } PCMEN_T;
 181
 182 typedef enum
 183 {
 184     PCM_I2S   = 0x0,
 185     PCM_EIAJ  = 0x1,
 186     PCM_MODEA = 0x2,
 187     PCM_MODEB = 0x3
 188 } PCMFMT_T;
 189
 190 typedef enum
 191 {
 192     PCM_8K  = 0x0,
 193     PCM_16K = 0x1
 194 } PCMMODE_T;
 195
 196 typedef enum
 197 {
 198     PCM_16BIT = 0x0,
 199     PCM_32BIT = 0x1
 200 } PCMWLEN_T;
 201
 202
 203 typedef enum
 204 {
 205     PCM_MASTER = 0x0,
 206     PCM_SLAVE = 0x1
 207 } PCMCLKSRC_T;
 208
 209
 210 typedef enum
 211 {
 212     PCM_GO_ASRC  = 0x0,         // (ASRC)       Set to 0 when source & destination uses different crystal
 213     PCM_GO_ASYNC_FIFO = 0x1     // (Async FIFO) Set to 1 when source & destination uses same crystal
 214 } PCMBYPASRC_T;
 215
 216
 217 typedef enum
 218 {
 219     PCM_DMTX = 0x0, // dual mic on TX
 220     PCM_SMTX = 0x1  // single mic on TX (In BT mode, only L channel data is sent on PCM TX.)
 221 } PCMBTMODE_T;
 222
 223
 224 typedef enum
 225 {
 226     PCM_SYNC_LEN_1_BCK = 0x0,
 227     PCM_SYNC_LEN_N_BCK = 0x1
 228 } PCMSYNCTYPE_T;
 229
 230 typedef enum
 231 {
 232     PCM_INT_MD = 0x0,
 233     PCM_EXT_MD = 0x1
 234 } PCMEXTMODEM_T;
 235
 236
 237 typedef enum
 238 {
 239     PCM_VBT_16K_MODE_DISABLE = 0x0,
 240     PCM_VBT_16K_MODE_ENABLE = 0x1
 241 } PCMVBT16KMODE_T;
 242
 243
 244 typedef enum
 245 {
 246     PCM_NOINV = 0x0,
 247     PCM_INV   = 0x1
 248 } PCMCLKINV_T;
 249
 250 typedef enum
 251 {
 252     PCM_LB_DISABLE = 0x0,
 253     PCM_LB_ENABLE  = 0x1
 254 } PCMLOOPENA_T;
 255
 256 typedef enum
 257 {
 258     PCM_TXFIX_OFF = 0x0,
 259     PCM_TXFIX_ON  = 0x1
 260 } PCMTXFIXEN_T;
 261
 262 typedef struct
 263 {
 264     PCMFMT_T        ePcmFmt;
 265     PCMMODE_T       ePcm8k16kmode;
 266     PCMWLEN_T       ePcmWlen;
 267     PCMCLKSRC_T     ePcmClkSrc;
 268     PCMBYPASRC_T    ePcmBypassASRC;
 269     PCMEXTMODEM_T   ePcmModemSel;
 270     PCMVBT16KMODE_T ePcmVbt16kSel;
 271 } PCM_INFO_T;
 272
 273
 274 // BT PCM
 275 typedef enum
 276 {
 277     BTPCM_DISABLE = 0x0,
 278     BTPCM_ENABLE  = 0x1
 279 } BTPCMEN_T;
 280
 281 typedef enum
 282 {
 283     BTPCM_8K  = 0x0,
 284     BTPCM_16K = 0x1
 285 } BTPCMMODE_T;
 286
 287
 288
 289 // Interconnection related
 290 typedef enum
 291 {
 292     I00 = 0,
 293     I01 = 1,
 294     I02 = 2,
 295     I03 = 3,
 296     I04 = 4,
 297     I05 = 5,
 298     I06 = 6,
 299     I07 = 7,
 300     I08 = 8,
 301     I09 = 9,
 302     IN_MAX
 303 } ITRCON_IN_T;
 304
 305 typedef enum
 306 {
 307     O00  = 0,
 308     O01  = 1,
 309     O02  = 2,
 310     O03  = 3,
 311     O04  = 4,
 312     O05  = 5,
 313     O06  = 6,
 314     O07  = 7,
 315     O08  = 8,
 316     O09  = 9,
 317     O010 = 10,
 318     O011 = 11,
 319     O012 = 12,
 320     OUT_MAX
 321 } ITRCON_OUT_T;
 322
 323 // IRQ related
 324 typedef enum
 325 {
 326     IRQ1 = 1,
 327     IRQ2 = 2,
 328     IRQ5 = 3, //HDMI
 329     IRQ6 = 4, //SPDIF
 330     IRQMAX
 331 } IRQTYPE_T;
 332
 333
 334 // Side tone filter related
 335 typedef enum
 336 {
 337     I3I4    = 0,
 338     HW_SINE = 1,
 339     I5I6    = 2,
 340 } STF_SRC_T;
 341
 342 // Sine wave generator related
 343 typedef enum
 344 {
 345     SINE_TONE_CH1    = 0,
 346     SINE_TONE_CH2    = 1,
 347     SINE_TONE_STEREO = 2
 348 } SINE_TONE_CH_T;
 349
 350 typedef enum
 351 {
 352     SINE_TONE_128   = 0,
 353     SINE_TONE_64    = 1,
 354     SINE_TONE_32    = 2,
 355     SINE_TONE_16    = 3,
 356     SINE_TONE_8     = 4,
 357     SINE_TONE_4     = 5,
 358     SINE_TONE_2     = 6,
 359     SINE_TONE_1     = 7
 360 } SINE_TONE_AMP_T;
 361
 362 typedef enum
 363 {
 364     SINE_TONE_8K        = 0,
 365     SINE_TONE_11K       = 1,
 366     SINE_TONE_12K       = 2,
 367     SINE_TONE_16K       = 3,
 368     SINE_TONE_22K       = 4,
 369     SINE_TONE_24K       = 5,
 370     SINE_TONE_32K       = 6,
 371     SINE_TONE_44K       = 7,
 372     SINE_TONE_48K       = 8,
 373     SINE_TONE_LOOPBACK  = 9
 374 } SINE_TONE_SINEMODE_T;
 375
 376 typedef enum
 377 {
 378     SINE_TONE_LOOPBACK_I0_I1   = 0,
 379     SINE_TONE_LOOPBACK_I2      = 1,
 380     SINE_TONE_LOOPBACK_I3_I4   = 2,
 381     SINE_TONE_LOOPBACK_I5_I6   = 3,
 382     SINE_TONE_LOOPBACK_I7_I8   = 4,
 383     SINE_TONE_LOOPBACK_I9_I10  = 5,
 384     SINE_TONE_LOOPBACK_I11_I12 = 6,
 385     SINE_TONE_LOOPBACK_O0_O1   = 7,
 386     SINE_TONE_LOOPBACK_O2      = 8,
 387     SINE_TONE_LOOPBACK_O3_O4   = 9,
 388     SINE_TONE_LOOPBACK_O5_O6   = 10,
 389     SINE_TONE_LOOPBACK_O7_O8   = 11,
 390     SINE_TONE_LOOPBACK_O9_O10  = 12,
 391     SINE_TONE_LOOPBACK_O11     = 13,
 392     SINE_TONE_LOOPBACK_O12     = 14
 393 } SINE_TONE_LOOPBACK_T;
 394
 395 typedef struct
 396 {
 397     uint32               u4ch1_freq_div; // 64/n sample/period
 398     SINE_TONE_AMP_T      rch1_amp_div;
 399     SINE_TONE_SINEMODE_T rch1_sine_mode;
 400     uint32               u4ch2_freq_div; // 64/n sample/period
 401     SINE_TONE_AMP_T      rch2_amp_div;
 402     SINE_TONE_SINEMODE_T rch2_sine_mode;
 403     SINE_TONE_LOOPBACK_T rloopback_mode;
 404 } AFE_SINEGEN_INFO_T;
 405
 406
 407 /*****************************************************************************
 408  *                          C O N S T A N T S
 409  *****************************************************************************/
 410 #define AUDIO_HW_PHYSICAL_BASE  (0x11220000)
 411 #define AUDIO_HW_VIRTUAL_BASE   (0xF1220000)
 412 #ifdef AUDIO_MEM_IOREMAP
 413 #define AFE_BASE                (0)
 414 #else
 415 #define AFE_BASE                (AUDIO_HW_VIRTUAL_BASE)
 416 #endif
 417
 418 //Internal sram: 0x12004000~0x12007FFF (16K)
 419 #define AFE_INTERNAL_SRAM_PHY_BASE  (0x11221000)
 420 #define AFE_INTERNAL_SRAM_VIR_BASE  (0xF1221000)
 421 #define AFE_INTERNAL_SRAM_SIZE  (0x4000)
 422
 423 //Dram
 424 #define AFE_EXTERNAL_DRAM_SIZE  (0x4000)
 425 /*****************************************************************************
 426  *                         M A C R O
 427  *****************************************************************************/
 428
 429 /*****************************************************************************
 430  *                  R E G I S T E R       D E F I N I T I O N
 431  *****************************************************************************/
 432 #define AUDIOAFE_TOP_CON0  (AFE_BASE + 0x0000)    //AUDIO_TOP_CON0
 433 #define AUDIO_TOP_CON1  (AFE_BASE + 0x0004)
 434 #define AUDIO_TOP_CON2  (AFE_BASE + 0x0008)
 435 #define AUDIO_TOP_CON3  (AFE_BASE + 0x000C)
 436 #define AFE_DAC_CON0      (AFE_BASE + 0x0010)
 437 #define AFE_DAC_CON1      (AFE_BASE + 0x0014)
 438 #define AFE_I2S_CON         (AFE_BASE + 0x0018)
 439 //#define  AFE_DAIBT_CON0  (AFE_BASE + 0x001c)
 440
 441 #define AFE_CONN0       (AFE_BASE + 0x0020)
 442 #define AFE_CONN1       (AFE_BASE + 0x0024)
 443 #define AFE_CONN2       (AFE_BASE + 0x0028)
 444 #define AFE_CONN3       (AFE_BASE + 0x002C)
 445 #define AFE_CONN4       (AFE_BASE + 0x0030)
 446
 447 #define AFE_I2S_CON1    (AFE_BASE + 0x0034)
 448 #define AFE_I2S_CON2    (AFE_BASE + 0x0038)
 449 //#define AFE_MRGIF_CON    (AFE_BASE + 0x003C)
 450
 451
 452 // Memory interface
 453 #define AFE_DL1_BASE     (AFE_BASE + 0x0040)
 454 #define AFE_DL1_CUR       (AFE_BASE + 0x0044)
 455 #define AFE_DL1_END       (AFE_BASE + 0x0048)
 456 #define AFE_I2S_CON3    (AFE_BASE + 0x004C)//
 457 #define AFE_DL2_BASE     (AFE_BASE + 0x0050)
 458 #define AFE_DL2_CUR       (AFE_BASE + 0x0054)
 459 #define AFE_DL2_END       (AFE_BASE + 0x0058)
 460 #define AFE_AWB_BASE   (AFE_BASE + 0x0070)
 461 #define AFE_AWB_END     (AFE_BASE + 0x0078)
 462 #define AFE_AWB_CUR     (AFE_BASE + 0x007C)
 463 #define AFE_VUL_BASE     (AFE_BASE + 0x0080)
 464 #define AFE_VUL_END       (AFE_BASE + 0x0088)
 465 #define AFE_VUL_CUR       (AFE_BASE + 0x008C)
 466 //#define AFE_DAI_BASE     (AFE_BASE + 0x0090)
 467 //#define AFE_DAI_END       (AFE_BASE + 0x0098)
 468 //#define AFE_DAI_CUR       (AFE_BASE + 0x009C)
 469
 470 //#define AFE_IRQ_CON         (AFE_BASE + 0x00A0)
 471
 472 // Memory interface monitor
 473 #define AFE_MEMIF_MON0 (AFE_BASE + 0x00D0)
 474 #define AFE_MEMIF_MON1 (AFE_BASE + 0x00D4)
 475 #define AFE_MEMIF_MON2 (AFE_BASE + 0x00D8)
 476 //#define AFE_MEMIF_MON3 (AFE_BASE + 0x00DC)
 477 #define AFE_MEMIF_MON4 (AFE_BASE + 0x00E0)
 478
 479 //ADDA
 480 #define AFE_ADDA_DL_SRC2_CON0 (AFE_BASE+0x0108)
 481 #define AFE_ADDA_DL_SRC2_CON1 (AFE_BASE+0x010C)
 482 #define AFE_ADDA_UL_SRC_CON0 (AFE_BASE+0x0114)
 483 #define AFE_ADDA_UL_SRC_CON1 (AFE_BASE+0x0118)
 484 #define AFE_ADDA_TOP_CON0 (AFE_BASE+0x0120)
 485 #define AFE_ADDA_UL_DL_CON0 (AFE_BASE+0x0124)
 486 #define AFE_ADDA_SRC_DEBUG (AFE_BASE+0x012C)
 487 #define AFE_ADDA_SRC_DEBUG_MON0 (AFE_BASE+0x0130)
 488 #define AFE_ADDA_SRC_DEBUG_MON1 (AFE_BASE+0x0134)
 489 #define AFE_ADDA_NEWIF_CFG0 (AFE_BASE+0x0138)
 490 #define AFE_ADDA_NEWIF_CFG1 (AFE_BASE+0x013C)
 491
 492
 493 //#define AFE_FOC_CON  (AFE_BASE + 0x0170)
 494 //#define AFE_FOC_CON1 (AFE_BASE + 0x0174)
 495 //#define AFE_FOC_CON2 (AFE_BASE + 0x0178)
 496 //#define AFE_FOC_CON3 (AFE_BASE + 0x017C)
 497 //#define AFE_FOC_CON4 (AFE_BASE + 0x0180)
 498 //#define AFE_FOC_CON5 (AFE_BASE + 0x0184)
 499 //#define AFE_MON_STEP        (AFE_BASE + 0x0188)
 500
 501 #define AFE_SIDETONE_DEBUG  (AFE_BASE + 0x01D0)
 502 #define AFE_SIDETONE_MON    (AFE_BASE + 0x01D4)
 503 #define AFE_SIDETONE_CON0   (AFE_BASE + 0x01E0)
 504 #define AFE_SIDETONE_COEFF  (AFE_BASE + 0x01E4)
 505 #define AFE_SIDETONE_CON1   (AFE_BASE + 0x01E8)
 506 #define AFE_SIDETONE_GAIN   (AFE_BASE + 0x01EC)
 507 #define AFE_SGEN_CON0         (AFE_BASE +0x01F0)
 508
 509 //#define AFE_MRG_MON0   (AFE_BASE + 0x0270)
 510 //#define AFE_MRG_MON1   (AFE_BASE + 0x0274)
 511 //#define AFE_MRG_MON2   (AFE_BASE + 0x0278)
 512
 513
 514 #define AFE_TOP_CON0    (AFE_BASE + 0x0200)
 515
 516 #define AFE_PREDIS_CON0 (AFE_BASE + 0x0260)
 517 #define AFE_PREDIS_CON1 (AFE_BASE + 0x0264)
 518
 519 #define AFE_MOD_PCM_BASE (AFE_BASE + 0x0330)
 520 #define AFE_MOD_PCM_END  (AFE_BASE + 0x0338)
 521 #define AFE_MOD_PCM_CUR  (AFE_BASE + 0x033C)
 522
 523 #define AFE_HDMI_OUT_CON0       (AFE_BASE + 0x0370) //8135 new
 524 #define AFE_HDMI_OUT_BASE       (AFE_BASE + 0x0374) //8135 new
 525 #define AFE_HDMI_OUT_CUR        (AFE_BASE + 0x0378) //8135 new
 526 #define AFE_HDMI_OUT_END        (AFE_BASE + 0x037C) //8135 new
 527 #define AFE_SPDIF_OUT_CON0      (AFE_BASE + 0x0380) //8135 new
 528 #define AFE_SPDIF_BASE          (AFE_BASE + 0x0384) //8135 new
 529 #define AFE_SPDIF_CUR           (AFE_BASE + 0x0388) //8135 new
 530 #define AFE_SPDIF_END           (AFE_BASE + 0x038C) //8135 new
 531 #define AFE_HDMI_CONN0          (AFE_BASE + 0x0390) //8135 new
 532 #define AFE_8CH_I2S_OUT_CON     (AFE_BASE + 0x0394) //8135 new
 533 #define AFE_HDMI_CONN1     (AFE_BASE + 0x0398) //8135 new
 534
 535 #define AFE_IRQ_MCU_CON             (AFE_BASE + 0x03A0)
 536 #define AFE_IRQ_MCU_STATUS      (AFE_BASE + 0x03A4)
 537 #define AFE_IRQ_CLR              (AFE_BASE + 0x03A8)
 538 #define AFE_IRQ_MCU_CNT1        (AFE_BASE + 0x03AC)
 539 #define AFE_IRQ_MCU_CNT2        (AFE_BASE + 0x03B0)
 540 #define AFE_IRQ_MCU_MON2        (AFE_BASE + 0x03B8)
 541 #define AFE_IRQ_MCU_CNT5        (AFE_BASE + 0x03BC)
 542 #define AFE_IRQ1_MCU_CNT_MON    (AFE_BASE + 0x03C0)
 543 #define AFE_IRQ2_MCU_CNT_MON    (AFE_BASE + 0x03C4)
 544 #define AFE_IRQ1_MCU_EN_CNT_MON (AFE_BASE + 0x03C8)
 545 #define AFE_IRQ5_MCU_EN_CNT_MON (AFE_BASE + 0x03cc)
 546 //#define AFE_MEMIF_MINLEN        (AFE_BASE + 0x03D0)  //removed in MT8127
 547 #define AFE_MEMIF_MAXLEN        (AFE_BASE + 0x03D4)
 548 #define AFE_MEMIF_PBUF_SIZE   (AFE_BASE + 0x03D8)
 549
 550 //AFE GAIN CONTROL REGISTER
 551 #define AFE_GAIN1_CON0         (AFE_BASE + 0x0410)
 552 #define AFE_GAIN1_CON1         (AFE_BASE + 0x0414)
 553 #define AFE_GAIN1_CON2         (AFE_BASE + 0x0418)
 554 #define AFE_GAIN1_CON3         (AFE_BASE + 0x041C)
 555 #define AFE_GAIN1_CONN         (AFE_BASE + 0x0420)
 556 #define AFE_GAIN1_CUR          (AFE_BASE + 0x0424)
 557 #define AFE_GAIN2_CON0         (AFE_BASE + 0x0428)
 558 #define AFE_GAIN2_CON1         (AFE_BASE + 0x042C)
 559 #define AFE_GAIN2_CON2         (AFE_BASE + 0x0430)
 560 #define AFE_GAIN2_CON3         (AFE_BASE + 0x0434)
 561 #define AFE_GAIN2_CONN         (AFE_BASE + 0x0438)
 562 #define AFE_GAIN2_CUR          (AFE_BASE + 0x043C)
 563 #define AFE_GAIN2_CONN2        (AFE_BASE + 0x0440)
 564
 565 #define AFE_IEC_CFG             (AFE_BASE + 0x0480) //8135 new
 566 #define AFE_IEC_NSNUM           (AFE_BASE + 0x0484) //8135 new
 567 #define AFE_IEC_BURST_INFO      (AFE_BASE + 0x0488) //8135 new
 568 #define AFE_IEC_BURST_LEN       (AFE_BASE + 0x048C) //8135 new
 569 #define AFE_IEC_NSADR           (AFE_BASE + 0x0490) //8135 new
 570 #define AFE_IEC_CHL_STAT0       (AFE_BASE + 0x04A0) //8135 new
 571 #define AFE_IEC_CHL_STAT1       (AFE_BASE + 0x04A4) //8135 new
 572 #define AFE_IEC_CHR_STAT0       (AFE_BASE + 0x04A8) //8135 new
 573 #define AFE_IEC_CHR_STAT1       (AFE_BASE + 0x04AC) //8135 new
 574
 575 // here is only fpga needed
 576 #define FPGA_CFG2           (AFE_BASE + 0x04B8)//
 577 #define FPGA_CFG3           (AFE_BASE + 0x04BC)//
 578 #define FPGA_CFG0           (AFE_BASE + 0x04C0)
 579 #define FPGA_CFG1           (AFE_BASE + 0x04C4)
 580 //#define FPGA_VERSION        (AFE_BASE + 0x04C8)
 581 #define FPGA_STC            (AFE_BASE + 0x04CC)//
 582
 583 #define AFE_ASRC_CON0   (AFE_BASE + 0x500)
 584 #define AFE_ASRC_CON1   (AFE_BASE + 0x504)
 585 #define AFE_ASRC_CON2   (AFE_BASE + 0x508)
 586 #define AFE_ASRC_CON3   (AFE_BASE + 0x50C)
 587 #define AFE_ASRC_CON4   (AFE_BASE + 0x510)
 588 #define AFE_ASRC_CON5   (AFE_BASE + 0x514)
 589 #define AFE_ASRC_CON6   (AFE_BASE + 0x518)
 590 #define AFE_ASRC_CON7   (AFE_BASE + 0x51C)
 591 #define AFE_ASRC_CON8   (AFE_BASE + 0x520)
 592 #define AFE_ASRC_CON9   (AFE_BASE + 0x524)
 593 #define AFE_ASRC_CON10  (AFE_BASE + 0x528)
 594 #define AFE_ASRC_CON11  (AFE_BASE + 0x52C)
 595
 596 #define PCM_INTF_CON1   (AFE_BASE + 0x530)
 597 #define PCM_INTF_CON2   (AFE_BASE + 0x538)
 598 #define PCM2_INTF_CON   (AFE_BASE + 0x53C)
 599
 600 //
 601 #define AFE_ASRC_CON13   (AFE_BASE + 0x550)
 602 #define AFE_ASRC_CON14   (AFE_BASE + 0x554)
 603 #define AFE_ASRC_CON15   (AFE_BASE + 0x558)
 604 #define AFE_ASRC_CON16   (AFE_BASE + 0x55C)
 605 #define AFE_ASRC_CON17   (AFE_BASE + 0x560)
 606 #define AFE_ASRC_CON18   (AFE_BASE + 0x564)
 607 #define AFE_ASRC_CON19   (AFE_BASE + 0x568)
 608 #define AFE_ASRC_CON20   (AFE_BASE + 0x56C)
 609 #define AFE_ASRC_CON21   (AFE_BASE + 0x570)
 610
 611
 612 /**********************************
 613  *  Detailed Definitions
 614  **********************************/
 615
 616 //AFE_TOP_CON0
 617 #define PDN_AFE  2
 618 #define PDN_ADC  5
 619 #define PDN_I2S  6
 620 #define APB_W2T 12
 621 #define APB_R2T 13
 622 #define APB_SRC 14
 623 #define PDN_APLL_TUNER 19
 624 #define PDN_HDMI_CK    20
 625 #define PDN_SPDF_CK    21
 626
 627 // AUDIO_TOP_CON3
 628 #define HDMI_SPEAKER_OUT_HDMI_POS 5
 629 #define HDMI_SPEAKER_OUT_HDMI_LEN 1
 630 #define HDMI_BCK_DIV_LEN      6
 631 #define HDMI_BCK_DIV_POS      8
 632 #define HDMI_2CH_SEL_POS      6
 633 #define HDMI_2CH_SEL_LEN      2
 634 #define HDMI_2CH_SEL_SDATA0 0
 635 #define HDMI_2CH_SEL_SDATA1 1
 636 #define HDMI_2CH_SEL_SDATA2 2
 637 #define HDMI_2CH_SEL_SDATA3 3
 638
 639 //AFE_DAC_CON0
 640 #define AFE_ON      0
 641 #define DL1_ON      1
 642 #define DL2_ON      2
 643 #define VUL_ON      3
 644 #define DAI_ON      4
 645 #define I2S_ON      5
 646 #define AWB_ON      6
 647 #define MOD_PCM_ON  7
 648 #define AFE_ON_RETM  12
 649 #define AFE_DL1_RETM 13
 650 #define AFE_DL2_RETM 14
 651 #define AFE_AWB_RETM 16
 652
 653 //AFE_DAC_CON1
 654 #define DL1_MODE_LEN    4
 655 #define DL1_MODE_POS    0
 656
 657 #define DL2_MODE_LEN    4
 658 #define DL2_MODE_POS    4
 659
 660 #define I2S_MODE_LEN    4
 661 #define I2S_MODE_POS    8
 662
 663 #define AWB_MODE_LEN    4
 664 #define AWB_MODE_POS    12
 665
 666 #define VUL_MODE_LEN    4
 667 #define VUL_MODE_POS    16
 668
 669 #define DAI_MODE_LEN    1
 670 #define DAI_MODE_POS    20
 671
 672 #define DL1_DATA_LEN    1
 673 #define DL1_DATA_POS    21
 674
 675 #define DL2_DATA_LEN    1
 676 #define DL2_DATA_POS    22
 677
 678 #define I2S_DATA_LEN    1
 679 #define I2S_DATA_POS    23
 680
 681 #define AWB_DATA_LEN    1
 682 #define AWB_DATA_POS    24
 683
 684 #define AWB_R_MONO_LEN  1
 685 #define AWB_R_MONO_POS  25
 686
 687 #define VUL_DATA_LEN    1
 688 #define VUL_DATA_POS    27
 689
 690 #define VUL_R_MONO_LEN  1
 691 #define VUL_R_MONO_POS  28
 692
 693 #define DAI_DUP_WR_LEN  1
 694 #define DAI_DUP_WR_POS  29
 695
 696 #define MOD_PCM_MODE_LEN    1
 697 #define MOD_PCM_MODE_POS    30
 698
 699 #define MOD_PCM_DUP_WR_LEN  1
 700 #define MOD_PCM_DUP_WR_POS  31
 701
 702 //AFE_I2S_CON1 and AFE_I2S_CON2
 703 #define AI2S_EN_POS             0
 704 #define AI2S_EN_LEN             1
 705 #define AI2S_WLEN_POS           1
 706 #define AI2S_WLEN_LEN           1
 707 #define AI2S_FMT_POS            3
 708 #define AI2S_FMT_LEN            1
 709 #define AI2S_OUT_MODE_POS       8
 710 #define AI2S_OUT_MODE_LEN       4
 711 #define AI2S_UPDATE_WORD_POS    24
 712 #define AI2S_UPDATE_WORD_LEN    5
 713 #define AI2S_LR_SWAP_POS        31
 714 #define AI2S_LR_SWAP_LEN        1
 715
 716 #define I2S_EN_POS          0
 717 #define I2S_EN_LEN          1
 718 #define I2S_WLEN_POS        1
 719 #define I2S_WLEN_LEN        1
 720 #define I2S_SRC_POS         2
 721 #define I2S_SRC_LEN         1
 722 #define I2S_FMT_POS         3
 723 #define I2S_FMT_LEN         1
 724 #define I2S_DIR_POS         4
 725 #define I2S_DIR_LEN         1
 726 #define I2S_OUT_MODE_POS    8
 727 #define I2S_OUT_MODE_LEN    4
 728
 729 #define FOC_EN_POS  0
 730 #define FOC_EN_LEN  1
 731
 732 // Modem PCM 1
 733 #define PCM_EN_POS          0
 734 #define PCM_EN_LEN          1
 735
 736 #define PCM_FMT_POS         1
 737 #define PCM_FMT_LEN         2
 738
 739 #define PCM_MODE_POS        3
 740 #define PCM_MODE_LEN        1
 741
 742 #define PCM_WLEN_POS        4
 743 #define PCM_WLEN_LEN        1
 744
 745 #define PCM_SLAVE_POS       5
 746 #define PCM_SLAVE_LEN       1
 747
 748 #define PCM_BYP_ASRC_POS    6
 749 #define PCM_BYP_ASRC_LEN    1
 750
 751 #define PCM_BTMODE_POS      7
 752 #define PCM_BTMODE_LEN      1
 753
 754 #define PCM_SYNC_TYPE_POS   8
 755 #define PCM_SYNC_TYPE_LEN   1
 756
 757 #define PCM_SYNC_LEN_POS    9
 758 #define PCM_SYNC_LEN_LEN    5
 759
 760 #define PCM_EXT_MODEM_POS   17
 761 #define PCM_EXT_MODEM_LEN   1
 762
 763 #define PCM_VBT16K_MODE_POS 18
 764 #define PCM_VBT16K_MODE_LEN 1
 765
 766 //#define PCM_BCKINV_POS      6
 767 //#define PCM_BCKINV_LEN      1
 768 //#define PCM_SYNCINV_POS     7
 769 //#define PCM_SYNCINV_LEN     1
 770
 771 #define PCM_SERLOOPBK_POS   28
 772 #define PCM_SERLOOPBK_LEN   1
 773
 774 #define PCM_PARLOOPBK_POS   29
 775 #define PCM_PARLOOPBK_LEN   1
 776
 777 #define PCM_BUFLOOPBK_POS   30
 778 #define PCM_BUFLOOPBK_LEN   1
 779
 780 #define PCM_FIX_VAL_SEL_POS 31
 781 #define PCM_FIX_VAL_SEL_LEN 1
 782
 783 // BT PCM
 784 #define DAIBT_EN_POS   0
 785 #define DAIBT_EN_LEN   1
 786 #define BTPCM_EN_POS   1
 787 #define BTPCM_EN_LEN   1
 788 #define BTPCM_SYNC_POS   2
 789 #define BTPCM_SYNC_LEN   1
 790 #define DAIBT_DATARDY_POS   3
 791 #define DAIBT_DATARDY_LEN   1
 792 #define BTPCM_LENGTH_POS   4
 793 #define BTPCM_LENGTH_LEN   3
 794 #define DAIBT_MODE_POS   9
 795 #define DAIBT_MODE_LEN   1
 796
 797 // AFE_IRQ_CON
 798 #define IRQ1_ON         0
 799 #define IRQ2_ON         1
 800 #define IRQ3_ON         2
 801 #define IRQ4_ON         3
 802 #define IRQ1_FS         4
 803 #define IRQ2_FS         8
 804 #define IRQ5_ON         12
 805 #define IRQ6_ON         13
 806 #define IRQ_SETTING_BIT 0x3003
 807
 808 // AFE_IRQ_MCU_STATUS
 809 #define IRQ1_ON_BIT     1<<0
 810 #define IRQ2_ON_BIT     1<<1
 811 #define IRQ3_ON_BIT     1<<2
 812 #define IRQ4_ON_BIT     1<<3
 813 #define IRQ5_ON_BIT     1<<4
 814 #define IRQ6_ON_BIT     1<<5
 815 #define IRQ_STATUS_BIT  0x3F
 816
 817 // AFE_IRQ_CLR
 818 #define IRQ1_CLR 1<<0
 819 #define IRQ2_CLR 1<<1
 820 #define IRQ3_CLR 1<<2
 821 #define IRQ4_CLR 1<<3
 822 #define IRQ_CLR  1<<4
 823
 824 #define IRQ1_MISS_CLR 1<<8
 825 #define IRQ2_MISS_CLR 1<<9
 826 #define IRQ3_MISS_CLR 1<<10
 827 #define IRQ4_MISS_CLR 1<<11
 828 #define IRQ5_MISS_CLR 1<<12
 829 #define IRQ6_MISS_CLR 1<<13
 830
 831 // AFE_IRQ_MCU_MON2
 832 #define IRQ1_MISS_BIT       1<<8
 833 #define IRQ2_MISS_BIT       1<<9
 834 #define IRQ3_MISS_BIT       1<<10
 835 #define IRQ4_MISS_BIT       1<<11
 836 #define IRQ5_MISS_BIT       1<<12
 837 #define IRQ6_MISS_BIT       1<<13
 838 #define IRQ_MISS_STATUS_BIT 0x3F00
 839
 840 // AUDIO_TOP_CON3
 841 #define HDMI_OUT_SPEAKER_BIT    4
 842 #define SPEAKER_OUT_HDMI        5
 843 #define HDMI_2CH_SEL_POS        6
 844 #define HDMI_2CH_SEL_LEN        2
 845
 846 // AFE_SIDETONE_DEBUG
 847 #define STF_SRC_SEL     16
 848 #define STF_I5I6_SEL    19
 849
 850 // AFE_SIDETONE_CON0
 851 #define STF_COEFF_VAL       0
 852 #define STF_COEFF_ADDRESS   16
 853 #define STF_CH_SEL          23
 854 #define STF_COEFF_W_ENABLE  24
 855 #define STF_W_ENABLE        25
 856 #define STF_COEFF_BIT       0x0000FFFF
 857
 858 // AFE_SIDETONE_CON1
 859 #define STF_TAP_NUM 0
 860 #define STF_ON      8
 861 #define STF_BYPASS  31
 862
 863 // AFE_SGEN_CON0
 864 #define SINE_TONE_FREQ_DIV_CH1  0
 865 #define SINE_TONE_AMP_DIV_CH1   5
 866 #define SINE_TONE_MODE_CH1      8
 867 #define SINE_TONE_FREQ_DIV_CH2  12
 868 #define SINE_TONE_AMP_DIV_CH2   17
 869 #define SINE_TONE_MODE_CH2      20
 870 #define SINE_TONE_MUTE_CH1      24
 871 #define SINE_TONE_MUTE_CH2      25
 872 #define SINE_TONE_ENABLE        26
 873 #define SINE_TONE_LOOPBACK_MOD  28
 874
 875 //FPGA_CFG0
 876 #define MCLK_MUX2_POS    26
 877 #define MCLK_MUX2_LEN    1
 878 #define MCLK_MUX1_POS    25
 879 #define MCLK_MUX1_LEN    1
 880 #define MCLK_MUX0_POS    24
 881 #define MCLK_MUX0_LEN    1
 882 #define SOFT_RST_POS   16
 883 #define SOFT_RST_LEN   8\14
 884 #define HOP26M_SEL_POS   12
 885 #define HOP26M_SEL_LEN   2
 886
 887 //FPGA_CFG1
 888 #define CODEC_SEL_POS   0
 889 #define DAC_SEL_POS     4
 890 #define ADC_SEL_POS     8
 891
 892 #define AUDPLL_CON3   (APMIXEDSYS_BASE+0x0408)
 893
 894 //apmixed sys AUDPLL_CON4
 895 #define AUDPLL_SDM_PCW_98M       0x3C7EA932
 896 #define AUDPLL_SDM_PCW_90M       0x37945EA6
 897 #define AUDPLL_TUNER_N_98M       0x3C7EA933   //48k-based , 98.304M , sdm_pcw+1
 898 #define AUDPLL_TUNER_N_90M       0x37945EA7   //44.1k-based , 90.3168M, sdm_pcw+1
 899
 900 //AUDPLL_CON0
 901 #define AUDPLL_EN_POS            0
 902 #define AUDPLL_EN_LEN            1
 903 #define AUDPLL_PREDIV_POS        4
 904 #define AUDPLL_PREDIV_LEN        2
 905 #define AUDPLL_POSDIV_POS        6
 906 #define AUDPLL_POSDIV_LEN        3
 907 //AUDPLL_CON1
 908 #define AUDPLL_SDM_PCW_POS       0
 909 #define AUDPLL_SDM_PCW_LEN      31
 910 #define AUDPLL_SDM_PCW_CHG_POS  31
 911 #define AUDPLL_SDM_PCW_CHG_LEN   1
 912 //AUDPLL_CON4
 913 #define AUDPLL_TUNER_N_INFO_POS  0
 914 #define AUDPLL_TUNER_N_INFO_LEN 31
 915 #define AUDPLL_TUNER_N_INFO_MASK 0x7FFFFFFF
 916 #define AUDPLL_TUNER_EN_POS     31
 917 #define AUDPLL_TUNER_EN_LEN      1
 918 #define AUDPLL_TUNER_EN_MASK     0x80000000
 919
 920 /* The maximum address offset of Audio Front End */
 921 #define AFE_MAX_ADDR_OFFSET     (0x570)
 922 #define CLK_APLL_SEL_POS     16
 923 #define CLK_APLL_SEL_LEN     3
 924 #define CLKSQ_MUX_CK     0
 925 #define AD_APLL_CK       1
 926 #define APLL_D4          2
 927 #define APLL_D8          3
 928 #define APLL_D16         4
 929 #define APLL_D24        5
 930 #define PDN_APLL_POS     23
 931 #define PDN_APLL_LEN      1
 932
 933 void Afe_Set_Reg(uint32 offset, uint32 value, uint32 mask);
 934 uint32  Afe_Get_Reg(uint32 offset);
 935
 936 // for debug usage
 937 void Afe_Log_Print(void);
 938
 939 void AP_Set_Reg(uint32 offset, uint32 value, uint32 mask);
 940 uint32 AP_Get_Reg(uint32 offset);
 941
 942 #endif
 943