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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / pmic_wrap / mt8127 / pwrap_hal.c
1 /******************************************************************************
2 * pwrap_hal.c - Linux pmic_wrapper Driver,hardware_dependent driver
3 *
4 *
5 * DESCRIPTION:
6 * This file provid the other drivers PMIC wrapper relative functions
7 *
8 ******************************************************************************/
9
10 #include <linux/spinlock.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/sched.h>
14 #include <mach/mt_typedefs.h>
15 #include <linux/timer.h>
16 #include <mach/mt_pmic_wrap.h>
17 #include <linux/io.h>
18 #include "pwrap_hal.h"
19
20 #define PMIC_WRAP_DEVICE "pmic_wrap"
21
22 static struct mt_pmic_wrap_driver *mt_wrp;
23
24 static spinlock_t wrp_lock = __SPIN_LOCK_UNLOCKED(lock);
25 //----------interral API ------------------------
26 static S32 _pwrap_init_dio( U32 dio_en );
27 static S32 _pwrap_init_cipher( void );
28 static S32 _pwrap_init_reg_clock( U32 regck_sel );
29
30 static S32 _pwrap_wacs2_nochk( U32 write, U32 adr, U32 wdata, U32 *rdata );
31 static S32 pwrap_write_nochk( U32 adr, U32 wdata );
32 static S32 pwrap_read_nochk( U32 adr, U32 *rdata );
33
34 /*-pwrap debug--------------------------------------------------------------------------*/
35 static inline void pwrap_dump_ap_register(void)
36 {
37 U32 i=0;
38 PWRAPREG("dump pwrap register, base=0x%x\n",PMIC_WRAP_BASE);
39 PWRAPREG("address : 3 2 1 0 7 6 5 4 B A 9 8 F E D C \n");
40 for(i=0;i<=0x150;i+=16)
41 {
42 PWRAPREG("offset 0x%.3x:0x%.8x 0x%.8x 0x%.8x 0x%.8x \n",i,
43 WRAP_RD32(PMIC_WRAP_BASE+i+0),
44 WRAP_RD32(PMIC_WRAP_BASE+i+4),
45 WRAP_RD32(PMIC_WRAP_BASE+i+8),
46 WRAP_RD32(PMIC_WRAP_BASE+i+12));
47 }
48 //PWRAPREG("elapse_time=%llx(ns)\n",elapse_time);
49 return;
50 }
51 static inline void pwrap_dump_pmic_register(void)
52 {
53 // U32 i=0;
54 // U32 reg_addr=0;
55 // U32 reg_value=0;
56 //
57 // PWRAPREG("dump dewrap register\n");
58 // for(i=0;i<=14;i++)
59 // {
60 // reg_addr=(DEW_BASE+i*4);
61 // reg_value=pwrap_read_nochk(reg_addr,&reg_value);
62 // PWRAPREG("0x%x=0x%x\n",reg_addr,reg_value);
63 // }
64 return;
65 }
66 static inline void pwrap_dump_all_register(void)
67 {
68 pwrap_dump_ap_register();
69 pwrap_dump_pmic_register();
70 return;
71 }
72 /******************************************************************************
73 wrapper timeout
74 ******************************************************************************/
75 #define PWRAP_TIMEOUT
76 #ifdef PWRAP_TIMEOUT
77 static U64 _pwrap_get_current_time(void)
78 {
79 return sched_clock(); ///TODO: fix me
80 }
81 //U64 elapse_time=0;
82
83 static BOOL _pwrap_timeout_ns (U64 start_time_ns, U64 timeout_time_ns)
84 {
85 U64 cur_time=0;
86 U64 elapse_time=0;
87
88 // get current tick
89 cur_time = _pwrap_get_current_time();//ns
90 if(cur_time < start_time_ns){
91 PWRAPERR("@@@@Timer overflow! start%lld cur timer%lld\n",start_time_ns,cur_time);
92 start_time_ns=cur_time;
93 timeout_time_ns=255*1000; //255us
94 PWRAPERR("@@@@reset timer! start%lld setting%lld\n",start_time_ns,timeout_time_ns);
95 }
96 elapse_time=cur_time-start_time_ns;
97
98 // check if timeout
99 if (timeout_time_ns <= elapse_time)
100 {
101 // timeout
102 return TRUE;
103 }
104 return FALSE;
105 }
106 static U64 _pwrap_time2ns (U64 time_us)
107 {
108 return time_us*1000;
109 }
110
111 #else
112 static U64 _pwrap_get_current_time(void)
113 {
114 return 0;
115 }
116 static BOOL _pwrap_timeout_ns (U64 start_time_ns, U64 elapse_time)//,U64 timeout_ns)
117 {
118 return FALSE;
119 }
120 static U64 _pwrap_time2ns (U64 time_us)
121 {
122 return 0;
123 }
124
125 #endif
126 //#####################################################################
127 //define macro and inline function (for do while loop)
128 //#####################################################################
129 typedef U32 (*loop_condition_fp)(U32);//define a function pointer
130
131 static inline U32 wait_for_fsm_idle(U32 x)
132 {
133 return (GET_WACS0_FSM( x ) != WACS_FSM_IDLE );
134 }
135 static inline U32 wait_for_fsm_vldclr(U32 x)
136 {
137 return (GET_WACS0_FSM( x ) != WACS_FSM_WFVLDCLR);
138 }
139 static inline U32 wait_for_sync(U32 x)
140 {
141 return (GET_SYNC_IDLE0(x) != WACS_SYNC_IDLE);
142 }
143 static inline U32 wait_for_idle_and_sync(U32 x)
144 {
145 return ((GET_WACS0_FSM(x) != WACS_FSM_IDLE) || (GET_SYNC_IDLE0(x) != WACS_SYNC_IDLE)) ;
146 }
147 static inline U32 wait_for_wrap_idle(U32 x)
148 {
149 return ((GET_WRAP_FSM(x) != 0x0) || (GET_WRAP_CH_DLE_RESTCNT(x) != 0x0));
150 }
151 static inline U32 wait_for_wrap_state_idle(U32 x)
152 {
153 return ( GET_WRAP_AG_DLE_RESTCNT( x ) != 0 ) ;
154 }
155 static inline U32 wait_for_man_idle_and_noreq(U32 x)
156 {
157 return ( (GET_MAN_REQ(x) != MAN_FSM_NO_REQ ) || (GET_MAN_FSM(x) != MAN_FSM_IDLE) );
158 }
159 static inline U32 wait_for_man_vldclr(U32 x)
160 {
161 return (GET_MAN_FSM( x ) != MAN_FSM_WFVLDCLR) ;
162 }
163 static inline U32 wait_for_cipher_ready(U32 x)
164 {
165 return (x!=3) ;
166 }
167 static inline U32 wait_for_stdupd_idle(U32 x)
168 {
169 return ( GET_STAUPD_FSM(x) != 0x0) ;
170 }
171
172 static inline U32 wait_for_state_ready_init(loop_condition_fp fp,U32 timeout_us,U32 wacs_register,U32 *read_reg)
173 {
174
175 U64 start_time_ns=0, timeout_ns=0;
176 U32 reg_rdata=0x0;
177 start_time_ns = _pwrap_get_current_time();
178 timeout_ns = _pwrap_time2ns(timeout_us);
179 do
180 {
181 if (_pwrap_timeout_ns(start_time_ns, timeout_ns))
182 {
183 PWRAPERR("wait_for_state_ready_init timeout when waiting for idle\n");
184 return E_PWR_WAIT_IDLE_TIMEOUT;
185 }
186 reg_rdata = WRAP_RD32(wacs_register);
187 } while( fp(reg_rdata)); //IDLE State
188 if(read_reg)
189 *read_reg=reg_rdata;
190 return 0;
191 }
192
193 static inline U32 wait_for_state_idle_init(loop_condition_fp fp,U32 timeout_us,U32 wacs_register,U32 wacs_vldclr_register,U32 *read_reg)
194 {
195
196 U64 start_time_ns=0, timeout_ns=0;
197 U32 reg_rdata;
198 start_time_ns = _pwrap_get_current_time();
199 timeout_ns = _pwrap_time2ns(timeout_us);
200 do
201 {
202 if (_pwrap_timeout_ns(start_time_ns, timeout_ns))
203 {
204 PWRAPERR("wait_for_state_idle_init timeout when waiting for idle\n");
205 pwrap_dump_ap_register();
206 //pwrap_trace_wacs2();
207 //BUG_ON(1);
208 return E_PWR_WAIT_IDLE_TIMEOUT;
209 }
210 reg_rdata = WRAP_RD32(wacs_register);
211 //if last read command timeout,clear vldclr bit
212 //read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;write:FSM_REQ-->idle
213 switch ( GET_WACS0_FSM( reg_rdata ) )
214 {
215 case WACS_FSM_WFVLDCLR:
216 WRAP_WR32(wacs_vldclr_register , 1);
217 PWRAPERR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
218 break;
219 case WACS_FSM_WFDLE:
220 PWRAPERR("WACS_FSM = WACS_FSM_WFDLE\n");
221 break;
222 case WACS_FSM_REQ:
223 PWRAPERR("WACS_FSM = WACS_FSM_REQ\n");
224 break;
225 default:
226 break;
227 }
228 }while( fp(reg_rdata)); //IDLE State
229 if(read_reg)
230 *read_reg=reg_rdata;
231 return 0;
232 }
233 static inline U32 wait_for_state_idle(loop_condition_fp fp,U32 timeout_us,U32 wacs_register,U32 wacs_vldclr_register,U32 *read_reg)
234 {
235
236 U64 start_time_ns=0, timeout_ns=0;
237 U32 reg_rdata;
238 start_time_ns = _pwrap_get_current_time();
239 timeout_ns = _pwrap_time2ns(timeout_us);
240 do
241 {
242 if (_pwrap_timeout_ns(start_time_ns, timeout_ns))
243 {
244 PWRAPERR("wait_for_state_idle timeout when waiting for idle\n");
245 pwrap_dump_ap_register();
246 //pwrap_trace_wacs2();
247 //BUG_ON(1);
248 return E_PWR_WAIT_IDLE_TIMEOUT;
249 }
250 reg_rdata = WRAP_RD32(wacs_register);
251 if( GET_INIT_DONE0( reg_rdata ) != WACS_INIT_DONE)
252 {
253 PWRAPERR("initialization isn't finished \n");
254 return E_PWR_NOT_INIT_DONE;
255 }
256 //if last read command timeout,clear vldclr bit
257 //read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;write:FSM_REQ-->idle
258 switch ( GET_WACS0_FSM( reg_rdata ) )
259 {
260 case WACS_FSM_WFVLDCLR:
261 WRAP_WR32(wacs_vldclr_register , 1);
262 PWRAPERR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
263 break;
264 case WACS_FSM_WFDLE:
265 PWRAPERR("WACS_FSM = WACS_FSM_WFDLE\n");
266 break;
267 case WACS_FSM_REQ:
268 PWRAPERR("WACS_FSM = WACS_FSM_REQ\n");
269 break;
270 default:
271 break;
272 }
273 }while( fp(reg_rdata)); //IDLE State
274 if(read_reg)
275 *read_reg=reg_rdata;
276 return 0;
277 }
278
279 static inline U32 wait_for_state_ready(loop_condition_fp fp,U32 timeout_us,U32 wacs_register,U32 *read_reg)
280 {
281
282 U64 start_time_ns=0, timeout_ns=0;
283 U32 reg_rdata;
284 start_time_ns = _pwrap_get_current_time();
285 timeout_ns = _pwrap_time2ns(timeout_us);
286 do
287 {
288 if (_pwrap_timeout_ns(start_time_ns, timeout_ns))
289 {
290 PWRAPERR("timeout when waiting for idle\n");
291 pwrap_dump_ap_register();
292 //pwrap_trace_wacs2();
293 return E_PWR_WAIT_IDLE_TIMEOUT;
294 }
295 reg_rdata = WRAP_RD32(wacs_register);
296
297 if( GET_INIT_DONE0( reg_rdata ) != WACS_INIT_DONE)
298 {
299 PWRAPERR("initialization isn't finished \n");
300 return E_PWR_NOT_INIT_DONE;
301 }
302 } while( fp(reg_rdata)); //IDLE State
303 if(read_reg)
304 *read_reg=reg_rdata;
305 return 0;
306 }
307 /********************************************************************************************/
308 //extern API for PMIC driver, INT related control, this INT is for PMIC chip to AP (72~92 no need this)
309 /********************************************************************************************/
310 U32 mt_pmic_wrap_eint_status(void)
311 {
312 return 0;
313 }
314
315 void mt_pmic_wrap_eint_clr(int offset)
316 {
317
318 }
319
320 //--------------------------------------------------------
321 // Function : pwrap_wacs2_hal()
322 // Description :
323 // Parameter :
324 // Return :
325 //--------------------------------------------------------
326 static S32 pwrap_wacs2_hal( U32 write, U32 adr, U32 wdata, U32 *rdata )
327 {
328 //U64 wrap_access_time=0x0;
329 U32 reg_rdata=0;
330 U32 wacs_write=0;
331 U32 wacs_adr=0;
332 U32 wacs_cmd=0;
333 U32 return_value=0;
334 unsigned long flags=0;
335 //PWRAPFUC();
336 //#ifndef CONFIG_MTK_LDVT_PMIC_WRAP
337 //PWRAPLOG("wrapper access,write=%x,add=%x,wdata=%x,rdata=%x\n",write,adr,wdata,rdata);
338 //#endif
339 // Check argument validation
340 if( (write & ~(0x1)) != 0) return E_PWR_INVALID_RW;
341 if( (adr & ~(0xffff)) != 0) return E_PWR_INVALID_ADDR;
342 if( (wdata & ~(0xffff)) != 0) return E_PWR_INVALID_WDAT;
343
344 spin_lock_irqsave(&wrp_lock,flags);
345 // Check IDLE & INIT_DONE in advance
346 return_value=wait_for_state_idle(wait_for_fsm_idle,TIMEOUT_WAIT_IDLE,PMIC_WRAP_WACS2_RDATA,PMIC_WRAP_WACS2_VLDCLR,0);
347 if(return_value!=0)
348 {
349 PWRAPERR("wait_for_fsm_idle fail,return_value=%d\n",return_value);
350 goto FAIL;
351 }
352 wacs_write = write << 31;
353 wacs_adr = (adr >> 1) << 16;
354 wacs_cmd= wacs_write | wacs_adr | wdata;
355
356 WRAP_WR32(PMIC_WRAP_WACS2_CMD,wacs_cmd);
357 if( write == 0 )
358 {
359 if (NULL == rdata)
360 {
361 PWRAPERR("rdata is a NULL pointer\n");
362 return_value= E_PWR_INVALID_ARG;
363 goto FAIL;
364 }
365 return_value=wait_for_state_ready(wait_for_fsm_vldclr,TIMEOUT_READ,PMIC_WRAP_WACS2_RDATA,&reg_rdata);
366 if(return_value!=0)
367 {
368 PWRAPERR("wait_for_fsm_vldclr fail,return_value=%d\n",return_value);
369 return_value+=1;//E_PWR_NOT_INIT_DONE_READ or E_PWR_WAIT_IDLE_TIMEOUT_READ
370 goto FAIL;
371 }
372 *rdata = GET_WACS0_RDATA( reg_rdata );
373 WRAP_WR32(PMIC_WRAP_WACS2_VLDCLR , 1);
374 }
375 FAIL:
376 spin_unlock_irqrestore(&wrp_lock,flags);
377 if(return_value!=0)
378 {
379 PWRAPERR("pwrap_wacs2_hal fail,return_value=%d\n",return_value);
380 PWRAPERR("timeout:BUG_ON here\n");
381 //BUG_ON(1);
382 }
383 //wrap_access_time=sched_clock();
384 //pwrap_trace(wrap_access_time,return_value,write, adr, wdata,(U32)rdata);
385 return return_value;
386 }
387
388 //S32 pwrap_wacs2( U32 write, U32 adr, U32 wdata, U32 *rdata )
389 //{
390 // return pwrap_wacs2_hal(write, adr,wdata,rdata );
391 //}
392 //EXPORT_SYMBOL(pwrap_wacs2);
393 //S32 pwrap_read( U32 adr, U32 *rdata )
394 //{
395 // return pwrap_wacs2( PWRAP_READ, adr,0,rdata );
396 //}
397 //EXPORT_SYMBOL(pwrap_read);
398 //
399 //S32 pwrap_write( U32 adr, U32 wdata )
400 //{
401 // return pwrap_wacs2( PWRAP_WRITE, adr,wdata,0 );
402 //}
403 //EXPORT_SYMBOL(pwrap_write);
404 //******************************************************************************
405 //--internal API for pwrap_init-------------------------------------------------
406 //******************************************************************************
407 //--------------------------------------------------------
408 // Function : _pwrap_wacs2_nochk()
409 // Description :
410 // Parameter :
411 // Return :
412 //--------------------------------------------------------
413
414 //static S32 pwrap_read_nochk( U32 adr, U32 *rdata )
415 static S32 pwrap_read_nochk( U32 adr, U32 *rdata )
416 {
417 return _pwrap_wacs2_nochk( 0, adr, 0, rdata );
418 }
419
420 static S32 pwrap_write_nochk( U32 adr, U32 wdata )
421 {
422 return _pwrap_wacs2_nochk( 1, adr,wdata,0 );
423 }
424
425 static S32 _pwrap_wacs2_nochk( U32 write, U32 adr, U32 wdata, U32 *rdata )
426 {
427 U32 reg_rdata=0x0;
428 U32 wacs_write=0x0;
429 U32 wacs_adr=0x0;
430 U32 wacs_cmd=0x0;
431 U32 return_value=0x0;
432 //PWRAPFUC();
433 // Check argument validation
434 if( (write & ~(0x1)) != 0) return E_PWR_INVALID_RW;
435 if( (adr & ~(0xffff)) != 0) return E_PWR_INVALID_ADDR;
436 if( (wdata & ~(0xffff)) != 0) return E_PWR_INVALID_WDAT;
437
438 // Check IDLE
439 return_value=wait_for_state_ready_init(wait_for_fsm_idle,TIMEOUT_WAIT_IDLE,PMIC_WRAP_WACS2_RDATA,0);
440 if(return_value!=0)
441 {
442 PWRAPERR("_pwrap_wacs2_nochk write command fail,return_value=%x\n", return_value);
443 return return_value;
444 }
445
446 wacs_write = write << 31;
447 wacs_adr = (adr >> 1) << 16;
448 wacs_cmd = wacs_write | wacs_adr | wdata;
449 WRAP_WR32(PMIC_WRAP_WACS2_CMD,wacs_cmd);
450
451 if( write == 0 )
452 {
453 if (NULL == rdata)
454 return E_PWR_INVALID_ARG;
455 // wait for read data ready
456 return_value=wait_for_state_ready_init(wait_for_fsm_vldclr,TIMEOUT_WAIT_IDLE,PMIC_WRAP_WACS2_RDATA,&reg_rdata);
457 if(return_value!=0)
458 {
459 PWRAPERR("_pwrap_wacs2_nochk read fail,return_value=%x\n", return_value);
460 return return_value;
461 }
462 *rdata = GET_WACS0_RDATA( reg_rdata );
463 WRAP_WR32(PMIC_WRAP_WACS2_VLDCLR , 1);
464 }
465 return 0;
466 }
467 //--------------------------------------------------------
468 // Function : _pwrap_init_dio()
469 // Description :call it in pwrap_init,mustn't check init done
470 // Parameter :
471 // Return :
472 //--------------------------------------------------------
473 static S32 _pwrap_init_dio( U32 dio_en )
474 {
475 U32 arb_en_backup=0x0;
476 U32 rdata=0x0;
477 U32 return_value=0;
478
479 //PWRAPFUC();
480 arb_en_backup = WRAP_RD32(PMIC_WRAP_HIPRIO_ARB_EN);
481 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN ,WACS2 ); // only WACS2
482 pwrap_write_nochk(DEW_DIO_EN, dio_en);
483
484 // Check IDLE & INIT_DONE in advance
485 return_value=wait_for_state_ready_init(wait_for_idle_and_sync,TIMEOUT_WAIT_IDLE,PMIC_WRAP_WACS2_RDATA,0);
486 if(return_value!=0)
487 {
488 PWRAPERR("_pwrap_init_dio fail,return_value=%x\n", return_value);
489 return return_value;
490 }
491 WRAP_WR32(PMIC_WRAP_DIO_EN , dio_en);
492 // Read Test
493 pwrap_read_nochk(DEW_READ_TEST,&rdata);
494 if( rdata != DEFAULT_VALUE_READ_TEST )
495 {
496 PWRAPERR("[Dio_mode][Read Test] fail,dio_en = %x, READ_TEST rdata=%x, exp=0x5aa5\n", dio_en, rdata);
497 return E_PWR_READ_TEST_FAIL;
498 }
499 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN , arb_en_backup);
500 return 0;
501 }
502
503 //--------------------------------------------------------
504 // Function : _pwrap_init_cipher()
505 // Description :
506 // Parameter :
507 // Return :
508 //--------------------------------------------------------
509 static S32 _pwrap_init_cipher( void )
510 {
511 U32 arb_en_backup=0;
512 U32 rdata=0;
513 U32 return_value=0;
514 U32 start_time_ns=0, timeout_ns=0;
515 //PWRAPFUC();
516 arb_en_backup = WRAP_RD32(PMIC_WRAP_HIPRIO_ARB_EN);
517
518 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN ,WACS2); // only WACS2
519
520 WRAP_WR32(PMIC_WRAP_CIPHER_SWRST , 1);
521 WRAP_WR32(PMIC_WRAP_CIPHER_SWRST , 0);
522 WRAP_WR32(PMIC_WRAP_CIPHER_KEY_SEL , 1);
523 WRAP_WR32(PMIC_WRAP_CIPHER_IV_SEL , 2);
524 WRAP_WR32(PMIC_WRAP_CIPHER_EN , 1);
525
526 //Config CIPHER @ PMIC
527 pwrap_write_nochk(DEW_CIPHER_SWRST, 0x1);
528 pwrap_write_nochk(DEW_CIPHER_SWRST, 0x0);
529 pwrap_write_nochk(DEW_CIPHER_KEY_SEL, 0x1);
530 pwrap_write_nochk(DEW_CIPHER_IV_SEL, 0x2);
531 #ifdef SLV_6397
532 pwrap_write_nochk(DEW_CIPHER_LOAD, 0x1);
533 pwrap_write_nochk(DEW_CIPHER_START, 0x1);
534 #elif defined SLV_6323
535 pwrap_write_nochk(DEW_CIPHER_EN, 0x1);
536 #endif
537
538 //wait for cipher data ready@AP
539 return_value=wait_for_state_ready_init(wait_for_cipher_ready,TIMEOUT_WAIT_IDLE,PMIC_WRAP_CIPHER_RDY,0);
540 if(return_value!=0)
541 {
542 PWRAPERR("wait for cipher data ready@AP fail,return_value=%x\n", return_value);
543 return return_value;
544 }
545
546 //wait for cipher data ready@PMIC
547 start_time_ns = _pwrap_get_current_time();
548 timeout_ns = _pwrap_time2ns(0xFFFFFF);
549 do
550 {
551 pwrap_read_nochk(DEW_CIPHER_RDY,&rdata);
552 if (_pwrap_timeout_ns(start_time_ns, timeout_ns))
553 {
554 PWRAPERR("wait for cipher data ready@PMIC\n");
555 //return E_PWR_WAIT_IDLE_TIMEOUT;
556 }
557 } while( rdata != 0x1 ); //cipher_ready
558
559 pwrap_write_nochk(DEW_CIPHER_MODE, 0x1);
560 //wait for cipher mode idle
561 return_value=wait_for_state_ready_init(wait_for_idle_and_sync,TIMEOUT_WAIT_IDLE,PMIC_WRAP_WACS2_RDATA,0);
562 if(return_value!=0)
563 {
564 PWRAPERR("wait for cipher mode idle fail,return_value=%x\n", return_value);
565 return return_value;
566 }
567 WRAP_WR32(PMIC_WRAP_CIPHER_MODE , 1);
568
569 // Read Test
570 pwrap_read_nochk(DEW_READ_TEST,&rdata);
571 if( rdata != DEFAULT_VALUE_READ_TEST )
572 {
573 PWRAPERR("_pwrap_init_cipher,read test error,error code=%x, rdata=%x\n", 1, rdata);
574 return E_PWR_READ_TEST_FAIL;
575 }
576 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN , arb_en_backup);
577 return 0;
578 }
579
580 //--------------------------------------------------------
581 // Function : _pwrap_init_sistrobe()
582 // Description : Initialize SI_CK_CON and SIDLY
583 // Parameter :
584 // Return :
585 //--------------------------------------------------------
586 static S32 _pwrap_init_sistrobe( void )
587 {
588 U32 arb_en_backup;
589 U32 rdata;
590 S32 ind, tmp1, tmp2;
591 U32 result;
592 U32 result_faulty;
593 U32 leading_one, tailing_one;
594
595 arb_en_backup = WRAP_RD32(PMIC_WRAP_HIPRIO_ARB_EN);
596
597 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN ,WACS2); // only WACS2
598
599 //---------------------------------------------------------------------
600 // Scan all possible input strobe by READ_TEST
601 //---------------------------------------------------------------------
602 result = 0;
603 result_faulty = 0;
604 for( ind=0; ind<24; ind++) // 24 sampling clock edge
605 {
606 WRAP_WR32(PMIC_WRAP_SI_CK_CON , (ind >> 2) & 0x7);
607 WRAP_WR32(PMIC_WRAP_SIDLY ,0x3 - (ind & 0x3));
608 _pwrap_wacs2_nochk(0, DEW_READ_TEST, 0, &rdata);
609 if( rdata == DEFAULT_VALUE_READ_TEST )
610 {
611 PWRAPLOG("_pwrap_init_sistrobe [Read Test] pass,index=%d rdata=%x\n", ind,rdata);
612 result |= (0x1 << ind);
613 }
614 else
615 PWRAPLOG("_pwrap_init_sistrobe [Read Test] fail,index=%d,rdata=%x\n", ind,rdata);
616 }
617
618 //---------------------------------------------------------------------
619 // Locate the leading one and trailing one
620 //---------------------------------------------------------------------
621 for( ind=23 ; ind>=0 ; ind-- )
622 {
623 if( result & (0x1 << ind) ) break;
624 }
625 leading_one = ind;
626
627 for( ind=0 ; ind<24 ; ind++ )
628 {
629 if( result & (0x1 << ind) ) break;
630 }
631 tailing_one = ind;
632
633 //---------------------------------------------------------------------
634 // Check the continuity of pass range
635 //---------------------------------------------------------------------
636 tmp1 = (0x1 << (leading_one+1)) - 1;
637 tmp2 = (0x1 << tailing_one) - 1;
638 if( (tmp1 - tmp2) != result )
639 {
640 /*TERR = "[DrvPWRAP_InitSiStrobe] Fail, tmp1:%d, tmp2:%d", tmp1, tmp2*/
641 PWRAPERR("_pwrap_init_sistrobe Fail,tmp1=%x,tmp2=%x\n", tmp1,tmp2);
642 result_faulty = 0x1;
643 }
644 //---------------------------------------------------------------------
645 // Config SICK and SIDLY to the middle point of pass range
646 //---------------------------------------------------------------------
647 ind = (leading_one + tailing_one)/2;
648 WRAP_WR32(PMIC_WRAP_SI_CK_CON , (ind >> 2) & 0x7);
649 WRAP_WR32(PMIC_WRAP_SIDLY , 0x3 - (ind & 0x3));
650
651 //---------------------------------------------------------------------
652 // Restore
653 //---------------------------------------------------------------------
654 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN , arb_en_backup);
655 if( result_faulty == 0 )
656 return 0;
657 else
658 {
659 /*TERR = "[DrvPWRAP_InitSiStrobe] Fail, result = %x", result*/
660 PWRAPERR("_pwrap_init_sistrobe Fail,result=%x\n", result);
661 return result_faulty;
662 }
663 }
664
665 //--------------------------------------------------------
666 // Function : _pwrap_reset_spislv()
667 // Description :
668 // Parameter :
669 // Return :
670 //--------------------------------------------------------
671
672 static S32 _pwrap_reset_spislv( void )
673 {
674 U32 ret=0;
675 U32 return_value=0;
676 //PWRAPFUC();
677 // This driver does not using _pwrap_switch_mux
678 // because the remaining requests are expected to fail anyway
679
680 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN , DISABLE_ALL);
681 WRAP_WR32(PMIC_WRAP_WRAP_EN , DISABLE);
682 WRAP_WR32(PMIC_WRAP_MUX_SEL , MANUAL_MODE);
683 WRAP_WR32(PMIC_WRAP_MAN_EN ,ENABLE);
684 WRAP_WR32(PMIC_WRAP_DIO_EN ,DISABLE);
685
686 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_CSL << 8)));
687 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_OUTS << 8))); //to reset counter
688 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_CSH << 8)));
689 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_OUTS << 8)));
690 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_OUTS << 8)));
691 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_OUTS << 8)));
692 WRAP_WR32(PMIC_WRAP_MAN_CMD , (OP_WR << 14) | ((OP_PMIC_SEL << 13)|(OP_OUTS << 8)));
693
694 return_value=wait_for_state_ready_init(wait_for_sync,TIMEOUT_WAIT_IDLE,PMIC_WRAP_WACS2_RDATA,0);
695 if(return_value!=0)
696 {
697 PWRAPERR("_pwrap_reset_spislv fail,return_value=%x\n", return_value);
698 ret=E_PWR_TIMEOUT;
699 goto timeout;
700 }
701
702 WRAP_WR32(PMIC_WRAP_MAN_EN ,DISABLE);
703 WRAP_WR32(PMIC_WRAP_MUX_SEL ,WRAPPER_MODE);
704
705 timeout:
706 WRAP_WR32(PMIC_WRAP_MAN_EN ,DISABLE);
707 WRAP_WR32(PMIC_WRAP_MUX_SEL ,WRAPPER_MODE);
708 return ret;
709 }
710
711 static S32 _pwrap_init_reg_clock( U32 regck_sel )
712 {
713 U32 wdata=0;
714 U32 rdata=0;
715 PWRAPFUC();
716
717 // Set reg clk freq
718 #ifdef SLV_6397
719 pwrap_read_nochk(PMIC_TOP_CKCON2,&rdata);
720 #endif
721
722 #ifdef SLV_6397
723 if( regck_sel == 1 )
724 wdata = (rdata & (~(0x3<<10))) | (0x1<<10);
725 else
726 wdata = rdata & ~(0x3 << 10);
727 #elif defined SLV_6323
728 if( regck_sel == 1 ) return 0x10; // not support in 6323!!
729 else wdata = 0x3;
730 #endif
731
732 #ifdef SLV_6397
733 pwrap_write_nochk(PMIC_TOP_CKCON2, wdata);
734 pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata);
735 #elif defined SLV_6323
736 pwrap_write_nochk(TOP_CKCON1_CLR, wdata);
737 pwrap_read_nochk(TOP_CKCON1, &rdata);
738 #endif
739
740 #ifdef SLV_6397
741 if( rdata != wdata )
742 {
743 PWRAPERR("_pwrap_init_reg_clock,PMIC_TOP_CKCON2 Write [15]=1 Fail, rdata=%x\n",rdata);
744 return E_PWR_WRITE_TEST_FAIL;
745 }
746 #elif defined SLV_6323
747 if( (rdata & 0x3) != 0)
748 {
749 PWRAPERR("_pwrap_init_reg_clock,PMIC_TOP_CKCON2 Write [15]=1 Fail, rdata=%x\n",rdata);
750 return E_PWR_WRITE_TEST_FAIL;
751 }
752 #endif
753
754 // Set Dummy cycle for both 6397(assume 12MHz)/6323 (assume 12MHz)
755 #ifdef SLV_6397
756 WRAP_WR32(PMIC_WRAP_RDDMY ,0xC);
757 #elif defined SLV_6323
758 pwrap_write_nochk(DEW_RDDMY_NO, 0x8);
759 WRAP_WR32(PMIC_WRAP_RDDMY ,0x8);
760 #endif
761
762 // Config SPI Waveform according to reg clk
763 if( regck_sel == 1 )
764 { // 6MHz in 6323 => no support ; // 12MHz in 6397
765 #ifdef SLV_6397
766 WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE , 0x0); // wait data written into register => 3T_PMIC
767 WRAP_WR32(PMIC_WRAP_CSHEXT_READ , 0x4); // for 6320, slave need enough time (4T of PMIC reg_ck) to back idle state
768 WRAP_WR32(PMIC_WRAP_CSLEXT_START , 0x0);
769 WRAP_WR32(PMIC_WRAP_CSLEXT_END , 0x4);
770 #else
771 WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE , 0x4); // wait data written into register => 3T_PMIC
772 WRAP_WR32(PMIC_WRAP_CSHEXT_READ , 0x5); // for 6320, slave need enough time (4T of PMIC reg_ck) to back idle state
773 WRAP_WR32(PMIC_WRAP_CSLEXT_START , 0x0);
774 WRAP_WR32(PMIC_WRAP_CSLEXT_END , 0x0);
775 #endif
776 } else if( regck_sel == 2 )
777 { // 12MHz in 6323; 24MHz in 6397
778 #ifdef SLV_6397
779 WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE , 0x4); // wait data written into register => 3T_PMIC: consists of CSLEXT_END(1T) + CSHEXT(6T)
780 WRAP_WR32(PMIC_WRAP_CSHEXT_READ , 0x0);
781 WRAP_WR32(PMIC_WRAP_CSLEXT_START , 0x2);
782 WRAP_WR32(PMIC_WRAP_CSLEXT_END , 0x2);
783 #else //SLV_6323
784 WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE , 0x5); // wait data written into register => 3T_PMIC: consists of CSLEXT_END(1T) + CSHEXT(6T)
785 WRAP_WR32(PMIC_WRAP_CSHEXT_READ , 0x0);
786 WRAP_WR32(PMIC_WRAP_CSLEXT_START , 0x2);
787 WRAP_WR32(PMIC_WRAP_CSLEXT_END , 0x2);
788 #endif
789 } else
790 { //Safe mode
791 WRAP_WR32(PMIC_WRAP_CSHEXT_WRITE , 0xf);
792 WRAP_WR32(PMIC_WRAP_CSHEXT_READ , 0xf);
793 WRAP_WR32(PMIC_WRAP_CSLEXT_START , 0xf);
794 WRAP_WR32(PMIC_WRAP_CSLEXT_END , 0xf);
795 }
796
797 return 0;
798 }
799
800 //--------------------------------------------------------
801 // Function : DrvPWRAP_Switch_Strobe_Setting()
802 // Description : used to switch input data calibration setting before system sleep or after system wakeup
803 // no use since SPI_CK (26MHz) is always kept unchanged
804 // Parameter :
805 // Return :
806 //--------------------------------------------------------
807 //void DrvPWRAP_Switch_Strobe_Setting (int si_ck_con, int sidly)
808 //{
809 // int reg_rdata;
810 // // turn off spi_wrap
811 // *PMIC_WRAP_WRAP_EN = 0;
812 // // wait for WRAP to be in idle state
813 // // and no remaining rdata to be received
814 // do
815 // {
816 // reg_rdata = *PMIC_WRAP_WRAP_STA;
817 // } while ( (GET_WRAP_FSM(reg_rdata) != 0) ||
818 // (GET_WRAP_CH_DLE_RESTCNT(reg_rdata)) != 0 );
819 //
820 // *PMIC_WRAP_SI_CK_CON = si_ck_con;
821 // *PMIC_WRAP_SIDLY = sidly;
822 //
823 // // turn on spi_wrap
824 // *PMIC_WRAP_WRAP_EN = 1;
825 //}
826
827
828 /*
829 *pmic_wrap init,init wrap interface
830 *
831 */
832 S32 pwrap_init ( void )
833 {
834 S32 sub_return=0;
835 S32 sub_return1=0;
836 //S32 ret=0;
837 U32 rdata=0x0;
838 U32 regValue;
839 //U32 timeout=0;
840 PWRAPFUC();
841 //###############################
842 //toggle PMIC_WRAP and pwrap_spictl reset
843 //###############################
844 PWRAP_SOFT_RESET;
845 regValue=WRAP_RD32(INFRA_GLOBALCON_RST0);
846 PWRAPLOG("the reset register0x%x = %x\n",INFRA_GLOBALCON_RST0,regValue);
847 regValue=WRAP_RD32(PMIC_WRAP_STAUPD_GRPEN);
848 PWRAPLOG("PMIC_WRAP_STAUPD_GRPEN =%x,it should be equal to 0x1\n",regValue);
849 //clear reset bit
850 PWRAP_CLEAR_SOFT_RESET_BIT;
851
852 //###############################
853 // Set SPI_CK_freq = 26MHz for both 6320/6323/6397
854 //###############################
855 WRAP_WR32(CLK_CFG_4_CLR,CLK_SPI_CK_26M);
856
857 //###############################
858 //toggle PERI_PWRAP_BRIDGE reset
859 //###############################
860 //WRAP_SET_BIT(0x04,PERI_GLOBALCON_RST1);
861 //WRAP_CLR_BIT(0x04,PERI_GLOBALCON_RST1);
862
863 //###############################
864 //Enable DCM
865 //###############################
866 WRAP_WR32(PMIC_WRAP_DCM_EN , ENABLE);
867 WRAP_WR32(PMIC_WRAP_DCM_DBC_PRD ,DISABLE);
868 //###############################
869 //Enable 6320 option
870 //###############################
871 #ifdef SLV_6323
872 WRAP_WR32(PMIC_WRAP_OP_TYPE ,OP_TYPE_CK);
873 WRAP_WR32(PMIC_WRAP_MSB_FIRST , MSB);
874 #endif
875
876 //###############################
877 //Reset SPISLV
878 //###############################
879 sub_return=_pwrap_reset_spislv();
880 if( sub_return != 0 )
881 {
882 PWRAPERR("error,_pwrap_reset_spislv fail,sub_return=%x\n",sub_return);
883 return E_PWR_INIT_RESET_SPI;
884 }
885 //###############################
886 // Enable WACS2
887 //###############################
888 WRAP_WR32(PMIC_WRAP_WRAP_EN,ENABLE);//enable wrap
889 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN,WACS2); //Only WACS2
890 WRAP_WR32(PMIC_WRAP_WACS2_EN,ENABLE);
891 //###############################
892 // Set Dummy cycle to make the cycle is the same at both AP and PMIC sides
893 //###############################
894 // (default value of 6320 dummy cycle is already 0x8)
895 #ifdef SLV_6323
896 WRAP_WR32(PMIC_WRAP_RDDMY , 0xF);
897 #endif
898
899 //###############################
900 // Input data calibration flow;
901 //###############################
902 sub_return = _pwrap_init_sistrobe();
903 if( sub_return != 0 )
904 {
905 PWRAPERR("error,DrvPWRAP_InitSiStrobe fail,sub_return=%x\n",sub_return);
906 return E_PWR_INIT_SIDLY;
907 }
908
909 //###############################
910 // SPI Waveform Configuration
911 //###############################
912 //6397; 0:safe mode, 1:12MHz, 2:24MHz
913 //6323; 0:safe mode, 1:NA, 2:12MHz
914 sub_return = _pwrap_init_reg_clock(2);
915 if( sub_return != 0)
916 {
917 PWRAPERR("error,_pwrap_init_reg_clock fail,sub_return=%x\n",sub_return);
918 return E_PWR_INIT_REG_CLOCK;
919 }
920
921 //###############################
922 // Enable PMIC dewrapper (only for 6320)
923 // (May not be necessary, depending on S/W partition)
924 //###############################
925 #ifdef SLV_6397
926 sub_return= pwrap_write_nochk(PMIC_WRP_CKPDN, 0);//set dewrap clock bit
927 sub_return1=pwrap_write_nochk(PMIC_WRP_RST_CON, 0);//clear dewrap reset bit
928 if(( sub_return != 0 )||( sub_return1 != 0 ))
929 {
930 PWRAPERR("Enable PMIC fail, sub_return=%x sub_return1=%x\n", sub_return,sub_return1);
931 return E_PWR_INIT_ENABLE_PMIC;
932 }
933 #endif
934
935 //###############################
936 // Enable DIO mode
937 //###############################
938 sub_return = _pwrap_init_dio(ENABLE);
939 if( sub_return != 0 )
940 {
941 PWRAPERR("_pwrap_init_dio test error,error code=%x, sub_return=%x\n", 0x11, sub_return);
942 return E_PWR_INIT_DIO;
943 }
944
945 //###############################
946 // Enable Encryption
947 //###############################
948 sub_return = _pwrap_init_cipher();
949 if( sub_return != 0 )
950 {
951 PWRAPERR("Enable Encryption fail, return=%x\n", sub_return);
952 return E_PWR_INIT_CIPHER;
953 }
954
955 //###############################
956 // Write test using WACS2
957 //###############################
958 sub_return = pwrap_write_nochk(DEW_WRITE_TEST, WRITE_TEST_VALUE);
959 sub_return1 = pwrap_read_nochk(DEW_WRITE_TEST,&rdata);
960 if(( rdata != WRITE_TEST_VALUE )||( sub_return != 0 )||( sub_return1 != 0 ))
961 {
962 PWRAPERR("write test error,rdata=0x%x,exp=0xa55a,sub_return=0x%x,sub_return1=0x%x\n", rdata,sub_return,sub_return1);
963 return E_PWR_INIT_WRITE_TEST;
964 }
965
966 //###############################
967 // Signature Checking - Using Write Test Register
968 // should be the last to modify WRITE_TEST
969 //###############################
970 //_pwrap_wacs2_nochk(1, DEW_WRITE_TEST, 0x5678, &rdata);
971 //WRAP_WR32(PMIC_WRAP_SIG_ADR,DEW_WRITE_TEST);
972 //WRAP_WR32(PMIC_WRAP_SIG_VALUE,0x5678);
973 //WRAP_WR32(PMIC_WRAP_SIG_MODE, 0x1);
974
975 //###############################
976 // Signature Checking - Using CRC
977 // should be the last to modify WRITE_TEST
978 //###############################
979 sub_return=pwrap_write_nochk(DEW_CRC_EN,ENABLE);
980 if( sub_return != 0 )
981 {
982 PWRAPERR("enable CRC fail,sub_return=%x\n", sub_return);
983 return E_PWR_INIT_ENABLE_CRC;
984 }
985 WRAP_WR32(PMIC_WRAP_CRC_EN ,ENABLE);
986 WRAP_WR32(PMIC_WRAP_SIG_MODE, CHECK_CRC);
987 WRAP_WR32(PMIC_WRAP_SIG_ADR , DEW_CRC_VAL);
988
989
990 //###############################
991 // PMIC_WRAP enables
992 //###############################
993 WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN,0x1ff);
994 //WRAP_WR32(PMIC_WRAP_RRARB_EN ,0x7);
995 WRAP_WR32(PMIC_WRAP_WACS0_EN,ENABLE);
996 WRAP_WR32(PMIC_WRAP_WACS1_EN,ENABLE);
997 //WRAP_WR32(PMIC_WRAP_WACS2_EN,0x1);//already enabled
998 // WRAP_WR32(PMIC_WRAP_EVENT_IN_EN,0x1);
999 //WRAP_WR32(PMIC_WRAP_EVENT_DST_EN,0xffff);
1000 WRAP_WR32(PMIC_WRAP_STAUPD_PRD, 0x5); //0x1:20us,for concurrence test,MP:0x5; //100us
1001 WRAP_WR32(PMIC_WRAP_STAUPD_GRPEN,0xff);
1002 WRAP_WR32(PMIC_WRAP_WDT_UNIT,0xf);
1003 WRAP_WR32(PMIC_WRAP_WDT_SRC_EN,0xffffffff);
1004 WRAP_WR32(PMIC_WRAP_TIMER_EN,0x1);
1005 WRAP_WR32(PMIC_WRAP_INT_EN,0x7ffffffb); //except for [31] debug_int
1006
1007
1008 //###############################
1009 // GPS_INTF initialization
1010 //###############################
1011 #ifdef SLV_6323
1012 WRAP_WR32(PMIC_WRAP_ADC_CMD_ADDR , AUXADC_CON21);
1013 WRAP_WR32(PMIC_WRAP_PWRAP_ADC_CMD , 0x8000);
1014 WRAP_WR32(PMIC_WRAP_ADC_RDY_ADDR , AUXADC_ADC12);
1015 WRAP_WR32(PMIC_WRAP_ADC_RDATA_ADDR1 , AUXADC_ADC13);
1016 WRAP_WR32(PMIC_WRAP_ADC_RDATA_ADDR2 , AUXADC_ADC14);
1017 #endif
1018
1019 //###############################
1020 // Initialization Done
1021 //###############################
1022 WRAP_WR32(PMIC_WRAP_INIT_DONE2 , 0x1);
1023
1024 //###############################
1025 //TBD: Should be configured by MD MCU
1026 //###############################
1027 #if 1 //CONFIG_MTK_LDVT_PMIC_WRAP
1028 WRAP_WR32(PMIC_WRAP_INIT_DONE0 ,1);
1029 WRAP_WR32(PMIC_WRAP_INIT_DONE1 , 1);
1030 //WRAP_WR32(PERI_PWRAP_BRIDGE_INIT_DONE3 , 1);
1031 //WRAP_WR32(PERI_PWRAP_BRIDGE_INIT_DONE4 , 1);
1032 #endif
1033 return 0;
1034 }
1035 //EXPORT_SYMBOL(pwrap_init);
1036
1037 /*Interrupt handler function*/
1038 static irqreturn_t mt_pmic_wrap_irq(int irqno, void *dev_id)
1039 {
1040 unsigned long flags=0;
1041
1042 PWRAPFUC();
1043 PWRAPREG("dump pwrap register\n");
1044 spin_lock_irqsave(&wrp_lock,flags);
1045 //*-----------------------------------------------------------------------
1046 pwrap_dump_all_register();
1047 //raise the priority of WACS2 for AP
1048 WRAP_WR32(PMIC_WRAP_HARB_HPRIO,1<<2);
1049
1050 //*-----------------------------------------------------------------------
1051 //clear interrupt flag
1052 WRAP_WR32(PMIC_WRAP_INT_CLR, 0xffffffff);
1053 BUG_ON(1);
1054 spin_unlock_irqrestore(&wrp_lock,flags);
1055 return IRQ_HANDLED;
1056 }
1057
1058 static U32 pwrap_read_test(void)
1059 {
1060 U32 rdata=0;
1061 U32 return_value=0;
1062 // Read Test
1063 return_value=pwrap_read(DEW_READ_TEST,&rdata);
1064 if( rdata != DEFAULT_VALUE_READ_TEST )
1065 {
1066 PWRAPREG("Read Test fail,rdata=0x%x, exp=0x5aa5,return_value=0x%x\n", rdata,return_value);
1067 return E_PWR_READ_TEST_FAIL;
1068 }
1069 else
1070 {
1071 PWRAPREG("Read Test pass,return_value=%d\n",return_value);
1072 return 0;
1073 }
1074 }
1075 static U32 pwrap_write_test(void)
1076 {
1077 U32 rdata=0;
1078 U32 sub_return=0;
1079 U32 sub_return1=0;
1080 //###############################
1081 // Write test using WACS2
1082 //###############################
1083 sub_return = pwrap_write(DEW_WRITE_TEST, WRITE_TEST_VALUE);
1084 PWRAPREG("after pwrap_write\n");
1085 sub_return1 = pwrap_read(DEW_WRITE_TEST,&rdata);
1086 if(( rdata != WRITE_TEST_VALUE )||( sub_return != 0 )||( sub_return1 != 0 ))
1087 {
1088 PWRAPREG("write test error,rdata=0x%x,exp=0xa55a,sub_return=0x%x,sub_return1=0x%x\n", rdata,sub_return,sub_return1);
1089 return E_PWR_INIT_WRITE_TEST;
1090 }
1091 else
1092 {
1093 PWRAPREG("write Test pass\n");
1094 return 0;
1095 }
1096 }
1097
1098 static void pwrap_ut(U32 ut_test)
1099 {
1100 switch(ut_test)
1101 {
1102 case 1:
1103 //pwrap_wacs2_para_test();
1104 break;
1105 case 2:
1106 //pwrap_wacs2_para_test();
1107 break;
1108
1109 default:
1110 PWRAPREG ( "default test.\n" );
1111 break;
1112 }
1113 return;
1114 }
1115 /*---------------------------------------------------------------------------*/
1116 static S32 mt_pwrap_show_hal(char *buf)
1117 {
1118 PWRAPFUC();
1119 return snprintf(buf, PAGE_SIZE, "%s\n","no implement" );
1120 }
1121 /*---------------------------------------------------------------------------*/
1122 static S32 mt_pwrap_store_hal(const char *buf,size_t count)
1123 {
1124 U32 reg_value=0;
1125 U32 reg_addr=0;
1126 U32 return_value=0;
1127 U32 ut_test=0;
1128 if(!strncmp(buf, "-h", 2))
1129 {
1130 PWRAPREG("PWRAP debug: [-dump_reg][-trace_wacs2][-init][-rdap][-wrap][-rdpmic][-wrpmic][-readtest][-writetest]\n");
1131 PWRAPREG("PWRAP UT: [1][2]\n");
1132 }
1133 //--------------------------------------pwrap debug-------------------------------------------------------------
1134 else if(!strncmp(buf, "-dump_reg", 9))
1135 {
1136 pwrap_dump_all_register();
1137 }
1138 else if(!strncmp(buf, "-trace_wacs2", 12))
1139 {
1140 //pwrap_trace_wacs2();
1141 }
1142 else if(!strncmp(buf, "-init", 5))
1143 {
1144 return_value=pwrap_init();
1145 if(return_value==0)
1146 PWRAPREG("pwrap_init pass,return_value=%d\n",return_value);
1147 else
1148 PWRAPREG("pwrap_init fail,return_value=%d\n",return_value);
1149 }
1150 else if (!strncmp(buf, "-rdap", 5) && (1 == sscanf(buf+5, "%x", &reg_addr)))
1151 {
1152 //pwrap_read_reg_on_ap(reg_addr);
1153 }
1154 else if (!strncmp(buf, "-wrap", 5) && (2 == sscanf(buf+5, "%x %x", &reg_addr,&reg_value)))
1155 {
1156 //pwrap_write_reg_on_ap(reg_addr,reg_value);
1157 }
1158 else if (!strncmp(buf, "-rdpmic", 7) && (1 == sscanf(buf+7, "%x", &reg_addr)))
1159 {
1160 //pwrap_read_reg_on_pmic(reg_addr);
1161 }
1162 else if (!strncmp(buf, "-wrpmic", 7) && (2 == sscanf(buf+7, "%x %x", &reg_addr,&reg_value)))
1163 {
1164 //pwrap_write_reg_on_pmic(reg_addr,reg_value);
1165 }
1166 else if(!strncmp(buf, "-readtest", 9))
1167 {
1168 pwrap_read_test();
1169 }
1170 else if(!strncmp(buf, "-writetest", 10))
1171 {
1172 pwrap_write_test();
1173 }
1174 //--------------------------------------pwrap UT-------------------------------------------------------------
1175 else if (!strncmp(buf, "-ut", 3) && (1 == sscanf(buf+3, "%d", &ut_test)))
1176 {
1177 pwrap_ut(ut_test);
1178 }else{
1179 PWRAPREG("wrong parameter\n");
1180 }
1181 return count;
1182 }
1183 /*---------------------------------------------------------------------------*/
1184 #define VERSION "$Revision$"
1185 static int __init mt_pwrap_init(void)
1186 {
1187 S32 ret = 0;
1188 PWRAPLOG("HAL init: version %s\n", VERSION);
1189 mt_wrp = get_mt_pmic_wrap_drv();
1190 mt_wrp->store_hal = mt_pwrap_store_hal;
1191 mt_wrp->show_hal = mt_pwrap_show_hal;
1192 mt_wrp->wacs2_hal = pwrap_wacs2_hal;
1193 ret = request_irq(MT_PMIC_WRAP_IRQ_ID, mt_pmic_wrap_irq, IRQF_TRIGGER_HIGH, PMIC_WRAP_DEVICE,0);
1194 if (ret) {
1195 PWRAPERR("register IRQ failed (%d)\n", ret);
1196 return ret;
1197 }
1198
1199 return ret;
1200 }
1201 postcore_initcall(mt_pwrap_init);
kernel source for telekom puls (alcatel/mediatek)