drivers/misc/mediatek/mmc-host/mt8127/sdio_autok.h

   1 #ifndef MT6582_AUTOK_H
   2 #define MT6582_AUTOK_H
   3
   4 #include <linux/mmc/card.h>
   5 #include <linux/mmc/host.h>
   6 #include <linux/mmc/sdio_func.h>
   7
   8 #include "mt_sd.h"
   9
  10 #define AUTOK_READ 0
  11 #define AUTOK_WRITE 1
  12
  13 #define PROC_BUF_SIZE 512
  14
  15 /*************************************************************************
  16 *           AutoK Implementation
  17 *************************************************************************/
  18 //#define AUTOK_DEBUG
  19 #define USE_KERNEL_THREAD
  20 //#define CHANGE_SCHED_POLICY
  21 //#define SCHED_POLICY_INFO
  22 #define PMIC_MT6323
  23
  24 /*TODO: just remove those def and include the correct one header*/
  25 #define SDIO_IP_WTMDR           (0x00B0)
  26 #define SDIO_IP_WTMCR           (0x00B4)
  27 #define SDIO_IP_WTMDPCR0        (0x00B8)
  28 #define SDIO_IP_WTMDPCR1        (0x00BC)
  29 #define SDIO_IP_WPLRCR          (0x00D4)
  30 #define TEST_MODE_STATUS        (0x100)
  31
  32 struct sdio_autok_params
  33 {
  34     u32 cmd_edge;
  35     u32 rdata_edge;
  36     u32 wdata_edge;
  37     u32 clk_drv;
  38     u32 cmd_drv;
  39     u32 dat_drv;
  40     u32 dat0_rd_dly;
  41     u32 dat1_rd_dly;
  42     u32 dat2_rd_dly;
  43     u32 dat3_rd_dly;
  44     u32 dat_wrd_dly;
  45     u32 cmd_resp_rd_dly;
  46     u32 cmd_rd_dly;
  47     u32 int_dat_latch_ck;
  48     u32 ckgen_msdc_dly_sel;
  49     u32 cmd_rsp_ta_cntr;
  50     u32 wrdat_crcs_ta_cntr;
  51     u32 pad_clk_txdly;
  52 };
  53
  54 #ifdef USE_KERNEL_THREAD
  55 struct sdio_autok_thread_data
  56 {
  57         struct msdc_host *host;
  58         struct sdio_func *sdioFunc;
  59         char autok_stage1_result[PROC_BUF_SIZE];
  60         int len;
  61         char stage;
  62 };
  63 #else   // USE_KERNEL_THREAD
  64 struct sdio_autok_workqueue_data
  65 {
  66         struct delayed_work autok_delayed_work;
  67         struct msdc_host *host;
  68         char autok_stage1_result[PROC_BUF_SIZE];
  69         int len;
  70         char stage;
  71 };
  72 #endif  // USE_KERNEL_THREAD
  73
  74 #define LTE_MODEM_FUNC (1)
  75 #define CMD_52         (52)
  76 #define CMD_53         (53)
  77
  78 #define REQ_CMD_EIO    (0x1 << 0)
  79 #define REQ_CMD_TMO    (0x1 << 1)
  80 #define REQ_DAT_ERR    (0x1 << 2)
  81
  82 #define MSDC_READ      (0)
  83 #define MSDC_WRITE     (1)
  84
  85 enum AUTOK_PARAM {
  86     CMD_EDGE,                       // command response sample selection (MSDC_SMPL_RISING, MSDC_SMPL_FALLING)
  87     RDATA_EDGE,                     // read data sample selection (MSDC_SMPL_RISING, MSDC_SMPL_FALLING)
  88     WDATA_EDGE,                    // write data sample selection (MSDC_SMPL_RISING, MSDC_SMPL_FALLING)
  89     CLK_DRV,                            // clock driving
  90     CMD_DRV,                          // command driving
  91     DAT_DRV,                           // data driving
  92     DAT0_RD_DLY,                   // DAT0 Pad RX Delay Line Control (for MSDC RD), Total 32 stages
  93     DAT1_RD_DLY,                   // DAT1 Pad RX Delay Line Control (for MSDC RD), Total 32 stages
  94     DAT2_RD_DLY,                   // DAT2 Pad RX Delay Line Control (for MSDC RD), Total 32 stages
  95     DAT3_RD_DLY,                   // DAT3 Pad RX Delay Line Control (for MSDC RD), Total 32 stages
  96     DAT_WRD_DLY,                  // Write Data Status Internal Delay Line Control. This register is used to fine-tune write status phase latched by MSDC internal clock. Total 32 stages
  97     DAT_RD_DLY,                  // Rx  Delay Line Control. Total 32 stages
  98     CMD_RESP_RD_DLY,          // CMD Response Internal Delay Line Control. This register is used to fine-tune response phase  latched by MSDC internal clock. Total 32 stages
  99     CMD_RD_DLY,                    // CMD Pad RX Delay Line Control. This register is used to fine-tune CMD pad macro respose latch timing. Total 32 stages
 100     DATA_DLYLINE_SEL,           // Data line delay line fine tune selection. 1'b0: All data line share one delay selection value indicated by PAD_TUNE.PAD_DAT_RD_RXDLY. 1'b1: Each data line has its own delay selection value indicated by Data line (x): DAT_RD_DLY(x).DAT0_RD_DLY
 101     READ_DATA_SMPL_SEL,     // Data line rising/falling latch  fine tune selection in read transaction. 1'b0: All data line share one value indicated by MSDC_IOCON.R_D_SMPL. 1'b1: Each data line has its own  selection value indicated by Data line (x): MSDC_IOCON.R_D(x)_SMPL
 102     WRITE_DATA_SMPL_SEL,   // Data line rising/falling latch  fine tune selection in write transaction. 1'b0: All data line share one value indicated by MSDC_IOCON.W_D_SMPL. 1'b1: Each data line has its own  selection value indicated by Data line (x): MSDC_IOCON.W_D(x)_SMPL
 103     INT_DAT_LATCH_CK,          // Internal MSDC clock phase selection. Total 8 stages, each stage can delay 1 clock period of msdc_src_ck
 104     CKGEN_MSDC_DLY_SEL,    // CKBUF in CKGEN Delay Selection. Total 32 stages
 105     CMD_RSP_TA_CNTR,          // CMD response turn around period. The turn around cycle = CMD_RSP_TA_CNTR + 2, Only for USH104 mode, this register should be set to 0 in non-UHS104 mode
 106     WRDAT_CRCS_TA_CNTR,   // Write data and CRC status turn around period. The turn around cycle = WRDAT_CRCS_TA_CNTR + 2, Only for USH104 mode,  this register should be set to 0 in non-UHS104 mode
 107     PAD_CLK_TXDLY,                // CLK Pad TX Delay Control. This register is used to add delay to CLK phase. Total 32 stages
 108     TOTAL_PARAM_COUNT
 109 };
 110
 111 int msdc_autok_read(struct msdc_host *host, unsigned int u4Addr, unsigned int u4Func, void *pBuffer, unsigned int u4Len, unsigned int u4Cmd);
 112 int msdc_autok_write(struct msdc_host *host, unsigned int u4Addr, unsigned int u4Func, void *pBuffer, unsigned int u4Len, unsigned int u4Cmd);
 113 int msdc_autok_adjust_param(struct msdc_host *host, enum AUTOK_PARAM param, u32 *value, int rw);
 114 int msdc_autok_stg1_cal(struct msdc_host *host, unsigned int offset_restore);
 115 int msdc_autok_stg1_data_get(void **ppData, int *pLen);
 116 int msdc_autok_stg2_cal(struct msdc_host *host, void *pData, int len, unsigned int vcore_uv);
 117
 118 int msdc_autok_apply_param(struct msdc_host *host, void *pData, int len, unsigned int vcore_uv);
 119 #endif /* end of MT6582_AUTOK_H */