drivers/misc/mediatek/jpeg/mt8127/jpeg_drv_6589_enc.c

   1 #include <mach/mt_typedefs.h>
   2 #include <asm/io.h>
   3 #include <linux/kernel.h>
   4 #include <linux/xlog.h>
   5
   6
   7 #include "jpeg_drv_6589_reg.h"
   8 #include "jpeg_drv_6589_common.h"
   9
  10
  11
  12 #define JPEG_ENC_RST_BIT                        0x1
  13
  14 #define JPEG_ENC_CTRL_ENABLE_BIT                0x01
  15 #define JPEG_ENC_CTRL_DIS_GMC_BIT               0x02
  16 #define JPEG_ENC_CTRL_INT_EN_BIT                0x04
  17 #define JPEG_ENC_CTRL_YUV_BIT                   0x18
  18 #define JPEG_ENC_CTRL_FILE_FORMAT_BIT           0x20
  19 #define JPEG_ENC_CTRL_GRAY_EN_BIT               0x80
  20 #define JPEG_ENC_CTRL_ULTRA_HIGH_EN_BIT         0x200
  21 #define JPEG_ENC_CTRL_RESTART_EN_BIT            0x400
  22 #define JPEG_ENC_CTRL_BURST_TYPE_MASK           0x00007000
  23 #define JPEG_ENC_CTRL_BURST_TYPE_SHIFT_COUNT    12
  24
  25 #define JPEG_ENC_EN_DIS_GMC                     (1 << 2)
  26 #define JPEG_ENC_EN_JFIF_EXIF                   (1 << 5)
  27 #define JPEG_ENC_EN_SELF_INIT                   (1 << 16)
  28
  29 #define JPEG_ENC_DEBUG_INFO0_GMC_IDLE_MASK      (1 << 13)
  30
  31 #if 0
  32 #define JPEG_MSG(...)   xlog_printk(ANDROID_LOG_DEBUG, "xlog/jpeg", __VA_ARGS__)
  33 #define JPEG_WRN(...)   xlog_printk(ANDROID_LOG_WARN,  "xlog/jpeg", __VA_ARGS__)
  34 #define JPEG_ERR(...)   xlog_printk(ANDROID_LOG_ERROR, "xlog/jpeg", __VA_ARGS__)
  35 #else
  36 #define JPEG_MSG printk
  37 #define JPEG_WRN printk
  38 #define JPEG_ERR printk
  39 #endif
  40 kal_uint32 _jpeg_enc_int_status = 0;
  41
  42
  43
  44
  45 int jpeg_isr_enc_lisr(void)
  46 {
  47    unsigned int tmp, tmp1 ;
  48     //_jpeg_enc_int_status = REG_JPEG_ENC_INTERRUPT_STATUS;
  49     tmp1 = REG_JPEG_ENC_INTERRUPT_STATUS ;
  50     tmp = tmp1 & (JPEG_DRV_ENC_INT_STATUS_MASK_ALLIRQ);
  51     if(tmp){
  52       _jpeg_enc_int_status = tmp ;
  53
  54       /// clear the interrupt status register
  55       //if(_jpeg_enc_int_status)
  56       //{
  57           IMG_REG_WRITE( 0, REG_ADDR_JPEG_ENC_INTERRUPT_STATUS);   //REG_JPEG_ENC_INTERRUPT_STATUS = 0;
  58           return 0;
  59       //}
  60     }else if(_jpeg_enc_int_status){
  61       IMG_REG_WRITE( 0, REG_ADDR_JPEG_ENC_INTERRUPT_STATUS);   //REG_JPEG_ENC_INTERRUPT_STATUS = 0;
  62       return 0;
  63     }
  64
  65     return -1;
  66 }
  67
  68
  69
  70
  71
  72 kal_uint32 jpeg_drv_enc_set_src_image(kal_uint32 width, kal_uint32 height, kal_uint32 yuv_format, kal_uint32 totalEncDU)
  73 {
  74
  75    kal_uint32 ret = 1;
  76
  77    ret &= jpeg_drv_enc_set_img_size(width, height);
  78
  79    ret &= jpeg_drv_enc_set_encFormat(yuv_format) ;
  80
  81    ret &= jpeg_drv_enc_set_blk_num(totalEncDU);
  82
  83
  84    return ret;
  85
  86 }
  87
  88
  89
  90 kal_uint32 jpeg_drv_enc_set_src_buf(kal_uint32 yuv_format, kal_uint32 img_stride, kal_uint32 mem_stride, kal_uint32 srcAddr, kal_uint32 srcAddr_C)
  91 {
  92    kal_uint32 ret = 1;
  93    if( yuv_format == 0x00 || yuv_format == 0x01 ){
  94      if( (mem_stride & 0x1f) || (img_stride & 0x1f) ){
  95        JPEG_MSG("JPEGENC: set image/memory stride not align 0x1f in fmt %x(%x/%x)!!\n", yuv_format, mem_stride, img_stride);
  96        ret = 0;
  97      }
  98    }
  99
 100    ret &= jpeg_drv_enc_set_image_stride(img_stride);
 101
 102    ret &= jpeg_drv_enc_set_memory_stride(mem_stride);
 103
 104    ret &= jpeg_drv_enc_set_luma_addr(srcAddr);
 105
 106    ret &= jpeg_drv_enc_set_chroma_addr(srcAddr_C);
 107
 108    return ret;
 109 }
 110
 111
 112 ///////////////////////////////////////////////////////////////////////////////
 113
 114
 115
 116
 117
 118 kal_uint32 jpeg_drv_enc_ctrl_cfg( kal_uint32 exif_en, kal_uint32 quality, kal_uint32 restart_interval)
 119 {
 120
 121     jpeg_drv_enc_set_quality(quality);
 122
 123     jpeg_drv_enc_set_restart_interval(restart_interval);
 124
 125     jpeg_drv_enc_set_EncodeMode(exif_en);
 126
 127     return 1;
 128
 129     //if (0 != ctrl_cfg.gmc_disable)
 130     //    REG_JPEG_ENC_CTRL |= JPEG_ENC_CTRL_DIS_GMC_BIT;
 131     //
 132     //REG_JPEG_ENC_CTRL |= JPEG_ENC_EN_SELF_INIT;
 133 }
 134
 135 void jpeg_drv_enc_dump_reg(void)
 136 {
 137     unsigned int reg_value = 0;
 138     unsigned int index = 0;
 139
 140     JPEG_MSG("===== JPEG ENC DUMP =====\n");
 141     for(index = 0x100 ; index < JPEG_ENC_REG_COUNT ; index += 4){
 142 #ifdef FPGA_VERSION
 143         reg_value = *(volatile kal_uint32 *)(JPEG_ENC_BASE + index);
 144 #else
 145         //reg_value = ioread32(JPEG_ENC_BASE + index);
 146         IMG_REG_READ(reg_value, JPEG_DEC_BASE + index);
 147 #endif
 148         JPEG_MSG("+0x%x 0x%08x\n", index, reg_value);
 149     }
 150 }
 151
 152 void jpeg_drv_enc_start(void)
 153 {
 154    unsigned int u4Value ;
 155
 156    u4Value = REG_JPEG_ENC_CTRL ;
 157    u4Value |= (JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT);
 158    IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);
 159    //REG_JPEG_ENC_CTRL |= (JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT);
 160 }
 161
 162 void jpeg_drv_enc_reset(void)
 163 {
 164
 165
 166    IMG_REG_WRITE( (0), REG_ADDR_JPEG_ENC_RSTB);  //REG_JPEG_ENC_RSTB = 0;
 167    IMG_REG_WRITE( (1), REG_ADDR_JPEG_ENC_RSTB);  //REG_JPEG_ENC_RSTB = 1;
 168
 169    IMG_REG_WRITE( (0), REG_ADDR_JPEG_ENC_CODEC_SEL);  //REG_JPEG_ENC_CODEC_SEL = 0; //switch SRAM to jpeg module
 170
 171    _jpeg_enc_int_status = 0;
 172 }
 173
 174
 175 kal_uint32 jpeg_drv_enc_warm_reset(void)
 176 {
 177     kal_uint32 timeout = 0xFFFFF;
 178
 179     REG_JPEG_ENC_CTRL &= ~JPEG_ENC_CTRL_ENABLE_BIT;
 180     REG_JPEG_ENC_CTRL |= JPEG_ENC_CTRL_ENABLE_BIT;
 181
 182
 183     while (0 == (REG_JPEG_ENC_DEBUG_INFO0 & JPEG_ENC_DEBUG_INFO0_GMC_IDLE_MASK))
 184     {
 185         timeout--;
 186         if (0 == timeout)
 187         {
 188             JPEG_MSG("Wait for GMC IDLE timeout\n");
 189             return 0;
 190         }
 191     }
 192
 193     REG_JPEG_ENC_RSTB &= ~(JPEG_ENC_RST_BIT);
 194     REG_JPEG_ENC_RSTB |= JPEG_ENC_RST_BIT;
 195
 196     IMG_REG_WRITE( (0), REG_ADDR_JPEG_ENC_CODEC_SEL);  //REG_JPEG_ENC_CODEC_SEL = 0;
 197
 198     _jpeg_enc_int_status = 0;
 199
 200     return 1;
 201 }
 202
 203
 204 kal_uint32 jpeg_drv_enc_set_encFormat(kal_uint32 encFormat)
 205 {
 206    kal_uint32 val ;
 207    unsigned int u4Value ;
 208
 209    if(encFormat & (~3)){
 210        JPEG_ERR("JPEG_DRV_ENC: set encFormat Err %d!!\n", encFormat );
 211        return 0;
 212    }
 213
 214    val = (encFormat & 3) << 3;
 215 #if 0
 216 //   REG_JPEG_ENC_CTRL &= ~JPEG_ENC_CTRL_YUV_BIT;
 217 //
 218 //   REG_JPEG_ENC_CTRL |= val;
 219 #else
 220
 221    u4Value = REG_JPEG_ENC_CTRL ;
 222
 223    u4Value &= ~JPEG_ENC_CTRL_YUV_BIT;
 224
 225    u4Value |= val;
 226
 227    IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);
 228
 229 #endif
 230
 231    return 1;
 232
 233 }
 234
 235
 236
 237 kal_uint32 jpeg_drv_enc_set_quality(kal_uint32 quality)
 238 {
 239    unsigned int u4Value ;
 240     if (quality == 0x8 || quality == 0xC)
 241     {
 242         JPEG_MSG("JPEGENC: set quality failed\n");
 243         return 0;
 244     }
 245     u4Value = REG_JPEG_ENC_QUALITY;
 246     u4Value = (u4Value & 0xFFFF0000) | quality ;
 247     IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_QUALITY);  //REG_JPEG_ENC_QUALITY = (REG_JPEG_ENC_QUALITY & 0xFFFF0000) | quality;
 248     return 1;
 249 }
 250
 251 kal_uint32 jpeg_drv_enc_set_img_size(kal_uint32 width, kal_uint32 height)
 252 {
 253    unsigned int u4Value ;
 254     if ((width & 0xffff0000) || (height & 0xffff0000))
 255     {
 256         JPEG_MSG("JPEGENC: img size exceed 65535, (%x, %x)!!\n", width, height);
 257         return 0;
 258     }
 259     u4Value = (width << 16) | height ;
 260
 261     IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_IMG_SIZE);   //REG_JPEG_ENC_IMG_SIZE = (width << 16) | height;
 262
 263     return 1;
 264 }
 265
 266 kal_uint32 jpeg_drv_enc_set_blk_num(kal_uint32 blk_num)  //NO_USE
 267 {
 268     if (blk_num < 4)
 269     {
 270         return 0;
 271     }
 272
 273     IMG_REG_WRITE( (blk_num), REG_ADDR_JPEG_ENC_BLK_NUM);   //REG_JPEG_ENC_BLK_NUM = blk_num;
 274
 275     return 1;
 276 }
 277
 278 kal_uint32 jpeg_drv_enc_set_luma_addr(kal_uint32 src_luma_addr)
 279 {
 280     if (src_luma_addr & 0x0F)
 281     {
 282         JPEG_MSG("JPEGENC: set LUMA addr not align (%x)!!\n", src_luma_addr);
 283         //return 0;
 284     }
 285
 286     IMG_REG_WRITE( (src_luma_addr), REG_ADDR_JPEG_ENC_SRC_LUMA_ADDR);  //REG_JPEG_ENC_SRC_LUMA_ADDR = src_luma_addr;
 287
 288     return 1;
 289 }
 290
 291 kal_uint32 jpeg_drv_enc_set_chroma_addr(kal_uint32 src_chroma_addr)
 292 {
 293     if (src_chroma_addr & 0x0F)
 294     {
 295         JPEG_MSG("JPEGENC: set CHROMA addr not align (%x)!!\n", src_chroma_addr);
 296         //return 0;
 297     }
 298
 299     IMG_REG_WRITE( (src_chroma_addr), REG_ADDR_JPEG_ENC_SRC_CHROMA_ADDR);  //REG_JPEG_ENC_SRC_CHROMA_ADDR = src_chroma_addr;
 300
 301     return 1;
 302 }
 303
 304 kal_uint32 jpeg_drv_enc_set_memory_stride(kal_uint32 mem_stride)
 305 {
 306     if ( mem_stride & 0x0F )
 307     {
 308         JPEG_MSG("JPEGENC: set memory stride failed, not align to 0x1f (%x)!!\n", mem_stride);
 309         return 0;
 310     }
 311
 312     IMG_REG_WRITE( (mem_stride), REG_ADDR_JPEG_ENC_STRIDE);  //REG_JPEG_ENC_STRIDE = (mem_stride);
 313
 314     return 1;
 315 }
 316
 317 kal_uint32 jpeg_drv_enc_set_image_stride(kal_uint32 img_stride)
 318 {
 319
 320     if (img_stride & 0x0F)
 321     {
 322         JPEG_MSG("JPEGENC: set image stride failed, not align to 0x0f (%x)!!\n", img_stride);
 323         return 0;
 324     }
 325
 326     IMG_REG_WRITE( (img_stride), REG_ADDR_JPEG_ENC_IMG_STRIDE); //REG_JPEG_ENC_IMG_STRIDE = (img_stride);
 327
 328     return 1;
 329 }
 330
 331 void jpeg_drv_enc_set_restart_interval(kal_uint32 restart_interval)
 332 {
 333    unsigned int u4Value ;
 334
 335    u4Value = REG_JPEG_ENC_CTRL ;
 336    if (0 != restart_interval)
 337    {
 338       u4Value |= JPEG_ENC_CTRL_RESTART_EN_BIT ;
 339       IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL); //REG_JPEG_ENC_CTRL |= JPEG_ENC_CTRL_RESTART_EN_BIT;
 340    }
 341    else
 342    {
 343       u4Value &= ~JPEG_ENC_CTRL_RESTART_EN_BIT;
 344       IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);  //REG_JPEG_ENC_CTRL &= ~JPEG_ENC_CTRL_RESTART_EN_BIT;
 345    }
 346    IMG_REG_WRITE( (restart_interval), REG_ADDR_JPEG_ENC_RST_MCU_NUM);  //REG_JPEG_ENC_RST_MCU_NUM = restart_interval;
 347 }
 348
 349
 350 kal_uint32 jpeg_drv_enc_set_offset_addr(kal_uint32 offset)
 351 {
 352    if (offset & 0x0F)
 353    {
 354       JPEG_MSG("JPEGENC:WARN set offset addr %x\n", offset);
 355       //return 0;
 356    }
 357
 358    IMG_REG_WRITE( (offset), REG_ADDR_JPEG_ENC_OFFSET_ADDR);  //REG_JPEG_ENC_OFFSET_ADDR = offset;
 359
 360    return 1;
 361 }
 362
 363 kal_uint32 jpeg_drv_enc_set_dst_buff(kal_uint32 dst_addr, kal_uint32 stall_size, kal_uint32 init_offset, kal_uint32 offset_mask)
 364 {
 365     if (stall_size < 624)
 366     {
 367         JPEG_MSG("JPEGENC:stall offset less than 624 to write header %d!!\n",stall_size);
 368         return 0;
 369     }
 370
 371    if (offset_mask & 0x0F)
 372    {
 373       JPEG_MSG("JPEGENC: set offset addr %x\n", offset_mask);
 374       //return 0;
 375    }
 376
 377    IMG_REG_WRITE( (init_offset & (~0xF)), REG_ADDR_JPEG_ENC_OFFSET_ADDR);   //REG_JPEG_ENC_OFFSET_ADDR = init_offset & (~0xF);
 378
 379    IMG_REG_WRITE( (offset_mask & 0xF), REG_ADDR_JPEG_ENC_BYTE_OFFSET_MASK);   //REG_JPEG_ENC_BYTE_OFFSET_MASK = (offset_mask & 0xF);
 380
 381    IMG_REG_WRITE( (dst_addr & (~0xF)), REG_ADDR_JPEG_ENC_DST_ADDR0);   //REG_JPEG_ENC_DST_ADDR0  = dst_addr & (~0xF);
 382
 383    IMG_REG_WRITE( ((dst_addr + stall_size) & (~0xF)), REG_ADDR_JPEG_ENC_STALL_ADDR0);   //REG_JPEG_ENC_STALL_ADDR0 = (dst_addr + stall_size) & (~0xF);
 384
 385
 386    return 1;
 387 }
 388
 389 // 0:JPG mode, 1:JFIF/EXIF mode
 390 void jpeg_drv_enc_set_EncodeMode(kal_uint32 exif_en)
 391 {
 392    unsigned int u4Value ;
 393
 394    u4Value = REG_JPEG_ENC_CTRL;
 395    u4Value &= ~(JPEG_ENC_CTRL_FILE_FORMAT_BIT);
 396    IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);   //REG_JPEG_ENC_CTRL &= ~(JPEG_ENC_CTRL_FILE_FORMAT_BIT);
 397
 398    if (exif_en)
 399    {
 400       u4Value = REG_JPEG_ENC_CTRL;
 401       u4Value |= JPEG_ENC_EN_JFIF_EXIF;
 402       IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);   //REG_JPEG_ENC_CTRL |= JPEG_ENC_EN_JFIF_EXIF;
 403    }
 404 }
 405
 406 void jpeg_drv_enc_set_gmc_disable_bit(void)
 407 {
 408    unsigned int u4Value ;
 409    u4Value = REG_JPEG_ENC_CTRL ;
 410    u4Value |= JPEG_ENC_EN_DIS_GMC;
 411    IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);
 412
 413 }
 414
 415
 416 void jpeg_drv_enc_set_burst_type(kal_uint32 burst_type)
 417 {
 418    unsigned int u4Value ;
 419
 420    u4Value = REG_JPEG_ENC_CTRL ;
 421
 422    u4Value &= ~JPEG_ENC_CTRL_BURST_TYPE_MASK;
 423    u4Value |= (burst_type << JPEG_ENC_CTRL_BURST_TYPE_SHIFT_COUNT);
 424
 425
 426    IMG_REG_WRITE( (u4Value), REG_ADDR_JPEG_ENC_CTRL);
 427 }
 428
 429 kal_uint32  jpeg_drv_enc_get_cycle_count()
 430 {
 431     return REG_JPEG_ENC_TOTAL_CYCLE;
 432 }
 433
 434
 435 kal_uint32 jpeg_drv_enc_get_file_size()
 436 {
 437     return REG_JPEG_ENC_DMA_ADDR0 - REG_JPEG_ENC_DST_ADDR0;
 438     //return REG_JPEG_ENC_CURR_DMA_ADDR - REG_JPEG_ENC_DST_ADDR0;
 439 }
 440
 441 #ifdef FPGA_VERSION
 442
 443 kal_uint32 jpeg_drv_enc_get_result()
 444 {
 445     kal_uint32 file_size;
 446     file_size = jpeg_drv_enc_get_file_size();
 447     return file_size;
 448 }
 449 #else
 450
 451 kal_uint32 jpeg_drv_enc_get_result(kal_uint32 *fileSize)
 452 {
 453     *fileSize = jpeg_drv_enc_get_file_size();
 454
 455     if(_jpeg_enc_int_status & JPEG_DRV_ENC_INT_STATUS_DONE)
 456     {
 457         return 0;
 458     }
 459     else if(_jpeg_enc_int_status & JPEG_DRV_ENC_INT_STATUS_STALL)
 460     {
 461         return 1;
 462     }else if( _jpeg_enc_int_status & JPEG_DRV_ENC_INT_STATUS_VCODEC_IRQ){
 463         return 2;
 464     }
 465
 466     JPEG_MSG("JPEGENC: int_st %x!!\n", _jpeg_enc_int_status);
 467     return 3;
 468 }
 469
 470
 471
 472 #endif
 473
 474
 475