drivers/misc/mediatek/emi_bwl/mt8127/emi_bwl.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/semaphore.h>
   5 #include <linux/device.h>
   6 #include <linux/platform_device.h>
   7 #include <linux/xlog.h>
   8
   9 #include "mach/mt_reg_base.h"
  10 #include "mach/emi_bwl.h"
  11 #include "mach/sync_write.h"
  12
  13 DEFINE_SEMAPHORE(emi_bwl_sem);
  14
  15 static struct platform_driver mem_bw_ctrl = {
  16     .driver     = {
  17         .name = "mem_bw_ctrl",
  18         .owner = THIS_MODULE,
  19     },
  20 };
  21
  22 static struct platform_driver ddr_type = {
  23     .driver     = {
  24         .name = "ddr_type",
  25         .owner = THIS_MODULE,
  26     },
  27 };
  28
  29 #if 0
  30
  31 static struct platform_driver dramc_high = {
  32     .driver     = {
  33         .name = "dramc_high",
  34         .owner = THIS_MODULE,
  35     },
  36 };
  37
  38 static struct platform_driver mem_bw_finetune_md = {
  39     .driver     = {
  40         .name = "mem_bw_finetune_md",
  41         .owner = THIS_MODULE,
  42     },
  43 };
  44
  45 static struct platform_driver mem_bw_finetune_mm = {
  46     .driver     = {
  47         .name = "mem_bw_finetune_mm",
  48         .owner = THIS_MODULE,
  49     },
  50 };
  51 #endif
  52
  53 /* define EMI bandwiwth limiter control table */
  54 static struct emi_bwl_ctrl ctrl_tbl[NR_CON_SCE];
  55
  56 /* current concurrency scenario */
  57 static int cur_con_sce = 0x0FFFFFFF;
  58
  59 /* define concurrency scenario strings */
  60 static const char *con_sce_str[] =
  61 {
  62 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) #con_sce,
  63 #include "mach/con_sce_lpddr2.h"
  64 #undef X_CON_SCE
  65 };
  66
  67 /* define EMI bandwidth allocation tables */
  68 /****************** For LPDDR2 ******************/
  69 static const unsigned int emi_arba_lpddr2_val[] =
  70 {
  71 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arba,
  72 #include "mach/con_sce_lpddr2.h"
  73 #undef X_CON_SCE
  74 };
  75
  76 static const unsigned int emi_arbb_lpddr2_val[] =
  77 {
  78 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbb,
  79 #include "mach/con_sce_lpddr2.h"
  80 #undef X_CON_SCE
  81 };
  82 static const unsigned int emi_arbc_lpddr2_val[] =
  83 {
  84 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbc,
  85 #include "mach/con_sce_lpddr2.h"
  86 #undef X_CON_SCE
  87 };
  88 static const unsigned int emi_arbd_lpddr2_val[] =
  89 {
  90 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbd,
  91 #include "mach/con_sce_lpddr2.h"
  92 #undef X_CON_SCE
  93 };
  94 static const unsigned int emi_arbe_lpddr2_val[] =
  95 {
  96 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbe,
  97 #include "mach/con_sce_lpddr2.h"
  98 #undef X_CON_SCE
  99 };
 100
 101 /****************** For DDR3-16bit ******************/
 102
 103 static const unsigned int emi_arba_ddr3_16_val[] =
 104 {
 105 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arba,
 106 #include "mach/con_sce_ddr3_16.h"
 107 #undef X_CON_SCE
 108 };
 109
 110 static const unsigned int emi_arbb_ddr3_16_val[] =
 111 {
 112 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbb,
 113 #include "mach/con_sce_ddr3_16.h"
 114 #undef X_CON_SCE
 115 };
 116 static const unsigned int emi_arbc_ddr3_16_val[] =
 117 {
 118 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbc,
 119 #include "mach/con_sce_ddr3_16.h"
 120 #undef X_CON_SCE
 121 };
 122 static const unsigned int emi_arbd_ddr3_16_val[] =
 123 {
 124 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbd,
 125 #include "mach/con_sce_ddr3_16.h"
 126 #undef X_CON_SCE
 127 };
 128 static const unsigned int emi_arbe_ddr3_16_val[] =
 129 {
 130 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbe,
 131 #include "mach/con_sce_ddr3_16.h"
 132 #undef X_CON_SCE
 133 };
 134
 135 /****************** For LPDDR3 ******************/
 136
 137 static const unsigned int emi_arba_lpddr3_val[] =
 138 {
 139 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arba,
 140 #include "mach/con_sce_lpddr3.h"
 141 #undef X_CON_SCE
 142 };
 143
 144 static const unsigned int emi_arbb_lpddr3_val[] =
 145 {
 146 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbb,
 147 #include "mach/con_sce_lpddr3.h"
 148 #undef X_CON_SCE
 149 };
 150 static const unsigned int emi_arbc_lpddr3_val[] =
 151 {
 152 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbc,
 153 #include "mach/con_sce_lpddr3.h"
 154 #undef X_CON_SCE
 155 };
 156 static const unsigned int emi_arbd_lpddr3_val[] =
 157 {
 158 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbd,
 159 #include "mach/con_sce_lpddr3.h"
 160 #undef X_CON_SCE
 161 };
 162 static const unsigned int emi_arbe_lpddr3_val[] =
 163 {
 164 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbe,
 165 #include "mach/con_sce_lpddr3.h"
 166 #undef X_CON_SCE
 167 };
 168
 169 int get_ddr_type(void)
 170 {
 171   unsigned int value;
 172
 173   value = DRAMC_READ(DRAMC_LPDDR2);
 174   if((value>>28) & 0x1) //check LPDDR2_EN
 175   {
 176     return LPDDR2;
 177   }
 178
 179   value = DRAMC_READ(DRAMC_PADCTL4);
 180   if((value>>7) & 0x1) //check DDR3_EN
 181   {
 182     if (DRAMC_READ(DRAMC_CONF1) & 0x1)
 183     {
 184       return DDR3_32;
 185     }
 186     else
 187     {
 188       return DDR3_16;
 189     }
 190   }
 191
 192   value = DRAMC_READ(DRAMC_ACTIM1);
 193   if((value>>28) & 0x1) //check LPDDR3_EN
 194   {
 195     return LPDDR3;
 196   }
 197
 198   return mDDR;
 199 }
 200
 201 /*
 202  * mtk_mem_bw_ctrl: set EMI bandwidth limiter for memory bandwidth control
 203  * @sce: concurrency scenario ID
 204  * @op: either ENABLE_CON_SCE or DISABLE_CON_SCE
 205  * Return 0 for success; return negative values for failure.
 206  */
 207 int mtk_mem_bw_ctrl(int sce, int op)
 208 {
 209   int i, highest;
 210
 211   if (sce >= NR_CON_SCE) {
 212     return -1;
 213   }
 214
 215   if (op != ENABLE_CON_SCE && op != DISABLE_CON_SCE) {
 216     return -1;
 217   }
 218   if (in_interrupt()) {
 219    return -1;
 220   }
 221
 222   down(&emi_bwl_sem);
 223
 224   if (op == ENABLE_CON_SCE) {
 225     ctrl_tbl[sce].ref_cnt++;
 226   }
 227   else if (op == DISABLE_CON_SCE) {
 228     if (ctrl_tbl[sce].ref_cnt != 0) {
 229       ctrl_tbl[sce].ref_cnt--;
 230     }
 231   }
 232
 233   /* find the scenario with the highest priority */
 234   highest = -1;
 235   for (i = 0; i < NR_CON_SCE; i++) {
 236       if (ctrl_tbl[i].ref_cnt != 0) {
 237           highest = i;
 238           break;
 239       }
 240   }
 241   if (highest == -1) {
 242       highest = CON_SCE_NORMAL;
 243   }
 244
 245   /* set new EMI bandwidth limiter value */
 246   if (highest != cur_con_sce) {
 247
 248 #if 1
 249     if(get_ddr_type() == LPDDR2)
 250     {
 251       mt65xx_reg_sync_writel(emi_arba_lpddr2_val[highest], EMI_ARBA);
 252       mt65xx_reg_sync_writel(emi_arbb_lpddr2_val[highest], EMI_ARBB);
 253       mt65xx_reg_sync_writel(emi_arbc_lpddr2_val[highest], EMI_ARBC);
 254       mt65xx_reg_sync_writel(emi_arbd_lpddr2_val[highest], EMI_ARBD);
 255       mt65xx_reg_sync_writel(emi_arbe_lpddr2_val[highest], EMI_ARBE);
 256     }
 257     else if(get_ddr_type() == DDR3_16)
 258     {
 259       mt65xx_reg_sync_writel(emi_arba_ddr3_16_val[highest], EMI_ARBA);
 260       mt65xx_reg_sync_writel(emi_arbb_ddr3_16_val[highest], EMI_ARBB);
 261       mt65xx_reg_sync_writel(emi_arbc_ddr3_16_val[highest], EMI_ARBC);
 262       mt65xx_reg_sync_writel(emi_arbd_ddr3_16_val[highest], EMI_ARBD);
 263       mt65xx_reg_sync_writel(emi_arbe_ddr3_16_val[highest], EMI_ARBE);
 264     }
 265     else if(get_ddr_type() == LPDDR3)
 266     {
 267       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBA);
 268       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBB);
 269       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBC);
 270       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBD);
 271       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBE);
 272     }
 273 #endif
 274       cur_con_sce = highest;
 275   }
 276
 277   up(&emi_bwl_sem);
 278
 279   return 0;
 280 }
 281
 282 /*
 283  * ddr_type_show: sysfs ddr_type file show function.
 284  * @driver:
 285  * @buf: the string of ddr type
 286  * Return the number of read bytes.
 287  */
 288 static ssize_t ddr_type_show(struct device_driver *driver, char *buf)
 289 {
 290     if(get_ddr_type() == LPDDR2)
 291     {
 292       sprintf(buf, "LPDDR2\n");
 293     }
 294     else if(get_ddr_type() == DDR3_16)
 295     {
 296       sprintf(buf, "DDR3_16\n");
 297     }
 298     else if(get_ddr_type() == DDR3_32)
 299     {
 300       sprintf(buf, "DDR3_32\n");
 301     }
 302     else if(get_ddr_type() == LPDDR3)
 303     {
 304       sprintf(buf, "LPDDR3\n");
 305     }
 306     else
 307     {
 308       sprintf(buf, "mDDR\n");
 309     }
 310
 311     return strlen(buf);
 312 }
 313
 314 /*
 315  * ddr_type_store: sysfs ddr_type file store function.
 316  * @driver:
 317  * @buf:
 318  * @count:
 319  * Return the number of write bytes.
 320  */
 321 static ssize_t ddr_type_store(struct device_driver *driver, const char *buf, size_t count)
 322 {
 323   /*do nothing*/
 324   return count;
 325 }
 326
 327 DRIVER_ATTR(ddr_type, 0644, ddr_type_show, ddr_type_store);
 328
 329 extern unsigned int get_actual_DRAM_size(void);
 330 /*
 331  * ddr_type_show: sysfs ddr_size file show function.
 332  * @driver:
 333  * @buf: the string of ddr type
 334  * Return the number of read bytes.
 335  */
 336 static ssize_t ddr_size_show(struct device_driver *driver, char *buf)
 337 {
 338     sprintf(buf, "%d\n", get_actual_DRAM_size());
 339
 340     return strlen(buf);
 341 }
 342 /*
 343  * ddr_size_store: sysfs ddr_size file store function.
 344  * @driver:
 345  * @buf:
 346  * @count:
 347  * Return the number of write bytes.
 348  */
 349 static ssize_t ddr_size_store(struct device_driver *driver, const char *buf, size_t count)
 350 {
 351   /*do nothing*/
 352   return count;
 353 }
 354
 355 DRIVER_ATTR(ddr_size, 0644, ddr_size_show, ddr_size_store);
 356 /*
 357  * con_sce_show: sysfs con_sce file show function.
 358  * @driver:
 359  * @buf:
 360  * Return the number of read bytes.
 361  */
 362 static ssize_t con_sce_show(struct device_driver *driver, char *buf)
 363 {
 364     if (cur_con_sce >= NR_CON_SCE) {
 365         sprintf(buf, "none\n");
 366     } else {
 367         sprintf(buf, "%s\n", con_sce_str[cur_con_sce]);
 368     }
 369
 370     return strlen(buf);
 371 }
 372
 373 /*
 374  * con_sce_store: sysfs con_sce file store function.
 375  * @driver:
 376  * @buf:
 377  * @count:
 378  * Return the number of write bytes.
 379  */
 380 static ssize_t con_sce_store(struct device_driver *driver, const char *buf, size_t count)
 381 {
 382   int i;
 383
 384   for (i = 0; i < NR_CON_SCE; i++) {
 385     if (!strncmp(buf, con_sce_str[i], strlen(con_sce_str[i]))) {
 386       if (!strncmp(buf + strlen(con_sce_str[i]) + 1, EN_CON_SCE_STR, strlen(EN_CON_SCE_STR))) {
 387         mtk_mem_bw_ctrl(i, ENABLE_CON_SCE);
 388         printk("concurrency scenario %s ON\n", con_sce_str[i]);
 389         break;
 390       }
 391       else if (!strncmp(buf + strlen(con_sce_str[i]) + 1, DIS_CON_SCE_STR, strlen(DIS_CON_SCE_STR))) {
 392         mtk_mem_bw_ctrl(i, DISABLE_CON_SCE);
 393         printk("concurrency scenario %s OFF\n", con_sce_str[i]);
 394         break;
 395       }
 396     }
 397   }
 398
 399   return count;
 400 }
 401
 402 DRIVER_ATTR(concurrency_scenario, 0644, con_sce_show, con_sce_store);
 403
 404
 405 /*
 406  * finetune_md_show: sysfs con_sce file show function.
 407  * @driver:
 408  * @buf:
 409  * Return the number of read bytes.
 410  */
 411 static ssize_t finetune_md_show(struct device_driver *driver, char *buf)
 412 {
 413   unsigned int dram_type;
 414
 415   dram_type = get_ddr_type();
 416
 417   if(dram_type == LPDDR2) /*LPDDR2. FIXME*/
 418   {
 419     switch(cur_con_sce)
 420     {
 421       case CON_SCE_VR:
 422         sprintf(buf, "true");
 423         break;
 424       default:
 425         sprintf(buf, "false");
 426         break;
 427     }
 428   }
 429   else if(dram_type == DDR3_16) /*DDR3-16bit. FIXME*/
 430   {
 431     /*TBD*/
 432   }
 433   else if(dram_type == DDR3_32) /*DDR3-32bit. FIXME*/
 434   {
 435     /*TBD*/
 436   }
 437   else if(dram_type == mDDR) /*mDDR. FIXME*/
 438   {
 439     /*TBD*/
 440   }
 441   else
 442   {
 443     /*unkown dram type*/
 444     sprintf(buf, "ERROR: unkown dram type!");
 445   }
 446
 447   return strlen(buf);
 448 }
 449
 450 /*
 451  * finetune_md_store: sysfs con_sce file store function.
 452  * @driver:
 453  * @buf:
 454  * @count:
 455  * Return the number of write bytes.
 456  */
 457 static ssize_t finetune_md_store(struct device_driver *driver, const char *buf, size_t count)
 458 {
 459   /*Do nothing*/
 460   return count;
 461 }
 462
 463 DRIVER_ATTR(finetune_md, 0644, finetune_md_show, finetune_md_store);
 464
 465
 466 /*
 467  * finetune_mm_show: sysfs con_sce file show function.
 468  * @driver:
 469  * @buf:
 470  * Return the number of read bytes.
 471  */
 472 static ssize_t finetune_mm_show(struct device_driver *driver, char *buf)
 473 {
 474   unsigned int dram_type;
 475
 476   dram_type = get_ddr_type();
 477
 478   if(dram_type == LPDDR2) /*LPDDR2. FIXME*/
 479   {
 480     switch(cur_con_sce)
 481     {
 482       default:
 483         sprintf(buf, "false");
 484         break;
 485     }
 486   }
 487   else if(dram_type == DDR3_16) /*DDR3-16bit. FIXME*/
 488   {
 489     /*TBD*/
 490   }
 491   else if(dram_type == DDR3_32) /*DDR3-32bit. FIXME*/
 492   {
 493     /*TBD*/
 494   }
 495   else if(dram_type == mDDR) /*mDDR. FIXME*/
 496   {
 497     /*TBD*/
 498   }
 499   else
 500   {
 501     /*unkown dram type*/
 502     sprintf(buf, "ERROR: unkown dram type!");
 503   }
 504
 505   return strlen(buf);
 506 }
 507
 508 /*
 509  * finetune_md_store: sysfs con_sce file store function.
 510  * @driver:
 511  * @buf:
 512  * @count:
 513  * Return the number of write bytes.
 514  */
 515 static ssize_t finetune_mm_store(struct device_driver *driver, const char *buf, size_t count)
 516 {
 517   /*Do nothing*/
 518   return count;
 519 }
 520
 521 DRIVER_ATTR(finetune_mm, 0644, finetune_mm_show, finetune_mm_store);
 522
 523 #if 0
 524 /*
 525  * dramc_high_show: show the status of DRAMC_HI_EN
 526  * @driver:
 527  * @buf:
 528  * Return the number of read bytes.
 529  */
 530 static ssize_t dramc_high_show(struct device_driver *driver, char *buf)
 531 {
 532  unsigned int dramc_hi;
 533
 534  dramc_hi = (readl(EMI_TESTB) >> 12) & 0x1;
 535  if(dramc_hi == 1)
 536   return sprintf(buf, "DRAMC_HI is ON\n");
 537  else
 538   return sprintf(buf, "DRAMC_HI is OFF\n");
 539 }
 540
 541 /*
 542  dramc_hign_store: enable/disable DRAMC untra high. WARNING: ONLY CAN BE ENABLED AT MD_STANDALONE!!!
 543  * @driver:
 544  * @buf: need to be "0" or "1"
 545  * @count:
 546  * Return the number of write bytes.
 547 */
 548 static ssize_t dramc_high_store(struct device_driver *driver, const char *buf, size_t count)
 549 {
 550   unsigned int value;
 551   unsigned int emi_testb;
 552
 553   if (sscanf(buf, "%u", &value) != 1)
 554     return -EINVAL;
 555
 556   emi_testb = readl(EMI_TESTB);
 557
 558   if(value == 1)
 559   {
 560     emi_testb |= 0x1000; /* Enable DRAM_HI */
 561     mt65xx_reg_sync_writel(emi_testb, EMI_TESTB);
 562   }
 563   else if(value == 0)
 564   {
 565     emi_testb &= ~0x1000; /* Disable DRAM_HI */
 566     mt65xx_reg_sync_writel(emi_testb, EMI_TESTB);
 567   }
 568   else
 569     return -EINVAL;
 570
 571   return count;
 572 }
 573
 574 DRIVER_ATTR(dramc_high, 0644, dramc_high_show, dramc_high_store);
 575 #endif
 576 /*
 577  * emi_bwl_mod_init: module init function.
 578  */
 579 static int __init emi_bwl_mod_init(void)
 580 {
 581   int ret;
 582
 583 #if 0 //Marcos: TBD
 584   if(get_ddr_type() == LPDDR2) //LPDDR2
 585   {
 586     /* apply co-sim result for LPDDR2. */
 587     mt65xx_reg_sync_writel(0x14212836, EMI_CONB);
 588     mt65xx_reg_sync_writel(0x0f131314, EMI_CONC);
 589     mt65xx_reg_sync_writel(0x14212836, EMI_COND);
 590     mt65xx_reg_sync_writel(0x0f131314, EMI_CONE);
 591     mt65xx_reg_sync_writel(0x0f131428, EMI_CONG);
 592     mt65xx_reg_sync_writel(0x0f131428, EMI_CONH);
 593     /* testing for MD2 timing fail */
 594     mt65xx_reg_sync_writel(0x0c8f0ccd, EMI_SLCT);
 595     //mt65xx_reg_sync_writel(0x088b08cd, EMI_SLCT);
 596     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK);
 597     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK_2ND);
 598     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ);
 599     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ_2ND);
 600     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI);
 601     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI_2ND);
 602     mt65xx_reg_sync_writel(0x00070714, EMI_TESTB);
 603     //mt65xx_reg_sync_writel(0x00070754, EMI_TESTB);
 604     //mt65xx_reg_sync_writel(0x10000000, EMI_TESTD);
 605   }
 606
 607   else if(get_ddr_type() == DDR3_16) //DDR3-16bit
 608   {
 609     //write overhead value
 610     mt65xx_reg_sync_writel(0x0B0B0E17, EMI_CONB);       //read  overhead for 4~1
 611     mt65xx_reg_sync_writel(0x0B0B0B0B, EMI_CONC);       //read  overhead for 8~5
 612     mt65xx_reg_sync_writel(0x1012161E, EMI_COND);       //write overhead for 4~1
 613     mt65xx_reg_sync_writel(0x0B0B0D0E, EMI_CONE);   //write overhead for 8~5
 614   }
 615   else if(get_ddr_type() == DDR3_32)
 616   {
 617     /* apply co-sim result for LPDDR2. */
 618     mt65xx_reg_sync_writel(0x14212836, EMI_CONB);
 619     mt65xx_reg_sync_writel(0x0f131314, EMI_CONC);
 620     mt65xx_reg_sync_writel(0x14212836, EMI_COND);
 621     mt65xx_reg_sync_writel(0x0f131314, EMI_CONE);
 622     mt65xx_reg_sync_writel(0x0f131428, EMI_CONG);
 623     mt65xx_reg_sync_writel(0x0f131428, EMI_CONH);
 624     /* testing for MD2 timing fail */
 625     mt65xx_reg_sync_writel(0x088b08cd, EMI_SLCT);
 626     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK);
 627     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK_2ND);
 628     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ);
 629     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ_2ND);
 630     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI);
 631     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI_2ND);
 632     mt65xx_reg_sync_writel(0x00070714, EMI_TESTB);
 633     //mt65xx_reg_sync_writel(0x00070754, EMI_TESTB);
 634     //mt65xx_reg_sync_writel(0x10000000, EMI_TESTD);
 635   }
 636   else if(get_ddr_type() == LPDDR3)
 637   {
 638     //TBD
 639   }  */
 640   else //mDDR
 641   {
 642     mt65xx_reg_sync_writel(0x2B2C2C2E, EMI_CONB);       //read  overhead for 4~1
 643     mt65xx_reg_sync_writel(0x2627292B, EMI_CONC);       //read  overhead for 8~5
 644     mt65xx_reg_sync_writel(0x2B2C2C2E, EMI_COND);       //write overhead for 4~1
 645     mt65xx_reg_sync_writel(0x2627292B, EMI_CONE);       //write overhead for 8~5
 646   }
 647 #endif
 648
 649   //write Filter Priority Encode
 650   //writel(0x01812488, EMI_ARBI); //TBD. need to set EMI_ARBI_2ND???
 651
 652   ret = mtk_mem_bw_ctrl(CON_SCE_NORMAL, ENABLE_CON_SCE);
 653   if (ret) {
 654     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to set EMI bandwidth limiter\n");
 655   }
 656
 657   /* Register BW ctrl interface */
 658   ret = platform_driver_register(&mem_bw_ctrl);
 659   if (ret) {
 660     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register EMI_BW_LIMITER driver\n");
 661   }
 662
 663   ret = driver_create_file(&mem_bw_ctrl.driver, &driver_attr_concurrency_scenario);
 664   if (ret) {
 665     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create EMI_BW_LIMITER sysfs file\n");
 666   }
 667
 668   /* Register DRAM type information interface */
 669   ret = platform_driver_register(&ddr_type);
 670   if (ret) {
 671     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register DRAM_TYPE driver\n");
 672   }
 673
 674   ret = driver_create_file(&ddr_type.driver, &driver_attr_ddr_type);
 675   if (ret) {
 676     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create DRAM_TYPE sysfs file\n");
 677   }
 678   ret = driver_create_file(&ddr_type.driver, &driver_attr_ddr_size);
 679   if (ret) {
 680     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create DRAM_SIZE sysfs file\n");
 681   }
 682 #if 0
 683   /* Register DRAMC ultra high interface */
 684   ret = platform_driver_register(&dramc_high);
 685   ret = driver_create_file(&dramc_high.driver, &driver_attr_dramc_high);
 686   if (ret) {
 687     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create DRAMC_HIGH sysfs file\n");
 688   }
 689 #endif
 690 #if 0
 691   /* Register MD feature fine-tune interface */
 692   ret = platform_driver_register(&mem_bw_finetune_md);
 693   if (ret) {
 694     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register EMI_BW_FINETUNE_MD driver\n");
 695   }
 696
 697   ret = driver_create_file(&mem_bw_finetune_md.driver, &driver_attr_finetune_md);
 698   if (ret) {
 699     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create EMI_BW_FINETUNE_MD sysfs file\n");
 700   }
 701
 702   /* Register MM feature fine-tune interface */
 703   ret = platform_driver_register(&mem_bw_finetune_mm);
 704   if (ret) {
 705     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register EMI_BW_FINETUNE_MM driver\n");
 706   }
 707
 708   ret = driver_create_file(&mem_bw_finetune_mm.driver, &driver_attr_finetune_mm);
 709   if (ret) {
 710     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create EMI_BW_FINETUNE_MM sysfs file\n");
 711   }
 712 #endif
 713
 714   return 0;
 715 }
 716
 717 /*
 718  * emi_bwl_mod_exit: module exit function.
 719  */
 720 static void __exit emi_bwl_mod_exit(void)
 721 {
 722 }
 723
 724 EXPORT_SYMBOL(get_ddr_type);
 725
 726 module_init(emi_bwl_mod_init);
 727 module_exit(emi_bwl_mod_exit);
 728