drivers/misc/mediatek/connectivity/combo/drv_wlan/mt6620/wlan/include/nic/hal.h

   1 /*
   2 ** $Id: //Department/DaVinci/BRANCHES/MT6620_WIFI_DRIVER_V2_3/include/nic/hal.h#1 $
   3 */
   4
   5 /*! \file   "hal.h"
   6     \brief  The declaration of hal functions
   7
   8     N/A
   9 */
  10
  11
  12
  13 /*
  14 ** $Log: hal.h $
  15  *
  16  * 04 01 2011 tsaiyuan.hsu
  17  * [WCXRP00000615] [MT 6620 Wi-Fi][Driver] Fix klocwork issues
  18  * fix the klocwork issues, 57500, 57501, 57502 and 57503.
  19  *
  20  * 03 21 2011 cp.wu
  21  * [WCXRP00000540] [MT5931][Driver] Add eHPI8/eHPI16 support to Linux Glue Layer
  22  * portability improvement
  23  *
  24  * 03 07 2011 terry.wu
  25  * [WCXRP00000521] [MT6620 Wi-Fi][Driver] Remove non-standard debug message
  26  * Toggle non-standard debug messages to comments.
  27  *
  28  * 11 08 2010 cp.wu
  29  * [WCXRP00000166] [MT6620 Wi-Fi][Driver] use SDIO CMD52 for enabling/disabling interrupt to reduce transaction period
  30  * change to use CMD52 for enabling/disabling interrupt to reduce SDIO transaction time
  31  *
  32  * 09 01 2010 cp.wu
  33  * NULL
  34  * move HIF CR initialization from where after sdioSetupCardFeature() to wlanAdapterStart()
  35  *
  36  * 07 08 2010 cp.wu
  37  *
  38  * [WPD00003833] [MT6620 and MT5931] Driver migration - move to new repository.
  39  *
  40  * 06 15 2010 cp.wu
  41  * [WPD00003833][MT6620 and MT5931] Driver migration
  42  * change zero-padding for TX port access to HAL.
  43  *
  44  * 06 06 2010 kevin.huang
  45  * [WPD00003832][MT6620 5931] Create driver base
  46  * [MT6620 5931] Create driver base
  47  *
  48  * 04 06 2010 cp.wu
  49  * [WPD00001943]Create WiFi test driver framework on WinXP
  50  * eliminate direct access for prGlueInfo->fgIsCardRemoved in non-glue layer
  51  *
  52  * 01 27 2010 cp.wu
  53  * [WPD00001943]Create WiFi test driver framework on WinXP
  54  * 1. eliminate improper variable in rHifInfo
  55  *  *  *  * 2. block TX/ordinary OID when RF test mode is engaged
  56  *  *  *  * 3. wait until firmware finish operation when entering into and leaving from RF test mode
  57  *  *  *  * 4. correct some HAL implementation
  58 **  \main\maintrunk.MT6620WiFiDriver_Prj\17 2009-12-16 18:02:26 GMT mtk02752
  59 **  include precomp.h
  60 **  \main\maintrunk.MT6620WiFiDriver_Prj\16 2009-12-10 16:43:16 GMT mtk02752
  61 **  code clean
  62 **  \main\maintrunk.MT6620WiFiDriver_Prj\15 2009-11-13 13:54:15 GMT mtk01084
  63 **  \main\maintrunk.MT6620WiFiDriver_Prj\14 2009-11-11 10:36:01 GMT mtk01084
  64 **  modify HAL functions
  65 **  \main\maintrunk.MT6620WiFiDriver_Prj\13 2009-11-09 22:56:28 GMT mtk01084
  66 **  modify HW access routines
  67 **  \main\maintrunk.MT6620WiFiDriver_Prj\12 2009-10-29 19:50:09 GMT mtk01084
  68 **  add new macro HAL_TX_PORT_WR
  69 **  \main\maintrunk.MT6620WiFiDriver_Prj\11 2009-10-23 16:08:10 GMT mtk01084
  70 **  \main\maintrunk.MT6620WiFiDriver_Prj\10 2009-10-13 21:58:50 GMT mtk01084
  71 **  update for new HW architecture design
  72 **  \main\maintrunk.MT6620WiFiDriver_Prj\9 2009-05-18 14:28:10 GMT mtk01084
  73 **  fix issue in HAL_DRIVER_OWN_BY_SDIO_CMD52()
  74 **  \main\maintrunk.MT6620WiFiDriver_Prj\8 2009-05-11 17:26:33 GMT mtk01084
  75 **  modify the bit definition to check driver own status
  76 **  \main\maintrunk.MT6620WiFiDriver_Prj\7 2009-04-28 10:30:22 GMT mtk01461
  77 **  Fix typo
  78 **  \main\maintrunk.MT6620WiFiDriver_Prj\6 2009-04-01 10:50:34 GMT mtk01461
  79 **  Redefine HAL_PORT_RD/WR macro for SW pre test
  80 **  \main\maintrunk.MT6620WiFiDriver_Prj\5 2009-03-24 09:46:49 GMT mtk01084
  81 **  fix LINT error
  82 **  \main\maintrunk.MT6620WiFiDriver_Prj\4 2009-03-23 16:53:38 GMT mtk01084
  83 **  add HAL_DRIVER_OWN_BY_SDIO_CMD52()
  84 **  \main\maintrunk.MT6620WiFiDriver_Prj\3 2009-03-18 20:53:13 GMT mtk01426
  85 **  Fixed lint warn
  86 **  \main\maintrunk.MT6620WiFiDriver_Prj\2 2009-03-10 20:16:20 GMT mtk01426
  87 **  Init for develop
  88 **
  89 */
  90
  91 #ifndef _HAL_H
  92 #define _HAL_H
  93
  94 /*******************************************************************************
  95 *                         C O M P I L E R   F L A G S
  96 ********************************************************************************
  97 */
  98
  99 /*******************************************************************************
 100 *                    E X T E R N A L   R E F E R E N C E S
 101 ********************************************************************************
 102 */
 103
 104 /*******************************************************************************
 105 *                              C O N S T A N T S
 106 ********************************************************************************
 107 */
 108
 109 /*******************************************************************************
 110 *                             D A T A   T Y P E S
 111 ********************************************************************************
 112 */
 113
 114 /*******************************************************************************
 115 *                            P U B L I C   D A T A
 116 ********************************************************************************
 117 */
 118
 119 /*******************************************************************************
 120 *                           P R I V A T E   D A T A
 121 ********************************************************************************
 122 */
 123
 124 /*******************************************************************************
 125 *                                 M A C R O S
 126 ********************************************************************************
 127 */
 128
 129 /* Macros for flag operations for the Adapter structure */
 130 #define HAL_SET_FLAG(_M, _F)             ((_M)->u4HwFlags |= (_F))
 131 #define HAL_CLEAR_FLAG(_M, _F)           ((_M)->u4HwFlags &= ~(_F))
 132 #define HAL_TEST_FLAG(_M, _F)            ((_M)->u4HwFlags & (_F))
 133 #define HAL_TEST_FLAGS(_M, _F)           (((_M)->u4HwFlags & (_F)) == (_F))
 134
 135 #if defined(_HIF_SDIO)
 136 #define HAL_MCR_RD(_prAdapter, _u4Offset, _pu4Value) \
 137     { \
 138         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 139             if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 140                 ASSERT(0); \
 141             } \
 142             if (kalDevRegRead(_prAdapter->prGlueInfo, _u4Offset, _pu4Value) == FALSE) {\
 143                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 144                 fgIsBusAccessFailed = TRUE; \
 145                 DBGLOG(HAL, ERROR, ("HAL_MCR_RD access fail! 0x%x: 0x%x\n", _u4Offset, *_pu4Value)); \
 146             } \
 147         } else { \
 148             DBGLOG(HAL, WARN, ("ignore HAL_MCR_RD access! 0x%x\n", _u4Offset)); \
 149         } \
 150     }
 151
 152 #define HAL_MCR_WR(_prAdapter, _u4Offset, _u4Value) \
 153     { \
 154         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 155             if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 156                 ASSERT(0); \
 157             } \
 158             if (kalDevRegWrite(_prAdapter->prGlueInfo, _u4Offset, _u4Value) == FALSE) {\
 159                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 160                 fgIsBusAccessFailed = TRUE; \
 161                 DBGLOG(HAL, ERROR, ("HAL_MCR_WR access fail! 0x%x: 0x%x\n", _u4Offset, _u4Value)); \
 162             } \
 163         } else { \
 164             DBGLOG(HAL, WARN, ("ignore HAL_MCR_WR access! 0x%x: 0x%x\n", _u4Offset, _u4Value)); \
 165         } \
 166      }
 167
 168 #define HAL_PORT_RD(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 169     { \
 170         /*fgResult = FALSE; */\
 171         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 172             ASSERT(0); \
 173         } \
 174         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 175             if (kalDevPortRead(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) == FALSE) {\
 176                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 177                 fgIsBusAccessFailed = TRUE; \
 178                 DBGLOG(HAL, ERROR, ("HAL_PORT_RD access fail! 0x%x\n", _u4Port)); \
 179             } \
 180             else { \
 181                 /*fgResult = TRUE;*/ } \
 182         } else { \
 183             DBGLOG(HAL, WARN, ("ignore HAL_PORT_RD access! 0x%x\n", _u4Port)); \
 184         } \
 185     }
 186
 187 #define HAL_PORT_WR(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 188     { \
 189         /*fgResult = FALSE; */\
 190         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 191             ASSERT(0); \
 192         } \
 193         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 194             if (kalDevPortWrite(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) == FALSE) {\
 195                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 196                 fgIsBusAccessFailed = TRUE; \
 197                 DBGLOG(HAL, ERROR, ("HAL_PORT_WR access fail! 0x%x\n", _u4Port)); \
 198             } \
 199             else { \
 200                 /*fgResult = TRUE;*/ } \
 201         } else { \
 202             DBGLOG(HAL, WARN, ("ignore HAL_PORT_WR access! 0x%x\n", _u4Port)); \
 203         } \
 204     }
 205
 206 #define HAL_BYTE_WR(_prAdapter, _u4Port, _ucBuf) \
 207     { \
 208         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 209             ASSERT(0); \
 210         } \
 211         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 212             if (kalDevWriteWithSdioCmd52(_prAdapter->prGlueInfo, _u4Port, _ucBuf) == FALSE) {\
 213                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 214                 fgIsBusAccessFailed = TRUE; \
 215                 DBGLOG(HAL, ERROR, ("HAL_BYTE_WR access fail! 0x%x\n", _u4Port)); \
 216             } \
 217             else { \
 218             } \
 219         } \
 220         else { \
 221             DBGLOG(HAL, WARN, ("ignore HAL_BYTE_WR access! 0x%x\n", _u4Port)); \
 222         } \
 223     }
 224
 225
 226 #define HAL_DRIVER_OWN_BY_SDIO_CMD52(_prAdapter, _pfgDriverIsOwnReady) \
 227     { \
 228         UINT_8 ucBuf = BIT(1); \
 229         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 230             ASSERT(0); \
 231         } \
 232         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 233             if (kalDevReadAfterWriteWithSdioCmd52(_prAdapter->prGlueInfo, MCR_WHLPCR_BYTE1, &ucBuf, 1) == FALSE) {\
 234                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 235                 fgIsBusAccessFailed = TRUE; \
 236                 DBGLOG(HAL, ERROR, ("kalDevReadAfterWriteWithSdioCmd52 access fail!\n")); \
 237             } \
 238             else { \
 239                 *_pfgDriverIsOwnReady = (ucBuf & BIT(0)) ? TRUE : FALSE; \
 240             } \
 241         } else { \
 242             DBGLOG(HAL, WARN, ("ignore HAL_DRIVER_OWN_BY_SDIO_CMD52 access!\n")); \
 243         } \
 244     }
 245
 246 #else                           /* #if defined(_HIF_SDIO) */
 247 #define HAL_MCR_RD(_prAdapter, _u4Offset, _pu4Value) \
 248     { \
 249         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 250             ASSERT(0); \
 251         } \
 252         kalDevRegRead(_prAdapter->prGlueInfo, _u4Offset, _pu4Value); \
 253     }
 254
 255 #define HAL_MCR_WR(_prAdapter, _u4Offset, _u4Value) \
 256     { \
 257         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 258             ASSERT(0); \
 259         } \
 260         kalDevRegWrite(_prAdapter->prGlueInfo, _u4Offset, _u4Value); \
 261     }
 262
 263 #define HAL_PORT_RD(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 264     { \
 265         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 266             ASSERT(0); \
 267         } \
 268         kalDevPortRead(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize); \
 269     }
 270
 271 #define HAL_PORT_WR(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 272     { \
 273         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 274             ASSERT(0); \
 275         } \
 276         kalDevPortWrite(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize); \
 277     }
 278
 279 #define HAL_BYTE_WR(_prAdapter, _u4Port, _ucBuf) \
 280     { \
 281         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 282             ASSERT(0); \
 283         } \
 284         kalDevWriteWithSdioCmd52(_prAdapter->prGlueInfo, _u4Port, _ucBuf); \
 285     }
 286
 287 #endif                          /* #if defined(_HIF_SDIO) */
 288
 289
 290 #define HAL_READ_RX_PORT(prAdapter, u4PortId, u4Len, pvBuf, _u4ValidBufSize) \
 291     { \
 292     ASSERT(u4PortId < 2); \
 293     HAL_PORT_RD(prAdapter, \
 294         ((u4PortId == 0) ? MCR_WRDR0 : MCR_WRDR1), \
 295         u4Len, \
 296         pvBuf, \
 297         _u4ValidBufSize/*temp!!*//*4Kbyte*/) \
 298     }
 299
 300 #define HAL_WRITE_TX_PORT(_prAdapter, _ucTxPortIdx, _u4Len, _pucBuf, _u4ValidBufSize) \
 301     { \
 302     ASSERT(_ucTxPortIdx < 2); \
 303     if ((_u4ValidBufSize - _u4Len) >= sizeof(UINT_32)) { \
 304         /* fill with single dword of zero as TX-aggregation termination */ \
 305         *(PUINT_32) (&((_pucBuf)[ALIGN_4(_u4Len)])) = 0; \
 306     } \
 307     HAL_PORT_WR(_prAdapter, \
 308                 (_ucTxPortIdx == 0) ? MCR_WTDR0 : MCR_WTDR1, \
 309                 _u4Len, \
 310                 _pucBuf, \
 311                 _u4ValidBufSize/*temp!!*//*4KByte*/) \
 312     }
 313
 314 /* The macro to read the given MCR several times to check if the wait
 315    condition come true. */
 316 #define HAL_MCR_RD_AND_WAIT(_pAdapter, _offset, _pReadValue, _waitCondition, _waitDelay, _waitCount, _status) \
 317         { \
 318             UINT_32 count; \
 319             (_status) = FALSE; \
 320             for (count = 0; count < (_waitCount); count++) { \
 321                 HAL_MCR_RD((_pAdapter), (_offset), (_pReadValue)); \
 322                 if ((_waitCondition)) { \
 323                     (_status) = TRUE; \
 324                     break; \
 325                 } \
 326                 kalUdelay((_waitDelay)); \
 327             } \
 328         }
 329
 330
 331 /* The macro to write 1 to a R/S bit and read it several times to check if the
 332    command is done */
 333 #define HAL_MCR_WR_AND_WAIT(_pAdapter, _offset, _writeValue, _busyMask, _waitDelay, _waitCount, _status) \
 334         { \
 335             UINT_32 u4Temp; \
 336             UINT_32 u4Count = _waitCount; \
 337             (_status) = FALSE; \
 338             HAL_MCR_WR((_pAdapter), (_offset), (_writeValue)); \
 339             do { \
 340                 kalUdelay((_waitDelay)); \
 341                 HAL_MCR_RD((_pAdapter), (_offset), &u4Temp); \
 342                 if (!(u4Temp & (_busyMask))) { \
 343                     (_status) = TRUE; \
 344                     break; \
 345                 } \
 346                 u4Count--; \
 347             } while (u4Count); \
 348         }
 349
 350 #define HAL_GET_CHIP_ID_VER(_prAdapter, pu2ChipId, pu2Version) \
 351     { \
 352     UINT_32 u4Value; \
 353     HAL_MCR_RD(_prAdapter, \
 354         MCR_WCIR, \
 355         &u4Value); \
 356     *pu2ChipId = (UINT_16)(u4Value & WCIR_CHIP_ID); \
 357     *pu2Version = (UINT_16)(u4Value & WCIR_REVISION_ID) >> 16; \
 358     }
 359
 360 #define HAL_WAIT_WIFI_FUNC_READY(_prAdapter) \
 361     { \
 362     UINT_32 u4Value; \
 363     UINT_32 i; \
 364     for (i = 0; i < 100; i++) { \
 365         HAL_MCR_RD(_prAdapter, \
 366             MCR_WCIR, \
 367             &u4Value); \
 368          if (u4Value & WCIR_WLAN_READY) { \
 369             break; \
 370          } \
 371         NdisMSleep(10); \
 372     } \
 373     }
 374
 375 #define HAL_INTR_DISABLE(_prAdapter) \
 376     HAL_MCR_WR(_prAdapter, \
 377         MCR_WHLPCR, \
 378         WHLPCR_INT_EN_CLR)
 379
 380 #define HAL_INTR_ENABLE(_prAdapter) \
 381     HAL_MCR_WR(_prAdapter, \
 382         MCR_WHLPCR, \
 383         WHLPCR_INT_EN_SET)
 384
 385 #define HAL_INTR_ENABLE_AND_LP_OWN_SET(_prAdapter) \
 386     HAL_MCR_WR(_prAdapter, \
 387         MCR_WHLPCR, \
 388         (WHLPCR_INT_EN_SET | WHLPCR_FW_OWN_REQ_SET))
 389
 390 #define HAL_LP_OWN_SET(_prAdapter) \
 391     HAL_MCR_WR(_prAdapter, \
 392         MCR_WHLPCR, \
 393         WHLPCR_FW_OWN_REQ_SET)
 394
 395 #define HAL_LP_OWN_CLR_OK(_prAdapter, _pfgResult) \
 396     { \
 397         UINT_32 i; \
 398         UINT_32 u4RegValue; \
 399         UINT_32 u4LoopCnt = 2048 / 8; \
 400         *_pfgResult = TRUE; \
 401         /* Software get LP ownership */ \
 402         HAL_MCR_WR(_prAdapter, \
 403             MCR_WHLPCR, \
 404             WHLPCR_FW_OWN_REQ_CLR) \
 405         for (i = 0; i < u4LoopCnt; i++) { \
 406             HAL_MCR_RD(_prAdapter, MCR_WHLPCR, &u4RegValue); \
 407             if (u4RegValue & WHLPCR_IS_DRIVER_OWN) { \
 408                 break; \
 409             } \
 410             else { \
 411                 kalUdelay(8); \
 412             } \
 413         } \
 414         if (i == u4LoopCnt) { \
 415             *_pfgResult = FALSE; \
 416             /*ERRORLOG(("LP cannot be own back (%ld)", u4LoopCnt));*/ \
 417             /* check the time of LP instructions need to perform from Sleep to On */ \
 418             /*ASSERT(0); */ \
 419         } \
 420     }
 421
 422 #define HAL_GET_ABNORMAL_INTERRUPT_REASON_CODE(_prAdapter, pu4AbnormalReason) \
 423     { \
 424     HAL_MCR_RD(_prAdapter, \
 425         MCR_WASR, \
 426         pu4AbnormalReason); \
 427     }
 428
 429
 430 #define HAL_DISABLE_RX_ENHANCE_MODE(_prAdapter) \
 431     { \
 432     UINT_32 u4Value; \
 433     HAL_MCR_RD(_prAdapter, \
 434         MCR_WHCR, \
 435         &u4Value); \
 436     HAL_MCR_WR(_prAdapter, \
 437         MCR_WHCR, \
 438         u4Value & ~WHCR_RX_ENHANCE_MODE_EN); \
 439     }
 440
 441 #define HAL_ENABLE_RX_ENHANCE_MODE(_prAdapter) \
 442     { \
 443     UINT_32 u4Value; \
 444     HAL_MCR_RD(_prAdapter, \
 445         MCR_WHCR, \
 446         &u4Value); \
 447     HAL_MCR_WR(_prAdapter, \
 448         MCR_WHCR, \
 449         u4Value | WHCR_RX_ENHANCE_MODE_EN); \
 450     }
 451
 452 #define HAL_CFG_MAX_HIF_RX_LEN_NUM(_prAdapter, _ucNumOfRxLen) \
 453     { \
 454     UINT_32 u4Value, ucNum; \
 455     ucNum = ((_ucNumOfRxLen >= 16) ? 0 : _ucNumOfRxLen); \
 456     u4Value = 0; \
 457     HAL_MCR_RD(_prAdapter, \
 458         MCR_WHCR, \
 459         &u4Value); \
 460     u4Value &= ~WHCR_MAX_HIF_RX_LEN_NUM; \
 461     u4Value |= ((((UINT_32)ucNum) << 4) & WHCR_MAX_HIF_RX_LEN_NUM); \
 462     HAL_MCR_WR(_prAdapter, \
 463         MCR_WHCR, \
 464         u4Value); \
 465     }
 466
 467 #define HAL_SET_INTR_STATUS_READ_CLEAR(prAdapter) \
 468     { \
 469     UINT_32 u4Value; \
 470     HAL_MCR_RD(prAdapter, \
 471         MCR_WHCR, \
 472         &u4Value); \
 473     HAL_MCR_WR(prAdapter, \
 474         MCR_WHCR, \
 475         u4Value & ~WHCR_W_INT_CLR_CTRL); \
 476     prAdapter->prGlueInfo->rHifInfo.fgIntReadClear = TRUE;\
 477     }
 478
 479 #define HAL_SET_INTR_STATUS_WRITE_1_CLEAR(prAdapter) \
 480     { \
 481     UINT_32 u4Value; \
 482     HAL_MCR_RD(prAdapter, \
 483         MCR_WHCR, \
 484         &u4Value); \
 485     HAL_MCR_WR(prAdapter, \
 486         MCR_WHCR, \
 487         u4Value | WHCR_W_INT_CLR_CTRL); \
 488     prAdapter->prGlueInfo->rHifInfo.fgIntReadClear = FALSE;\
 489     }
 490
 491 /* Note: enhance mode structure may also carried inside the buffer,
 492          if the length of the buffer is long enough */
 493 #define HAL_READ_INTR_STATUS(prAdapter, length, pvBuf) \
 494     HAL_PORT_RD(prAdapter, \
 495         MCR_WHISR, \
 496         length, \
 497         pvBuf, \
 498         length)
 499
 500 #define HAL_READ_TX_RELEASED_COUNT(_prAdapter, aucTxReleaseCount) \
 501     { \
 502     PUINT_32 pu4Value = (PUINT_32)aucTxReleaseCount; \
 503     HAL_MCR_RD(_prAdapter, \
 504         MCR_WTSR0, \
 505         &pu4Value[0]); \
 506     HAL_MCR_RD(_prAdapter, \
 507         MCR_WTSR1, \
 508         &pu4Value[1]); \
 509     }
 510
 511 #define HAL_READ_RX_LENGTH(prAdapter, pu2Rx0Len, pu2Rx1Len) \
 512     { \
 513     UINT_32 u4Value; \
 514     u4Value = 0; \
 515     HAL_MCR_RD(prAdapter, \
 516         MCR_WRPLR, \
 517         &u4Value); \
 518     *pu2Rx0Len = (UINT_16)u4Value; \
 519     *pu2Rx1Len = (UINT_16)(u4Value >> 16); \
 520     }
 521
 522 #define HAL_GET_INTR_STATUS_FROM_ENHANCE_MODE_STRUCT(pvBuf, u2Len, pu4Status) \
 523     { \
 524     PUINT_32 pu4Buf = (PUINT_32)pvBuf; \
 525     *pu4Status = pu4Buf[0]; \
 526     }
 527
 528 #define HAL_GET_TX_STATUS_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu4BufOut, u4LenBufOut) \
 529     { \
 530     PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
 531     ASSERT(u4LenBufOut >= 8); \
 532     pu4BufOut[0] = pu4Buf[1]; \
 533     pu4BufOut[1] = pu4Buf[2]; \
 534     }
 535
 536 #define HAL_GET_RX_LENGTH_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu2Rx0Num, au2Rx0Len, pu2Rx1Num, au2Rx1Len) \
 537     { \
 538     PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
 539     ASSERT((sizeof(au2Rx0Len) / sizeof(UINT_16)) >= 16); \
 540     ASSERT((sizeof(au2Rx1Len) / sizeof(UINT_16)) >= 16); \
 541     *pu2Rx0Num = (UINT_16)pu4Buf[3]; \
 542     *pu2Rx1Num = (UINT_16)(pu4Buf[3] >> 16); \
 543     kalMemCopy(au2Rx0Len, &pu4Buf[4], 8); \
 544     kalMemCopy(au2Rx1Len, &pu4Buf[12], 8); \
 545     }
 546
 547 #define HAL_GET_MAILBOX_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu4Mailbox0, pu4Mailbox1) \
 548     { \
 549     PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
 550     *pu4Mailbox0 = (UINT_16)pu4Buf[21]; \
 551     *pu4Mailbox1 = (UINT_16)pu4Buf[22]; \
 552     }
 553
 554 #define HAL_IS_TX_DONE_INTR(u4IntrStatus) \
 555    ((u4IntrStatus & WHISR_TX_DONE_INT) ? TRUE : FALSE)
 556
 557 #define HAL_IS_RX_DONE_INTR(u4IntrStatus) \
 558     ((u4IntrStatus & (WHISR_RX0_DONE_INT | WHISR_RX1_DONE_INT)) ? TRUE : FALSE)
 559
 560 #define HAL_IS_ABNORMAL_INTR(u4IntrStatus) \
 561     ((u4IntrStatus & WHISR_ABNORMAL_INT) ? TRUE : FALSE)
 562
 563 #define HAL_IS_FW_OWNBACK_INTR(u4IntrStatus) \
 564     ((u4IntrStatus & WHISR_FW_OWN_BACK_INT) ? TRUE : FALSE)
 565
 566 #define HAL_PUT_MAILBOX(prAdapter, u4MboxId, u4Data) \
 567     { \
 568     ASSERT(u4MboxId < 2); \
 569     HAL_MCR_WR(prAdapter, \
 570         ((u4MboxId == 0) ? MCR_H2DSM0R : MCR_H2DSM1R), \
 571         u4Data); \
 572     }
 573
 574 #define HAL_GET_MAILBOX(prAdapter, u4MboxId, pu4Data) \
 575     { \
 576     ASSERT(u4MboxId < 2); \
 577     HAL_MCR_RD(prAdapter, \
 578         ((u4MboxId == 0) ? MCR_D2HRM0R : MCR_D2HRM1R), \
 579         pu4Data); \
 580     }
 581
 582 #define HAL_SET_MAILBOX_READ_CLEAR(prAdapter, fgEnableReadClear) \
 583     { \
 584         UINT_32 u4Value; \
 585         HAL_MCR_RD(prAdapter, MCR_WHCR, &u4Value);\
 586         HAL_MCR_WR(prAdapter, MCR_WHCR, \
 587                     (fgEnableReadClear) ? \
 588                         (u4Value | WHCR_W_MAILBOX_RD_CLR_EN) : \
 589                         (u4Value & ~WHCR_W_MAILBOX_RD_CLR_EN)); \
 590         prAdapter->prGlueInfo->rHifInfo.fgMbxReadClear = fgEnableReadClear;\
 591     }
 592
 593 #define HAL_GET_MAILBOX_READ_CLEAR(prAdapter) (prAdapter->prGlueInfo->rHifInfo.fgMbxReadClear)
 594
 595
 596 /*******************************************************************************
 597 *                   F U N C T I O N   D E C L A R A T I O N S
 598 ********************************************************************************
 599 */
 600
 601
 602
 603 /*******************************************************************************
 604 *                              F U N C T I O N S
 605 ********************************************************************************
 606 */
 607
 608 #endif                          /* _HAL_H */