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26319ca72e38a50bdf4542168d20f18b377d6e1c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / omap-usb-host.c
1 /**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/gpio.h>
28 #include <linux/platform_device.h>
29 #include <linux/platform_data/usb-omap.h>
30 #include <linux/pm_runtime.h>
31
32 #include "omap-usb.h"
33
34 #define USBHS_DRIVER_NAME "usbhs_omap"
35 #define OMAP_EHCI_DEVICE "ehci-omap"
36 #define OMAP_OHCI_DEVICE "ohci-omap3"
37
38 /* OMAP USBHOST Register addresses */
39
40 /* UHH Register Set */
41 #define OMAP_UHH_REVISION (0x00)
42 #define OMAP_UHH_SYSCONFIG (0x10)
43 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
44 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
45 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
46 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
47 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
48 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
49
50 #define OMAP_UHH_SYSSTATUS (0x14)
51 #define OMAP_UHH_HOSTCONFIG (0x40)
52 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
53 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
54 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
55 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
56 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
57 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
58 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
59 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
60 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
61 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
62 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
63 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
64
65 /* OMAP4-specific defines */
66 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
67 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
68 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
69 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
70 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
71
72 #define OMAP4_P1_MODE_CLEAR (3 << 16)
73 #define OMAP4_P1_MODE_TLL (1 << 16)
74 #define OMAP4_P1_MODE_HSIC (3 << 16)
75 #define OMAP4_P2_MODE_CLEAR (3 << 18)
76 #define OMAP4_P2_MODE_TLL (1 << 18)
77 #define OMAP4_P2_MODE_HSIC (3 << 18)
78
79 #define OMAP_UHH_DEBUG_CSR (0x44)
80
81 /* Values of UHH_REVISION - Note: these are not given in the TRM */
82 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
83 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
84
85 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
86 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
87
88 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
89 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
90 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
91
92
93 struct usbhs_hcd_omap {
94 int nports;
95
96 struct clk *xclk60mhsp1_ck;
97 struct clk *xclk60mhsp2_ck;
98 struct clk *utmi_p1_fck;
99 struct clk *usbhost_p1_fck;
100 struct clk *utmi_p2_fck;
101 struct clk *usbhost_p2_fck;
102 struct clk *init_60m_fclk;
103 struct clk *ehci_logic_fck;
104
105 void __iomem *uhh_base;
106
107 struct usbhs_omap_platform_data *pdata;
108
109 u32 usbhs_rev;
110 spinlock_t lock;
111 };
112 /*-------------------------------------------------------------------------*/
113
114 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
115 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
116
117 /*-------------------------------------------------------------------------*/
118
119 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
120 {
121 __raw_writel(val, base + reg);
122 }
123
124 static inline u32 usbhs_read(void __iomem *base, u32 reg)
125 {
126 return __raw_readl(base + reg);
127 }
128
129 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
130 {
131 __raw_writeb(val, base + reg);
132 }
133
134 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
135 {
136 return __raw_readb(base + reg);
137 }
138
139 /*-------------------------------------------------------------------------*/
140
141 static struct platform_device *omap_usbhs_alloc_child(const char *name,
142 struct resource *res, int num_resources, void *pdata,
143 size_t pdata_size, struct device *dev)
144 {
145 struct platform_device *child;
146 int ret;
147
148 child = platform_device_alloc(name, 0);
149
150 if (!child) {
151 dev_err(dev, "platform_device_alloc %s failed\n", name);
152 goto err_end;
153 }
154
155 ret = platform_device_add_resources(child, res, num_resources);
156 if (ret) {
157 dev_err(dev, "platform_device_add_resources failed\n");
158 goto err_alloc;
159 }
160
161 ret = platform_device_add_data(child, pdata, pdata_size);
162 if (ret) {
163 dev_err(dev, "platform_device_add_data failed\n");
164 goto err_alloc;
165 }
166
167 child->dev.dma_mask = &usbhs_dmamask;
168 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
169 child->dev.parent = dev;
170
171 ret = platform_device_add(child);
172 if (ret) {
173 dev_err(dev, "platform_device_add failed\n");
174 goto err_alloc;
175 }
176
177 return child;
178
179 err_alloc:
180 platform_device_put(child);
181
182 err_end:
183 return NULL;
184 }
185
186 static int omap_usbhs_alloc_children(struct platform_device *pdev)
187 {
188 struct device *dev = &pdev->dev;
189 struct usbhs_omap_platform_data *pdata = dev->platform_data;
190 struct platform_device *ehci;
191 struct platform_device *ohci;
192 struct resource *res;
193 struct resource resources[2];
194 int ret;
195
196 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
197 if (!res) {
198 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
199 ret = -ENODEV;
200 goto err_end;
201 }
202 resources[0] = *res;
203
204 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
205 if (!res) {
206 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
207 ret = -ENODEV;
208 goto err_end;
209 }
210 resources[1] = *res;
211
212 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
213 sizeof(*pdata), dev);
214
215 if (!ehci) {
216 dev_err(dev, "omap_usbhs_alloc_child failed\n");
217 ret = -ENOMEM;
218 goto err_end;
219 }
220
221 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
222 if (!res) {
223 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
224 ret = -ENODEV;
225 goto err_ehci;
226 }
227 resources[0] = *res;
228
229 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
230 if (!res) {
231 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
232 ret = -ENODEV;
233 goto err_ehci;
234 }
235 resources[1] = *res;
236
237 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
238 sizeof(*pdata), dev);
239 if (!ohci) {
240 dev_err(dev, "omap_usbhs_alloc_child failed\n");
241 ret = -ENOMEM;
242 goto err_ehci;
243 }
244
245 return 0;
246
247 err_ehci:
248 platform_device_unregister(ehci);
249
250 err_end:
251 return ret;
252 }
253
254 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
255 {
256 switch (pmode) {
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
258 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
259 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
260 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
261 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
262 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
263 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
264 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
265 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
266 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
267 return true;
268
269 default:
270 return false;
271 }
272 }
273
274 static int usbhs_runtime_resume(struct device *dev)
275 {
276 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
277 struct usbhs_omap_platform_data *pdata = omap->pdata;
278 unsigned long flags;
279
280 dev_dbg(dev, "usbhs_runtime_resume\n");
281
282 omap_tll_enable();
283 spin_lock_irqsave(&omap->lock, flags);
284
285 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
286 clk_enable(omap->ehci_logic_fck);
287
288 if (is_ehci_tll_mode(pdata->port_mode[0]))
289 clk_enable(omap->usbhost_p1_fck);
290 if (is_ehci_tll_mode(pdata->port_mode[1]))
291 clk_enable(omap->usbhost_p2_fck);
292
293 clk_enable(omap->utmi_p1_fck);
294 clk_enable(omap->utmi_p2_fck);
295
296 spin_unlock_irqrestore(&omap->lock, flags);
297
298 return 0;
299 }
300
301 static int usbhs_runtime_suspend(struct device *dev)
302 {
303 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
304 struct usbhs_omap_platform_data *pdata = omap->pdata;
305 unsigned long flags;
306
307 dev_dbg(dev, "usbhs_runtime_suspend\n");
308
309 spin_lock_irqsave(&omap->lock, flags);
310
311 if (is_ehci_tll_mode(pdata->port_mode[0]))
312 clk_disable(omap->usbhost_p1_fck);
313 if (is_ehci_tll_mode(pdata->port_mode[1]))
314 clk_disable(omap->usbhost_p2_fck);
315
316 clk_disable(omap->utmi_p2_fck);
317 clk_disable(omap->utmi_p1_fck);
318
319 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
320 clk_disable(omap->ehci_logic_fck);
321
322 spin_unlock_irqrestore(&omap->lock, flags);
323 omap_tll_disable();
324
325 return 0;
326 }
327
328 static void omap_usbhs_init(struct device *dev)
329 {
330 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
331 struct usbhs_omap_platform_data *pdata = omap->pdata;
332 unsigned long flags;
333 unsigned reg;
334
335 dev_dbg(dev, "starting TI HSUSB Controller\n");
336
337 if (pdata->phy_reset) {
338 if (gpio_is_valid(pdata->reset_gpio_port[0]))
339 gpio_request_one(pdata->reset_gpio_port[0],
340 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
341
342 if (gpio_is_valid(pdata->reset_gpio_port[1]))
343 gpio_request_one(pdata->reset_gpio_port[1],
344 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
345
346 /* Hold the PHY in RESET for enough time till DIR is high */
347 udelay(10);
348 }
349
350 pm_runtime_get_sync(dev);
351 spin_lock_irqsave(&omap->lock, flags);
352
353 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
354 /* setup ULPI bypass and burst configurations */
355 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
356 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
357 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
358 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
359 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
360
361 if (is_omap_usbhs_rev1(omap)) {
362 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
363 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
364 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
365 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
366 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
367 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
368
369 /* Bypass the TLL module for PHY mode operation */
370 if (pdata->single_ulpi_bypass) {
371 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
372 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
373 is_ehci_phy_mode(pdata->port_mode[1]) ||
374 is_ehci_phy_mode(pdata->port_mode[2]))
375 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
376 else
377 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
378 } else {
379 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
380 if (is_ehci_phy_mode(pdata->port_mode[0]))
381 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
382 else
383 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
384 if (is_ehci_phy_mode(pdata->port_mode[1]))
385 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
386 else
387 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
388 if (is_ehci_phy_mode(pdata->port_mode[2]))
389 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
390 else
391 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
392 }
393 } else if (is_omap_usbhs_rev2(omap)) {
394 /* Clear port mode fields for PHY mode*/
395 reg &= ~OMAP4_P1_MODE_CLEAR;
396 reg &= ~OMAP4_P2_MODE_CLEAR;
397
398 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
399 (is_ohci_port(pdata->port_mode[0])))
400 reg |= OMAP4_P1_MODE_TLL;
401 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
402 reg |= OMAP4_P1_MODE_HSIC;
403
404 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
405 (is_ohci_port(pdata->port_mode[1])))
406 reg |= OMAP4_P2_MODE_TLL;
407 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
408 reg |= OMAP4_P2_MODE_HSIC;
409 }
410
411 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
412 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
413
414 spin_unlock_irqrestore(&omap->lock, flags);
415
416 pm_runtime_put_sync(dev);
417 if (pdata->phy_reset) {
418 /* Hold the PHY in RESET for enough time till
419 * PHY is settled and ready
420 */
421 udelay(10);
422
423 if (gpio_is_valid(pdata->reset_gpio_port[0]))
424 gpio_set_value_cansleep
425 (pdata->reset_gpio_port[0], 1);
426
427 if (gpio_is_valid(pdata->reset_gpio_port[1]))
428 gpio_set_value_cansleep
429 (pdata->reset_gpio_port[1], 1);
430 }
431 }
432
433 static void omap_usbhs_deinit(struct device *dev)
434 {
435 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
436 struct usbhs_omap_platform_data *pdata = omap->pdata;
437
438 if (pdata->phy_reset) {
439 if (gpio_is_valid(pdata->reset_gpio_port[0]))
440 gpio_free(pdata->reset_gpio_port[0]);
441
442 if (gpio_is_valid(pdata->reset_gpio_port[1]))
443 gpio_free(pdata->reset_gpio_port[1]);
444 }
445 }
446
447
448 /**
449 * usbhs_omap_probe - initialize TI-based HCDs
450 *
451 * Allocates basic resources for this USB host controller.
452 */
453 static int usbhs_omap_probe(struct platform_device *pdev)
454 {
455 struct device *dev = &pdev->dev;
456 struct usbhs_omap_platform_data *pdata = dev->platform_data;
457 struct usbhs_hcd_omap *omap;
458 struct resource *res;
459 int ret = 0;
460 int i;
461
462 if (!pdata) {
463 dev_err(dev, "Missing platform data\n");
464 return -ENODEV;
465 }
466
467 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
468 if (!omap) {
469 dev_err(dev, "Memory allocation failed\n");
470 return -ENOMEM;
471 }
472
473 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
474 omap->uhh_base = devm_request_and_ioremap(dev, res);
475 if (!omap->uhh_base) {
476 dev_err(dev, "Resource request/ioremap failed\n");
477 return -EADDRNOTAVAIL;
478 }
479
480 spin_lock_init(&omap->lock);
481
482 omap->pdata = pdata;
483
484 pm_runtime_enable(dev);
485
486 platform_set_drvdata(pdev, omap);
487 pm_runtime_get_sync(dev);
488
489 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
490
491 /* we need to call runtime suspend before we update omap->nports
492 * to prevent unbalanced clk_disable()
493 */
494 pm_runtime_put_sync(dev);
495
496 switch (omap->usbhs_rev) {
497 case OMAP_USBHS_REV1:
498 omap->nports = 3;
499 break;
500 case OMAP_USBHS_REV2:
501 omap->nports = 2;
502 break;
503 default:
504 omap->nports = OMAP3_HS_USB_PORTS;
505 dev_dbg(dev,
506 "USB HOST Rev : 0x%d not recognized, assuming %d ports\n",
507 omap->usbhs_rev, omap->nports);
508 break;
509 }
510
511 for (i = 0; i < omap->nports; i++)
512 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
513 is_ehci_hsic_mode(i)) {
514 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
515 if (IS_ERR(omap->ehci_logic_fck)) {
516 ret = PTR_ERR(omap->ehci_logic_fck);
517 dev_warn(dev, "ehci_logic_fck failed:%d\n",
518 ret);
519 }
520 break;
521 }
522
523 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
524 if (IS_ERR(omap->utmi_p1_fck)) {
525 ret = PTR_ERR(omap->utmi_p1_fck);
526 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
527 goto err_end;
528 }
529
530 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
531 if (IS_ERR(omap->xclk60mhsp1_ck)) {
532 ret = PTR_ERR(omap->xclk60mhsp1_ck);
533 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
534 goto err_utmi_p1_fck;
535 }
536
537 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
538 if (IS_ERR(omap->utmi_p2_fck)) {
539 ret = PTR_ERR(omap->utmi_p2_fck);
540 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
541 goto err_xclk60mhsp1_ck;
542 }
543
544 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
545 if (IS_ERR(omap->xclk60mhsp2_ck)) {
546 ret = PTR_ERR(omap->xclk60mhsp2_ck);
547 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
548 goto err_utmi_p2_fck;
549 }
550
551 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
552 if (IS_ERR(omap->usbhost_p1_fck)) {
553 ret = PTR_ERR(omap->usbhost_p1_fck);
554 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
555 goto err_xclk60mhsp2_ck;
556 }
557
558 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
559 if (IS_ERR(omap->usbhost_p2_fck)) {
560 ret = PTR_ERR(omap->usbhost_p2_fck);
561 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
562 goto err_usbhost_p1_fck;
563 }
564
565 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
566 if (IS_ERR(omap->init_60m_fclk)) {
567 ret = PTR_ERR(omap->init_60m_fclk);
568 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
569 goto err_usbhost_p2_fck;
570 }
571
572 if (is_ehci_phy_mode(pdata->port_mode[0])) {
573 /* for OMAP3 , the clk set paretn fails */
574 ret = clk_set_parent(omap->utmi_p1_fck,
575 omap->xclk60mhsp1_ck);
576 if (ret != 0)
577 dev_err(dev, "xclk60mhsp1_ck set parent"
578 "failed error:%d\n", ret);
579 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
580 ret = clk_set_parent(omap->utmi_p1_fck,
581 omap->init_60m_fclk);
582 if (ret != 0)
583 dev_err(dev, "init_60m_fclk set parent"
584 "failed error:%d\n", ret);
585 }
586
587 if (is_ehci_phy_mode(pdata->port_mode[1])) {
588 ret = clk_set_parent(omap->utmi_p2_fck,
589 omap->xclk60mhsp2_ck);
590 if (ret != 0)
591 dev_err(dev, "xclk60mhsp2_ck set parent"
592 "failed error:%d\n", ret);
593 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
594 ret = clk_set_parent(omap->utmi_p2_fck,
595 omap->init_60m_fclk);
596 if (ret != 0)
597 dev_err(dev, "init_60m_fclk set parent"
598 "failed error:%d\n", ret);
599 }
600
601 omap_usbhs_init(dev);
602 ret = omap_usbhs_alloc_children(pdev);
603 if (ret) {
604 dev_err(dev, "omap_usbhs_alloc_children failed\n");
605 goto err_alloc;
606 }
607
608 return 0;
609
610 err_alloc:
611 omap_usbhs_deinit(&pdev->dev);
612 clk_put(omap->init_60m_fclk);
613
614 err_usbhost_p2_fck:
615 clk_put(omap->usbhost_p2_fck);
616
617 err_usbhost_p1_fck:
618 clk_put(omap->usbhost_p1_fck);
619
620 err_xclk60mhsp2_ck:
621 clk_put(omap->xclk60mhsp2_ck);
622
623 err_utmi_p2_fck:
624 clk_put(omap->utmi_p2_fck);
625
626 err_xclk60mhsp1_ck:
627 clk_put(omap->xclk60mhsp1_ck);
628
629 err_utmi_p1_fck:
630 clk_put(omap->utmi_p1_fck);
631
632 err_end:
633 clk_put(omap->ehci_logic_fck);
634 pm_runtime_disable(dev);
635
636 return ret;
637 }
638
639 /**
640 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
641 * @pdev: USB Host Controller being removed
642 *
643 * Reverses the effect of usbhs_omap_probe().
644 */
645 static int usbhs_omap_remove(struct platform_device *pdev)
646 {
647 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
648
649 omap_usbhs_deinit(&pdev->dev);
650 clk_put(omap->init_60m_fclk);
651 clk_put(omap->usbhost_p2_fck);
652 clk_put(omap->usbhost_p1_fck);
653 clk_put(omap->xclk60mhsp2_ck);
654 clk_put(omap->utmi_p2_fck);
655 clk_put(omap->xclk60mhsp1_ck);
656 clk_put(omap->utmi_p1_fck);
657 clk_put(omap->ehci_logic_fck);
658 pm_runtime_disable(&pdev->dev);
659
660 return 0;
661 }
662
663 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
664 .runtime_suspend = usbhs_runtime_suspend,
665 .runtime_resume = usbhs_runtime_resume,
666 };
667
668 static struct platform_driver usbhs_omap_driver = {
669 .driver = {
670 .name = (char *)usbhs_driver_name,
671 .owner = THIS_MODULE,
672 .pm = &usbhsomap_dev_pm_ops,
673 },
674 .remove = __exit_p(usbhs_omap_remove),
675 };
676
677 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
678 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
679 MODULE_LICENSE("GPL v2");
680 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
681
682 static int __init omap_usbhs_drvinit(void)
683 {
684 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
685 }
686
687 /*
688 * init before ehci and ohci drivers;
689 * The usbhs core driver should be initialized much before
690 * the omap ehci and ohci probe functions are called.
691 * This usbhs core driver should be initialized after
692 * usb tll driver
693 */
694 fs_initcall_sync(omap_usbhs_drvinit);
695
696 static void __exit omap_usbhs_drvexit(void)
697 {
698 platform_driver_unregister(&usbhs_omap_driver);
699 }
700 module_exit(omap_usbhs_drvexit);
kernel source for telekom puls (alcatel/mediatek)