projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / message / fusion / lsi / mpi_cnfg.h
1 /*
2 * Copyright (c) 2000-2003 LSI Logic Corporation.
3 *
4 *
5 * Name: mpi_cnfg.h
6 * Title: MPI Config message, structures, and Pages
7 * Creation Date: July 27, 2000
8 *
9 * mpi_cnfg.h Version: 01.05.xx
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17 * 06-06-00 01.00.01 Update version number for 1.0 release.
18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20 * fields to FC_DEVICE_0 page, updated the page version.
21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23 * and updated the page versions.
24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25 * page and updated the page version.
26 * Added Information field and _INFO_PARAMS_NEGOTIATED
27 * definitionto SCSI_DEVICE_0 page.
28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
29 * page version.
30 * Added BucketsRemaining to LAN_1 page, redefined the
31 * state values, and updated the page version.
32 * Revised bus width definitions in SCSI_PORT_0,
33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
35 * version.
36 * Moved FC_DEVICE_0 PageAddress description to spec.
37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38 * widths in IOC_0 page and updated the page version.
39 * 11-02-00 01.01.01 Original release for post 1.0 work
40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41 * Port Page 2, FC Port Page 4, FC Port Page 5
42 * 11-15-00 01.01.02 Interim changes to match proposals
43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44 * 12-05-00 01.01.04 Modified config page actions.
45 * 01-09-01 01.01.05 Added defines for page address formats.
46 * Data size for Manufacturing pages 2 and 3 no longer
47 * defined here.
48 * Io Unit Page 2 size is fixed at 4 adapters and some
49 * flags were changed.
50 * SCSI Port Page 2 Device Settings modified.
51 * New fields added to FC Port Page 0 and some flags
52 * cleaned up.
53 * Removed impedance flash from FC Port Page 1.
54 * Added FC Port pages 6 and 7.
55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57 * Added some LinkType defines for FcPortPage0.
58 * 02-20-01 01.01.08 Started using MPI_POINTER.
59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61 * Added definitions and structures for IOC Page 2 and
62 * RAID Volume Page 2.
63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65 * Added VendorId and ProductRevLevel fields to
66 * RAIDVOL2_IM_PHYS_ID struct.
67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68 * defines to make them compatible to MPI version 1.0.
69 * Added structure offset comments.
70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71 * removed some obsolete ones.
72 * Added IO Unit Page 3.
73 * Modified defines for Scsi Port Page 2.
74 * Modified RAID Volume Pages.
75 * 08-08-01 01.02.01 Original release for v1.2 work.
76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77 * Added defines for the SEP bits in RVP2 VolumeSettings.
78 * Modified the DeviceSettings field in RVP2 to use the
79 * proper structure.
80 * Added defines for SES, SAF-TE, and cross channel for
81 * IOCPage2 CapabilitiesFlags.
82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
83 * Removed define for
84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96 * Added rejected bits to SCSI Device Page 0 Information.
97 * Increased size of ALPA array in FC Port Page 2 by one
98 * and removed a one byte reserved field.
99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101 * Added structures for Manufacturing Page 4, IO Unit
102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103 * RAID PhysDisk Page 0.
104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105 * Modified some of the new defines to make them 32
106 * character unique.
107 * Modified how variable length pages (arrays) are defined.
108 * Added generic defines for hot spare pools and RAID
109 * volume types.
110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112 * related define, and bumped the page version define.
113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114 * reserved byte and added a define.
115 * Added define for
116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117 * Added new config page: CONFIG_PAGE_IOC_5.
118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119 * fields to CONFIG_PAGE_FC_PORT_0.
120 * Added AltConnector and NumRequestedAliases fields to
121 * CONFIG_PAGE_FC_PORT_1.
122 * Added new config page: CONFIG_PAGE_FC_PORT_10.
123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
126 * Added define for
127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135 * CONFIG_PAGE_FC_PORT_1.
136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
137 * an alias.
138 * Added more device id defines.
139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140 * Added TargetConfig and IDConfig fields to
141 * CONFIG_PAGE_SCSI_PORT_1.
142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
143 * to control DV.
144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146 * with ADISCHardALPA.
147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
148 * --------------------------------------------------------------------------
149 */
150
151 #ifndef MPI_CNFG_H
152 #define MPI_CNFG_H
153
154
155 /*****************************************************************************
156 *
157 * C o n f i g M e s s a g e a n d S t r u c t u r e s
158 *
159 *****************************************************************************/
160
161 typedef struct _CONFIG_PAGE_HEADER
162 {
163 U8 PageVersion; /* 00h */
164 U8 PageLength; /* 01h */
165 U8 PageNumber; /* 02h */
166 U8 PageType; /* 03h */
167 } fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
168 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
169
170 typedef union _CONFIG_PAGE_HEADER_UNION
171 {
172 ConfigPageHeader_t Struct;
173 U8 Bytes[4];
174 U16 Word16[2];
175 U32 Word32;
176 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
177 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
178
179 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
180 {
181 U8 PageVersion; /* 00h */
182 U8 Reserved1; /* 01h */
183 U8 PageNumber; /* 02h */
184 U8 PageType; /* 03h */
185 U16 ExtPageLength; /* 04h */
186 U8 ExtPageType; /* 06h */
187 U8 Reserved2; /* 07h */
188 } fCONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
189 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
190
191
192
193 /****************************************************************************
194 * PageType field values
195 ****************************************************************************/
196 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
197 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
198 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
199 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
200 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
201
202 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
203 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
204 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
205 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
206 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
207 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
208 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
209 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
210 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
211 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
212 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
213 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
214 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
215 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
216
217 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
218
219
220 /****************************************************************************
221 * ExtPageType field values
222 ****************************************************************************/
223 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
224 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
225 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
226 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
227
228
229 /****************************************************************************
230 * PageAddress field values
231 ****************************************************************************/
232 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
233
234 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
235 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
236 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
237 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
238
239 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
240 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
241 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
242 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
243 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
244 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
245
246 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
247 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
248 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
249 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
250 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
251 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
252 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
253 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
254 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
255 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
256 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
257 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
258 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
259
260 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
261 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
262
263 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
264 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
265 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
266 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
267 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
268 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
269 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
270 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
271 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
272 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
273 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
274 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
275 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
276
277 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x00FF0000)
278 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (16)
279 #define MPI_SAS_PHY_PGAD_DEVHANDLE_MASK (0x0000FFFF)
280 #define MPI_SAS_PHY_PGAD_DEVHANDLE_SHIFT (0)
281
282
283 /****************************************************************************
284 * Config Request Message
285 ****************************************************************************/
286 typedef struct _MSG_CONFIG
287 {
288 U8 Action; /* 00h */
289 U8 Reserved; /* 01h */
290 U8 ChainOffset; /* 02h */
291 U8 Function; /* 03h */
292 U16 ExtPageLength; /* 04h */
293 U8 ExtPageType; /* 06h */
294 U8 MsgFlags; /* 07h */
295 U32 MsgContext; /* 08h */
296 U8 Reserved2[8]; /* 0Ch */
297 fCONFIG_PAGE_HEADER Header; /* 14h */
298 U32 PageAddress; /* 18h */
299 SGE_IO_UNION PageBufferSGE; /* 1Ch */
300 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
301 Config_t, MPI_POINTER pConfig_t;
302
303
304 /****************************************************************************
305 * Action field values
306 ****************************************************************************/
307 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
308 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
309 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
310 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
311 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
312 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
313 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
314
315
316 /* Config Reply Message */
317 typedef struct _MSG_CONFIG_REPLY
318 {
319 U8 Action; /* 00h */
320 U8 Reserved; /* 01h */
321 U8 MsgLength; /* 02h */
322 U8 Function; /* 03h */
323 U16 ExtPageLength; /* 04h */
324 U8 ExtPageType; /* 06h */
325 U8 MsgFlags; /* 07h */
326 U32 MsgContext; /* 08h */
327 U8 Reserved2[2]; /* 0Ch */
328 U16 IOCStatus; /* 0Eh */
329 U32 IOCLogInfo; /* 10h */
330 fCONFIG_PAGE_HEADER Header; /* 14h */
331 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
332 ConfigReply_t, MPI_POINTER pConfigReply_t;
333
334
335
336 /*****************************************************************************
337 *
338 * C o n f i g u r a t i o n P a g e s
339 *
340 *****************************************************************************/
341
342 /****************************************************************************
343 * Manufacturing Config pages
344 ****************************************************************************/
345 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
346 /* Fibre Channel */
347 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
348 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
349 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
350 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
351 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
352 /* SCSI */
353 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
354 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
355 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
356 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
357 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
358 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
359 /* SAS */
360 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
361
362
363 typedef struct _CONFIG_PAGE_MANUFACTURING_0
364 {
365 fCONFIG_PAGE_HEADER Header; /* 00h */
366 U8 ChipName[16]; /* 04h */
367 U8 ChipRevision[8]; /* 14h */
368 U8 BoardName[16]; /* 1Ch */
369 U8 BoardAssembly[16]; /* 2Ch */
370 U8 BoardTracerNumber[16]; /* 3Ch */
371
372 } fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
373 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
374
375 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
376
377
378 typedef struct _CONFIG_PAGE_MANUFACTURING_1
379 {
380 fCONFIG_PAGE_HEADER Header; /* 00h */
381 U8 VPD[256]; /* 04h */
382 } fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
383 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
384
385 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
386
387
388 typedef struct _MPI_CHIP_REVISION_ID
389 {
390 U16 DeviceID; /* 00h */
391 U8 PCIRevisionID; /* 02h */
392 U8 Reserved; /* 03h */
393 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
394 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
395
396
397 /*
398 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
399 * one and check Header.PageLength at runtime.
400 */
401 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
402 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
403 #endif
404
405 typedef struct _CONFIG_PAGE_MANUFACTURING_2
406 {
407 fCONFIG_PAGE_HEADER Header; /* 00h */
408 MPI_CHIP_REVISION_ID ChipId; /* 04h */
409 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
410 } fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
411 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
412
413 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
414
415
416 /*
417 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
418 * one and check Header.PageLength at runtime.
419 */
420 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
421 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
422 #endif
423
424 typedef struct _CONFIG_PAGE_MANUFACTURING_3
425 {
426 fCONFIG_PAGE_HEADER Header; /* 00h */
427 MPI_CHIP_REVISION_ID ChipId; /* 04h */
428 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
429 } fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
430 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
431
432 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
433
434
435 typedef struct _CONFIG_PAGE_MANUFACTURING_4
436 {
437 fCONFIG_PAGE_HEADER Header; /* 00h */
438 U32 Reserved1; /* 04h */
439 U8 InfoOffset0; /* 08h */
440 U8 InfoSize0; /* 09h */
441 U8 InfoOffset1; /* 0Ah */
442 U8 InfoSize1; /* 0Bh */
443 U8 InquirySize; /* 0Ch */
444 U8 Flags; /* 0Dh */
445 U16 Reserved2; /* 0Eh */
446 U8 InquiryData[56]; /* 10h */
447 U32 ISVolumeSettings; /* 48h */
448 U32 IMEVolumeSettings; /* 4Ch */
449 U32 IMVolumeSettings; /* 50h */
450 } fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
451 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
452
453 #define MPI_MANUFACTURING4_PAGEVERSION (0x01)
454
455 /* defines for the Flags field */
456 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
457
458
459 typedef struct _CONFIG_PAGE_MANUFACTURING_5
460 {
461 fCONFIG_PAGE_HEADER Header; /* 00h */
462 U64 BaseWWID; /* 04h */
463 } fCONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
464 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
465
466 #define MPI_MANUFACTURING5_PAGEVERSION (0x00)
467
468
469 typedef struct _CONFIG_PAGE_MANUFACTURING_6
470 {
471 fCONFIG_PAGE_HEADER Header; /* 00h */
472 U32 ProductSpecificInfo;/* 04h */
473 } fCONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
474 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
475
476 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
477
478
479 /****************************************************************************
480 * IO Unit Config Pages
481 ****************************************************************************/
482
483 typedef struct _CONFIG_PAGE_IO_UNIT_0
484 {
485 fCONFIG_PAGE_HEADER Header; /* 00h */
486 U64 UniqueValue; /* 04h */
487 } fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
488 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
489
490 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
491
492
493 typedef struct _CONFIG_PAGE_IO_UNIT_1
494 {
495 fCONFIG_PAGE_HEADER Header; /* 00h */
496 U32 Flags; /* 04h */
497 } fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
498 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
499
500 #define MPI_IOUNITPAGE1_PAGEVERSION (0x01)
501
502 /* IO Unit Page 1 Flags defines */
503 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
504 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
505 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
506 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
507 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
508 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
509 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
510 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
511 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
512
513
514 typedef struct _MPI_ADAPTER_INFO
515 {
516 U8 PciBusNumber; /* 00h */
517 U8 PciDeviceAndFunctionNumber; /* 01h */
518 U16 AdapterFlags; /* 02h */
519 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
520 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
521
522 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
523 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
524
525 typedef struct _CONFIG_PAGE_IO_UNIT_2
526 {
527 fCONFIG_PAGE_HEADER Header; /* 00h */
528 U32 Flags; /* 04h */
529 U32 BiosVersion; /* 08h */
530 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
531 } fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
532 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
533
534 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00)
535
536 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
537 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
538 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
539 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
540
541 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
542 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
543 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
544 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
545
546
547 /*
548 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
549 * one and check Header.PageLength at runtime.
550 */
551 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
552 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
553 #endif
554
555 typedef struct _CONFIG_PAGE_IO_UNIT_3
556 {
557 fCONFIG_PAGE_HEADER Header; /* 00h */
558 U8 GPIOCount; /* 04h */
559 U8 Reserved1; /* 05h */
560 U16 Reserved2; /* 06h */
561 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
562 } fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
563 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
564
565 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
566
567 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
568 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
569 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
570 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
571
572
573 /****************************************************************************
574 * IOC Config Pages
575 ****************************************************************************/
576
577 typedef struct _CONFIG_PAGE_IOC_0
578 {
579 fCONFIG_PAGE_HEADER Header; /* 00h */
580 U32 TotalNVStore; /* 04h */
581 U32 FreeNVStore; /* 08h */
582 U16 VendorID; /* 0Ch */
583 U16 DeviceID; /* 0Eh */
584 U8 RevisionID; /* 10h */
585 U8 Reserved[3]; /* 11h */
586 U32 ClassCode; /* 14h */
587 U16 SubsystemVendorID; /* 18h */
588 U16 SubsystemID; /* 1Ah */
589 } fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
590 IOCPage0_t, MPI_POINTER pIOCPage0_t;
591
592 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
593
594
595 typedef struct _CONFIG_PAGE_IOC_1
596 {
597 fCONFIG_PAGE_HEADER Header; /* 00h */
598 U32 Flags; /* 04h */
599 U32 CoalescingTimeout; /* 08h */
600 U8 CoalescingDepth; /* 0Ch */
601 U8 PCISlotNum; /* 0Dh */
602 U8 Reserved[2]; /* 0Eh */
603 } fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
604 IOCPage1_t, MPI_POINTER pIOCPage1_t;
605
606 #define MPI_IOCPAGE1_PAGEVERSION (0x01)
607
608 /* defines for the Flags field */
609 #define MPI_IOCPAGE1_EEDP_HOST_SUPPORTS_DIF (0x08000000)
610 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
611 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
612 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
613 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
614 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
615
616 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
617
618
619 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
620 {
621 U8 VolumeID; /* 00h */
622 U8 VolumeBus; /* 01h */
623 U8 VolumeIOC; /* 02h */
624 U8 VolumePageNumber; /* 03h */
625 U8 VolumeType; /* 04h */
626 U8 Flags; /* 05h */
627 U16 Reserved3; /* 06h */
628 } fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
629 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
630
631 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
632
633 #define MPI_RAID_VOL_TYPE_IS (0x00)
634 #define MPI_RAID_VOL_TYPE_IME (0x01)
635 #define MPI_RAID_VOL_TYPE_IM (0x02)
636
637 /* IOC Page 2 Volume Flags values */
638
639 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
640
641 /*
642 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
643 * one and check Header.PageLength at runtime.
644 */
645 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
646 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
647 #endif
648
649 typedef struct _CONFIG_PAGE_IOC_2
650 {
651 fCONFIG_PAGE_HEADER Header; /* 00h */
652 U32 CapabilitiesFlags; /* 04h */
653 U8 NumActiveVolumes; /* 08h */
654 U8 MaxVolumes; /* 09h */
655 U8 NumActivePhysDisks; /* 0Ah */
656 U8 MaxPhysDisks; /* 0Bh */
657 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
658 } fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
659 IOCPage2_t, MPI_POINTER pIOCPage2_t;
660
661 #define MPI_IOCPAGE2_PAGEVERSION (0x02)
662
663 /* IOC Page 2 Capabilities flags */
664
665 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
666 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
667 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
668 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
669 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
670 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
671
672
673 typedef struct _IOC_3_PHYS_DISK
674 {
675 U8 PhysDiskID; /* 00h */
676 U8 PhysDiskBus; /* 01h */
677 U8 PhysDiskIOC; /* 02h */
678 U8 PhysDiskNum; /* 03h */
679 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
680 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
681
682 /*
683 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
684 * one and check Header.PageLength at runtime.
685 */
686 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
687 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
688 #endif
689
690 typedef struct _CONFIG_PAGE_IOC_3
691 {
692 fCONFIG_PAGE_HEADER Header; /* 00h */
693 U8 NumPhysDisks; /* 04h */
694 U8 Reserved1; /* 05h */
695 U16 Reserved2; /* 06h */
696 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
697 } fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
698 IOCPage3_t, MPI_POINTER pIOCPage3_t;
699
700 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
701
702
703 typedef struct _IOC_4_SEP
704 {
705 U8 SEPTargetID; /* 00h */
706 U8 SEPBus; /* 01h */
707 U16 Reserved; /* 02h */
708 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
709 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
710
711 /*
712 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
713 * one and check Header.PageLength at runtime.
714 */
715 #ifndef MPI_IOC_PAGE_4_SEP_MAX
716 #define MPI_IOC_PAGE_4_SEP_MAX (1)
717 #endif
718
719 typedef struct _CONFIG_PAGE_IOC_4
720 {
721 fCONFIG_PAGE_HEADER Header; /* 00h */
722 U8 ActiveSEP; /* 04h */
723 U8 MaxSEP; /* 05h */
724 U16 Reserved1; /* 06h */
725 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
726 } fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
727 IOCPage4_t, MPI_POINTER pIOCPage4_t;
728
729 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
730
731
732 typedef struct _IOC_5_HOT_SPARE
733 {
734 U8 PhysDiskNum; /* 00h */
735 U8 Reserved; /* 01h */
736 U8 HotSparePool; /* 02h */
737 U8 Flags; /* 03h */
738 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
739 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
740
741 /* IOC Page 5 HotSpare Flags */
742 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
743
744 /*
745 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
746 * one and check Header.PageLength at runtime.
747 */
748 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
749 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
750 #endif
751
752 typedef struct _CONFIG_PAGE_IOC_5
753 {
754 fCONFIG_PAGE_HEADER Header; /* 00h */
755 U32 Reserved1; /* 04h */
756 U8 NumHotSpares; /* 08h */
757 U8 Reserved2; /* 09h */
758 U16 Reserved3; /* 0Ah */
759 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
760 } fCONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
761 IOCPage5_t, MPI_POINTER pIOCPage5_t;
762
763 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
764
765
766 /****************************************************************************
767 * BIOS Port Config Pages
768 ****************************************************************************/
769
770 typedef struct _CONFIG_PAGE_BIOS_1
771 {
772 fCONFIG_PAGE_HEADER Header; /* 00h */
773 U32 BiosOptions; /* 04h */
774 U32 IOCSettings; /* 08h */
775 U32 Reserved1; /* 0Ch */
776 U32 DeviceSettings; /* 10h */
777 U16 NumberOfDevices; /* 14h */
778 U16 Reserved2; /* 16h */
779 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
780 U16 IOTimeoutSequential; /* 1Ah */
781 U16 IOTimeoutOther; /* 1Ch */
782 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
783 } fCONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
784 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
785
786 #define MPI_BIOSPAGE1_PAGEVERSION (0x00)
787
788 /* values for the BiosOptions field */
789 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
790 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
791 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
792 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
793
794 /* values for the IOCSettings field */
795 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
796 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
797
798 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
799 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
800 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
801 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
802
803 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
804 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
805 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
806 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
807 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
808
809 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
810
811 /* values for the DeviceSettings field */
812 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
813 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
814 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
815 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
816
817
818 /****************************************************************************
819 * SCSI Port Config Pages
820 ****************************************************************************/
821
822 typedef struct _CONFIG_PAGE_SCSI_PORT_0
823 {
824 fCONFIG_PAGE_HEADER Header; /* 00h */
825 U32 Capabilities; /* 04h */
826 U32 PhysicalInterface; /* 08h */
827 } fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
828 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
829
830 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01)
831
832 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
833 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
834 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
835 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
836 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
837 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
838 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
839 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
840 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
841 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
842 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
843 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
844 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
845
846 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
847 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
848 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \
849 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
850 )
851 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
852 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
853 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
854 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \
855 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
856 )
857 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
858 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
859
860 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
861 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
862 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
863 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
864 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
865 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
866 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
867 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
868
869
870 typedef struct _CONFIG_PAGE_SCSI_PORT_1
871 {
872 fCONFIG_PAGE_HEADER Header; /* 00h */
873 U32 Configuration; /* 04h */
874 U32 OnBusTimerValue; /* 08h */
875 U8 TargetConfig; /* 0Ch */
876 U8 Reserved1; /* 0Dh */
877 U16 IDConfig; /* 0Eh */
878 } fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
879 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
880
881 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
882
883 /* Configuration values */
884 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
885 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
886 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
887
888 /* TargetConfig values */
889 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
890 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
891
892
893 typedef struct _MPI_DEVICE_INFO
894 {
895 U8 Timeout; /* 00h */
896 U8 SyncFactor; /* 01h */
897 U16 DeviceFlags; /* 02h */
898 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
899 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
900
901 typedef struct _CONFIG_PAGE_SCSI_PORT_2
902 {
903 fCONFIG_PAGE_HEADER Header; /* 00h */
904 U32 PortFlags; /* 04h */
905 U32 PortSettings; /* 08h */
906 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
907 } fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
908 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
909
910 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
911
912 /* PortFlags values */
913 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
914 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
915 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
916 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
917
918 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
919 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
920 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
921 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
922
923
924 /* PortSettings values */
925 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
926 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
927 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
928 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
929 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
930 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
931 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
932 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
933 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
934 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
935 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
936 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
937 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
938 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
939 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
940 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
941
942 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
943 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
944 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
945 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
946 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
947 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
948
949
950 /****************************************************************************
951 * SCSI Target Device Config Pages
952 ****************************************************************************/
953
954 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
955 {
956 fCONFIG_PAGE_HEADER Header; /* 00h */
957 U32 NegotiatedParameters; /* 04h */
958 U32 Information; /* 08h */
959 } fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
960 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
961
962 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03)
963
964 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
965 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
966 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
967 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
968 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
969 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
970 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
971 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
972 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
973 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
974 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
975 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
976 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
977 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
978
979 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
980 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
981 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
982 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
983
984
985 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
986 {
987 fCONFIG_PAGE_HEADER Header; /* 00h */
988 U32 RequestedParameters; /* 04h */
989 U32 Reserved; /* 08h */
990 U32 Configuration; /* 0Ch */
991 } fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
992 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
993
994 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04)
995
996 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
997 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
998 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
999 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1000 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1001 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1002 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1003 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1004 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1005 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1006 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1007 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1008 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1009 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1010
1011 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1012 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1013 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1014 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1015
1016
1017 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1018 {
1019 fCONFIG_PAGE_HEADER Header; /* 00h */
1020 U32 DomainValidation; /* 04h */
1021 U32 ParityPipeSelect; /* 08h */
1022 U32 DataPipeSelect; /* 0Ch */
1023 } fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1024 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1025
1026 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1027
1028 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1029 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1030 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1031 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1032 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1033 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1034 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1035 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1036 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1037
1038 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1039
1040 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1041 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1042 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1043 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1044 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1045 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1046 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1047 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1048 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1049 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1050 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1051 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1052 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1053 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1054 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1055 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1056
1057
1058 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1059 {
1060 fCONFIG_PAGE_HEADER Header; /* 00h */
1061 U16 MsgRejectCount; /* 04h */
1062 U16 PhaseErrorCount; /* 06h */
1063 U16 ParityErrorCount; /* 08h */
1064 U16 Reserved; /* 0Ah */
1065 } fCONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1066 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1067
1068 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1069
1070 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1071 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1072
1073
1074 /****************************************************************************
1075 * FC Port Config Pages
1076 ****************************************************************************/
1077
1078 typedef struct _CONFIG_PAGE_FC_PORT_0
1079 {
1080 fCONFIG_PAGE_HEADER Header; /* 00h */
1081 U32 Flags; /* 04h */
1082 U8 MPIPortNumber; /* 08h */
1083 U8 LinkType; /* 09h */
1084 U8 PortState; /* 0Ah */
1085 U8 Reserved; /* 0Bh */
1086 U32 PortIdentifier; /* 0Ch */
1087 U64 WWNN; /* 10h */
1088 U64 WWPN; /* 18h */
1089 U32 SupportedServiceClass; /* 20h */
1090 U32 SupportedSpeeds; /* 24h */
1091 U32 CurrentSpeed; /* 28h */
1092 U32 MaxFrameSize; /* 2Ch */
1093 U64 FabricWWNN; /* 30h */
1094 U64 FabricWWPN; /* 38h */
1095 U32 DiscoveredPortsCount; /* 40h */
1096 U32 MaxInitiators; /* 44h */
1097 U8 MaxAliasesSupported; /* 48h */
1098 U8 MaxHardAliasesSupported; /* 49h */
1099 U8 NumCurrentAliases; /* 4Ah */
1100 U8 Reserved1; /* 4Bh */
1101 } fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1102 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1103
1104 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1105
1106 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1107 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1108 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1109 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1110 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1111
1112 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1113 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1114 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1115
1116 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1117 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1118 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1119 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1120 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1121 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1122
1123 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1124 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1125 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1126 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1127 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1128 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1129 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1130 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1131 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1132 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1133 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1134 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1135 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1136 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1137 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1138 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1139
1140 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1141 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1142 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1143 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1144 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1145 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1146 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1147 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1148
1149 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1150 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1151 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1152
1153 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1154 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1155 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1156 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1157 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1158
1159 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1160 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1161 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1162 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1163 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1164 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1165
1166
1167
1168 typedef struct _CONFIG_PAGE_FC_PORT_1
1169 {
1170 fCONFIG_PAGE_HEADER Header; /* 00h */
1171 U32 Flags; /* 04h */
1172 U64 NoSEEPROMWWNN; /* 08h */
1173 U64 NoSEEPROMWWPN; /* 10h */
1174 U8 HardALPA; /* 18h */
1175 U8 LinkConfig; /* 19h */
1176 U8 TopologyConfig; /* 1Ah */
1177 U8 AltConnector; /* 1Bh */
1178 U8 NumRequestedAliases; /* 1Ch */
1179 U8 RR_TOV; /* 1Dh */
1180 U8 InitiatorDeviceTimeout; /* 1Eh */
1181 U8 InitiatorIoPendTimeout; /* 1Fh */
1182 } fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1183 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1184
1185 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1186
1187 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1188 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1189 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1190 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1191 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1192 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1193 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1194 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1195 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1196 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1197 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1198 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1199 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1200
1201 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1202 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1203 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1204 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1205 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1206 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1207
1208 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1209 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1210 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1211 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1212
1213 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1214
1215 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1216 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1217 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1218 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1219 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1220 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1221
1222 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1223 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1224 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1225 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1226
1227 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1228
1229 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1230
1231
1232 typedef struct _CONFIG_PAGE_FC_PORT_2
1233 {
1234 fCONFIG_PAGE_HEADER Header; /* 00h */
1235 U8 NumberActive; /* 04h */
1236 U8 ALPA[127]; /* 05h */
1237 } fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1238 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1239
1240 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1241
1242
1243 typedef struct _WWN_FORMAT
1244 {
1245 U64 WWNN; /* 00h */
1246 U64 WWPN; /* 08h */
1247 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1248 WWNFormat, MPI_POINTER pWWNFormat;
1249
1250 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1251 {
1252 WWN_FORMAT WWN;
1253 U32 Did;
1254 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1255 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1256
1257 typedef struct _FC_PORT_PERSISTENT
1258 {
1259 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1260 U8 TargetID; /* 10h */
1261 U8 Bus; /* 11h */
1262 U16 Flags; /* 12h */
1263 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1264 PersistentData_t, MPI_POINTER pPersistentData_t;
1265
1266 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1267 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1268 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1269 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1270 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1271 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1272
1273 /*
1274 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1275 * one and check Header.PageLength at runtime.
1276 */
1277 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1278 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1279 #endif
1280
1281 typedef struct _CONFIG_PAGE_FC_PORT_3
1282 {
1283 fCONFIG_PAGE_HEADER Header; /* 00h */
1284 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1285 } fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1286 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1287
1288 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1289
1290
1291 typedef struct _CONFIG_PAGE_FC_PORT_4
1292 {
1293 fCONFIG_PAGE_HEADER Header; /* 00h */
1294 U32 PortFlags; /* 04h */
1295 U32 PortSettings; /* 08h */
1296 } fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1297 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1298
1299 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1300
1301 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1302
1303 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1304 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1305 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1306 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1307 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1308 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1309 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1310
1311
1312 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1313 {
1314 U8 Flags; /* 00h */
1315 U8 AliasAlpa; /* 01h */
1316 U16 Reserved; /* 02h */
1317 U64 AliasWWNN; /* 04h */
1318 U64 AliasWWPN; /* 0Ch */
1319 } fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1320 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1321 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1322
1323 typedef struct _CONFIG_PAGE_FC_PORT_5
1324 {
1325 fCONFIG_PAGE_HEADER Header; /* 00h */
1326 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1327 } fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1328 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1329
1330 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1331
1332 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1333 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1334 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1335 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1336 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1337
1338 typedef struct _CONFIG_PAGE_FC_PORT_6
1339 {
1340 fCONFIG_PAGE_HEADER Header; /* 00h */
1341 U32 Reserved; /* 04h */
1342 U64 TimeSinceReset; /* 08h */
1343 U64 TxFrames; /* 10h */
1344 U64 RxFrames; /* 18h */
1345 U64 TxWords; /* 20h */
1346 U64 RxWords; /* 28h */
1347 U64 LipCount; /* 30h */
1348 U64 NosCount; /* 38h */
1349 U64 ErrorFrames; /* 40h */
1350 U64 DumpedFrames; /* 48h */
1351 U64 LinkFailureCount; /* 50h */
1352 U64 LossOfSyncCount; /* 58h */
1353 U64 LossOfSignalCount; /* 60h */
1354 U64 PrimativeSeqErrCount; /* 68h */
1355 U64 InvalidTxWordCount; /* 70h */
1356 U64 InvalidCrcCount; /* 78h */
1357 U64 FcpInitiatorIoCount; /* 80h */
1358 } fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1359 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1360
1361 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1362
1363
1364 typedef struct _CONFIG_PAGE_FC_PORT_7
1365 {
1366 fCONFIG_PAGE_HEADER Header; /* 00h */
1367 U32 Reserved; /* 04h */
1368 U8 PortSymbolicName[256]; /* 08h */
1369 } fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1370 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1371
1372 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1373
1374
1375 typedef struct _CONFIG_PAGE_FC_PORT_8
1376 {
1377 fCONFIG_PAGE_HEADER Header; /* 00h */
1378 U32 BitVector[8]; /* 04h */
1379 } fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1380 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1381
1382 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1383
1384
1385 typedef struct _CONFIG_PAGE_FC_PORT_9
1386 {
1387 fCONFIG_PAGE_HEADER Header; /* 00h */
1388 U32 Reserved; /* 04h */
1389 U64 GlobalWWPN; /* 08h */
1390 U64 GlobalWWNN; /* 10h */
1391 U32 UnitType; /* 18h */
1392 U32 PhysicalPortNumber; /* 1Ch */
1393 U32 NumAttachedNodes; /* 20h */
1394 U16 IPVersion; /* 24h */
1395 U16 UDPPortNumber; /* 26h */
1396 U8 IPAddress[16]; /* 28h */
1397 U16 Reserved1; /* 38h */
1398 U16 TopologyDiscoveryFlags; /* 3Ah */
1399 } fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1400 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1401
1402 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1403
1404
1405 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1406 {
1407 U8 Id; /* 10h */
1408 U8 ExtId; /* 11h */
1409 U8 Connector; /* 12h */
1410 U8 Transceiver[8]; /* 13h */
1411 U8 Encoding; /* 1Bh */
1412 U8 BitRate_100mbs; /* 1Ch */
1413 U8 Reserved1; /* 1Dh */
1414 U8 Length9u_km; /* 1Eh */
1415 U8 Length9u_100m; /* 1Fh */
1416 U8 Length50u_10m; /* 20h */
1417 U8 Length62p5u_10m; /* 21h */
1418 U8 LengthCopper_m; /* 22h */
1419 U8 Reseverved2; /* 22h */
1420 U8 VendorName[16]; /* 24h */
1421 U8 Reserved3; /* 34h */
1422 U8 VendorOUI[3]; /* 35h */
1423 U8 VendorPN[16]; /* 38h */
1424 U8 VendorRev[4]; /* 48h */
1425 U16 Reserved4; /* 4Ch */
1426 U8 Reserved5; /* 4Eh */
1427 U8 CC_BASE; /* 4Fh */
1428 } fCONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1429 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1430 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1431
1432 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
1433 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
1434 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
1435 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
1436 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
1437 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
1438 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1439
1440 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
1441 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
1442 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
1443 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
1444 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
1445 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
1446 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
1447 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
1448 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1449
1450 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
1451 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
1452 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
1453 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
1454 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
1455 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
1456 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
1457 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
1458 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
1459 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
1460 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
1461 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
1462 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
1463 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
1464 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
1465 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
1466 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
1467 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
1468 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
1469
1470 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
1471 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
1472 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
1473 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
1474 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
1475
1476
1477 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
1478 {
1479 U8 Options[2]; /* 50h */
1480 U8 BitRateMax; /* 52h */
1481 U8 BitRateMin; /* 53h */
1482 U8 VendorSN[16]; /* 54h */
1483 U8 DateCode[8]; /* 64h */
1484 U8 Reserved5[3]; /* 6Ch */
1485 U8 CC_EXT; /* 6Fh */
1486 } fCONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1487 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1488 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
1489
1490 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
1491 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
1492 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
1493 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
1494 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
1495
1496
1497 typedef struct _CONFIG_PAGE_FC_PORT_10
1498 {
1499 fCONFIG_PAGE_HEADER Header; /* 00h */
1500 U8 Flags; /* 04h */
1501 U8 Reserved1; /* 05h */
1502 U16 Reserved2; /* 06h */
1503 U32 HwConfig1; /* 08h */
1504 U32 HwConfig2; /* 0Ch */
1505 fCONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
1506 fCONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
1507 U8 VendorSpecific[32]; /* 70h */
1508 } fCONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
1509 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
1510
1511 #define MPI_FCPORTPAGE10_PAGEVERSION (0x00)
1512
1513 /* standard MODDEF pin definitions (from GBIC spec.) */
1514 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
1515 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
1516 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
1517 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
1518 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
1519 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
1520 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
1521 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
1522 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
1523 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
1524 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
1525 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
1526
1527 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
1528 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
1529
1530
1531 /****************************************************************************
1532 * FC Device Config Pages
1533 ****************************************************************************/
1534
1535 typedef struct _CONFIG_PAGE_FC_DEVICE_0
1536 {
1537 fCONFIG_PAGE_HEADER Header; /* 00h */
1538 U64 WWNN; /* 04h */
1539 U64 WWPN; /* 0Ch */
1540 U32 PortIdentifier; /* 14h */
1541 U8 Protocol; /* 18h */
1542 U8 Flags; /* 19h */
1543 U16 BBCredit; /* 1Ah */
1544 U16 MaxRxFrameSize; /* 1Ch */
1545 U8 ADISCHardALPA; /* 1Eh */
1546 U8 PortNumber; /* 1Fh */
1547 U8 FcPhLowestVersion; /* 20h */
1548 U8 FcPhHighestVersion; /* 21h */
1549 U8 CurrentTargetID; /* 22h */
1550 U8 CurrentBus; /* 23h */
1551 } fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1552 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1553
1554 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
1555
1556 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
1557 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
1558 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
1559
1560 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
1561 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
1562 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
1563 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
1564
1565 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
1566 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
1567 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
1568 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
1569 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
1570 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
1571 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
1572 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
1573
1574 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
1575
1576 /****************************************************************************
1577 * RAID Volume Config Pages
1578 ****************************************************************************/
1579
1580 typedef struct _RAID_VOL0_PHYS_DISK
1581 {
1582 U16 Reserved; /* 00h */
1583 U8 PhysDiskMap; /* 02h */
1584 U8 PhysDiskNum; /* 03h */
1585 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
1586 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
1587
1588 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1589 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1590
1591 typedef struct _RAID_VOL0_STATUS
1592 {
1593 U8 Flags; /* 00h */
1594 U8 State; /* 01h */
1595 U16 Reserved; /* 02h */
1596 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1597 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1598
1599 /* RAID Volume Page 0 VolumeStatus defines */
1600
1601 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
1602 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
1603 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
1604 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
1605
1606 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
1607 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
1608 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
1609
1610 typedef struct _RAID_VOL0_SETTINGS
1611 {
1612 U16 Settings; /* 00h */
1613 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
1614 U8 Reserved; /* 02h */
1615 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
1616 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
1617
1618 /* RAID Volume Page 0 VolumeSettings defines */
1619
1620 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
1621 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
1622 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
1623 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
1624 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
1625 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
1626
1627 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1628 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
1629 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
1630 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
1631 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
1632 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
1633 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
1634 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
1635 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
1636
1637 /*
1638 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1639 * one and check Header.PageLength at runtime.
1640 */
1641 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
1642 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1643 #endif
1644
1645 typedef struct _CONFIG_PAGE_RAID_VOL_0
1646 {
1647 fCONFIG_PAGE_HEADER Header; /* 00h */
1648 U8 VolumeID; /* 04h */
1649 U8 VolumeBus; /* 05h */
1650 U8 VolumeIOC; /* 06h */
1651 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
1652 RAID_VOL0_STATUS VolumeStatus; /* 08h */
1653 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
1654 U32 MaxLBA; /* 10h */
1655 U32 Reserved1; /* 14h */
1656 U32 StripeSize; /* 18h */
1657 U32 Reserved2; /* 1Ch */
1658 U32 Reserved3; /* 20h */
1659 U8 NumPhysDisks; /* 24h */
1660 U8 Reserved4; /* 25h */
1661 U16 Reserved5; /* 26h */
1662 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
1663 } fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
1664 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
1665
1666 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01)
1667
1668
1669 /****************************************************************************
1670 * RAID Physical Disk Config Pages
1671 ****************************************************************************/
1672
1673 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
1674 {
1675 U8 ErrorCdbByte; /* 00h */
1676 U8 ErrorSenseKey; /* 01h */
1677 U16 Reserved; /* 02h */
1678 U16 ErrorCount; /* 04h */
1679 U8 ErrorASC; /* 06h */
1680 U8 ErrorASCQ; /* 07h */
1681 U16 SmartCount; /* 08h */
1682 U8 SmartASC; /* 0Ah */
1683 U8 SmartASCQ; /* 0Bh */
1684 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
1685 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
1686
1687 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
1688 {
1689 U8 VendorID[8]; /* 00h */
1690 U8 ProductID[16]; /* 08h */
1691 U8 ProductRevLevel[4]; /* 18h */
1692 U8 Info[32]; /* 1Ch */
1693 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
1694 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
1695
1696 typedef struct _RAID_PHYS_DISK0_SETTINGS
1697 {
1698 U8 SepID; /* 00h */
1699 U8 SepBus; /* 01h */
1700 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
1701 U8 PhysDiskSettings; /* 03h */
1702 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
1703 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
1704
1705 typedef struct _RAID_PHYS_DISK0_STATUS
1706 {
1707 U8 Flags; /* 00h */
1708 U8 State; /* 01h */
1709 U16 Reserved; /* 02h */
1710 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
1711 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
1712
1713 /* RAID Volume 2 IM Physical Disk DiskStatus flags */
1714
1715 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
1716 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
1717
1718 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
1719 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
1720 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
1721 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
1722 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
1723 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
1724 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
1725 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
1726
1727 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
1728 {
1729 fCONFIG_PAGE_HEADER Header; /* 00h */
1730 U8 PhysDiskID; /* 04h */
1731 U8 PhysDiskBus; /* 05h */
1732 U8 PhysDiskIOC; /* 06h */
1733 U8 PhysDiskNum; /* 07h */
1734 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
1735 U32 Reserved1; /* 0Ch */
1736 U32 Reserved2; /* 10h */
1737 U32 Reserved3; /* 14h */
1738 U8 DiskIdentifier[16]; /* 18h */
1739 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
1740 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
1741 U32 MaxLBA; /* 68h */
1742 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
1743 } fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
1744 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
1745
1746 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00)
1747
1748
1749 /****************************************************************************
1750 * LAN Config Pages
1751 ****************************************************************************/
1752
1753 typedef struct _CONFIG_PAGE_LAN_0
1754 {
1755 ConfigPageHeader_t Header; /* 00h */
1756 U16 TxRxModes; /* 04h */
1757 U16 Reserved; /* 06h */
1758 U32 PacketPrePad; /* 08h */
1759 } fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
1760 LANPage0_t, MPI_POINTER pLANPage0_t;
1761
1762 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
1763
1764 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
1765 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
1766 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
1767
1768 typedef struct _CONFIG_PAGE_LAN_1
1769 {
1770 ConfigPageHeader_t Header; /* 00h */
1771 U16 Reserved; /* 04h */
1772 U8 CurrentDeviceState; /* 06h */
1773 U8 Reserved1; /* 07h */
1774 U32 MinPacketSize; /* 08h */
1775 U32 MaxPacketSize; /* 0Ch */
1776 U32 HardwareAddressLow; /* 10h */
1777 U32 HardwareAddressHigh; /* 14h */
1778 U32 MaxWireSpeedLow; /* 18h */
1779 U32 MaxWireSpeedHigh; /* 1Ch */
1780 U32 BucketsRemaining; /* 20h */
1781 U32 MaxReplySize; /* 24h */
1782 U32 NegWireSpeedLow; /* 28h */
1783 U32 NegWireSpeedHigh; /* 2Ch */
1784 } fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
1785 LANPage1_t, MPI_POINTER pLANPage1_t;
1786
1787 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
1788
1789 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
1790 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
1791
1792
1793 /****************************************************************************
1794 * Inband Config Pages
1795 ****************************************************************************/
1796
1797 typedef struct _CONFIG_PAGE_INBAND_0
1798 {
1799 fCONFIG_PAGE_HEADER Header; /* 00h */
1800 MPI_VERSION_FORMAT InbandVersion; /* 04h */
1801 U16 MaximumBuffers; /* 08h */
1802 U16 Reserved1; /* 0Ah */
1803 } fCONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
1804 InbandPage0_t, MPI_POINTER pInbandPage0_t;
1805
1806 #define MPI_INBAND_PAGEVERSION (0x00)
1807
1808
1809
1810 /****************************************************************************
1811 * SAS IO Unit Config Pages
1812 ****************************************************************************/
1813
1814 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
1815 {
1816 U8 Port; /* 00h */
1817 U8 PortFlags; /* 01h */
1818 U8 PhyFlags; /* 02h */
1819 U8 NegotiatedLinkRate; /* 03h */
1820 U32 ControllerPhyDeviceInfo;/* 04h */
1821 U16 AttachedDeviceHandle; /* 08h */
1822 U16 ControllerDevHandle; /* 0Ah */
1823 U32 Reserved2; /* 0Ch */
1824 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
1825 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
1826
1827 /*
1828 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1829 * one and check Header.PageLength at runtime.
1830 */
1831 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
1832 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
1833 #endif
1834
1835 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
1836 {
1837 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
1838 U32 Reserved1; /* 08h */
1839 U8 NumPhys; /* 0Ch */
1840 U8 Reserved2; /* 0Dh */
1841 U16 Reserved3; /* 0Eh */
1842 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
1843 } fCONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
1844 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
1845
1846 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x00)
1847
1848 /* values for SAS IO Unit Page 0 PortFlags */
1849 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
1850 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
1851 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
1852 #define MPI_SAS_IOUNIT0_PORT_FLAGS_WAIT_FOR_PORTENABLE (0x02)
1853 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1854
1855 /* values for SAS IO Unit Page 0 PhyFlags */
1856 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
1857 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
1858 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
1859
1860 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
1861 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
1862 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
1863 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
1864 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
1865 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
1866 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
1867
1868 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1869
1870
1871 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
1872 {
1873 U8 Port; /* 00h */
1874 U8 PortFlags; /* 01h */
1875 U8 PhyFlags; /* 02h */
1876 U8 MaxMinLinkRate; /* 03h */
1877 U32 ControllerPhyDeviceInfo;/* 04h */
1878 U32 Reserved1; /* 08h */
1879 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
1880 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
1881
1882 /*
1883 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1884 * one and check Header.PageLength at runtime.
1885 */
1886 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
1887 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
1888 #endif
1889
1890 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
1891 {
1892 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
1893 U32 Reserved1; /* 08h */
1894 U8 NumPhys; /* 0Ch */
1895 U8 Reserved2; /* 0Dh */
1896 U16 Reserved3; /* 0Eh */
1897 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 10h */
1898 } fCONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
1899 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
1900
1901 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x00)
1902
1903 /* values for SAS IO Unit Page 0 PortFlags */
1904 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
1905 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
1906 #define MPI_SAS_IOUNIT1_PORT_FLAGS_WAIT_FOR_PORTENABLE (0x02)
1907 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1908
1909 /* values for SAS IO Unit Page 0 PhyFlags */
1910 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
1911 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
1912 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
1913
1914 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
1915 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
1916 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
1917 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
1918 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
1919 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
1920 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
1921
1922 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1923
1924
1925 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
1926 {
1927 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
1928 U32 Reserved1; /* 08h */
1929 U16 MaxPersistentIDs; /* 0Ch */
1930 U16 NumPersistentIDsUsed; /* 0Eh */
1931 U8 Status; /* 10h */
1932 U8 Flags; /* 11h */
1933 U16 Reserved2; /* 12h */
1934 } fCONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
1935 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
1936
1937 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x00)
1938
1939 /* values for SAS IO Unit Page 2 Status field */
1940 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
1941 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
1942
1943 /* values for SAS IO Unit Page 2 Flags field */
1944 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
1945
1946
1947 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
1948 {
1949 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
1950 U32 Reserved1; /* 08h */
1951 U32 MaxInvalidDwordCount; /* 0Ch */
1952 U32 InvalidDwordCountTime; /* 10h */
1953 U32 MaxRunningDisparityErrorCount; /* 14h */
1954 U32 RunningDisparityErrorTime; /* 18h */
1955 U32 MaxLossDwordSynchCount; /* 1Ch */
1956 U32 LossDwordSynchCountTime; /* 20h */
1957 U32 MaxPhyResetProblemCount; /* 24h */
1958 U32 PhyResetProblemTime; /* 28h */
1959 } fCONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
1960 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
1961
1962 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
1963
1964
1965 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
1966 {
1967 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
1968 U32 Reserved1; /* 08h */
1969 U64 SASAddress; /* 0Ch */
1970 U32 Reserved2; /* 14h */
1971 U16 DevHandle; /* 18h */
1972 U16 ParentDevHandle; /* 1Ah */
1973 U16 ExpanderChangeCount; /* 1Ch */
1974 U16 ExpanderRouteIndexes; /* 1Eh */
1975 U8 NumPhys; /* 20h */
1976 U8 SASLevel; /* 21h */
1977 U8 Flags; /* 22h */
1978 U8 Reserved3; /* 23h */
1979 } fCONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
1980 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
1981
1982 #define MPI_SASEXPANDER0_PAGEVERSION (0x00)
1983
1984 /* values for SAS Expander Page 0 Flags field */
1985 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
1986 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
1987
1988
1989 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
1990 {
1991 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
1992 U32 Reserved1; /* 08h */
1993 U64 SASAddress; /* 0Ch */
1994 U32 Reserved2; /* 14h */
1995 U16 DevHandle; /* 18h */
1996 U8 TargetID; /* 1Ah */
1997 U8 Bus; /* 1Bh */
1998 U32 DeviceInfo; /* 1Ch */
1999 U16 Flags; /* 20h */
2000 U8 PhysicalPort; /* 22h */
2001 U8 Reserved3; /* 23h */
2002 } fCONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2003 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2004
2005 #define MPI_SASDEVICE0_PAGEVERSION (0x00)
2006
2007 /* values for SAS Device Page 0 Flags field */
2008 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x04)
2009 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x02)
2010 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x01)
2011
2012 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2013
2014
2015 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2016 {
2017 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2018 U32 Reserved1; /* 08h */
2019 U64 SASAddress; /* 0Ch */
2020 U32 Reserved2; /* 14h */
2021 U16 DevHandle; /* 18h */
2022 U8 TargetID; /* 1Ah */
2023 U8 Bus; /* 1Bh */
2024 U8 InitialRegDeviceFIS[20];/* 1Ch */
2025 } fCONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2026 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2027
2028 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2029
2030
2031 typedef struct _CONFIG_PAGE_SAS_PHY_0
2032 {
2033 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2034 U32 Reserved1; /* 08h */
2035 U64 SASAddress; /* 0Ch */
2036 U16 AttachedDevHandle; /* 14h */
2037 U8 AttachedPhyIdentifier; /* 16h */
2038 U8 Reserved2; /* 17h */
2039 U32 AttachedDeviceInfo; /* 18h */
2040 U8 ProgrammedLinkRate; /* 20h */
2041 U8 HwLinkRate; /* 21h */
2042 U8 ChangeCount; /* 22h */
2043 U8 Reserved3; /* 23h */
2044 U32 PhyInfo; /* 24h */
2045 } fCONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2046 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2047
2048 #define MPI_SASPHY0_PAGEVERSION (0x00)
2049
2050 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2051 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2052 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2053 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2054 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2055 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2056 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2057 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2058 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2059
2060 /* values for SAS PHY Page 0 HwLinkRate field */
2061 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2062 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2063 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2064 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2065 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2066 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2067
2068 /* values for SAS PHY Page 0 PhyInfo field */
2069 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2070 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2071 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2072
2073 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2074 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2075
2076 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2077 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2078 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2079 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2080
2081 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2082 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2083 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2084 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
2085 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
2086 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
2087 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
2088
2089
2090 typedef struct _CONFIG_PAGE_SAS_PHY_1
2091 {
2092 fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2093 U32 Reserved1; /* 08h */
2094 U32 InvalidDwordCount; /* 0Ch */
2095 U32 RunningDisparityErrorCount; /* 10h */
2096 U32 LossDwordSynchCount; /* 14h */
2097 U32 PhyResetProblemCount; /* 18h */
2098 } fCONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2099 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2100
2101 #define MPI_SASPHY1_PAGEVERSION (0x00)
2102
2103
2104 #endif
2105
kernel source for telekom puls (alcatel/mediatek)