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V4L/DVB: cx18, cx23885, v4l2 doc, MAINTAINERS: Update Andy Walls' email address
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / cx23885 / cx23888-ir.c
1 /*
2 * Driver for the Conexant CX23885/7/8 PCIe bridge
3 *
4 * CX23888 Integrated Consumer Infrared Controller
5 *
6 * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * 02110-1301, USA.
22 */
23
24 #include <linux/kfifo.h>
25 #include <linux/slab.h>
26
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-chip-ident.h>
29
30 #include "cx23885.h"
31
32 static unsigned int ir_888_debug;
33 module_param(ir_888_debug, int, 0644);
34 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
35
36 #define CX23888_IR_REG_BASE 0x170000
37 /*
38 * These CX23888 register offsets have a straightforward one to one mapping
39 * to the CX23885 register offsets of 0x200 through 0x218
40 */
41 #define CX23888_IR_CNTRL_REG 0x170000
42 #define CNTRL_WIN_3_3 0x00000000
43 #define CNTRL_WIN_4_3 0x00000001
44 #define CNTRL_WIN_3_4 0x00000002
45 #define CNTRL_WIN_4_4 0x00000003
46 #define CNTRL_WIN 0x00000003
47 #define CNTRL_EDG_NONE 0x00000000
48 #define CNTRL_EDG_FALL 0x00000004
49 #define CNTRL_EDG_RISE 0x00000008
50 #define CNTRL_EDG_BOTH 0x0000000C
51 #define CNTRL_EDG 0x0000000C
52 #define CNTRL_DMD 0x00000010
53 #define CNTRL_MOD 0x00000020
54 #define CNTRL_RFE 0x00000040
55 #define CNTRL_TFE 0x00000080
56 #define CNTRL_RXE 0x00000100
57 #define CNTRL_TXE 0x00000200
58 #define CNTRL_RIC 0x00000400
59 #define CNTRL_TIC 0x00000800
60 #define CNTRL_CPL 0x00001000
61 #define CNTRL_LBM 0x00002000
62 #define CNTRL_R 0x00004000
63
64 #define CX23888_IR_TXCLK_REG 0x170004
65 #define TXCLK_TCD 0x0000FFFF
66
67 #define CX23888_IR_RXCLK_REG 0x170008
68 #define RXCLK_RCD 0x0000FFFF
69
70 #define CX23888_IR_CDUTY_REG 0x17000C
71 #define CDUTY_CDC 0x0000000F
72
73 #define CX23888_IR_STATS_REG 0x170010
74 #define STATS_RTO 0x00000001
75 #define STATS_ROR 0x00000002
76 #define STATS_RBY 0x00000004
77 #define STATS_TBY 0x00000008
78 #define STATS_RSR 0x00000010
79 #define STATS_TSR 0x00000020
80
81 #define CX23888_IR_IRQEN_REG 0x170014
82 #define IRQEN_RTE 0x00000001
83 #define IRQEN_ROE 0x00000002
84 #define IRQEN_RSE 0x00000010
85 #define IRQEN_TSE 0x00000020
86
87 #define CX23888_IR_FILTR_REG 0x170018
88 #define FILTR_LPF 0x0000FFFF
89
90 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
91 #define CX23888_IR_FIFO_REG 0x170040
92 #define FIFO_RXTX 0x0000FFFF
93 #define FIFO_RXTX_LVL 0x00010000
94 #define FIFO_RXTX_RTO 0x0001FFFF
95 #define FIFO_RX_NDV 0x00020000
96 #define FIFO_RX_DEPTH 8
97 #define FIFO_TX_DEPTH 8
98
99 /* CX23888 unique registers */
100 #define CX23888_IR_SEEDP_REG 0x17001C
101 #define CX23888_IR_TIMOL_REG 0x170020
102 #define CX23888_IR_WAKE0_REG 0x170024
103 #define CX23888_IR_WAKE1_REG 0x170028
104 #define CX23888_IR_WAKE2_REG 0x17002C
105 #define CX23888_IR_MASK0_REG 0x170030
106 #define CX23888_IR_MASK1_REG 0x170034
107 #define CX23888_IR_MAKS2_REG 0x170038
108 #define CX23888_IR_DPIPG_REG 0x17003C
109 #define CX23888_IR_LEARN_REG 0x170044
110
111 #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
112 #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
113
114 #define CX23888_IR_RX_KFIFO_SIZE (512 * sizeof(u32))
115 #define CX23888_IR_TX_KFIFO_SIZE (512 * sizeof(u32))
116
117 struct cx23888_ir_state {
118 struct v4l2_subdev sd;
119 struct cx23885_dev *dev;
120 u32 id;
121 u32 rev;
122
123 struct v4l2_subdev_ir_parameters rx_params;
124 struct mutex rx_params_lock;
125 atomic_t rxclk_divider;
126 atomic_t rx_invert;
127
128 struct kfifo rx_kfifo;
129 spinlock_t rx_kfifo_lock;
130
131 struct v4l2_subdev_ir_parameters tx_params;
132 struct mutex tx_params_lock;
133 atomic_t txclk_divider;
134 };
135
136 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
137 {
138 return v4l2_get_subdevdata(sd);
139 }
140
141 /*
142 * IR register block read and write functions
143 */
144 static
145 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
146 {
147 cx_write(addr, value);
148 return 0;
149 }
150
151 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
152 {
153 return cx_read(addr);
154 }
155
156 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
157 u32 and_mask, u32 or_value)
158 {
159 cx_andor(addr, ~and_mask, or_value);
160 return 0;
161 }
162
163 /*
164 * Rx and Tx Clock Divider register computations
165 *
166 * Note the largest clock divider value of 0xffff corresponds to:
167 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
168 * which fits in 21 bits, so we'll use unsigned int for time arguments.
169 */
170 static inline u16 count_to_clock_divider(unsigned int d)
171 {
172 if (d > RXCLK_RCD + 1)
173 d = RXCLK_RCD;
174 else if (d < 2)
175 d = 1;
176 else
177 d--;
178 return (u16) d;
179 }
180
181 static inline u16 ns_to_clock_divider(unsigned int ns)
182 {
183 return count_to_clock_divider(
184 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
185 }
186
187 static inline unsigned int clock_divider_to_ns(unsigned int divider)
188 {
189 /* Period of the Rx or Tx clock in ns */
190 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
191 CX23888_IR_REFCLK_FREQ / 1000000);
192 }
193
194 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
195 {
196 return count_to_clock_divider(
197 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
198 }
199
200 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
201 {
202 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
203 }
204
205 static inline u16 freq_to_clock_divider(unsigned int freq,
206 unsigned int rollovers)
207 {
208 return count_to_clock_divider(
209 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
210 }
211
212 static inline unsigned int clock_divider_to_freq(unsigned int divider,
213 unsigned int rollovers)
214 {
215 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
216 (divider + 1) * rollovers);
217 }
218
219 /*
220 * Low Pass Filter register calculations
221 *
222 * Note the largest count value of 0xffff corresponds to:
223 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
224 * which fits in 21 bits, so we'll use unsigned int for time arguments.
225 */
226 static inline u16 count_to_lpf_count(unsigned int d)
227 {
228 if (d > FILTR_LPF)
229 d = FILTR_LPF;
230 else if (d < 4)
231 d = 0;
232 return (u16) d;
233 }
234
235 static inline u16 ns_to_lpf_count(unsigned int ns)
236 {
237 return count_to_lpf_count(
238 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
239 }
240
241 static inline unsigned int lpf_count_to_ns(unsigned int count)
242 {
243 /* Duration of the Low Pass Filter rejection window in ns */
244 return DIV_ROUND_CLOSEST(count * 1000,
245 CX23888_IR_REFCLK_FREQ / 1000000);
246 }
247
248 static inline unsigned int lpf_count_to_us(unsigned int count)
249 {
250 /* Duration of the Low Pass Filter rejection window in us */
251 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
252 }
253
254 /*
255 * FIFO register pulse width count compuations
256 */
257 static u32 clock_divider_to_resolution(u16 divider)
258 {
259 /*
260 * Resolution is the duration of 1 tick of the readable portion of
261 * of the pulse width counter as read from the FIFO. The two lsb's are
262 * not readable, hence the << 2. This function returns ns.
263 */
264 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
265 CX23888_IR_REFCLK_FREQ / 1000000);
266 }
267
268 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
269 {
270 u64 n;
271 u32 rem;
272
273 /*
274 * The 2 lsb's of the pulse width timer count are not readable, hence
275 * the (count << 2) | 0x3
276 */
277 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
278 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
279 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
280 n++;
281 return n;
282 }
283
284 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
285 {
286 u64 n;
287 u32 rem;
288
289 /*
290 * The 2 lsb's of the pulse width timer count are not readable, hence
291 * the (count << 2) | 0x3
292 */
293 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
294 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
295 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
296 n++;
297 return (unsigned int) n;
298 }
299
300 /*
301 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
302 *
303 * The total pulse clock count is an 18 bit pulse width timer count as the most
304 * significant part and (up to) 16 bit clock divider count as a modulus.
305 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
306 * width timer count's least significant bit.
307 */
308 static u64 ns_to_pulse_clocks(u32 ns)
309 {
310 u64 clocks;
311 u32 rem;
312 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
313 rem = do_div(clocks, 1000); /* /1000 = cycles */
314 if (rem >= 1000 / 2)
315 clocks++;
316 return clocks;
317 }
318
319 static u16 pulse_clocks_to_clock_divider(u64 count)
320 {
321 u32 rem;
322
323 rem = do_div(count, (FIFO_RXTX << 2) | 0x3);
324
325 /* net result needs to be rounded down and decremented by 1 */
326 if (count > RXCLK_RCD + 1)
327 count = RXCLK_RCD;
328 else if (count < 2)
329 count = 1;
330 else
331 count--;
332 return (u16) count;
333 }
334
335 /*
336 * IR Control Register helpers
337 */
338 enum tx_fifo_watermark {
339 TX_FIFO_HALF_EMPTY = 0,
340 TX_FIFO_EMPTY = CNTRL_TIC,
341 };
342
343 enum rx_fifo_watermark {
344 RX_FIFO_HALF_FULL = 0,
345 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
346 };
347
348 static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
349 enum tx_fifo_watermark level)
350 {
351 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
352 }
353
354 static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
355 enum rx_fifo_watermark level)
356 {
357 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
358 }
359
360 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
361 {
362 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
363 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
364 }
365
366 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
367 {
368 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
369 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
370 }
371
372 static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
373 bool enable)
374 {
375 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
376 enable ? CNTRL_MOD : 0);
377 }
378
379 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
380 bool enable)
381 {
382 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
383 enable ? CNTRL_DMD : 0);
384 }
385
386 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
387 u32 edge_types)
388 {
389 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
390 edge_types & CNTRL_EDG_BOTH);
391 }
392
393 static void control_rx_s_carrier_window(struct cx23885_dev *dev,
394 unsigned int carrier,
395 unsigned int *carrier_range_low,
396 unsigned int *carrier_range_high)
397 {
398 u32 v;
399 unsigned int c16 = carrier * 16;
400
401 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
402 v = CNTRL_WIN_3_4;
403 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
404 } else {
405 v = CNTRL_WIN_3_3;
406 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
407 }
408
409 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
410 v |= CNTRL_WIN_4_3;
411 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
412 } else {
413 v |= CNTRL_WIN_3_3;
414 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
415 }
416 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
417 }
418
419 static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
420 bool invert)
421 {
422 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
423 invert ? CNTRL_CPL : 0);
424 }
425
426 /*
427 * IR Rx & Tx Clock Register helpers
428 */
429 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
430 unsigned int freq,
431 u16 *divider)
432 {
433 *divider = carrier_freq_to_clock_divider(freq);
434 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
435 return clock_divider_to_carrier_freq(*divider);
436 }
437
438 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
439 unsigned int freq,
440 u16 *divider)
441 {
442 *divider = carrier_freq_to_clock_divider(freq);
443 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
444 return clock_divider_to_carrier_freq(*divider);
445 }
446
447 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
448 u16 *divider)
449 {
450 u64 pulse_clocks;
451
452 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
453 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
454 pulse_clocks = ns_to_pulse_clocks(ns);
455 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
456 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
457 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
458 }
459
460 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
461 u16 *divider)
462 {
463 u64 pulse_clocks;
464
465 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
466 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
467 pulse_clocks = ns_to_pulse_clocks(ns);
468 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
469 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
470 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
471 }
472
473 /*
474 * IR Tx Carrier Duty Cycle register helpers
475 */
476 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
477 unsigned int duty_cycle)
478 {
479 u32 n;
480 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
481 if (n != 0)
482 n--;
483 if (n > 15)
484 n = 15;
485 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
486 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
487 }
488
489 /*
490 * IR Filter Register helpers
491 */
492 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
493 {
494 u32 count = ns_to_lpf_count(min_width_ns);
495 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
496 return lpf_count_to_ns(count);
497 }
498
499 /*
500 * IR IRQ Enable Register helpers
501 */
502 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
503 {
504 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
505 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
506 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
507 }
508
509 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
510 {
511 mask &= IRQEN_TSE;
512 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
513 }
514
515 /*
516 * V4L2 Subdevice IR Ops
517 */
518 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
519 bool *handled)
520 {
521 struct cx23888_ir_state *state = to_state(sd);
522 struct cx23885_dev *dev = state->dev;
523 unsigned long flags;
524
525 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
526 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
527 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
528
529 u32 rx_data[FIFO_RX_DEPTH];
530 int i, j, k;
531 u32 events, v;
532 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
533
534 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
535 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
536 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
537 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
538
539 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
540 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
541 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
542 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
543
544 *handled = false;
545 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
546 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
547 rto ? "rto" : " ", ror ? "ror" : " ",
548 stats & STATS_TBY ? "tby" : " ",
549 stats & STATS_RBY ? "rby" : " ");
550
551 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
552 tse ? "tse" : " ", rse ? "rse" : " ",
553 rte ? "rte" : " ", roe ? "roe" : " ");
554
555 /*
556 * Transmitter interrupt service
557 */
558 if (tse && tsr) {
559 /*
560 * TODO:
561 * Check the watermark threshold setting
562 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
563 * Push the data to the hardware FIFO.
564 * If there was nothing more to send in the tx_kfifo, disable
565 * the TSR IRQ and notify the v4l2_device.
566 * If there was something in the tx_kfifo, check the tx_kfifo
567 * level and notify the v4l2_device, if it is low.
568 */
569 /* For now, inhibit TSR interrupt until Tx is implemented */
570 irqenable_tx(dev, 0);
571 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
572 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
573 *handled = true;
574 }
575
576 /*
577 * Receiver interrupt service
578 */
579 kror = 0;
580 if ((rse && rsr) || (rte && rto)) {
581 /*
582 * Receive data on RSR to clear the STATS_RSR.
583 * Receive data on RTO, since we may not have yet hit the RSR
584 * watermark when we receive the RTO.
585 */
586 for (i = 0, v = FIFO_RX_NDV;
587 (v & FIFO_RX_NDV) && !kror; i = 0) {
588 for (j = 0;
589 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
590 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
591 rx_data[i++] = v & ~FIFO_RX_NDV;
592 }
593 if (i == 0)
594 break;
595 j = i * sizeof(u32);
596 k = kfifo_in_locked(&state->rx_kfifo,
597 (unsigned char *) rx_data, j,
598 &state->rx_kfifo_lock);
599 if (k != j)
600 kror++; /* rx_kfifo over run */
601 }
602 *handled = true;
603 }
604
605 events = 0;
606 v = 0;
607 if (kror) {
608 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
609 v4l2_err(sd, "IR receiver software FIFO overrun\n");
610 }
611 if (roe && ror) {
612 /*
613 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
614 * the Rx FIFO Over Run status (STATS_ROR)
615 */
616 v |= CNTRL_RFE;
617 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
618 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
619 }
620 if (rte && rto) {
621 /*
622 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
623 * the Rx Pulse Width Timer Time Out (STATS_RTO)
624 */
625 v |= CNTRL_RXE;
626 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
627 }
628 if (v) {
629 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
630 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
631 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
632 *handled = true;
633 }
634
635 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
636 if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
637 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
638 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
639
640 if (events)
641 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
642 return 0;
643 }
644
645 /* Receiver */
646 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
647 ssize_t *num)
648 {
649 struct cx23888_ir_state *state = to_state(sd);
650 bool invert = (bool) atomic_read(&state->rx_invert);
651 u16 divider = (u16) atomic_read(&state->rxclk_divider);
652
653 unsigned int i, n;
654 u32 *p;
655 u32 u, v;
656
657 n = count / sizeof(u32) * sizeof(u32);
658 if (n == 0) {
659 *num = 0;
660 return 0;
661 }
662
663 n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
664
665 n /= sizeof(u32);
666 *num = n * sizeof(u32);
667
668 for (p = (u32 *) buf, i = 0; i < n; p++, i++) {
669 if ((*p & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
670 *p = V4L2_SUBDEV_IR_PULSE_RX_SEQ_END;
671 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
672 continue;
673 }
674
675 u = (*p & FIFO_RXTX_LVL) ? V4L2_SUBDEV_IR_PULSE_LEVEL_MASK : 0;
676 if (invert)
677 u = u ? 0 : V4L2_SUBDEV_IR_PULSE_LEVEL_MASK;
678
679 v = (u32) pulse_width_count_to_ns((u16) (*p & FIFO_RXTX),
680 divider);
681 if (v >= V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
682 v = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS - 1;
683
684 *p = u | v;
685
686 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s\n",
687 v, u ? "mark" : "space");
688 }
689 return 0;
690 }
691
692 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
693 struct v4l2_subdev_ir_parameters *p)
694 {
695 struct cx23888_ir_state *state = to_state(sd);
696 mutex_lock(&state->rx_params_lock);
697 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
698 mutex_unlock(&state->rx_params_lock);
699 return 0;
700 }
701
702 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
703 {
704 struct cx23888_ir_state *state = to_state(sd);
705 struct cx23885_dev *dev = state->dev;
706
707 mutex_lock(&state->rx_params_lock);
708
709 /* Disable or slow down all IR Rx circuits and counters */
710 irqenable_rx(dev, 0);
711 control_rx_enable(dev, false);
712 control_rx_demodulation_enable(dev, false);
713 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
714 filter_rx_s_min_width(dev, 0);
715 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
716
717 state->rx_params.shutdown = true;
718
719 mutex_unlock(&state->rx_params_lock);
720 return 0;
721 }
722
723 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
724 struct v4l2_subdev_ir_parameters *p)
725 {
726 struct cx23888_ir_state *state = to_state(sd);
727 struct cx23885_dev *dev = state->dev;
728 struct v4l2_subdev_ir_parameters *o = &state->rx_params;
729 u16 rxclk_divider;
730
731 if (p->shutdown)
732 return cx23888_ir_rx_shutdown(sd);
733
734 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
735 return -ENOSYS;
736
737 mutex_lock(&state->rx_params_lock);
738
739 o->shutdown = p->shutdown;
740
741 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
742
743 o->bytes_per_data_element = p->bytes_per_data_element = sizeof(u32);
744
745 /* Before we tweak the hardware, we have to disable the receiver */
746 irqenable_rx(dev, 0);
747 control_rx_enable(dev, false);
748
749 control_rx_demodulation_enable(dev, p->modulation);
750 o->modulation = p->modulation;
751
752 if (p->modulation) {
753 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
754 &rxclk_divider);
755
756 o->carrier_freq = p->carrier_freq;
757
758 o->duty_cycle = p->duty_cycle = 50;
759
760 control_rx_s_carrier_window(dev, p->carrier_freq,
761 &p->carrier_range_lower,
762 &p->carrier_range_upper);
763 o->carrier_range_lower = p->carrier_range_lower;
764 o->carrier_range_upper = p->carrier_range_upper;
765 } else {
766 p->max_pulse_width =
767 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
768 &rxclk_divider);
769 o->max_pulse_width = p->max_pulse_width;
770 }
771 atomic_set(&state->rxclk_divider, rxclk_divider);
772
773 p->noise_filter_min_width =
774 filter_rx_s_min_width(dev, p->noise_filter_min_width);
775 o->noise_filter_min_width = p->noise_filter_min_width;
776
777 p->resolution = clock_divider_to_resolution(rxclk_divider);
778 o->resolution = p->resolution;
779
780 /* FIXME - make this dependent on resolution for better performance */
781 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
782
783 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
784
785 o->invert = p->invert;
786 atomic_set(&state->rx_invert, p->invert);
787
788 o->interrupt_enable = p->interrupt_enable;
789 o->enable = p->enable;
790 if (p->enable) {
791 unsigned long flags;
792
793 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
794 kfifo_reset(&state->rx_kfifo);
795 /* reset tx_fifo too if there is one... */
796 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
797 if (p->interrupt_enable)
798 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
799 control_rx_enable(dev, p->enable);
800 }
801
802 mutex_unlock(&state->rx_params_lock);
803 return 0;
804 }
805
806 /* Transmitter */
807 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
808 ssize_t *num)
809 {
810 struct cx23888_ir_state *state = to_state(sd);
811 struct cx23885_dev *dev = state->dev;
812 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
813 irqenable_tx(dev, IRQEN_TSE);
814 *num = count;
815 return 0;
816 }
817
818 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
819 struct v4l2_subdev_ir_parameters *p)
820 {
821 struct cx23888_ir_state *state = to_state(sd);
822 mutex_lock(&state->tx_params_lock);
823 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
824 mutex_unlock(&state->tx_params_lock);
825 return 0;
826 }
827
828 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
829 {
830 struct cx23888_ir_state *state = to_state(sd);
831 struct cx23885_dev *dev = state->dev;
832
833 mutex_lock(&state->tx_params_lock);
834
835 /* Disable or slow down all IR Tx circuits and counters */
836 irqenable_tx(dev, 0);
837 control_tx_enable(dev, false);
838 control_tx_modulation_enable(dev, false);
839 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
840
841 state->tx_params.shutdown = true;
842
843 mutex_unlock(&state->tx_params_lock);
844 return 0;
845 }
846
847 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
848 struct v4l2_subdev_ir_parameters *p)
849 {
850 struct cx23888_ir_state *state = to_state(sd);
851 struct cx23885_dev *dev = state->dev;
852 struct v4l2_subdev_ir_parameters *o = &state->tx_params;
853 u16 txclk_divider;
854
855 if (p->shutdown)
856 return cx23888_ir_tx_shutdown(sd);
857
858 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
859 return -ENOSYS;
860
861 mutex_lock(&state->tx_params_lock);
862
863 o->shutdown = p->shutdown;
864
865 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
866
867 o->bytes_per_data_element = p->bytes_per_data_element = sizeof(u32);
868
869 /* Before we tweak the hardware, we have to disable the transmitter */
870 irqenable_tx(dev, 0);
871 control_tx_enable(dev, false);
872
873 control_tx_modulation_enable(dev, p->modulation);
874 o->modulation = p->modulation;
875
876 if (p->modulation) {
877 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
878 &txclk_divider);
879 o->carrier_freq = p->carrier_freq;
880
881 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
882 o->duty_cycle = p->duty_cycle;
883 } else {
884 p->max_pulse_width =
885 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
886 &txclk_divider);
887 o->max_pulse_width = p->max_pulse_width;
888 }
889 atomic_set(&state->txclk_divider, txclk_divider);
890
891 p->resolution = clock_divider_to_resolution(txclk_divider);
892 o->resolution = p->resolution;
893
894 /* FIXME - make this dependent on resolution for better performance */
895 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
896
897 control_tx_polarity_invert(dev, p->invert);
898 o->invert = p->invert;
899
900 o->interrupt_enable = p->interrupt_enable;
901 o->enable = p->enable;
902 if (p->enable) {
903 if (p->interrupt_enable)
904 irqenable_tx(dev, IRQEN_TSE);
905 control_tx_enable(dev, p->enable);
906 }
907
908 mutex_unlock(&state->tx_params_lock);
909 return 0;
910 }
911
912
913 /*
914 * V4L2 Subdevice Core Ops
915 */
916 static int cx23888_ir_log_status(struct v4l2_subdev *sd)
917 {
918 struct cx23888_ir_state *state = to_state(sd);
919 struct cx23885_dev *dev = state->dev;
920 char *s;
921 int i, j;
922
923 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
924 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
925 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
926 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
927 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
928 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
929 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
930
931 v4l2_info(sd, "IR Receiver:\n");
932 v4l2_info(sd, "\tEnabled: %s\n",
933 cntrl & CNTRL_RXE ? "yes" : "no");
934 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
935 cntrl & CNTRL_DMD ? "enabled" : "disabled");
936 v4l2_info(sd, "\tFIFO: %s\n",
937 cntrl & CNTRL_RFE ? "enabled" : "disabled");
938 switch (cntrl & CNTRL_EDG) {
939 case CNTRL_EDG_NONE:
940 s = "disabled";
941 break;
942 case CNTRL_EDG_FALL:
943 s = "falling edge";
944 break;
945 case CNTRL_EDG_RISE:
946 s = "rising edge";
947 break;
948 case CNTRL_EDG_BOTH:
949 s = "rising & falling edges";
950 break;
951 default:
952 s = "??? edge";
953 break;
954 }
955 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
956 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
957 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
958 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
959 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
960 v4l2_info(sd, "\tLoopback mode: %s\n",
961 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
962 if (cntrl & CNTRL_DMD) {
963 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
964 clock_divider_to_carrier_freq(rxclk));
965 switch (cntrl & CNTRL_WIN) {
966 case CNTRL_WIN_3_3:
967 i = 3;
968 j = 3;
969 break;
970 case CNTRL_WIN_4_3:
971 i = 4;
972 j = 3;
973 break;
974 case CNTRL_WIN_3_4:
975 i = 3;
976 j = 4;
977 break;
978 case CNTRL_WIN_4_4:
979 i = 4;
980 j = 4;
981 break;
982 default:
983 i = 0;
984 j = 0;
985 break;
986 }
987 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
988 "-%1d/+%1d, %u to %u Hz\n", i, j,
989 clock_divider_to_freq(rxclk, 16 + j),
990 clock_divider_to_freq(rxclk, 16 - i));
991 } else {
992 v4l2_info(sd, "\tMax measurable pulse width: %u us, "
993 "%llu ns\n",
994 pulse_width_count_to_us(FIFO_RXTX, rxclk),
995 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
996 }
997 v4l2_info(sd, "\tLow pass filter: %s\n",
998 filtr ? "enabled" : "disabled");
999 if (filtr)
1000 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
1001 "%u ns\n",
1002 lpf_count_to_us(filtr),
1003 lpf_count_to_ns(filtr));
1004 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1005 stats & STATS_RTO ? "yes" : "no");
1006 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1007 irqen & IRQEN_RTE ? "enabled" : "disabled");
1008 v4l2_info(sd, "\tFIFO overrun: %s\n",
1009 stats & STATS_ROR ? "yes" : "no");
1010 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1011 irqen & IRQEN_ROE ? "enabled" : "disabled");
1012 v4l2_info(sd, "\tBusy: %s\n",
1013 stats & STATS_RBY ? "yes" : "no");
1014 v4l2_info(sd, "\tFIFO service requested: %s\n",
1015 stats & STATS_RSR ? "yes" : "no");
1016 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1017 irqen & IRQEN_RSE ? "enabled" : "disabled");
1018
1019 v4l2_info(sd, "IR Transmitter:\n");
1020 v4l2_info(sd, "\tEnabled: %s\n",
1021 cntrl & CNTRL_TXE ? "yes" : "no");
1022 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1023 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1024 v4l2_info(sd, "\tFIFO: %s\n",
1025 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1026 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1027 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1028 v4l2_info(sd, "\tSignal polarity: %s\n",
1029 cntrl & CNTRL_CPL ? "0:mark 1:space" : "0:space 1:mark");
1030 if (cntrl & CNTRL_MOD) {
1031 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1032 clock_divider_to_carrier_freq(txclk));
1033 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1034 cduty + 1);
1035 } else {
1036 v4l2_info(sd, "\tMax pulse width: %u us, "
1037 "%llu ns\n",
1038 pulse_width_count_to_us(FIFO_RXTX, txclk),
1039 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1040 }
1041 v4l2_info(sd, "\tBusy: %s\n",
1042 stats & STATS_TBY ? "yes" : "no");
1043 v4l2_info(sd, "\tFIFO service requested: %s\n",
1044 stats & STATS_TSR ? "yes" : "no");
1045 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1046 irqen & IRQEN_TSE ? "enabled" : "disabled");
1047
1048 return 0;
1049 }
1050
1051 static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match)
1052 {
1053 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2;
1054 }
1055
1056 static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd,
1057 struct v4l2_dbg_chip_ident *chip)
1058 {
1059 struct cx23888_ir_state *state = to_state(sd);
1060
1061 if (cx23888_ir_dbg_match(&chip->match)) {
1062 chip->ident = state->id;
1063 chip->revision = state->rev;
1064 }
1065 return 0;
1066 }
1067
1068 #ifdef CONFIG_VIDEO_ADV_DEBUG
1069 static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1070 struct v4l2_dbg_register *reg)
1071 {
1072 struct cx23888_ir_state *state = to_state(sd);
1073 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1074
1075 if (!cx23888_ir_dbg_match(&reg->match))
1076 return -EINVAL;
1077 if ((addr & 0x3) != 0)
1078 return -EINVAL;
1079 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1080 return -EINVAL;
1081 if (!capable(CAP_SYS_ADMIN))
1082 return -EPERM;
1083 reg->size = 4;
1084 reg->val = cx23888_ir_read4(state->dev, addr);
1085 return 0;
1086 }
1087
1088 static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1089 struct v4l2_dbg_register *reg)
1090 {
1091 struct cx23888_ir_state *state = to_state(sd);
1092 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1093
1094 if (!cx23888_ir_dbg_match(&reg->match))
1095 return -EINVAL;
1096 if ((addr & 0x3) != 0)
1097 return -EINVAL;
1098 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1099 return -EINVAL;
1100 if (!capable(CAP_SYS_ADMIN))
1101 return -EPERM;
1102 cx23888_ir_write4(state->dev, addr, reg->val);
1103 return 0;
1104 }
1105 #endif
1106
1107 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1108 .g_chip_ident = cx23888_ir_g_chip_ident,
1109 .log_status = cx23888_ir_log_status,
1110 #ifdef CONFIG_VIDEO_ADV_DEBUG
1111 .g_register = cx23888_ir_g_register,
1112 .s_register = cx23888_ir_s_register,
1113 #endif
1114 };
1115
1116 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1117 .interrupt_service_routine = cx23888_ir_irq_handler,
1118
1119 .rx_read = cx23888_ir_rx_read,
1120 .rx_g_parameters = cx23888_ir_rx_g_parameters,
1121 .rx_s_parameters = cx23888_ir_rx_s_parameters,
1122
1123 .tx_write = cx23888_ir_tx_write,
1124 .tx_g_parameters = cx23888_ir_tx_g_parameters,
1125 .tx_s_parameters = cx23888_ir_tx_s_parameters,
1126 };
1127
1128 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1129 .core = &cx23888_ir_core_ops,
1130 .ir = &cx23888_ir_ir_ops,
1131 };
1132
1133 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1134 .bytes_per_data_element = sizeof(u32),
1135 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1136
1137 .enable = false,
1138 .interrupt_enable = false,
1139 .shutdown = true,
1140
1141 .modulation = true,
1142 .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1143
1144 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1145 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1146 .noise_filter_min_width = 333333, /* ns */
1147 .carrier_range_lower = 35000,
1148 .carrier_range_upper = 37000,
1149 .invert = false,
1150 };
1151
1152 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1153 .bytes_per_data_element = sizeof(u32),
1154 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1155
1156 .enable = false,
1157 .interrupt_enable = false,
1158 .shutdown = true,
1159
1160 .modulation = true,
1161 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1162 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1163 .invert = false,
1164 };
1165
1166 int cx23888_ir_probe(struct cx23885_dev *dev)
1167 {
1168 struct cx23888_ir_state *state;
1169 struct v4l2_subdev *sd;
1170 struct v4l2_subdev_ir_parameters default_params;
1171 int ret;
1172
1173 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1174 if (state == NULL)
1175 return -ENOMEM;
1176
1177 spin_lock_init(&state->rx_kfifo_lock);
1178 if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1179 return -ENOMEM;
1180
1181 state->dev = dev;
1182 state->id = V4L2_IDENT_CX23888_IR;
1183 state->rev = 0;
1184 sd = &state->sd;
1185
1186 v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1187 v4l2_set_subdevdata(sd, state);
1188 /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
1189 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1190 sd->grp_id = CX23885_HW_888_IR;
1191
1192 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1193 if (ret == 0) {
1194 /*
1195 * Ensure no interrupts arrive from '888 specific conditions,
1196 * since we ignore them in this driver to have commonality with
1197 * similar IR controller cores.
1198 */
1199 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1200
1201 mutex_init(&state->rx_params_lock);
1202 memcpy(&default_params, &default_rx_params,
1203 sizeof(struct v4l2_subdev_ir_parameters));
1204 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1205
1206 mutex_init(&state->tx_params_lock);
1207 memcpy(&default_params, &default_tx_params,
1208 sizeof(struct v4l2_subdev_ir_parameters));
1209 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1210 } else {
1211 kfifo_free(&state->rx_kfifo);
1212 }
1213 return ret;
1214 }
1215
1216 int cx23888_ir_remove(struct cx23885_dev *dev)
1217 {
1218 struct v4l2_subdev *sd;
1219 struct cx23888_ir_state *state;
1220
1221 sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1222 if (sd == NULL)
1223 return -ENODEV;
1224
1225 cx23888_ir_rx_shutdown(sd);
1226 cx23888_ir_tx_shutdown(sd);
1227
1228 state = to_state(sd);
1229 v4l2_device_unregister_subdev(sd);
1230 kfifo_free(&state->rx_kfifo);
1231 kfree(state);
1232 /* Nothing more to free() as state held the actual v4l2_subdev object */
1233 return 0;
1234 }
kernel source for telekom puls (alcatel/mediatek)