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Linux 3.8-rc1
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / platform / soc_camera / mx2_camera.c
1 /*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
26 #include <linux/mm.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/mutex.h>
32 #include <linux/clk.h>
33
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-dev.h>
36 #include <media/videobuf2-core.h>
37 #include <media/videobuf2-dma-contig.h>
38 #include <media/soc_camera.h>
39 #include <media/soc_mediabus.h>
40
41 #include <linux/videodev2.h>
42
43 #include <linux/platform_data/camera-mx2.h>
44
45 #include <asm/dma.h>
46
47 #define MX2_CAM_DRV_NAME "mx2-camera"
48 #define MX2_CAM_VERSION "0.0.6"
49 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
50
51 /* reset values */
52 #define CSICR1_RESET_VAL 0x40000800
53 #define CSICR2_RESET_VAL 0x0
54 #define CSICR3_RESET_VAL 0x0
55
56 /* csi control reg 1 */
57 #define CSICR1_SWAP16_EN (1 << 31)
58 #define CSICR1_EXT_VSYNC (1 << 30)
59 #define CSICR1_EOF_INTEN (1 << 29)
60 #define CSICR1_PRP_IF_EN (1 << 28)
61 #define CSICR1_CCIR_MODE (1 << 27)
62 #define CSICR1_COF_INTEN (1 << 26)
63 #define CSICR1_SF_OR_INTEN (1 << 25)
64 #define CSICR1_RF_OR_INTEN (1 << 24)
65 #define CSICR1_STATFF_LEVEL (3 << 22)
66 #define CSICR1_STATFF_INTEN (1 << 21)
67 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
68 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
69 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
70 #define CSICR1_RXFF_INTEN (1 << 18)
71 #define CSICR1_SOF_POL (1 << 17)
72 #define CSICR1_SOF_INTEN (1 << 16)
73 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
74 #define CSICR1_HSYNC_POL (1 << 11)
75 #define CSICR1_CCIR_EN (1 << 10)
76 #define CSICR1_MCLKEN (1 << 9)
77 #define CSICR1_FCC (1 << 8)
78 #define CSICR1_PACK_DIR (1 << 7)
79 #define CSICR1_CLR_STATFIFO (1 << 6)
80 #define CSICR1_CLR_RXFIFO (1 << 5)
81 #define CSICR1_GCLK_MODE (1 << 4)
82 #define CSICR1_INV_DATA (1 << 3)
83 #define CSICR1_INV_PCLK (1 << 2)
84 #define CSICR1_REDGE (1 << 1)
85 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
86
87 #define SHIFT_STATFF_LEVEL 22
88 #define SHIFT_RXFF_LEVEL 19
89 #define SHIFT_MCLKDIV 12
90
91 /* control reg 3 */
92 #define CSICR3_FRMCNT (0xFFFF << 16)
93 #define CSICR3_FRMCNT_RST (1 << 15)
94 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
95 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
96 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
97 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
98 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
99 #define CSICR3_CSI_SUP (1 << 3)
100 #define CSICR3_ZERO_PACK_EN (1 << 2)
101 #define CSICR3_ECC_INT_EN (1 << 1)
102 #define CSICR3_ECC_AUTO_EN (1 << 0)
103
104 #define SHIFT_FRMCNT 16
105
106 /* csi status reg */
107 #define CSISR_SFF_OR_INT (1 << 25)
108 #define CSISR_RFF_OR_INT (1 << 24)
109 #define CSISR_STATFF_INT (1 << 21)
110 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
111 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
112 #define CSISR_RXFF_INT (1 << 18)
113 #define CSISR_EOF_INT (1 << 17)
114 #define CSISR_SOF_INT (1 << 16)
115 #define CSISR_F2_INT (1 << 15)
116 #define CSISR_F1_INT (1 << 14)
117 #define CSISR_COF_INT (1 << 13)
118 #define CSISR_ECC_INT (1 << 1)
119 #define CSISR_DRDY (1 << 0)
120
121 #define CSICR1 0x00
122 #define CSICR2 0x04
123 #define CSISR_IMX25 0x18
124 #define CSISR_IMX27 0x08
125 #define CSISTATFIFO 0x0c
126 #define CSIRFIFO 0x10
127 #define CSIRXCNT 0x14
128 #define CSICR3_IMX25 0x08
129 #define CSICR3_IMX27 0x1c
130 #define CSIDMASA_STATFIFO 0x20
131 #define CSIDMATA_STATFIFO 0x24
132 #define CSIDMASA_FB1 0x28
133 #define CSIDMASA_FB2 0x2c
134 #define CSIFBUF_PARA 0x30
135 #define CSIIMAG_PARA 0x34
136
137 /* EMMA PrP */
138 #define PRP_CNTL 0x00
139 #define PRP_INTR_CNTL 0x04
140 #define PRP_INTRSTATUS 0x08
141 #define PRP_SOURCE_Y_PTR 0x0c
142 #define PRP_SOURCE_CB_PTR 0x10
143 #define PRP_SOURCE_CR_PTR 0x14
144 #define PRP_DEST_RGB1_PTR 0x18
145 #define PRP_DEST_RGB2_PTR 0x1c
146 #define PRP_DEST_Y_PTR 0x20
147 #define PRP_DEST_CB_PTR 0x24
148 #define PRP_DEST_CR_PTR 0x28
149 #define PRP_SRC_FRAME_SIZE 0x2c
150 #define PRP_DEST_CH1_LINE_STRIDE 0x30
151 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
152 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
153 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
154 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
155 #define PRP_SRC_LINE_STRIDE 0x44
156 #define PRP_CSC_COEF_012 0x48
157 #define PRP_CSC_COEF_345 0x4c
158 #define PRP_CSC_COEF_678 0x50
159 #define PRP_CH1_RZ_HORI_COEF1 0x54
160 #define PRP_CH1_RZ_HORI_COEF2 0x58
161 #define PRP_CH1_RZ_HORI_VALID 0x5c
162 #define PRP_CH1_RZ_VERT_COEF1 0x60
163 #define PRP_CH1_RZ_VERT_COEF2 0x64
164 #define PRP_CH1_RZ_VERT_VALID 0x68
165 #define PRP_CH2_RZ_HORI_COEF1 0x6c
166 #define PRP_CH2_RZ_HORI_COEF2 0x70
167 #define PRP_CH2_RZ_HORI_VALID 0x74
168 #define PRP_CH2_RZ_VERT_COEF1 0x78
169 #define PRP_CH2_RZ_VERT_COEF2 0x7c
170 #define PRP_CH2_RZ_VERT_VALID 0x80
171
172 #define PRP_CNTL_CH1EN (1 << 0)
173 #define PRP_CNTL_CH2EN (1 << 1)
174 #define PRP_CNTL_CSIEN (1 << 2)
175 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
176 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
177 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
178 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
179 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
180 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
181 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
182 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
183 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
184 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
185 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
186 #define PRP_CNTL_CH1_LEN (1 << 9)
187 #define PRP_CNTL_CH2_LEN (1 << 10)
188 #define PRP_CNTL_SKIP_FRAME (1 << 11)
189 #define PRP_CNTL_SWRST (1 << 12)
190 #define PRP_CNTL_CLKEN (1 << 13)
191 #define PRP_CNTL_WEN (1 << 14)
192 #define PRP_CNTL_CH1BYP (1 << 15)
193 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
194 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
195 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
196 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
197 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
198 #define PRP_CNTL_CH2B1EN (1 << 29)
199 #define PRP_CNTL_CH2B2EN (1 << 30)
200 #define PRP_CNTL_CH2FEN (1 << 31)
201
202 /* IRQ Enable and status register */
203 #define PRP_INTR_RDERR (1 << 0)
204 #define PRP_INTR_CH1WERR (1 << 1)
205 #define PRP_INTR_CH2WERR (1 << 2)
206 #define PRP_INTR_CH1FC (1 << 3)
207 #define PRP_INTR_CH2FC (1 << 5)
208 #define PRP_INTR_LBOVF (1 << 7)
209 #define PRP_INTR_CH2OVF (1 << 8)
210
211 /* Resizing registers */
212 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
213 #define PRP_RZ_VALID_BILINEAR (1 << 31)
214
215 #define MAX_VIDEO_MEM 16
216
217 #define RESIZE_NUM_MIN 1
218 #define RESIZE_NUM_MAX 20
219 #define BC_COEF 3
220 #define SZ_COEF (1 << BC_COEF)
221
222 #define RESIZE_DIR_H 0
223 #define RESIZE_DIR_V 1
224
225 #define RESIZE_ALGO_BILINEAR 0
226 #define RESIZE_ALGO_AVERAGING 1
227
228 struct mx2_prp_cfg {
229 int channel;
230 u32 in_fmt;
231 u32 out_fmt;
232 u32 src_pixel;
233 u32 ch1_pixel;
234 u32 irq_flags;
235 u32 csicr1;
236 };
237
238 /* prp resizing parameters */
239 struct emma_prp_resize {
240 int algo; /* type of algorithm used */
241 int len; /* number of coefficients */
242 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
243 };
244
245 /* prp configuration for a client-host fmt pair */
246 struct mx2_fmt_cfg {
247 enum v4l2_mbus_pixelcode in_fmt;
248 u32 out_fmt;
249 struct mx2_prp_cfg cfg;
250 };
251
252 enum mx2_buffer_state {
253 MX2_STATE_QUEUED,
254 MX2_STATE_ACTIVE,
255 MX2_STATE_DONE,
256 };
257
258 struct mx2_buf_internal {
259 struct list_head queue;
260 int bufnum;
261 bool discard;
262 };
263
264 /* buffer for one video frame */
265 struct mx2_buffer {
266 /* common v4l buffer stuff -- must be first */
267 struct vb2_buffer vb;
268 enum mx2_buffer_state state;
269 struct mx2_buf_internal internal;
270 };
271
272 enum mx2_camera_type {
273 IMX25_CAMERA,
274 IMX27_CAMERA,
275 };
276
277 struct mx2_camera_dev {
278 struct device *dev;
279 struct soc_camera_host soc_host;
280 struct soc_camera_device *icd;
281 struct clk *clk_emma_ahb, *clk_emma_ipg;
282 struct clk *clk_csi_ahb, *clk_csi_per;
283
284 void __iomem *base_csi, *base_emma;
285
286 struct mx2_camera_platform_data *pdata;
287 unsigned long platform_flags;
288
289 struct list_head capture;
290 struct list_head active_bufs;
291 struct list_head discard;
292
293 spinlock_t lock;
294
295 int dma;
296 struct mx2_buffer *active;
297 struct mx2_buffer *fb1_active;
298 struct mx2_buffer *fb2_active;
299
300 u32 csicr1;
301 u32 reg_csisr;
302 u32 reg_csicr3;
303 enum mx2_camera_type devtype;
304
305 struct mx2_buf_internal buf_discard[2];
306 void *discard_buffer;
307 dma_addr_t discard_buffer_dma;
308 size_t discard_size;
309 struct mx2_fmt_cfg *emma_prp;
310 struct emma_prp_resize resizing[2];
311 unsigned int s_width, s_height;
312 u32 frame_count;
313 struct vb2_alloc_ctx *alloc_ctx;
314 };
315
316 static struct platform_device_id mx2_camera_devtype[] = {
317 {
318 .name = "imx25-camera",
319 .driver_data = IMX25_CAMERA,
320 }, {
321 .name = "imx27-camera",
322 .driver_data = IMX27_CAMERA,
323 }, {
324 /* sentinel */
325 }
326 };
327 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
328
329 static inline int is_imx25_camera(struct mx2_camera_dev *pcdev)
330 {
331 return pcdev->devtype == IMX25_CAMERA;
332 }
333
334 static inline int is_imx27_camera(struct mx2_camera_dev *pcdev)
335 {
336 return pcdev->devtype == IMX27_CAMERA;
337 }
338
339 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
340 {
341 return container_of(int_buf, struct mx2_buffer, internal);
342 }
343
344 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
345 /*
346 * This is a generic configuration which is valid for most
347 * prp input-output format combinations.
348 * We set the incomming and outgoing pixelformat to a
349 * 16 Bit wide format and adjust the bytesperline
350 * accordingly. With this configuration the inputdata
351 * will not be changed by the emma and could be any type
352 * of 16 Bit Pixelformat.
353 */
354 {
355 .in_fmt = 0,
356 .out_fmt = 0,
357 .cfg = {
358 .channel = 1,
359 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
360 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
361 .src_pixel = 0x2ca00565, /* RGB565 */
362 .ch1_pixel = 0x2ca00565, /* RGB565 */
363 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
364 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
365 .csicr1 = 0,
366 }
367 },
368 {
369 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
370 .out_fmt = V4L2_PIX_FMT_YUYV,
371 .cfg = {
372 .channel = 1,
373 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
374 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
375 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
376 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
377 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
378 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
379 .csicr1 = CSICR1_SWAP16_EN,
380 }
381 },
382 {
383 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
384 .out_fmt = V4L2_PIX_FMT_YUYV,
385 .cfg = {
386 .channel = 1,
387 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
388 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
389 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
390 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
391 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
392 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
393 .csicr1 = CSICR1_PACK_DIR,
394 }
395 },
396 {
397 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
398 .out_fmt = V4L2_PIX_FMT_YUV420,
399 .cfg = {
400 .channel = 2,
401 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
402 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
403 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
404 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
405 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
406 PRP_INTR_CH2OVF,
407 .csicr1 = CSICR1_PACK_DIR,
408 }
409 },
410 {
411 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
412 .out_fmt = V4L2_PIX_FMT_YUV420,
413 .cfg = {
414 .channel = 2,
415 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
416 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
417 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
418 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
419 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
420 PRP_INTR_CH2OVF,
421 .csicr1 = CSICR1_SWAP16_EN,
422 }
423 },
424 };
425
426 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
427 enum v4l2_mbus_pixelcode in_fmt,
428 u32 out_fmt)
429 {
430 int i;
431
432 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
433 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
434 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
435 return &mx27_emma_prp_table[i];
436 }
437 /* If no match return the most generic configuration */
438 return &mx27_emma_prp_table[0];
439 };
440
441 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
442 unsigned long phys, int bufnum)
443 {
444 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
445
446 if (prp->cfg.channel == 1) {
447 writel(phys, pcdev->base_emma +
448 PRP_DEST_RGB1_PTR + 4 * bufnum);
449 } else {
450 writel(phys, pcdev->base_emma +
451 PRP_DEST_Y_PTR - 0x14 * bufnum);
452 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
453 u32 imgsize = pcdev->icd->user_height *
454 pcdev->icd->user_width;
455
456 writel(phys + imgsize, pcdev->base_emma +
457 PRP_DEST_CB_PTR - 0x14 * bufnum);
458 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
459 PRP_DEST_CR_PTR - 0x14 * bufnum);
460 }
461 }
462 }
463
464 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
465 {
466 unsigned long flags;
467
468 clk_disable_unprepare(pcdev->clk_csi_ahb);
469 clk_disable_unprepare(pcdev->clk_csi_per);
470 writel(0, pcdev->base_csi + CSICR1);
471 if (is_imx27_camera(pcdev)) {
472 writel(0, pcdev->base_emma + PRP_CNTL);
473 } else if (is_imx25_camera(pcdev)) {
474 spin_lock_irqsave(&pcdev->lock, flags);
475 pcdev->fb1_active = NULL;
476 pcdev->fb2_active = NULL;
477 writel(0, pcdev->base_csi + CSIDMASA_FB1);
478 writel(0, pcdev->base_csi + CSIDMASA_FB2);
479 spin_unlock_irqrestore(&pcdev->lock, flags);
480 }
481 }
482
483 /*
484 * The following two functions absolutely depend on the fact, that
485 * there can be only one camera on mx2 camera sensor interface
486 */
487 static int mx2_camera_add_device(struct soc_camera_device *icd)
488 {
489 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
490 struct mx2_camera_dev *pcdev = ici->priv;
491 int ret;
492 u32 csicr1;
493
494 if (pcdev->icd)
495 return -EBUSY;
496
497 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
498 if (ret < 0)
499 return ret;
500
501 ret = clk_prepare_enable(pcdev->clk_csi_per);
502 if (ret < 0)
503 goto exit_csi_ahb;
504
505 csicr1 = CSICR1_MCLKEN;
506
507 if (is_imx27_camera(pcdev))
508 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
509 CSICR1_RXFF_LEVEL(0);
510
511 pcdev->csicr1 = csicr1;
512 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
513
514 pcdev->icd = icd;
515 pcdev->frame_count = 0;
516
517 dev_info(icd->parent, "Camera driver attached to camera %d\n",
518 icd->devnum);
519
520 return 0;
521
522 exit_csi_ahb:
523 clk_disable_unprepare(pcdev->clk_csi_ahb);
524
525 return ret;
526 }
527
528 static void mx2_camera_remove_device(struct soc_camera_device *icd)
529 {
530 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
531 struct mx2_camera_dev *pcdev = ici->priv;
532
533 BUG_ON(icd != pcdev->icd);
534
535 dev_info(icd->parent, "Camera driver detached from camera %d\n",
536 icd->devnum);
537
538 mx2_camera_deactivate(pcdev);
539
540 pcdev->icd = NULL;
541 }
542
543 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
544 int state)
545 {
546 struct vb2_buffer *vb;
547 struct mx2_buffer *buf;
548 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
549 &pcdev->fb2_active;
550 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
551 unsigned long flags;
552
553 spin_lock_irqsave(&pcdev->lock, flags);
554
555 if (*fb_active == NULL)
556 goto out;
557
558 vb = &(*fb_active)->vb;
559 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
560 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
561
562 do_gettimeofday(&vb->v4l2_buf.timestamp);
563 vb->v4l2_buf.sequence++;
564 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
565
566 if (list_empty(&pcdev->capture)) {
567 buf = NULL;
568 writel(0, pcdev->base_csi + fb_reg);
569 } else {
570 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
571 internal.queue);
572 vb = &buf->vb;
573 list_del(&buf->internal.queue);
574 buf->state = MX2_STATE_ACTIVE;
575 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
576 pcdev->base_csi + fb_reg);
577 }
578
579 *fb_active = buf;
580
581 out:
582 spin_unlock_irqrestore(&pcdev->lock, flags);
583 }
584
585 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
586 {
587 struct mx2_camera_dev *pcdev = data;
588 u32 status = readl(pcdev->base_csi + pcdev->reg_csisr);
589
590 if (status & CSISR_DMA_TSF_FB1_INT)
591 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
592 else if (status & CSISR_DMA_TSF_FB2_INT)
593 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
594
595 /* FIXME: handle CSISR_RFF_OR_INT */
596
597 writel(status, pcdev->base_csi + pcdev->reg_csisr);
598
599 return IRQ_HANDLED;
600 }
601
602 /*
603 * Videobuf operations
604 */
605 static int mx2_videobuf_setup(struct vb2_queue *vq,
606 const struct v4l2_format *fmt,
607 unsigned int *count, unsigned int *num_planes,
608 unsigned int sizes[], void *alloc_ctxs[])
609 {
610 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
611 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
612 struct mx2_camera_dev *pcdev = ici->priv;
613
614 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
615
616 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
617 if (fmt != NULL)
618 return -ENOTTY;
619
620 alloc_ctxs[0] = pcdev->alloc_ctx;
621
622 sizes[0] = icd->sizeimage;
623
624 if (0 == *count)
625 *count = 32;
626 if (!*num_planes &&
627 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
628 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
629
630 *num_planes = 1;
631
632 return 0;
633 }
634
635 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
636 {
637 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
638 int ret = 0;
639
640 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
641 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
642
643 #ifdef DEBUG
644 /*
645 * This can be useful if you want to see if we actually fill
646 * the buffer with something
647 */
648 memset((void *)vb2_plane_vaddr(vb, 0),
649 0xaa, vb2_get_plane_payload(vb, 0));
650 #endif
651
652 vb2_set_plane_payload(vb, 0, icd->sizeimage);
653 if (vb2_plane_vaddr(vb, 0) &&
654 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
655 ret = -EINVAL;
656 goto out;
657 }
658
659 return 0;
660
661 out:
662 return ret;
663 }
664
665 static void mx2_videobuf_queue(struct vb2_buffer *vb)
666 {
667 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
668 struct soc_camera_host *ici =
669 to_soc_camera_host(icd->parent);
670 struct mx2_camera_dev *pcdev = ici->priv;
671 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
672 unsigned long flags;
673
674 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
675 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
676
677 spin_lock_irqsave(&pcdev->lock, flags);
678
679 buf->state = MX2_STATE_QUEUED;
680 list_add_tail(&buf->internal.queue, &pcdev->capture);
681
682 if (is_imx25_camera(pcdev)) {
683 u32 csicr3, dma_inten = 0;
684
685 if (pcdev->fb1_active == NULL) {
686 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
687 pcdev->base_csi + CSIDMASA_FB1);
688 pcdev->fb1_active = buf;
689 dma_inten = CSICR1_FB1_DMA_INTEN;
690 } else if (pcdev->fb2_active == NULL) {
691 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
692 pcdev->base_csi + CSIDMASA_FB2);
693 pcdev->fb2_active = buf;
694 dma_inten = CSICR1_FB2_DMA_INTEN;
695 }
696
697 if (dma_inten) {
698 list_del(&buf->internal.queue);
699 buf->state = MX2_STATE_ACTIVE;
700
701 csicr3 = readl(pcdev->base_csi + pcdev->reg_csicr3);
702
703 /* Reflash DMA */
704 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
705 pcdev->base_csi + pcdev->reg_csicr3);
706
707 /* clear & enable interrupts */
708 writel(dma_inten, pcdev->base_csi + pcdev->reg_csisr);
709 pcdev->csicr1 |= dma_inten;
710 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
711
712 /* enable DMA */
713 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
714 writel(csicr3, pcdev->base_csi + pcdev->reg_csicr3);
715 }
716 }
717
718 spin_unlock_irqrestore(&pcdev->lock, flags);
719 }
720
721 static void mx2_videobuf_release(struct vb2_buffer *vb)
722 {
723 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
724 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
725 struct mx2_camera_dev *pcdev = ici->priv;
726 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
727 unsigned long flags;
728
729 #ifdef DEBUG
730 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
731 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
732
733 switch (buf->state) {
734 case MX2_STATE_ACTIVE:
735 dev_info(icd->parent, "%s (active)\n", __func__);
736 break;
737 case MX2_STATE_QUEUED:
738 dev_info(icd->parent, "%s (queued)\n", __func__);
739 break;
740 default:
741 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
742 buf->state);
743 break;
744 }
745 #endif
746
747 /*
748 * Terminate only queued but inactive buffers. Active buffers are
749 * released when they become inactive after videobuf_waiton().
750 *
751 * FIXME: implement forced termination of active buffers for mx27 and
752 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
753 * state. This requires a specific handling for each of the these DMA
754 * types.
755 */
756
757 spin_lock_irqsave(&pcdev->lock, flags);
758 if (is_imx25_camera(pcdev) && buf->state == MX2_STATE_ACTIVE) {
759 if (pcdev->fb1_active == buf) {
760 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
761 writel(0, pcdev->base_csi + CSIDMASA_FB1);
762 pcdev->fb1_active = NULL;
763 } else if (pcdev->fb2_active == buf) {
764 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
765 writel(0, pcdev->base_csi + CSIDMASA_FB2);
766 pcdev->fb2_active = NULL;
767 }
768 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
769 }
770 spin_unlock_irqrestore(&pcdev->lock, flags);
771 }
772
773 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
774 int bytesperline)
775 {
776 struct soc_camera_host *ici =
777 to_soc_camera_host(icd->parent);
778 struct mx2_camera_dev *pcdev = ici->priv;
779 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
780
781 writel((pcdev->s_width << 16) | pcdev->s_height,
782 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
783 writel(prp->cfg.src_pixel,
784 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
785 if (prp->cfg.channel == 1) {
786 writel((icd->user_width << 16) | icd->user_height,
787 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
788 writel(bytesperline,
789 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
790 writel(prp->cfg.ch1_pixel,
791 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
792 } else { /* channel 2 */
793 writel((icd->user_width << 16) | icd->user_height,
794 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
795 }
796
797 /* Enable interrupts */
798 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
799 }
800
801 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
802 {
803 int dir;
804
805 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
806 unsigned char *s = pcdev->resizing[dir].s;
807 int len = pcdev->resizing[dir].len;
808 unsigned int coeff[2] = {0, 0};
809 unsigned int valid = 0;
810 int i;
811
812 if (len == 0)
813 continue;
814
815 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
816 int j;
817
818 j = i > 9 ? 1 : 0;
819 coeff[j] = (coeff[j] << BC_COEF) |
820 (s[i] & (SZ_COEF - 1));
821
822 if (i == 5 || i == 15)
823 coeff[j] <<= 1;
824
825 valid = (valid << 1) | (s[i] >> BC_COEF);
826 }
827
828 valid |= PRP_RZ_VALID_TBL_LEN(len);
829
830 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
831 valid |= PRP_RZ_VALID_BILINEAR;
832
833 if (pcdev->emma_prp->cfg.channel == 1) {
834 if (dir == RESIZE_DIR_H) {
835 writel(coeff[0], pcdev->base_emma +
836 PRP_CH1_RZ_HORI_COEF1);
837 writel(coeff[1], pcdev->base_emma +
838 PRP_CH1_RZ_HORI_COEF2);
839 writel(valid, pcdev->base_emma +
840 PRP_CH1_RZ_HORI_VALID);
841 } else {
842 writel(coeff[0], pcdev->base_emma +
843 PRP_CH1_RZ_VERT_COEF1);
844 writel(coeff[1], pcdev->base_emma +
845 PRP_CH1_RZ_VERT_COEF2);
846 writel(valid, pcdev->base_emma +
847 PRP_CH1_RZ_VERT_VALID);
848 }
849 } else {
850 if (dir == RESIZE_DIR_H) {
851 writel(coeff[0], pcdev->base_emma +
852 PRP_CH2_RZ_HORI_COEF1);
853 writel(coeff[1], pcdev->base_emma +
854 PRP_CH2_RZ_HORI_COEF2);
855 writel(valid, pcdev->base_emma +
856 PRP_CH2_RZ_HORI_VALID);
857 } else {
858 writel(coeff[0], pcdev->base_emma +
859 PRP_CH2_RZ_VERT_COEF1);
860 writel(coeff[1], pcdev->base_emma +
861 PRP_CH2_RZ_VERT_COEF2);
862 writel(valid, pcdev->base_emma +
863 PRP_CH2_RZ_VERT_VALID);
864 }
865 }
866 }
867 }
868
869 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
870 {
871 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
872 struct soc_camera_host *ici =
873 to_soc_camera_host(icd->parent);
874 struct mx2_camera_dev *pcdev = ici->priv;
875 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
876 struct vb2_buffer *vb;
877 struct mx2_buffer *buf;
878 unsigned long phys;
879 int bytesperline;
880
881 if (is_imx27_camera(pcdev)) {
882 unsigned long flags;
883 if (count < 2)
884 return -EINVAL;
885
886 spin_lock_irqsave(&pcdev->lock, flags);
887
888 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
889 internal.queue);
890 buf->internal.bufnum = 0;
891 vb = &buf->vb;
892 buf->state = MX2_STATE_ACTIVE;
893
894 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
895 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
896 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
897
898 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
899 internal.queue);
900 buf->internal.bufnum = 1;
901 vb = &buf->vb;
902 buf->state = MX2_STATE_ACTIVE;
903
904 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
905 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
906 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
907
908 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
909 icd->current_fmt->host_fmt);
910 if (bytesperline < 0) {
911 spin_unlock_irqrestore(&pcdev->lock, flags);
912 return bytesperline;
913 }
914
915 /*
916 * I didn't manage to properly enable/disable the prp
917 * on a per frame basis during running transfers,
918 * thus we allocate a buffer here and use it to
919 * discard frames when no buffer is available.
920 * Feel free to work on this ;)
921 */
922 pcdev->discard_size = icd->user_height * bytesperline;
923 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
924 pcdev->discard_size, &pcdev->discard_buffer_dma,
925 GFP_KERNEL);
926 if (!pcdev->discard_buffer) {
927 spin_unlock_irqrestore(&pcdev->lock, flags);
928 return -ENOMEM;
929 }
930
931 pcdev->buf_discard[0].discard = true;
932 list_add_tail(&pcdev->buf_discard[0].queue,
933 &pcdev->discard);
934
935 pcdev->buf_discard[1].discard = true;
936 list_add_tail(&pcdev->buf_discard[1].queue,
937 &pcdev->discard);
938
939 mx2_prp_resize_commit(pcdev);
940
941 mx27_camera_emma_buf_init(icd, bytesperline);
942
943 if (prp->cfg.channel == 1) {
944 writel(PRP_CNTL_CH1EN |
945 PRP_CNTL_CSIEN |
946 prp->cfg.in_fmt |
947 prp->cfg.out_fmt |
948 PRP_CNTL_CH1_LEN |
949 PRP_CNTL_CH1BYP |
950 PRP_CNTL_CH1_TSKIP(0) |
951 PRP_CNTL_IN_TSKIP(0),
952 pcdev->base_emma + PRP_CNTL);
953 } else {
954 writel(PRP_CNTL_CH2EN |
955 PRP_CNTL_CSIEN |
956 prp->cfg.in_fmt |
957 prp->cfg.out_fmt |
958 PRP_CNTL_CH2_LEN |
959 PRP_CNTL_CH2_TSKIP(0) |
960 PRP_CNTL_IN_TSKIP(0),
961 pcdev->base_emma + PRP_CNTL);
962 }
963 spin_unlock_irqrestore(&pcdev->lock, flags);
964 }
965
966 return 0;
967 }
968
969 static int mx2_stop_streaming(struct vb2_queue *q)
970 {
971 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
972 struct soc_camera_host *ici =
973 to_soc_camera_host(icd->parent);
974 struct mx2_camera_dev *pcdev = ici->priv;
975 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
976 unsigned long flags;
977 void *b;
978 u32 cntl;
979
980 if (is_imx27_camera(pcdev)) {
981 spin_lock_irqsave(&pcdev->lock, flags);
982
983 cntl = readl(pcdev->base_emma + PRP_CNTL);
984 if (prp->cfg.channel == 1) {
985 writel(cntl & ~PRP_CNTL_CH1EN,
986 pcdev->base_emma + PRP_CNTL);
987 } else {
988 writel(cntl & ~PRP_CNTL_CH2EN,
989 pcdev->base_emma + PRP_CNTL);
990 }
991 INIT_LIST_HEAD(&pcdev->capture);
992 INIT_LIST_HEAD(&pcdev->active_bufs);
993 INIT_LIST_HEAD(&pcdev->discard);
994
995 b = pcdev->discard_buffer;
996 pcdev->discard_buffer = NULL;
997
998 spin_unlock_irqrestore(&pcdev->lock, flags);
999
1000 dma_free_coherent(ici->v4l2_dev.dev,
1001 pcdev->discard_size, b, pcdev->discard_buffer_dma);
1002 }
1003
1004 return 0;
1005 }
1006
1007 static struct vb2_ops mx2_videobuf_ops = {
1008 .queue_setup = mx2_videobuf_setup,
1009 .buf_prepare = mx2_videobuf_prepare,
1010 .buf_queue = mx2_videobuf_queue,
1011 .buf_cleanup = mx2_videobuf_release,
1012 .start_streaming = mx2_start_streaming,
1013 .stop_streaming = mx2_stop_streaming,
1014 };
1015
1016 static int mx2_camera_init_videobuf(struct vb2_queue *q,
1017 struct soc_camera_device *icd)
1018 {
1019 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1020 q->io_modes = VB2_MMAP | VB2_USERPTR;
1021 q->drv_priv = icd;
1022 q->ops = &mx2_videobuf_ops;
1023 q->mem_ops = &vb2_dma_contig_memops;
1024 q->buf_struct_size = sizeof(struct mx2_buffer);
1025
1026 return vb2_queue_init(q);
1027 }
1028
1029 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
1030 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
1031 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
1032 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
1033 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
1034 V4L2_MBUS_PCLK_SAMPLE_RISING | \
1035 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
1036 V4L2_MBUS_DATA_ACTIVE_HIGH | \
1037 V4L2_MBUS_DATA_ACTIVE_LOW)
1038
1039 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
1040 {
1041 u32 cntl;
1042 int count = 0;
1043
1044 cntl = readl(pcdev->base_emma + PRP_CNTL);
1045 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
1046 while (count++ < 100) {
1047 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
1048 return 0;
1049 barrier();
1050 udelay(1);
1051 }
1052
1053 return -ETIMEDOUT;
1054 }
1055
1056 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
1057 {
1058 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1059 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1060 struct mx2_camera_dev *pcdev = ici->priv;
1061 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1062 unsigned long common_flags;
1063 int ret;
1064 int bytesperline;
1065 u32 csicr1 = pcdev->csicr1;
1066
1067 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1068 if (!ret) {
1069 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
1070 if (!common_flags) {
1071 dev_warn(icd->parent,
1072 "Flags incompatible: camera 0x%x, host 0x%x\n",
1073 cfg.flags, MX2_BUS_FLAGS);
1074 return -EINVAL;
1075 }
1076 } else if (ret != -ENOIOCTLCMD) {
1077 return ret;
1078 } else {
1079 common_flags = MX2_BUS_FLAGS;
1080 }
1081
1082 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1083 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1084 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
1085 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1086 else
1087 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1088 }
1089
1090 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1091 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1092 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
1093 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1094 else
1095 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1096 }
1097
1098 cfg.flags = common_flags;
1099 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1100 if (ret < 0 && ret != -ENOIOCTLCMD) {
1101 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1102 common_flags, ret);
1103 return ret;
1104 }
1105
1106 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
1107
1108 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1109 csicr1 |= CSICR1_REDGE;
1110 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1111 csicr1 |= CSICR1_SOF_POL;
1112 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1113 csicr1 |= CSICR1_HSYNC_POL;
1114 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
1115 csicr1 |= CSICR1_EXT_VSYNC;
1116 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
1117 csicr1 |= CSICR1_CCIR_EN;
1118 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
1119 csicr1 |= CSICR1_CCIR_MODE;
1120 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
1121 csicr1 |= CSICR1_GCLK_MODE;
1122 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
1123 csicr1 |= CSICR1_INV_DATA;
1124
1125 pcdev->csicr1 = csicr1;
1126
1127 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
1128 icd->current_fmt->host_fmt);
1129 if (bytesperline < 0)
1130 return bytesperline;
1131
1132 if (is_imx27_camera(pcdev)) {
1133 ret = mx27_camera_emma_prp_reset(pcdev);
1134 if (ret)
1135 return ret;
1136 } else if (is_imx25_camera(pcdev)) {
1137 writel((bytesperline * icd->user_height) >> 2,
1138 pcdev->base_csi + CSIRXCNT);
1139 writel((bytesperline << 16) | icd->user_height,
1140 pcdev->base_csi + CSIIMAG_PARA);
1141 }
1142
1143 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
1144
1145 return 0;
1146 }
1147
1148 static int mx2_camera_set_crop(struct soc_camera_device *icd,
1149 const struct v4l2_crop *a)
1150 {
1151 struct v4l2_crop a_writable = *a;
1152 struct v4l2_rect *rect = &a_writable.c;
1153 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1154 struct v4l2_mbus_framefmt mf;
1155 int ret;
1156
1157 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
1158 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
1159
1160 ret = v4l2_subdev_call(sd, video, s_crop, a);
1161 if (ret < 0)
1162 return ret;
1163
1164 /* The capture device might have changed its output */
1165 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1166 if (ret < 0)
1167 return ret;
1168
1169 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
1170 mf.width, mf.height);
1171
1172 icd->user_width = mf.width;
1173 icd->user_height = mf.height;
1174
1175 return ret;
1176 }
1177
1178 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1179 unsigned int idx,
1180 struct soc_camera_format_xlate *xlate)
1181 {
1182 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1183 const struct soc_mbus_pixelfmt *fmt;
1184 struct device *dev = icd->parent;
1185 enum v4l2_mbus_pixelcode code;
1186 int ret, formats = 0;
1187
1188 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1189 if (ret < 0)
1190 /* no more formats */
1191 return 0;
1192
1193 fmt = soc_mbus_get_fmtdesc(code);
1194 if (!fmt) {
1195 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1196 return 0;
1197 }
1198
1199 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1200 code == V4L2_MBUS_FMT_UYVY8_2X8) {
1201 formats++;
1202 if (xlate) {
1203 /*
1204 * CH2 can output YUV420 which is a standard format in
1205 * soc_mediabus.c
1206 */
1207 xlate->host_fmt =
1208 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1209 xlate->code = code;
1210 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1211 xlate->host_fmt->name, code);
1212 xlate++;
1213 }
1214 }
1215
1216 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
1217 formats++;
1218 if (xlate) {
1219 xlate->host_fmt =
1220 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
1221 xlate->code = code;
1222 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1223 xlate->host_fmt->name, code);
1224 xlate++;
1225 }
1226 }
1227
1228 /* Generic pass-trough */
1229 formats++;
1230 if (xlate) {
1231 xlate->host_fmt = fmt;
1232 xlate->code = code;
1233 xlate++;
1234 }
1235 return formats;
1236 }
1237
1238 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1239 struct v4l2_mbus_framefmt *mf_in,
1240 struct v4l2_pix_format *pix_out, bool apply)
1241 {
1242 int num, den;
1243 unsigned long m;
1244 int i, dir;
1245
1246 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1247 struct emma_prp_resize tmprsz;
1248 unsigned char *s = tmprsz.s;
1249 int len = 0;
1250 int in, out;
1251
1252 if (dir == RESIZE_DIR_H) {
1253 in = mf_in->width;
1254 out = pix_out->width;
1255 } else {
1256 in = mf_in->height;
1257 out = pix_out->height;
1258 }
1259
1260 if (in < out)
1261 return -EINVAL;
1262 else if (in == out)
1263 continue;
1264
1265 /* Calculate ratio */
1266 m = gcd(in, out);
1267 num = in / m;
1268 den = out / m;
1269 if (num > RESIZE_NUM_MAX)
1270 return -EINVAL;
1271
1272 if ((num >= 2 * den) && (den == 1) &&
1273 (num < 9) && (!(num & 0x01))) {
1274 int sum = 0;
1275 int j;
1276
1277 /* Average scaling for >= 2:1 ratios */
1278 /* Support can be added for num >=9 and odd values */
1279
1280 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1281 len = num;
1282
1283 for (i = 0; i < (len / 2); i++)
1284 s[i] = 8;
1285
1286 do {
1287 for (i = 0; i < (len / 2); i++) {
1288 s[i] = s[i] >> 1;
1289 sum = 0;
1290 for (j = 0; j < (len / 2); j++)
1291 sum += s[j];
1292 if (sum == 4)
1293 break;
1294 }
1295 } while (sum != 4);
1296
1297 for (i = (len / 2); i < len; i++)
1298 s[i] = s[len - i - 1];
1299
1300 s[len - 1] |= SZ_COEF;
1301 } else {
1302 /* bilinear scaling for < 2:1 ratios */
1303 int v; /* overflow counter */
1304 int coeff, nxt; /* table output */
1305 int in_pos_inc = 2 * den;
1306 int out_pos = num;
1307 int out_pos_inc = 2 * num;
1308 int init_carry = num - den;
1309 int carry = init_carry;
1310
1311 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1312 v = den + in_pos_inc;
1313 do {
1314 coeff = v - out_pos;
1315 out_pos += out_pos_inc;
1316 carry += out_pos_inc;
1317 for (nxt = 0; v < out_pos; nxt++) {
1318 v += in_pos_inc;
1319 carry -= in_pos_inc;
1320 }
1321
1322 if (len > RESIZE_NUM_MAX)
1323 return -EINVAL;
1324
1325 coeff = ((coeff << BC_COEF) +
1326 (in_pos_inc >> 1)) / in_pos_inc;
1327
1328 if (coeff >= (SZ_COEF - 1))
1329 coeff--;
1330
1331 coeff |= SZ_COEF;
1332 s[len] = (unsigned char)coeff;
1333 len++;
1334
1335 for (i = 1; i < nxt; i++) {
1336 if (len >= RESIZE_NUM_MAX)
1337 return -EINVAL;
1338 s[len] = 0;
1339 len++;
1340 }
1341 } while (carry != init_carry);
1342 }
1343 tmprsz.len = len;
1344 if (dir == RESIZE_DIR_H)
1345 mf_in->width = pix_out->width;
1346 else
1347 mf_in->height = pix_out->height;
1348
1349 if (apply)
1350 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1351 }
1352 return 0;
1353 }
1354
1355 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1356 struct v4l2_format *f)
1357 {
1358 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1359 struct mx2_camera_dev *pcdev = ici->priv;
1360 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1361 const struct soc_camera_format_xlate *xlate;
1362 struct v4l2_pix_format *pix = &f->fmt.pix;
1363 struct v4l2_mbus_framefmt mf;
1364 int ret;
1365
1366 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1367 __func__, pix->width, pix->height);
1368
1369 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1370 if (!xlate) {
1371 dev_warn(icd->parent, "Format %x not found\n",
1372 pix->pixelformat);
1373 return -EINVAL;
1374 }
1375
1376 mf.width = pix->width;
1377 mf.height = pix->height;
1378 mf.field = pix->field;
1379 mf.colorspace = pix->colorspace;
1380 mf.code = xlate->code;
1381
1382 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1383 if (ret < 0 && ret != -ENOIOCTLCMD)
1384 return ret;
1385
1386 /* Store width and height returned by the sensor for resizing */
1387 pcdev->s_width = mf.width;
1388 pcdev->s_height = mf.height;
1389 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1390 __func__, pcdev->s_width, pcdev->s_height);
1391
1392 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1393 xlate->host_fmt->fourcc);
1394
1395 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1396 if ((mf.width != pix->width || mf.height != pix->height) &&
1397 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1398 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1399 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1400 }
1401
1402 if (mf.code != xlate->code)
1403 return -EINVAL;
1404
1405 pix->width = mf.width;
1406 pix->height = mf.height;
1407 pix->field = mf.field;
1408 pix->colorspace = mf.colorspace;
1409 icd->current_fmt = xlate;
1410
1411 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1412 __func__, pix->width, pix->height);
1413
1414 return 0;
1415 }
1416
1417 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1418 struct v4l2_format *f)
1419 {
1420 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1421 const struct soc_camera_format_xlate *xlate;
1422 struct v4l2_pix_format *pix = &f->fmt.pix;
1423 struct v4l2_mbus_framefmt mf;
1424 __u32 pixfmt = pix->pixelformat;
1425 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1426 struct mx2_camera_dev *pcdev = ici->priv;
1427 struct mx2_fmt_cfg *emma_prp;
1428 unsigned int width_limit;
1429 int ret;
1430
1431 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1432 __func__, pix->width, pix->height);
1433
1434 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1435 if (pixfmt && !xlate) {
1436 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1437 return -EINVAL;
1438 }
1439
1440 /* FIXME: implement MX27 limits */
1441
1442 /* limit to MX25 hardware capabilities */
1443 if (is_imx25_camera(pcdev)) {
1444 if (xlate->host_fmt->bits_per_sample <= 8)
1445 width_limit = 0xffff * 4;
1446 else
1447 width_limit = 0xffff * 2;
1448 /* CSIIMAG_PARA limit */
1449 if (pix->width > width_limit)
1450 pix->width = width_limit;
1451 if (pix->height > 0xffff)
1452 pix->height = 0xffff;
1453
1454 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1455 xlate->host_fmt);
1456 if (pix->bytesperline < 0)
1457 return pix->bytesperline;
1458 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1459 pix->bytesperline, pix->height);
1460 /* Check against the CSIRXCNT limit */
1461 if (pix->sizeimage > 4 * 0x3ffff) {
1462 /* Adjust geometry, preserve aspect ratio */
1463 unsigned int new_height = int_sqrt(div_u64(0x3ffffULL *
1464 4 * pix->height, pix->bytesperline));
1465 pix->width = new_height * pix->width / pix->height;
1466 pix->height = new_height;
1467 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1468 xlate->host_fmt);
1469 BUG_ON(pix->bytesperline < 0);
1470 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1471 pix->bytesperline, pix->height);
1472 }
1473 }
1474
1475 /* limit to sensor capabilities */
1476 mf.width = pix->width;
1477 mf.height = pix->height;
1478 mf.field = pix->field;
1479 mf.colorspace = pix->colorspace;
1480 mf.code = xlate->code;
1481
1482 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1483 if (ret < 0)
1484 return ret;
1485
1486 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1487 __func__, pcdev->s_width, pcdev->s_height);
1488
1489 /* If the sensor does not support image size try PrP resizing */
1490 emma_prp = mx27_emma_prp_get_format(xlate->code,
1491 xlate->host_fmt->fourcc);
1492
1493 if ((mf.width != pix->width || mf.height != pix->height) &&
1494 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1495 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1496 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1497 }
1498
1499 if (mf.field == V4L2_FIELD_ANY)
1500 mf.field = V4L2_FIELD_NONE;
1501 /*
1502 * Driver supports interlaced images provided they have
1503 * both fields so that they can be processed as if they
1504 * were progressive.
1505 */
1506 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1507 dev_err(icd->parent, "Field type %d unsupported.\n",
1508 mf.field);
1509 return -EINVAL;
1510 }
1511
1512 pix->width = mf.width;
1513 pix->height = mf.height;
1514 pix->field = mf.field;
1515 pix->colorspace = mf.colorspace;
1516
1517 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1518 __func__, pix->width, pix->height);
1519
1520 return 0;
1521 }
1522
1523 static int mx2_camera_querycap(struct soc_camera_host *ici,
1524 struct v4l2_capability *cap)
1525 {
1526 /* cap->name is set by the friendly caller:-> */
1527 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1528 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1529
1530 return 0;
1531 }
1532
1533 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1534 {
1535 struct soc_camera_device *icd = file->private_data;
1536
1537 return vb2_poll(&icd->vb2_vidq, file, pt);
1538 }
1539
1540 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1541 .owner = THIS_MODULE,
1542 .add = mx2_camera_add_device,
1543 .remove = mx2_camera_remove_device,
1544 .set_fmt = mx2_camera_set_fmt,
1545 .set_crop = mx2_camera_set_crop,
1546 .get_formats = mx2_camera_get_formats,
1547 .try_fmt = mx2_camera_try_fmt,
1548 .init_videobuf2 = mx2_camera_init_videobuf,
1549 .poll = mx2_camera_poll,
1550 .querycap = mx2_camera_querycap,
1551 .set_bus_param = mx2_camera_set_bus_param,
1552 };
1553
1554 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1555 int bufnum, bool err)
1556 {
1557 #ifdef DEBUG
1558 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1559 #endif
1560 struct mx2_buf_internal *ibuf;
1561 struct mx2_buffer *buf;
1562 struct vb2_buffer *vb;
1563 unsigned long phys;
1564
1565 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1566 queue);
1567
1568 BUG_ON(ibuf->bufnum != bufnum);
1569
1570 if (ibuf->discard) {
1571 /*
1572 * Discard buffer must not be returned to user space.
1573 * Just return it to the discard queue.
1574 */
1575 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1576 } else {
1577 buf = mx2_ibuf_to_buf(ibuf);
1578
1579 vb = &buf->vb;
1580 #ifdef DEBUG
1581 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1582 if (prp->cfg.channel == 1) {
1583 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1584 4 * bufnum) != phys) {
1585 dev_err(pcdev->dev, "%lx != %x\n", phys,
1586 readl(pcdev->base_emma +
1587 PRP_DEST_RGB1_PTR + 4 * bufnum));
1588 }
1589 } else {
1590 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1591 0x14 * bufnum) != phys) {
1592 dev_err(pcdev->dev, "%lx != %x\n", phys,
1593 readl(pcdev->base_emma +
1594 PRP_DEST_Y_PTR - 0x14 * bufnum));
1595 }
1596 }
1597 #endif
1598 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1599 vb2_plane_vaddr(vb, 0),
1600 vb2_get_plane_payload(vb, 0));
1601
1602 list_del_init(&buf->internal.queue);
1603 do_gettimeofday(&vb->v4l2_buf.timestamp);
1604 vb->v4l2_buf.sequence = pcdev->frame_count;
1605 if (err)
1606 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1607 else
1608 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1609 }
1610
1611 pcdev->frame_count++;
1612
1613 if (list_empty(&pcdev->capture)) {
1614 if (list_empty(&pcdev->discard)) {
1615 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1616 __func__);
1617 return;
1618 }
1619
1620 ibuf = list_first_entry(&pcdev->discard,
1621 struct mx2_buf_internal, queue);
1622 ibuf->bufnum = bufnum;
1623
1624 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1625 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1626 return;
1627 }
1628
1629 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1630 internal.queue);
1631
1632 buf->internal.bufnum = bufnum;
1633
1634 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1635
1636 vb = &buf->vb;
1637 buf->state = MX2_STATE_ACTIVE;
1638
1639 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1640 mx27_update_emma_buf(pcdev, phys, bufnum);
1641 }
1642
1643 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1644 {
1645 struct mx2_camera_dev *pcdev = data;
1646 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1647 struct mx2_buf_internal *ibuf;
1648
1649 spin_lock(&pcdev->lock);
1650
1651 if (list_empty(&pcdev->active_bufs)) {
1652 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1653 __func__);
1654
1655 if (!status) {
1656 spin_unlock(&pcdev->lock);
1657 return IRQ_NONE;
1658 }
1659 }
1660
1661 if (status & (1 << 7)) { /* overflow */
1662 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1663 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1664 pcdev->base_emma + PRP_CNTL);
1665 writel(cntl, pcdev->base_emma + PRP_CNTL);
1666
1667 ibuf = list_first_entry(&pcdev->active_bufs,
1668 struct mx2_buf_internal, queue);
1669 mx27_camera_frame_done_emma(pcdev,
1670 ibuf->bufnum, true);
1671
1672 status &= ~(1 << 7);
1673 } else if (((status & (3 << 5)) == (3 << 5)) ||
1674 ((status & (3 << 3)) == (3 << 3))) {
1675 /*
1676 * Both buffers have triggered, process the one we're expecting
1677 * to first
1678 */
1679 ibuf = list_first_entry(&pcdev->active_bufs,
1680 struct mx2_buf_internal, queue);
1681 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1682 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1683 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1684 mx27_camera_frame_done_emma(pcdev, 0, false);
1685 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1686 mx27_camera_frame_done_emma(pcdev, 1, false);
1687 }
1688
1689 spin_unlock(&pcdev->lock);
1690 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1691
1692 return IRQ_HANDLED;
1693 }
1694
1695 static int __devinit mx27_camera_emma_init(struct platform_device *pdev)
1696 {
1697 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1698 struct resource *res_emma;
1699 int irq_emma;
1700 int err = 0;
1701
1702 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1703 irq_emma = platform_get_irq(pdev, 1);
1704 if (!res_emma || !irq_emma) {
1705 dev_err(pcdev->dev, "no EMMA resources\n");
1706 err = -ENODEV;
1707 goto out;
1708 }
1709
1710 pcdev->base_emma = devm_request_and_ioremap(pcdev->dev, res_emma);
1711 if (!pcdev->base_emma) {
1712 err = -EADDRNOTAVAIL;
1713 goto out;
1714 }
1715
1716 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1717 MX2_CAM_DRV_NAME, pcdev);
1718 if (err) {
1719 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1720 goto out;
1721 }
1722
1723 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1724 if (IS_ERR(pcdev->clk_emma_ipg)) {
1725 err = PTR_ERR(pcdev->clk_emma_ipg);
1726 goto out;
1727 }
1728
1729 clk_prepare_enable(pcdev->clk_emma_ipg);
1730
1731 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1732 if (IS_ERR(pcdev->clk_emma_ahb)) {
1733 err = PTR_ERR(pcdev->clk_emma_ahb);
1734 goto exit_clk_emma_ipg;
1735 }
1736
1737 clk_prepare_enable(pcdev->clk_emma_ahb);
1738
1739 err = mx27_camera_emma_prp_reset(pcdev);
1740 if (err)
1741 goto exit_clk_emma_ahb;
1742
1743 return err;
1744
1745 exit_clk_emma_ahb:
1746 clk_disable_unprepare(pcdev->clk_emma_ahb);
1747 exit_clk_emma_ipg:
1748 clk_disable_unprepare(pcdev->clk_emma_ipg);
1749 out:
1750 return err;
1751 }
1752
1753 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1754 {
1755 struct mx2_camera_dev *pcdev;
1756 struct resource *res_csi;
1757 int irq_csi;
1758 int err = 0;
1759
1760 dev_dbg(&pdev->dev, "initialising\n");
1761
1762 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1763 irq_csi = platform_get_irq(pdev, 0);
1764 if (res_csi == NULL || irq_csi < 0) {
1765 dev_err(&pdev->dev, "Missing platform resources data\n");
1766 err = -ENODEV;
1767 goto exit;
1768 }
1769
1770 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1771 if (!pcdev) {
1772 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1773 err = -ENOMEM;
1774 goto exit;
1775 }
1776
1777 pcdev->devtype = pdev->id_entry->driver_data;
1778 switch (pcdev->devtype) {
1779 case IMX25_CAMERA:
1780 pcdev->reg_csisr = CSISR_IMX25;
1781 pcdev->reg_csicr3 = CSICR3_IMX25;
1782 break;
1783 case IMX27_CAMERA:
1784 pcdev->reg_csisr = CSISR_IMX27;
1785 pcdev->reg_csicr3 = CSICR3_IMX27;
1786 break;
1787 default:
1788 break;
1789 }
1790
1791 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1792 if (IS_ERR(pcdev->clk_csi_ahb)) {
1793 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1794 err = PTR_ERR(pcdev->clk_csi_ahb);
1795 goto exit;
1796 }
1797
1798 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1799 if (IS_ERR(pcdev->clk_csi_per)) {
1800 dev_err(&pdev->dev, "Could not get csi per clock\n");
1801 err = PTR_ERR(pcdev->clk_csi_per);
1802 goto exit;
1803 }
1804
1805 pcdev->pdata = pdev->dev.platform_data;
1806 if (pcdev->pdata) {
1807 long rate;
1808
1809 pcdev->platform_flags = pcdev->pdata->flags;
1810
1811 rate = clk_round_rate(pcdev->clk_csi_per,
1812 pcdev->pdata->clk * 2);
1813 if (rate <= 0) {
1814 err = -ENODEV;
1815 goto exit;
1816 }
1817 err = clk_set_rate(pcdev->clk_csi_per, rate);
1818 if (err < 0)
1819 goto exit;
1820 }
1821
1822 INIT_LIST_HEAD(&pcdev->capture);
1823 INIT_LIST_HEAD(&pcdev->active_bufs);
1824 INIT_LIST_HEAD(&pcdev->discard);
1825 spin_lock_init(&pcdev->lock);
1826
1827 pcdev->base_csi = devm_request_and_ioremap(&pdev->dev, res_csi);
1828 if (!pcdev->base_csi) {
1829 err = -EADDRNOTAVAIL;
1830 goto exit;
1831 }
1832
1833 pcdev->dev = &pdev->dev;
1834 platform_set_drvdata(pdev, pcdev);
1835
1836 if (is_imx25_camera(pcdev)) {
1837 err = devm_request_irq(&pdev->dev, irq_csi, mx25_camera_irq, 0,
1838 MX2_CAM_DRV_NAME, pcdev);
1839 if (err) {
1840 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1841 goto exit;
1842 }
1843 }
1844
1845 if (is_imx27_camera(pcdev)) {
1846 err = mx27_camera_emma_init(pdev);
1847 if (err)
1848 goto exit;
1849 }
1850
1851 /*
1852 * We're done with drvdata here. Clear the pointer so that
1853 * v4l2 core can start using drvdata on its purpose.
1854 */
1855 platform_set_drvdata(pdev, NULL);
1856
1857 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1858 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1859 pcdev->soc_host.priv = pcdev;
1860 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1861 pcdev->soc_host.nr = pdev->id;
1862 if (is_imx25_camera(pcdev))
1863 pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE;
1864
1865 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1866 if (IS_ERR(pcdev->alloc_ctx)) {
1867 err = PTR_ERR(pcdev->alloc_ctx);
1868 goto eallocctx;
1869 }
1870 err = soc_camera_host_register(&pcdev->soc_host);
1871 if (err)
1872 goto exit_free_emma;
1873
1874 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1875 clk_get_rate(pcdev->clk_csi_per));
1876
1877 return 0;
1878
1879 exit_free_emma:
1880 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1881 eallocctx:
1882 if (is_imx27_camera(pcdev)) {
1883 clk_disable_unprepare(pcdev->clk_emma_ipg);
1884 clk_disable_unprepare(pcdev->clk_emma_ahb);
1885 }
1886 exit:
1887 return err;
1888 }
1889
1890 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1891 {
1892 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1893 struct mx2_camera_dev *pcdev = container_of(soc_host,
1894 struct mx2_camera_dev, soc_host);
1895
1896 soc_camera_host_unregister(&pcdev->soc_host);
1897
1898 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1899
1900 if (is_imx27_camera(pcdev)) {
1901 clk_disable_unprepare(pcdev->clk_emma_ipg);
1902 clk_disable_unprepare(pcdev->clk_emma_ahb);
1903 }
1904
1905 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1906
1907 return 0;
1908 }
1909
1910 static struct platform_driver mx2_camera_driver = {
1911 .driver = {
1912 .name = MX2_CAM_DRV_NAME,
1913 },
1914 .id_table = mx2_camera_devtype,
1915 .remove = __devexit_p(mx2_camera_remove),
1916 };
1917
1918
1919 static int __init mx2_camera_init(void)
1920 {
1921 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1922 }
1923
1924 static void __exit mx2_camera_exit(void)
1925 {
1926 return platform_driver_unregister(&mx2_camera_driver);
1927 }
1928
1929 module_init(mx2_camera_init);
1930 module_exit(mx2_camera_exit);
1931
1932 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1933 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1934 MODULE_LICENSE("GPL");
1935 MODULE_VERSION(MX2_CAM_VERSION);
kernel source for telekom puls (alcatel/mediatek)