projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[media] rc: unlock on error in show_protocols()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / platform / soc_camera / mx2_camera.c
1 /*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
26 #include <linux/mm.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/mutex.h>
32 #include <linux/clk.h>
33
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-dev.h>
36 #include <media/videobuf2-core.h>
37 #include <media/videobuf2-dma-contig.h>
38 #include <media/soc_camera.h>
39 #include <media/soc_mediabus.h>
40
41 #include <linux/videodev2.h>
42
43 #include <linux/platform_data/camera-mx2.h>
44 #include <mach/hardware.h>
45
46 #include <asm/dma.h>
47
48 #define MX2_CAM_DRV_NAME "mx2-camera"
49 #define MX2_CAM_VERSION "0.0.6"
50 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51
52 /* reset values */
53 #define CSICR1_RESET_VAL 0x40000800
54 #define CSICR2_RESET_VAL 0x0
55 #define CSICR3_RESET_VAL 0x0
56
57 /* csi control reg 1 */
58 #define CSICR1_SWAP16_EN (1 << 31)
59 #define CSICR1_EXT_VSYNC (1 << 30)
60 #define CSICR1_EOF_INTEN (1 << 29)
61 #define CSICR1_PRP_IF_EN (1 << 28)
62 #define CSICR1_CCIR_MODE (1 << 27)
63 #define CSICR1_COF_INTEN (1 << 26)
64 #define CSICR1_SF_OR_INTEN (1 << 25)
65 #define CSICR1_RF_OR_INTEN (1 << 24)
66 #define CSICR1_STATFF_LEVEL (3 << 22)
67 #define CSICR1_STATFF_INTEN (1 << 21)
68 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
69 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
70 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
71 #define CSICR1_RXFF_INTEN (1 << 18)
72 #define CSICR1_SOF_POL (1 << 17)
73 #define CSICR1_SOF_INTEN (1 << 16)
74 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
75 #define CSICR1_HSYNC_POL (1 << 11)
76 #define CSICR1_CCIR_EN (1 << 10)
77 #define CSICR1_MCLKEN (1 << 9)
78 #define CSICR1_FCC (1 << 8)
79 #define CSICR1_PACK_DIR (1 << 7)
80 #define CSICR1_CLR_STATFIFO (1 << 6)
81 #define CSICR1_CLR_RXFIFO (1 << 5)
82 #define CSICR1_GCLK_MODE (1 << 4)
83 #define CSICR1_INV_DATA (1 << 3)
84 #define CSICR1_INV_PCLK (1 << 2)
85 #define CSICR1_REDGE (1 << 1)
86 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
87
88 #define SHIFT_STATFF_LEVEL 22
89 #define SHIFT_RXFF_LEVEL 19
90 #define SHIFT_MCLKDIV 12
91
92 /* control reg 3 */
93 #define CSICR3_FRMCNT (0xFFFF << 16)
94 #define CSICR3_FRMCNT_RST (1 << 15)
95 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
96 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
97 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
98 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
99 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
100 #define CSICR3_CSI_SUP (1 << 3)
101 #define CSICR3_ZERO_PACK_EN (1 << 2)
102 #define CSICR3_ECC_INT_EN (1 << 1)
103 #define CSICR3_ECC_AUTO_EN (1 << 0)
104
105 #define SHIFT_FRMCNT 16
106
107 /* csi status reg */
108 #define CSISR_SFF_OR_INT (1 << 25)
109 #define CSISR_RFF_OR_INT (1 << 24)
110 #define CSISR_STATFF_INT (1 << 21)
111 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
112 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
113 #define CSISR_RXFF_INT (1 << 18)
114 #define CSISR_EOF_INT (1 << 17)
115 #define CSISR_SOF_INT (1 << 16)
116 #define CSISR_F2_INT (1 << 15)
117 #define CSISR_F1_INT (1 << 14)
118 #define CSISR_COF_INT (1 << 13)
119 #define CSISR_ECC_INT (1 << 1)
120 #define CSISR_DRDY (1 << 0)
121
122 #define CSICR1 0x00
123 #define CSICR2 0x04
124 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
125 #define CSISTATFIFO 0x0c
126 #define CSIRFIFO 0x10
127 #define CSIRXCNT 0x14
128 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
129 #define CSIDMASA_STATFIFO 0x20
130 #define CSIDMATA_STATFIFO 0x24
131 #define CSIDMASA_FB1 0x28
132 #define CSIDMASA_FB2 0x2c
133 #define CSIFBUF_PARA 0x30
134 #define CSIIMAG_PARA 0x34
135
136 /* EMMA PrP */
137 #define PRP_CNTL 0x00
138 #define PRP_INTR_CNTL 0x04
139 #define PRP_INTRSTATUS 0x08
140 #define PRP_SOURCE_Y_PTR 0x0c
141 #define PRP_SOURCE_CB_PTR 0x10
142 #define PRP_SOURCE_CR_PTR 0x14
143 #define PRP_DEST_RGB1_PTR 0x18
144 #define PRP_DEST_RGB2_PTR 0x1c
145 #define PRP_DEST_Y_PTR 0x20
146 #define PRP_DEST_CB_PTR 0x24
147 #define PRP_DEST_CR_PTR 0x28
148 #define PRP_SRC_FRAME_SIZE 0x2c
149 #define PRP_DEST_CH1_LINE_STRIDE 0x30
150 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
151 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
152 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
153 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
154 #define PRP_SRC_LINE_STRIDE 0x44
155 #define PRP_CSC_COEF_012 0x48
156 #define PRP_CSC_COEF_345 0x4c
157 #define PRP_CSC_COEF_678 0x50
158 #define PRP_CH1_RZ_HORI_COEF1 0x54
159 #define PRP_CH1_RZ_HORI_COEF2 0x58
160 #define PRP_CH1_RZ_HORI_VALID 0x5c
161 #define PRP_CH1_RZ_VERT_COEF1 0x60
162 #define PRP_CH1_RZ_VERT_COEF2 0x64
163 #define PRP_CH1_RZ_VERT_VALID 0x68
164 #define PRP_CH2_RZ_HORI_COEF1 0x6c
165 #define PRP_CH2_RZ_HORI_COEF2 0x70
166 #define PRP_CH2_RZ_HORI_VALID 0x74
167 #define PRP_CH2_RZ_VERT_COEF1 0x78
168 #define PRP_CH2_RZ_VERT_COEF2 0x7c
169 #define PRP_CH2_RZ_VERT_VALID 0x80
170
171 #define PRP_CNTL_CH1EN (1 << 0)
172 #define PRP_CNTL_CH2EN (1 << 1)
173 #define PRP_CNTL_CSIEN (1 << 2)
174 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
175 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
176 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
177 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
178 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
179 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
180 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
181 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
182 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
183 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
184 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
185 #define PRP_CNTL_CH1_LEN (1 << 9)
186 #define PRP_CNTL_CH2_LEN (1 << 10)
187 #define PRP_CNTL_SKIP_FRAME (1 << 11)
188 #define PRP_CNTL_SWRST (1 << 12)
189 #define PRP_CNTL_CLKEN (1 << 13)
190 #define PRP_CNTL_WEN (1 << 14)
191 #define PRP_CNTL_CH1BYP (1 << 15)
192 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
193 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
194 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
195 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
196 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
197 #define PRP_CNTL_CH2B1EN (1 << 29)
198 #define PRP_CNTL_CH2B2EN (1 << 30)
199 #define PRP_CNTL_CH2FEN (1 << 31)
200
201 /* IRQ Enable and status register */
202 #define PRP_INTR_RDERR (1 << 0)
203 #define PRP_INTR_CH1WERR (1 << 1)
204 #define PRP_INTR_CH2WERR (1 << 2)
205 #define PRP_INTR_CH1FC (1 << 3)
206 #define PRP_INTR_CH2FC (1 << 5)
207 #define PRP_INTR_LBOVF (1 << 7)
208 #define PRP_INTR_CH2OVF (1 << 8)
209
210 /* Resizing registers */
211 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
212 #define PRP_RZ_VALID_BILINEAR (1 << 31)
213
214 #define MAX_VIDEO_MEM 16
215
216 #define RESIZE_NUM_MIN 1
217 #define RESIZE_NUM_MAX 20
218 #define BC_COEF 3
219 #define SZ_COEF (1 << BC_COEF)
220
221 #define RESIZE_DIR_H 0
222 #define RESIZE_DIR_V 1
223
224 #define RESIZE_ALGO_BILINEAR 0
225 #define RESIZE_ALGO_AVERAGING 1
226
227 struct mx2_prp_cfg {
228 int channel;
229 u32 in_fmt;
230 u32 out_fmt;
231 u32 src_pixel;
232 u32 ch1_pixel;
233 u32 irq_flags;
234 u32 csicr1;
235 };
236
237 /* prp resizing parameters */
238 struct emma_prp_resize {
239 int algo; /* type of algorithm used */
240 int len; /* number of coefficients */
241 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
242 };
243
244 /* prp configuration for a client-host fmt pair */
245 struct mx2_fmt_cfg {
246 enum v4l2_mbus_pixelcode in_fmt;
247 u32 out_fmt;
248 struct mx2_prp_cfg cfg;
249 };
250
251 enum mx2_buffer_state {
252 MX2_STATE_QUEUED,
253 MX2_STATE_ACTIVE,
254 MX2_STATE_DONE,
255 };
256
257 struct mx2_buf_internal {
258 struct list_head queue;
259 int bufnum;
260 bool discard;
261 };
262
263 /* buffer for one video frame */
264 struct mx2_buffer {
265 /* common v4l buffer stuff -- must be first */
266 struct vb2_buffer vb;
267 enum mx2_buffer_state state;
268 struct mx2_buf_internal internal;
269 };
270
271 struct mx2_camera_dev {
272 struct device *dev;
273 struct soc_camera_host soc_host;
274 struct soc_camera_device *icd;
275 struct clk *clk_csi, *clk_emma_ahb, *clk_emma_ipg;
276
277 void __iomem *base_csi, *base_emma;
278
279 struct mx2_camera_platform_data *pdata;
280 unsigned long platform_flags;
281
282 struct list_head capture;
283 struct list_head active_bufs;
284 struct list_head discard;
285
286 spinlock_t lock;
287
288 int dma;
289 struct mx2_buffer *active;
290 struct mx2_buffer *fb1_active;
291 struct mx2_buffer *fb2_active;
292
293 u32 csicr1;
294
295 struct mx2_buf_internal buf_discard[2];
296 void *discard_buffer;
297 dma_addr_t discard_buffer_dma;
298 size_t discard_size;
299 struct mx2_fmt_cfg *emma_prp;
300 struct emma_prp_resize resizing[2];
301 unsigned int s_width, s_height;
302 u32 frame_count;
303 struct vb2_alloc_ctx *alloc_ctx;
304 };
305
306 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
307 {
308 return container_of(int_buf, struct mx2_buffer, internal);
309 }
310
311 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
312 /*
313 * This is a generic configuration which is valid for most
314 * prp input-output format combinations.
315 * We set the incomming and outgoing pixelformat to a
316 * 16 Bit wide format and adjust the bytesperline
317 * accordingly. With this configuration the inputdata
318 * will not be changed by the emma and could be any type
319 * of 16 Bit Pixelformat.
320 */
321 {
322 .in_fmt = 0,
323 .out_fmt = 0,
324 .cfg = {
325 .channel = 1,
326 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
327 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
328 .src_pixel = 0x2ca00565, /* RGB565 */
329 .ch1_pixel = 0x2ca00565, /* RGB565 */
330 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
331 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
332 .csicr1 = 0,
333 }
334 },
335 {
336 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
337 .out_fmt = V4L2_PIX_FMT_YUYV,
338 .cfg = {
339 .channel = 1,
340 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
341 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
342 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
343 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
344 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
345 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
346 .csicr1 = CSICR1_SWAP16_EN,
347 }
348 },
349 {
350 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
351 .out_fmt = V4L2_PIX_FMT_YUYV,
352 .cfg = {
353 .channel = 1,
354 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
355 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
356 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
357 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
358 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
359 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
360 .csicr1 = CSICR1_PACK_DIR,
361 }
362 },
363 {
364 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
365 .out_fmt = V4L2_PIX_FMT_YUV420,
366 .cfg = {
367 .channel = 2,
368 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
369 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
370 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
371 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
372 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
373 PRP_INTR_CH2OVF,
374 .csicr1 = CSICR1_PACK_DIR,
375 }
376 },
377 {
378 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
379 .out_fmt = V4L2_PIX_FMT_YUV420,
380 .cfg = {
381 .channel = 2,
382 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
383 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
384 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
385 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
386 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
387 PRP_INTR_CH2OVF,
388 .csicr1 = CSICR1_SWAP16_EN,
389 }
390 },
391 };
392
393 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
394 enum v4l2_mbus_pixelcode in_fmt,
395 u32 out_fmt)
396 {
397 int i;
398
399 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
400 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
401 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
402 return &mx27_emma_prp_table[i];
403 }
404 /* If no match return the most generic configuration */
405 return &mx27_emma_prp_table[0];
406 };
407
408 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
409 unsigned long phys, int bufnum)
410 {
411 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
412
413 if (prp->cfg.channel == 1) {
414 writel(phys, pcdev->base_emma +
415 PRP_DEST_RGB1_PTR + 4 * bufnum);
416 } else {
417 writel(phys, pcdev->base_emma +
418 PRP_DEST_Y_PTR - 0x14 * bufnum);
419 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
420 u32 imgsize = pcdev->icd->user_height *
421 pcdev->icd->user_width;
422
423 writel(phys + imgsize, pcdev->base_emma +
424 PRP_DEST_CB_PTR - 0x14 * bufnum);
425 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
426 PRP_DEST_CR_PTR - 0x14 * bufnum);
427 }
428 }
429 }
430
431 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
432 {
433 unsigned long flags;
434
435 clk_disable_unprepare(pcdev->clk_csi);
436 writel(0, pcdev->base_csi + CSICR1);
437 if (cpu_is_mx27()) {
438 writel(0, pcdev->base_emma + PRP_CNTL);
439 } else if (cpu_is_mx25()) {
440 spin_lock_irqsave(&pcdev->lock, flags);
441 pcdev->fb1_active = NULL;
442 pcdev->fb2_active = NULL;
443 writel(0, pcdev->base_csi + CSIDMASA_FB1);
444 writel(0, pcdev->base_csi + CSIDMASA_FB2);
445 spin_unlock_irqrestore(&pcdev->lock, flags);
446 }
447 }
448
449 /*
450 * The following two functions absolutely depend on the fact, that
451 * there can be only one camera on mx2 camera sensor interface
452 */
453 static int mx2_camera_add_device(struct soc_camera_device *icd)
454 {
455 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
456 struct mx2_camera_dev *pcdev = ici->priv;
457 int ret;
458 u32 csicr1;
459
460 if (pcdev->icd)
461 return -EBUSY;
462
463 ret = clk_prepare_enable(pcdev->clk_csi);
464 if (ret < 0)
465 return ret;
466
467 csicr1 = CSICR1_MCLKEN;
468
469 if (cpu_is_mx27())
470 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
471 CSICR1_RXFF_LEVEL(0);
472
473 pcdev->csicr1 = csicr1;
474 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
475
476 pcdev->icd = icd;
477 pcdev->frame_count = 0;
478
479 dev_info(icd->parent, "Camera driver attached to camera %d\n",
480 icd->devnum);
481
482 return 0;
483 }
484
485 static void mx2_camera_remove_device(struct soc_camera_device *icd)
486 {
487 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
488 struct mx2_camera_dev *pcdev = ici->priv;
489
490 BUG_ON(icd != pcdev->icd);
491
492 dev_info(icd->parent, "Camera driver detached from camera %d\n",
493 icd->devnum);
494
495 mx2_camera_deactivate(pcdev);
496
497 pcdev->icd = NULL;
498 }
499
500 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
501 int state)
502 {
503 struct vb2_buffer *vb;
504 struct mx2_buffer *buf;
505 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
506 &pcdev->fb2_active;
507 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
508 unsigned long flags;
509
510 spin_lock_irqsave(&pcdev->lock, flags);
511
512 if (*fb_active == NULL)
513 goto out;
514
515 vb = &(*fb_active)->vb;
516 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
517 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
518
519 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
520 vb->v4l2_buf.sequence++;
521 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
522
523 if (list_empty(&pcdev->capture)) {
524 buf = NULL;
525 writel(0, pcdev->base_csi + fb_reg);
526 } else {
527 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
528 internal.queue);
529 vb = &buf->vb;
530 list_del(&buf->internal.queue);
531 buf->state = MX2_STATE_ACTIVE;
532 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
533 pcdev->base_csi + fb_reg);
534 }
535
536 *fb_active = buf;
537
538 out:
539 spin_unlock_irqrestore(&pcdev->lock, flags);
540 }
541
542 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
543 {
544 struct mx2_camera_dev *pcdev = data;
545 u32 status = readl(pcdev->base_csi + CSISR);
546
547 if (status & CSISR_DMA_TSF_FB1_INT)
548 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
549 else if (status & CSISR_DMA_TSF_FB2_INT)
550 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
551
552 /* FIXME: handle CSISR_RFF_OR_INT */
553
554 writel(status, pcdev->base_csi + CSISR);
555
556 return IRQ_HANDLED;
557 }
558
559 /*
560 * Videobuf operations
561 */
562 static int mx2_videobuf_setup(struct vb2_queue *vq,
563 const struct v4l2_format *fmt,
564 unsigned int *count, unsigned int *num_planes,
565 unsigned int sizes[], void *alloc_ctxs[])
566 {
567 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
568 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
569 struct mx2_camera_dev *pcdev = ici->priv;
570
571 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
572
573 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
574 if (fmt != NULL)
575 return -ENOTTY;
576
577 alloc_ctxs[0] = pcdev->alloc_ctx;
578
579 sizes[0] = icd->sizeimage;
580
581 if (0 == *count)
582 *count = 32;
583 if (!*num_planes &&
584 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
585 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
586
587 *num_planes = 1;
588
589 return 0;
590 }
591
592 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
593 {
594 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
595 int ret = 0;
596
597 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
598 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
599
600 #ifdef DEBUG
601 /*
602 * This can be useful if you want to see if we actually fill
603 * the buffer with something
604 */
605 memset((void *)vb2_plane_vaddr(vb, 0),
606 0xaa, vb2_get_plane_payload(vb, 0));
607 #endif
608
609 vb2_set_plane_payload(vb, 0, icd->sizeimage);
610 if (vb2_plane_vaddr(vb, 0) &&
611 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
612 ret = -EINVAL;
613 goto out;
614 }
615
616 return 0;
617
618 out:
619 return ret;
620 }
621
622 static void mx2_videobuf_queue(struct vb2_buffer *vb)
623 {
624 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
625 struct soc_camera_host *ici =
626 to_soc_camera_host(icd->parent);
627 struct mx2_camera_dev *pcdev = ici->priv;
628 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
629 unsigned long flags;
630
631 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
632 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
633
634 spin_lock_irqsave(&pcdev->lock, flags);
635
636 buf->state = MX2_STATE_QUEUED;
637 list_add_tail(&buf->internal.queue, &pcdev->capture);
638
639 if (cpu_is_mx25()) {
640 u32 csicr3, dma_inten = 0;
641
642 if (pcdev->fb1_active == NULL) {
643 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
644 pcdev->base_csi + CSIDMASA_FB1);
645 pcdev->fb1_active = buf;
646 dma_inten = CSICR1_FB1_DMA_INTEN;
647 } else if (pcdev->fb2_active == NULL) {
648 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
649 pcdev->base_csi + CSIDMASA_FB2);
650 pcdev->fb2_active = buf;
651 dma_inten = CSICR1_FB2_DMA_INTEN;
652 }
653
654 if (dma_inten) {
655 list_del(&buf->internal.queue);
656 buf->state = MX2_STATE_ACTIVE;
657
658 csicr3 = readl(pcdev->base_csi + CSICR3);
659
660 /* Reflash DMA */
661 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
662 pcdev->base_csi + CSICR3);
663
664 /* clear & enable interrupts */
665 writel(dma_inten, pcdev->base_csi + CSISR);
666 pcdev->csicr1 |= dma_inten;
667 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
668
669 /* enable DMA */
670 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
671 writel(csicr3, pcdev->base_csi + CSICR3);
672 }
673 }
674
675 spin_unlock_irqrestore(&pcdev->lock, flags);
676 }
677
678 static void mx2_videobuf_release(struct vb2_buffer *vb)
679 {
680 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
681 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
682 struct mx2_camera_dev *pcdev = ici->priv;
683 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
684 unsigned long flags;
685
686 #ifdef DEBUG
687 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
688 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
689
690 switch (buf->state) {
691 case MX2_STATE_ACTIVE:
692 dev_info(icd->parent, "%s (active)\n", __func__);
693 break;
694 case MX2_STATE_QUEUED:
695 dev_info(icd->parent, "%s (queued)\n", __func__);
696 break;
697 default:
698 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
699 buf->state);
700 break;
701 }
702 #endif
703
704 /*
705 * Terminate only queued but inactive buffers. Active buffers are
706 * released when they become inactive after videobuf_waiton().
707 *
708 * FIXME: implement forced termination of active buffers for mx27 and
709 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
710 * state. This requires a specific handling for each of the these DMA
711 * types.
712 */
713
714 spin_lock_irqsave(&pcdev->lock, flags);
715 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
716 if (pcdev->fb1_active == buf) {
717 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
718 writel(0, pcdev->base_csi + CSIDMASA_FB1);
719 pcdev->fb1_active = NULL;
720 } else if (pcdev->fb2_active == buf) {
721 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
722 writel(0, pcdev->base_csi + CSIDMASA_FB2);
723 pcdev->fb2_active = NULL;
724 }
725 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
726 }
727 spin_unlock_irqrestore(&pcdev->lock, flags);
728 }
729
730 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
731 int bytesperline)
732 {
733 struct soc_camera_host *ici =
734 to_soc_camera_host(icd->parent);
735 struct mx2_camera_dev *pcdev = ici->priv;
736 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
737
738 writel((pcdev->s_width << 16) | pcdev->s_height,
739 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
740 writel(prp->cfg.src_pixel,
741 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
742 if (prp->cfg.channel == 1) {
743 writel((icd->user_width << 16) | icd->user_height,
744 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
745 writel(bytesperline,
746 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
747 writel(prp->cfg.ch1_pixel,
748 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
749 } else { /* channel 2 */
750 writel((icd->user_width << 16) | icd->user_height,
751 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
752 }
753
754 /* Enable interrupts */
755 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
756 }
757
758 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
759 {
760 int dir;
761
762 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
763 unsigned char *s = pcdev->resizing[dir].s;
764 int len = pcdev->resizing[dir].len;
765 unsigned int coeff[2] = {0, 0};
766 unsigned int valid = 0;
767 int i;
768
769 if (len == 0)
770 continue;
771
772 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
773 int j;
774
775 j = i > 9 ? 1 : 0;
776 coeff[j] = (coeff[j] << BC_COEF) |
777 (s[i] & (SZ_COEF - 1));
778
779 if (i == 5 || i == 15)
780 coeff[j] <<= 1;
781
782 valid = (valid << 1) | (s[i] >> BC_COEF);
783 }
784
785 valid |= PRP_RZ_VALID_TBL_LEN(len);
786
787 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
788 valid |= PRP_RZ_VALID_BILINEAR;
789
790 if (pcdev->emma_prp->cfg.channel == 1) {
791 if (dir == RESIZE_DIR_H) {
792 writel(coeff[0], pcdev->base_emma +
793 PRP_CH1_RZ_HORI_COEF1);
794 writel(coeff[1], pcdev->base_emma +
795 PRP_CH1_RZ_HORI_COEF2);
796 writel(valid, pcdev->base_emma +
797 PRP_CH1_RZ_HORI_VALID);
798 } else {
799 writel(coeff[0], pcdev->base_emma +
800 PRP_CH1_RZ_VERT_COEF1);
801 writel(coeff[1], pcdev->base_emma +
802 PRP_CH1_RZ_VERT_COEF2);
803 writel(valid, pcdev->base_emma +
804 PRP_CH1_RZ_VERT_VALID);
805 }
806 } else {
807 if (dir == RESIZE_DIR_H) {
808 writel(coeff[0], pcdev->base_emma +
809 PRP_CH2_RZ_HORI_COEF1);
810 writel(coeff[1], pcdev->base_emma +
811 PRP_CH2_RZ_HORI_COEF2);
812 writel(valid, pcdev->base_emma +
813 PRP_CH2_RZ_HORI_VALID);
814 } else {
815 writel(coeff[0], pcdev->base_emma +
816 PRP_CH2_RZ_VERT_COEF1);
817 writel(coeff[1], pcdev->base_emma +
818 PRP_CH2_RZ_VERT_COEF2);
819 writel(valid, pcdev->base_emma +
820 PRP_CH2_RZ_VERT_VALID);
821 }
822 }
823 }
824 }
825
826 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
827 {
828 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
829 struct soc_camera_host *ici =
830 to_soc_camera_host(icd->parent);
831 struct mx2_camera_dev *pcdev = ici->priv;
832 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
833 struct vb2_buffer *vb;
834 struct mx2_buffer *buf;
835 unsigned long phys;
836 int bytesperline;
837
838 if (cpu_is_mx27()) {
839 unsigned long flags;
840 if (count < 2)
841 return -EINVAL;
842
843 spin_lock_irqsave(&pcdev->lock, flags);
844
845 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
846 internal.queue);
847 buf->internal.bufnum = 0;
848 vb = &buf->vb;
849 buf->state = MX2_STATE_ACTIVE;
850
851 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
852 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
853 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
854
855 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
856 internal.queue);
857 buf->internal.bufnum = 1;
858 vb = &buf->vb;
859 buf->state = MX2_STATE_ACTIVE;
860
861 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
862 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
863 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
864
865 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
866 icd->current_fmt->host_fmt);
867 if (bytesperline < 0) {
868 spin_unlock_irqrestore(&pcdev->lock, flags);
869 return bytesperline;
870 }
871
872 /*
873 * I didn't manage to properly enable/disable the prp
874 * on a per frame basis during running transfers,
875 * thus we allocate a buffer here and use it to
876 * discard frames when no buffer is available.
877 * Feel free to work on this ;)
878 */
879 pcdev->discard_size = icd->user_height * bytesperline;
880 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
881 pcdev->discard_size, &pcdev->discard_buffer_dma,
882 GFP_ATOMIC);
883 if (!pcdev->discard_buffer) {
884 spin_unlock_irqrestore(&pcdev->lock, flags);
885 return -ENOMEM;
886 }
887
888 pcdev->buf_discard[0].discard = true;
889 list_add_tail(&pcdev->buf_discard[0].queue,
890 &pcdev->discard);
891
892 pcdev->buf_discard[1].discard = true;
893 list_add_tail(&pcdev->buf_discard[1].queue,
894 &pcdev->discard);
895
896 mx2_prp_resize_commit(pcdev);
897
898 mx27_camera_emma_buf_init(icd, bytesperline);
899
900 if (prp->cfg.channel == 1) {
901 writel(PRP_CNTL_CH1EN |
902 PRP_CNTL_CSIEN |
903 prp->cfg.in_fmt |
904 prp->cfg.out_fmt |
905 PRP_CNTL_CH1_LEN |
906 PRP_CNTL_CH1BYP |
907 PRP_CNTL_CH1_TSKIP(0) |
908 PRP_CNTL_IN_TSKIP(0),
909 pcdev->base_emma + PRP_CNTL);
910 } else {
911 writel(PRP_CNTL_CH2EN |
912 PRP_CNTL_CSIEN |
913 prp->cfg.in_fmt |
914 prp->cfg.out_fmt |
915 PRP_CNTL_CH2_LEN |
916 PRP_CNTL_CH2_TSKIP(0) |
917 PRP_CNTL_IN_TSKIP(0),
918 pcdev->base_emma + PRP_CNTL);
919 }
920 spin_unlock_irqrestore(&pcdev->lock, flags);
921 }
922
923 return 0;
924 }
925
926 static int mx2_stop_streaming(struct vb2_queue *q)
927 {
928 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
929 struct soc_camera_host *ici =
930 to_soc_camera_host(icd->parent);
931 struct mx2_camera_dev *pcdev = ici->priv;
932 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
933 unsigned long flags;
934 void *b;
935 u32 cntl;
936
937 if (cpu_is_mx27()) {
938 spin_lock_irqsave(&pcdev->lock, flags);
939
940 cntl = readl(pcdev->base_emma + PRP_CNTL);
941 if (prp->cfg.channel == 1) {
942 writel(cntl & ~PRP_CNTL_CH1EN,
943 pcdev->base_emma + PRP_CNTL);
944 } else {
945 writel(cntl & ~PRP_CNTL_CH2EN,
946 pcdev->base_emma + PRP_CNTL);
947 }
948 INIT_LIST_HEAD(&pcdev->capture);
949 INIT_LIST_HEAD(&pcdev->active_bufs);
950 INIT_LIST_HEAD(&pcdev->discard);
951
952 b = pcdev->discard_buffer;
953 pcdev->discard_buffer = NULL;
954
955 spin_unlock_irqrestore(&pcdev->lock, flags);
956
957 dma_free_coherent(ici->v4l2_dev.dev,
958 pcdev->discard_size, b, pcdev->discard_buffer_dma);
959 }
960
961 return 0;
962 }
963
964 static struct vb2_ops mx2_videobuf_ops = {
965 .queue_setup = mx2_videobuf_setup,
966 .buf_prepare = mx2_videobuf_prepare,
967 .buf_queue = mx2_videobuf_queue,
968 .buf_cleanup = mx2_videobuf_release,
969 .start_streaming = mx2_start_streaming,
970 .stop_streaming = mx2_stop_streaming,
971 };
972
973 static int mx2_camera_init_videobuf(struct vb2_queue *q,
974 struct soc_camera_device *icd)
975 {
976 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
977 q->io_modes = VB2_MMAP | VB2_USERPTR;
978 q->drv_priv = icd;
979 q->ops = &mx2_videobuf_ops;
980 q->mem_ops = &vb2_dma_contig_memops;
981 q->buf_struct_size = sizeof(struct mx2_buffer);
982
983 return vb2_queue_init(q);
984 }
985
986 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
987 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
988 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
989 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
990 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
991 V4L2_MBUS_PCLK_SAMPLE_RISING | \
992 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
993 V4L2_MBUS_DATA_ACTIVE_HIGH | \
994 V4L2_MBUS_DATA_ACTIVE_LOW)
995
996 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
997 {
998 u32 cntl;
999 int count = 0;
1000
1001 cntl = readl(pcdev->base_emma + PRP_CNTL);
1002 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
1003 while (count++ < 100) {
1004 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
1005 return 0;
1006 barrier();
1007 udelay(1);
1008 }
1009
1010 return -ETIMEDOUT;
1011 }
1012
1013 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
1014 {
1015 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1016 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1017 struct mx2_camera_dev *pcdev = ici->priv;
1018 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1019 unsigned long common_flags;
1020 int ret;
1021 int bytesperline;
1022 u32 csicr1 = pcdev->csicr1;
1023
1024 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1025 if (!ret) {
1026 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
1027 if (!common_flags) {
1028 dev_warn(icd->parent,
1029 "Flags incompatible: camera 0x%x, host 0x%x\n",
1030 cfg.flags, MX2_BUS_FLAGS);
1031 return -EINVAL;
1032 }
1033 } else if (ret != -ENOIOCTLCMD) {
1034 return ret;
1035 } else {
1036 common_flags = MX2_BUS_FLAGS;
1037 }
1038
1039 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1040 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1041 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
1042 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1043 else
1044 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1045 }
1046
1047 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1048 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1049 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
1050 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1051 else
1052 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1053 }
1054
1055 cfg.flags = common_flags;
1056 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1057 if (ret < 0 && ret != -ENOIOCTLCMD) {
1058 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1059 common_flags, ret);
1060 return ret;
1061 }
1062
1063 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
1064
1065 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1066 csicr1 |= CSICR1_REDGE;
1067 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1068 csicr1 |= CSICR1_SOF_POL;
1069 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1070 csicr1 |= CSICR1_HSYNC_POL;
1071 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
1072 csicr1 |= CSICR1_EXT_VSYNC;
1073 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
1074 csicr1 |= CSICR1_CCIR_EN;
1075 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
1076 csicr1 |= CSICR1_CCIR_MODE;
1077 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
1078 csicr1 |= CSICR1_GCLK_MODE;
1079 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
1080 csicr1 |= CSICR1_INV_DATA;
1081
1082 pcdev->csicr1 = csicr1;
1083
1084 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
1085 icd->current_fmt->host_fmt);
1086 if (bytesperline < 0)
1087 return bytesperline;
1088
1089 if (cpu_is_mx27()) {
1090 ret = mx27_camera_emma_prp_reset(pcdev);
1091 if (ret)
1092 return ret;
1093 } else if (cpu_is_mx25()) {
1094 writel((bytesperline * icd->user_height) >> 2,
1095 pcdev->base_csi + CSIRXCNT);
1096 writel((bytesperline << 16) | icd->user_height,
1097 pcdev->base_csi + CSIIMAG_PARA);
1098 }
1099
1100 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
1101
1102 return 0;
1103 }
1104
1105 static int mx2_camera_set_crop(struct soc_camera_device *icd,
1106 const struct v4l2_crop *a)
1107 {
1108 struct v4l2_crop a_writable = *a;
1109 struct v4l2_rect *rect = &a_writable.c;
1110 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1111 struct v4l2_mbus_framefmt mf;
1112 int ret;
1113
1114 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
1115 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
1116
1117 ret = v4l2_subdev_call(sd, video, s_crop, a);
1118 if (ret < 0)
1119 return ret;
1120
1121 /* The capture device might have changed its output */
1122 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1123 if (ret < 0)
1124 return ret;
1125
1126 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
1127 mf.width, mf.height);
1128
1129 icd->user_width = mf.width;
1130 icd->user_height = mf.height;
1131
1132 return ret;
1133 }
1134
1135 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1136 unsigned int idx,
1137 struct soc_camera_format_xlate *xlate)
1138 {
1139 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1140 const struct soc_mbus_pixelfmt *fmt;
1141 struct device *dev = icd->parent;
1142 enum v4l2_mbus_pixelcode code;
1143 int ret, formats = 0;
1144
1145 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1146 if (ret < 0)
1147 /* no more formats */
1148 return 0;
1149
1150 fmt = soc_mbus_get_fmtdesc(code);
1151 if (!fmt) {
1152 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1153 return 0;
1154 }
1155
1156 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1157 code == V4L2_MBUS_FMT_UYVY8_2X8) {
1158 formats++;
1159 if (xlate) {
1160 /*
1161 * CH2 can output YUV420 which is a standard format in
1162 * soc_mediabus.c
1163 */
1164 xlate->host_fmt =
1165 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1166 xlate->code = code;
1167 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1168 xlate->host_fmt->name, code);
1169 xlate++;
1170 }
1171 }
1172
1173 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
1174 formats++;
1175 if (xlate) {
1176 xlate->host_fmt =
1177 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
1178 xlate->code = code;
1179 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1180 xlate->host_fmt->name, code);
1181 xlate++;
1182 }
1183 }
1184
1185 /* Generic pass-trough */
1186 formats++;
1187 if (xlate) {
1188 xlate->host_fmt = fmt;
1189 xlate->code = code;
1190 xlate++;
1191 }
1192 return formats;
1193 }
1194
1195 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1196 struct v4l2_mbus_framefmt *mf_in,
1197 struct v4l2_pix_format *pix_out, bool apply)
1198 {
1199 int num, den;
1200 unsigned long m;
1201 int i, dir;
1202
1203 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1204 struct emma_prp_resize tmprsz;
1205 unsigned char *s = tmprsz.s;
1206 int len = 0;
1207 int in, out;
1208
1209 if (dir == RESIZE_DIR_H) {
1210 in = mf_in->width;
1211 out = pix_out->width;
1212 } else {
1213 in = mf_in->height;
1214 out = pix_out->height;
1215 }
1216
1217 if (in < out)
1218 return -EINVAL;
1219 else if (in == out)
1220 continue;
1221
1222 /* Calculate ratio */
1223 m = gcd(in, out);
1224 num = in / m;
1225 den = out / m;
1226 if (num > RESIZE_NUM_MAX)
1227 return -EINVAL;
1228
1229 if ((num >= 2 * den) && (den == 1) &&
1230 (num < 9) && (!(num & 0x01))) {
1231 int sum = 0;
1232 int j;
1233
1234 /* Average scaling for >= 2:1 ratios */
1235 /* Support can be added for num >=9 and odd values */
1236
1237 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1238 len = num;
1239
1240 for (i = 0; i < (len / 2); i++)
1241 s[i] = 8;
1242
1243 do {
1244 for (i = 0; i < (len / 2); i++) {
1245 s[i] = s[i] >> 1;
1246 sum = 0;
1247 for (j = 0; j < (len / 2); j++)
1248 sum += s[j];
1249 if (sum == 4)
1250 break;
1251 }
1252 } while (sum != 4);
1253
1254 for (i = (len / 2); i < len; i++)
1255 s[i] = s[len - i - 1];
1256
1257 s[len - 1] |= SZ_COEF;
1258 } else {
1259 /* bilinear scaling for < 2:1 ratios */
1260 int v; /* overflow counter */
1261 int coeff, nxt; /* table output */
1262 int in_pos_inc = 2 * den;
1263 int out_pos = num;
1264 int out_pos_inc = 2 * num;
1265 int init_carry = num - den;
1266 int carry = init_carry;
1267
1268 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1269 v = den + in_pos_inc;
1270 do {
1271 coeff = v - out_pos;
1272 out_pos += out_pos_inc;
1273 carry += out_pos_inc;
1274 for (nxt = 0; v < out_pos; nxt++) {
1275 v += in_pos_inc;
1276 carry -= in_pos_inc;
1277 }
1278
1279 if (len > RESIZE_NUM_MAX)
1280 return -EINVAL;
1281
1282 coeff = ((coeff << BC_COEF) +
1283 (in_pos_inc >> 1)) / in_pos_inc;
1284
1285 if (coeff >= (SZ_COEF - 1))
1286 coeff--;
1287
1288 coeff |= SZ_COEF;
1289 s[len] = (unsigned char)coeff;
1290 len++;
1291
1292 for (i = 1; i < nxt; i++) {
1293 if (len >= RESIZE_NUM_MAX)
1294 return -EINVAL;
1295 s[len] = 0;
1296 len++;
1297 }
1298 } while (carry != init_carry);
1299 }
1300 tmprsz.len = len;
1301 if (dir == RESIZE_DIR_H)
1302 mf_in->width = pix_out->width;
1303 else
1304 mf_in->height = pix_out->height;
1305
1306 if (apply)
1307 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1308 }
1309 return 0;
1310 }
1311
1312 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1313 struct v4l2_format *f)
1314 {
1315 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1316 struct mx2_camera_dev *pcdev = ici->priv;
1317 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1318 const struct soc_camera_format_xlate *xlate;
1319 struct v4l2_pix_format *pix = &f->fmt.pix;
1320 struct v4l2_mbus_framefmt mf;
1321 int ret;
1322
1323 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1324 __func__, pix->width, pix->height);
1325
1326 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1327 if (!xlate) {
1328 dev_warn(icd->parent, "Format %x not found\n",
1329 pix->pixelformat);
1330 return -EINVAL;
1331 }
1332
1333 mf.width = pix->width;
1334 mf.height = pix->height;
1335 mf.field = pix->field;
1336 mf.colorspace = pix->colorspace;
1337 mf.code = xlate->code;
1338
1339 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1340 if (ret < 0 && ret != -ENOIOCTLCMD)
1341 return ret;
1342
1343 /* Store width and height returned by the sensor for resizing */
1344 pcdev->s_width = mf.width;
1345 pcdev->s_height = mf.height;
1346 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1347 __func__, pcdev->s_width, pcdev->s_height);
1348
1349 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1350 xlate->host_fmt->fourcc);
1351
1352 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1353 if ((mf.width != pix->width || mf.height != pix->height) &&
1354 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1355 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1356 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1357 }
1358
1359 if (mf.code != xlate->code)
1360 return -EINVAL;
1361
1362 pix->width = mf.width;
1363 pix->height = mf.height;
1364 pix->field = mf.field;
1365 pix->colorspace = mf.colorspace;
1366 icd->current_fmt = xlate;
1367
1368 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1369 __func__, pix->width, pix->height);
1370
1371 return 0;
1372 }
1373
1374 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1375 struct v4l2_format *f)
1376 {
1377 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1378 const struct soc_camera_format_xlate *xlate;
1379 struct v4l2_pix_format *pix = &f->fmt.pix;
1380 struct v4l2_mbus_framefmt mf;
1381 __u32 pixfmt = pix->pixelformat;
1382 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1383 struct mx2_camera_dev *pcdev = ici->priv;
1384 struct mx2_fmt_cfg *emma_prp;
1385 unsigned int width_limit;
1386 int ret;
1387
1388 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1389 __func__, pix->width, pix->height);
1390
1391 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1392 if (pixfmt && !xlate) {
1393 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1394 return -EINVAL;
1395 }
1396
1397 /* limit to MX25 hardware capabilities */
1398 if (cpu_is_mx25()) {
1399 if (xlate->host_fmt->bits_per_sample <= 8)
1400 width_limit = 0xffff * 4;
1401 else
1402 width_limit = 0xffff * 2;
1403 /* CSIIMAG_PARA limit */
1404 if (pix->width > width_limit)
1405 pix->width = width_limit;
1406 if (pix->height > 0xffff)
1407 pix->height = 0xffff;
1408
1409 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1410 xlate->host_fmt);
1411 if (pix->bytesperline < 0)
1412 return pix->bytesperline;
1413 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1414 pix->bytesperline, pix->height);
1415 /* Check against the CSIRXCNT limit */
1416 if (pix->sizeimage > 4 * 0x3ffff) {
1417 /* Adjust geometry, preserve aspect ratio */
1418 unsigned int new_height = int_sqrt(div_u64(0x3ffffULL *
1419 4 * pix->height, pix->bytesperline));
1420 pix->width = new_height * pix->width / pix->height;
1421 pix->height = new_height;
1422 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1423 xlate->host_fmt);
1424 BUG_ON(pix->bytesperline < 0);
1425 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1426 pix->bytesperline, pix->height);
1427 }
1428 } else {
1429 /*
1430 * Width must be a multiple of 8 as requested by the CSI.
1431 * (Table 39-2 in the i.MX27 Reference Manual).
1432 */
1433 pix->width &= ~0x7;
1434 }
1435
1436 /* limit to sensor capabilities */
1437 mf.width = pix->width;
1438 mf.height = pix->height;
1439 mf.field = pix->field;
1440 mf.colorspace = pix->colorspace;
1441 mf.code = xlate->code;
1442
1443 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1444 if (ret < 0)
1445 return ret;
1446
1447 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1448 __func__, pcdev->s_width, pcdev->s_height);
1449
1450 /* If the sensor does not support image size try PrP resizing */
1451 emma_prp = mx27_emma_prp_get_format(xlate->code,
1452 xlate->host_fmt->fourcc);
1453
1454 if ((mf.width != pix->width || mf.height != pix->height) &&
1455 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1456 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1457 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1458 }
1459
1460 if (mf.field == V4L2_FIELD_ANY)
1461 mf.field = V4L2_FIELD_NONE;
1462 /*
1463 * Driver supports interlaced images provided they have
1464 * both fields so that they can be processed as if they
1465 * were progressive.
1466 */
1467 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1468 dev_err(icd->parent, "Field type %d unsupported.\n",
1469 mf.field);
1470 return -EINVAL;
1471 }
1472
1473 pix->width = mf.width;
1474 pix->height = mf.height;
1475 pix->field = mf.field;
1476 pix->colorspace = mf.colorspace;
1477
1478 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1479 __func__, pix->width, pix->height);
1480
1481 return 0;
1482 }
1483
1484 static int mx2_camera_querycap(struct soc_camera_host *ici,
1485 struct v4l2_capability *cap)
1486 {
1487 /* cap->name is set by the friendly caller:-> */
1488 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1489 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1490
1491 return 0;
1492 }
1493
1494 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1495 {
1496 struct soc_camera_device *icd = file->private_data;
1497
1498 return vb2_poll(&icd->vb2_vidq, file, pt);
1499 }
1500
1501 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1502 .owner = THIS_MODULE,
1503 .add = mx2_camera_add_device,
1504 .remove = mx2_camera_remove_device,
1505 .set_fmt = mx2_camera_set_fmt,
1506 .set_crop = mx2_camera_set_crop,
1507 .get_formats = mx2_camera_get_formats,
1508 .try_fmt = mx2_camera_try_fmt,
1509 .init_videobuf2 = mx2_camera_init_videobuf,
1510 .poll = mx2_camera_poll,
1511 .querycap = mx2_camera_querycap,
1512 .set_bus_param = mx2_camera_set_bus_param,
1513 };
1514
1515 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1516 int bufnum, bool err)
1517 {
1518 #ifdef DEBUG
1519 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1520 #endif
1521 struct mx2_buf_internal *ibuf;
1522 struct mx2_buffer *buf;
1523 struct vb2_buffer *vb;
1524 unsigned long phys;
1525
1526 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1527 queue);
1528
1529 BUG_ON(ibuf->bufnum != bufnum);
1530
1531 if (ibuf->discard) {
1532 /*
1533 * Discard buffer must not be returned to user space.
1534 * Just return it to the discard queue.
1535 */
1536 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1537 } else {
1538 buf = mx2_ibuf_to_buf(ibuf);
1539
1540 vb = &buf->vb;
1541 #ifdef DEBUG
1542 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1543 if (prp->cfg.channel == 1) {
1544 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1545 4 * bufnum) != phys) {
1546 dev_err(pcdev->dev, "%lx != %x\n", phys,
1547 readl(pcdev->base_emma +
1548 PRP_DEST_RGB1_PTR + 4 * bufnum));
1549 }
1550 } else {
1551 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1552 0x14 * bufnum) != phys) {
1553 dev_err(pcdev->dev, "%lx != %x\n", phys,
1554 readl(pcdev->base_emma +
1555 PRP_DEST_Y_PTR - 0x14 * bufnum));
1556 }
1557 }
1558 #endif
1559 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1560 vb2_plane_vaddr(vb, 0),
1561 vb2_get_plane_payload(vb, 0));
1562
1563 list_del_init(&buf->internal.queue);
1564 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
1565 vb->v4l2_buf.sequence = pcdev->frame_count;
1566 if (err)
1567 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1568 else
1569 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1570 }
1571
1572 pcdev->frame_count++;
1573
1574 if (list_empty(&pcdev->capture)) {
1575 if (list_empty(&pcdev->discard)) {
1576 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1577 __func__);
1578 return;
1579 }
1580
1581 ibuf = list_first_entry(&pcdev->discard,
1582 struct mx2_buf_internal, queue);
1583 ibuf->bufnum = bufnum;
1584
1585 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1586 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1587 return;
1588 }
1589
1590 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1591 internal.queue);
1592
1593 buf->internal.bufnum = bufnum;
1594
1595 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1596
1597 vb = &buf->vb;
1598 buf->state = MX2_STATE_ACTIVE;
1599
1600 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1601 mx27_update_emma_buf(pcdev, phys, bufnum);
1602 }
1603
1604 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1605 {
1606 struct mx2_camera_dev *pcdev = data;
1607 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1608 struct mx2_buf_internal *ibuf;
1609
1610 spin_lock(&pcdev->lock);
1611
1612 if (list_empty(&pcdev->active_bufs)) {
1613 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1614 __func__);
1615
1616 if (!status) {
1617 spin_unlock(&pcdev->lock);
1618 return IRQ_NONE;
1619 }
1620 }
1621
1622 if (status & (1 << 7)) { /* overflow */
1623 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1624 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1625 pcdev->base_emma + PRP_CNTL);
1626 writel(cntl, pcdev->base_emma + PRP_CNTL);
1627
1628 ibuf = list_first_entry(&pcdev->active_bufs,
1629 struct mx2_buf_internal, queue);
1630 mx27_camera_frame_done_emma(pcdev,
1631 ibuf->bufnum, true);
1632
1633 status &= ~(1 << 7);
1634 } else if (((status & (3 << 5)) == (3 << 5)) ||
1635 ((status & (3 << 3)) == (3 << 3))) {
1636 /*
1637 * Both buffers have triggered, process the one we're expecting
1638 * to first
1639 */
1640 ibuf = list_first_entry(&pcdev->active_bufs,
1641 struct mx2_buf_internal, queue);
1642 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1643 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1644 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1645 mx27_camera_frame_done_emma(pcdev, 0, false);
1646 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1647 mx27_camera_frame_done_emma(pcdev, 1, false);
1648 }
1649
1650 spin_unlock(&pcdev->lock);
1651 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1652
1653 return IRQ_HANDLED;
1654 }
1655
1656 static int __devinit mx27_camera_emma_init(struct platform_device *pdev)
1657 {
1658 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1659 struct resource *res_emma;
1660 int irq_emma;
1661 int err = 0;
1662
1663 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1664 irq_emma = platform_get_irq(pdev, 1);
1665 if (!res_emma || !irq_emma) {
1666 dev_err(pcdev->dev, "no EMMA resources\n");
1667 err = -ENODEV;
1668 goto out;
1669 }
1670
1671 pcdev->base_emma = devm_request_and_ioremap(pcdev->dev, res_emma);
1672 if (!pcdev->base_emma) {
1673 err = -EADDRNOTAVAIL;
1674 goto out;
1675 }
1676
1677 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1678 MX2_CAM_DRV_NAME, pcdev);
1679 if (err) {
1680 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1681 goto out;
1682 }
1683
1684 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1685 if (IS_ERR(pcdev->clk_emma_ipg)) {
1686 err = PTR_ERR(pcdev->clk_emma_ipg);
1687 goto out;
1688 }
1689
1690 clk_prepare_enable(pcdev->clk_emma_ipg);
1691
1692 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1693 if (IS_ERR(pcdev->clk_emma_ahb)) {
1694 err = PTR_ERR(pcdev->clk_emma_ahb);
1695 goto exit_clk_emma_ipg;
1696 }
1697
1698 clk_prepare_enable(pcdev->clk_emma_ahb);
1699
1700 err = mx27_camera_emma_prp_reset(pcdev);
1701 if (err)
1702 goto exit_clk_emma_ahb;
1703
1704 return err;
1705
1706 exit_clk_emma_ahb:
1707 clk_disable_unprepare(pcdev->clk_emma_ahb);
1708 exit_clk_emma_ipg:
1709 clk_disable_unprepare(pcdev->clk_emma_ipg);
1710 out:
1711 return err;
1712 }
1713
1714 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1715 {
1716 struct mx2_camera_dev *pcdev;
1717 struct resource *res_csi;
1718 int irq_csi;
1719 int err = 0;
1720
1721 dev_dbg(&pdev->dev, "initialising\n");
1722
1723 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1724 irq_csi = platform_get_irq(pdev, 0);
1725 if (res_csi == NULL || irq_csi < 0) {
1726 dev_err(&pdev->dev, "Missing platform resources data\n");
1727 err = -ENODEV;
1728 goto exit;
1729 }
1730
1731 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1732 if (!pcdev) {
1733 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1734 err = -ENOMEM;
1735 goto exit;
1736 }
1737
1738 pcdev->clk_csi = devm_clk_get(&pdev->dev, "ahb");
1739 if (IS_ERR(pcdev->clk_csi)) {
1740 dev_err(&pdev->dev, "Could not get csi clock\n");
1741 err = PTR_ERR(pcdev->clk_csi);
1742 goto exit;
1743 }
1744
1745 pcdev->pdata = pdev->dev.platform_data;
1746 if (pcdev->pdata) {
1747 long rate;
1748
1749 pcdev->platform_flags = pcdev->pdata->flags;
1750
1751 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1752 if (rate <= 0) {
1753 err = -ENODEV;
1754 goto exit;
1755 }
1756 err = clk_set_rate(pcdev->clk_csi, rate);
1757 if (err < 0)
1758 goto exit;
1759 }
1760
1761 INIT_LIST_HEAD(&pcdev->capture);
1762 INIT_LIST_HEAD(&pcdev->active_bufs);
1763 INIT_LIST_HEAD(&pcdev->discard);
1764 spin_lock_init(&pcdev->lock);
1765
1766 pcdev->base_csi = devm_request_and_ioremap(&pdev->dev, res_csi);
1767 if (!pcdev->base_csi) {
1768 err = -EADDRNOTAVAIL;
1769 goto exit;
1770 }
1771
1772 pcdev->dev = &pdev->dev;
1773 platform_set_drvdata(pdev, pcdev);
1774
1775 if (cpu_is_mx25()) {
1776 err = devm_request_irq(&pdev->dev, irq_csi, mx25_camera_irq, 0,
1777 MX2_CAM_DRV_NAME, pcdev);
1778 if (err) {
1779 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1780 goto exit;
1781 }
1782 }
1783
1784 if (cpu_is_mx27()) {
1785 err = mx27_camera_emma_init(pdev);
1786 if (err)
1787 goto exit;
1788 }
1789
1790 /*
1791 * We're done with drvdata here. Clear the pointer so that
1792 * v4l2 core can start using drvdata on its purpose.
1793 */
1794 platform_set_drvdata(pdev, NULL);
1795
1796 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1797 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1798 pcdev->soc_host.priv = pcdev;
1799 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1800 pcdev->soc_host.nr = pdev->id;
1801 if (cpu_is_mx25())
1802 pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE;
1803
1804 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1805 if (IS_ERR(pcdev->alloc_ctx)) {
1806 err = PTR_ERR(pcdev->alloc_ctx);
1807 goto eallocctx;
1808 }
1809 err = soc_camera_host_register(&pcdev->soc_host);
1810 if (err)
1811 goto exit_free_emma;
1812
1813 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1814 clk_get_rate(pcdev->clk_csi));
1815
1816 return 0;
1817
1818 exit_free_emma:
1819 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1820 eallocctx:
1821 if (cpu_is_mx27()) {
1822 clk_disable_unprepare(pcdev->clk_emma_ipg);
1823 clk_disable_unprepare(pcdev->clk_emma_ahb);
1824 }
1825 exit:
1826 return err;
1827 }
1828
1829 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1830 {
1831 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1832 struct mx2_camera_dev *pcdev = container_of(soc_host,
1833 struct mx2_camera_dev, soc_host);
1834
1835 soc_camera_host_unregister(&pcdev->soc_host);
1836
1837 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1838
1839 if (cpu_is_mx27()) {
1840 clk_disable_unprepare(pcdev->clk_emma_ipg);
1841 clk_disable_unprepare(pcdev->clk_emma_ahb);
1842 }
1843
1844 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1845
1846 return 0;
1847 }
1848
1849 static struct platform_driver mx2_camera_driver = {
1850 .driver = {
1851 .name = MX2_CAM_DRV_NAME,
1852 },
1853 .remove = __devexit_p(mx2_camera_remove),
1854 };
1855
1856
1857 static int __init mx2_camera_init(void)
1858 {
1859 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1860 }
1861
1862 static void __exit mx2_camera_exit(void)
1863 {
1864 return platform_driver_unregister(&mx2_camera_driver);
1865 }
1866
1867 module_init(mx2_camera_init);
1868 module_exit(mx2_camera_exit);
1869
1870 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1871 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1872 MODULE_LICENSE("GPL");
1873 MODULE_VERSION(MX2_CAM_VERSION);
kernel source for telekom puls (alcatel/mediatek)