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Merge tag 'pci-v3.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / platform / s5p-mfc / s5p_mfc_opr_v6.c
1 /*
2 * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
3 *
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
6 *
7 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
8 * http://www.samsung.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #undef DEBUG
16
17 #include <linux/delay.h>
18 #include <linux/mm.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/firmware.h>
22 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25
26 #include <asm/cacheflush.h>
27
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_cmd.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_pm.h"
32 #include "s5p_mfc_debug.h"
33 #include "s5p_mfc_opr.h"
34 #include "s5p_mfc_opr_v6.h"
35
36 /* #define S5P_MFC_DEBUG_REGWRITE */
37 #ifdef S5P_MFC_DEBUG_REGWRITE
38 #undef writel
39 #define writel(v, r) \
40 do { \
41 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
42 __raw_writel(v, r); \
43 } while (0)
44 #endif /* S5P_MFC_DEBUG_REGWRITE */
45
46 #define READL(offset) readl(dev->regs_base + (offset))
47 #define WRITEL(data, offset) writel((data), dev->regs_base + (offset))
48 #define OFFSETA(x) (((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET)
49 #define OFFSETB(x) (((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET)
50
51 /* Allocate temporary buffers for decoding */
52 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
53 {
54 /* NOP */
55
56 return 0;
57 }
58
59 /* Release temproary buffers for decoding */
60 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
61 {
62 /* NOP */
63 }
64
65 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
66 {
67 /* NOP */
68 return -1;
69 }
70
71 /* Allocate codec buffers */
72 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
73 {
74 struct s5p_mfc_dev *dev = ctx->dev;
75 unsigned int mb_width, mb_height;
76 int ret;
77
78 mb_width = MB_WIDTH(ctx->img_width);
79 mb_height = MB_HEIGHT(ctx->img_height);
80
81 if (ctx->type == MFCINST_DECODER) {
82 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
83 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
84 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
85 } else if (ctx->type == MFCINST_ENCODER) {
86 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
87 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
88 S5P_FIMV_TMV_BUFFER_ALIGN_V6);
89 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
90 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
91 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
92 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
93 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
94 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
95 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
96 ctx->img_width, ctx->img_height,
97 mb_width, mb_height),
98 S5P_FIMV_ME_BUFFER_ALIGN_V6);
99
100 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
101 ctx->luma_dpb_size, ctx->chroma_dpb_size);
102 } else {
103 return -EINVAL;
104 }
105
106 /* Codecs have different memory requirements */
107 switch (ctx->codec_mode) {
108 case S5P_MFC_CODEC_H264_DEC:
109 case S5P_MFC_CODEC_H264_MVC_DEC:
110 ctx->scratch_buf_size =
111 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
112 mb_width,
113 mb_height);
114 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
115 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
116 ctx->bank1.size =
117 ctx->scratch_buf_size +
118 (ctx->mv_count * ctx->mv_size);
119 break;
120 case S5P_MFC_CODEC_MPEG4_DEC:
121 ctx->scratch_buf_size =
122 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
123 mb_width,
124 mb_height);
125 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
126 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
127 ctx->bank1.size = ctx->scratch_buf_size;
128 break;
129 case S5P_MFC_CODEC_VC1RCV_DEC:
130 case S5P_MFC_CODEC_VC1_DEC:
131 ctx->scratch_buf_size =
132 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
133 mb_width,
134 mb_height);
135 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
136 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
137 ctx->bank1.size = ctx->scratch_buf_size;
138 break;
139 case S5P_MFC_CODEC_MPEG2_DEC:
140 ctx->bank1.size = 0;
141 ctx->bank2.size = 0;
142 break;
143 case S5P_MFC_CODEC_H263_DEC:
144 ctx->scratch_buf_size =
145 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
146 mb_width,
147 mb_height);
148 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
149 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
150 ctx->bank1.size = ctx->scratch_buf_size;
151 break;
152 case S5P_MFC_CODEC_VP8_DEC:
153 ctx->scratch_buf_size =
154 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
155 mb_width,
156 mb_height);
157 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
158 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
159 ctx->bank1.size = ctx->scratch_buf_size;
160 break;
161 case S5P_MFC_CODEC_H264_ENC:
162 ctx->scratch_buf_size =
163 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
164 mb_width,
165 mb_height);
166 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
167 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
168 ctx->bank1.size =
169 ctx->scratch_buf_size + ctx->tmv_buffer_size +
170 (ctx->dpb_count * (ctx->luma_dpb_size +
171 ctx->chroma_dpb_size + ctx->me_buffer_size));
172 ctx->bank2.size = 0;
173 break;
174 case S5P_MFC_CODEC_MPEG4_ENC:
175 case S5P_MFC_CODEC_H263_ENC:
176 ctx->scratch_buf_size =
177 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
178 mb_width,
179 mb_height);
180 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
181 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
182 ctx->bank1.size =
183 ctx->scratch_buf_size + ctx->tmv_buffer_size +
184 (ctx->dpb_count * (ctx->luma_dpb_size +
185 ctx->chroma_dpb_size + ctx->me_buffer_size));
186 ctx->bank2.size = 0;
187 break;
188 default:
189 break;
190 }
191
192 /* Allocate only if memory from bank 1 is necessary */
193 if (ctx->bank1.size > 0) {
194 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
195 if (ret) {
196 mfc_err("Failed to allocate Bank1 memory\n");
197 return ret;
198 }
199 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
200 }
201
202 return 0;
203 }
204
205 /* Release buffers allocated for codec */
206 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
207 {
208 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
209 }
210
211 /* Allocate memory for instance data buffer */
212 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
213 {
214 struct s5p_mfc_dev *dev = ctx->dev;
215 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
216 int ret;
217
218 mfc_debug_enter();
219
220 switch (ctx->codec_mode) {
221 case S5P_MFC_CODEC_H264_DEC:
222 case S5P_MFC_CODEC_H264_MVC_DEC:
223 ctx->ctx.size = buf_size->h264_dec_ctx;
224 break;
225 case S5P_MFC_CODEC_MPEG4_DEC:
226 case S5P_MFC_CODEC_H263_DEC:
227 case S5P_MFC_CODEC_VC1RCV_DEC:
228 case S5P_MFC_CODEC_VC1_DEC:
229 case S5P_MFC_CODEC_MPEG2_DEC:
230 case S5P_MFC_CODEC_VP8_DEC:
231 ctx->ctx.size = buf_size->other_dec_ctx;
232 break;
233 case S5P_MFC_CODEC_H264_ENC:
234 ctx->ctx.size = buf_size->h264_enc_ctx;
235 break;
236 case S5P_MFC_CODEC_MPEG4_ENC:
237 case S5P_MFC_CODEC_H263_ENC:
238 ctx->ctx.size = buf_size->other_enc_ctx;
239 break;
240 default:
241 ctx->ctx.size = 0;
242 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
243 break;
244 }
245
246 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
247 if (ret) {
248 mfc_err("Failed to allocate instance buffer\n");
249 return ret;
250 }
251
252 memset(ctx->ctx.virt, 0, ctx->ctx.size);
253 wmb();
254
255 mfc_debug_leave();
256
257 return 0;
258 }
259
260 /* Release instance buffer */
261 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
262 {
263 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
264 }
265
266 /* Allocate context buffers for SYS_INIT */
267 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
268 {
269 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
270 int ret;
271
272 mfc_debug_enter();
273
274 dev->ctx_buf.size = buf_size->dev_ctx;
275 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
276 if (ret) {
277 mfc_err("Failed to allocate device context buffer\n");
278 return ret;
279 }
280
281 memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
282 wmb();
283
284 mfc_debug_leave();
285
286 return 0;
287 }
288
289 /* Release context buffers for SYS_INIT */
290 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
291 {
292 s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
293 }
294
295 static int calc_plane(int width, int height)
296 {
297 int mbX, mbY;
298
299 mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
300 mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
301
302 if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
303 mbY = (mbY + 1) / 2 * 2;
304
305 return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
306 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
307 }
308
309 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
310 {
311 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
312 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
313 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
314 "buffer dimensions: %dx%d\n", ctx->img_width,
315 ctx->img_height, ctx->buf_width, ctx->buf_height);
316
317 ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
318 ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
319 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
320 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
321 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
322 ctx->img_height);
323 ctx->mv_size = ALIGN(ctx->mv_size, 16);
324 } else {
325 ctx->mv_size = 0;
326 }
327 }
328
329 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
330 {
331 unsigned int mb_width, mb_height;
332
333 mb_width = MB_WIDTH(ctx->img_width);
334 mb_height = MB_HEIGHT(ctx->img_height);
335
336 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
337 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
338 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
339 }
340
341 /* Set registers for decoding stream buffer */
342 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
343 int buf_addr, unsigned int start_num_byte,
344 unsigned int strm_size)
345 {
346 struct s5p_mfc_dev *dev = ctx->dev;
347 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
348
349 mfc_debug_enter();
350 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
351 "buf_size: 0x%08x (%d)\n",
352 ctx->inst_no, buf_addr, strm_size, strm_size);
353 WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
354 WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
355 WRITEL(buf_size->cpb, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
356 WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
357
358 mfc_debug_leave();
359 return 0;
360 }
361
362 /* Set decoding frame buffer */
363 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
364 {
365 unsigned int frame_size, i;
366 unsigned int frame_size_ch, frame_size_mv;
367 struct s5p_mfc_dev *dev = ctx->dev;
368 size_t buf_addr1;
369 int buf_size1;
370 int align_gap;
371
372 buf_addr1 = ctx->bank1.dma;
373 buf_size1 = ctx->bank1.size;
374
375 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
376 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
377 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
378
379 WRITEL(ctx->total_dpb_count, S5P_FIMV_D_NUM_DPB_V6);
380 WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
381 WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
382
383 WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
384 WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
385 buf_addr1 += ctx->scratch_buf_size;
386 buf_size1 -= ctx->scratch_buf_size;
387
388 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
389 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
390 WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
391 WRITEL(ctx->mv_count, S5P_FIMV_D_NUM_MV_V6);
392 }
393
394 frame_size = ctx->luma_size;
395 frame_size_ch = ctx->chroma_size;
396 frame_size_mv = ctx->mv_size;
397 mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
398 frame_size, frame_size_ch, frame_size_mv);
399
400 for (i = 0; i < ctx->total_dpb_count; i++) {
401 /* Bank2 */
402 mfc_debug(2, "Luma %d: %x\n", i,
403 ctx->dst_bufs[i].cookie.raw.luma);
404 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
405 S5P_FIMV_D_LUMA_DPB_V6 + i * 4);
406 mfc_debug(2, "\tChroma %d: %x\n", i,
407 ctx->dst_bufs[i].cookie.raw.chroma);
408 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
409 S5P_FIMV_D_CHROMA_DPB_V6 + i * 4);
410 }
411 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
412 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
413 for (i = 0; i < ctx->mv_count; i++) {
414 /* To test alignment */
415 align_gap = buf_addr1;
416 buf_addr1 = ALIGN(buf_addr1, 16);
417 align_gap = buf_addr1 - align_gap;
418 buf_size1 -= align_gap;
419
420 mfc_debug(2, "\tBuf1: %x, size: %d\n",
421 buf_addr1, buf_size1);
422 WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER_V6 + i * 4);
423 buf_addr1 += frame_size_mv;
424 buf_size1 -= frame_size_mv;
425 }
426 }
427
428 mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
429 buf_addr1, buf_size1, ctx->total_dpb_count);
430 if (buf_size1 < 0) {
431 mfc_debug(2, "Not enough memory has been allocated.\n");
432 return -ENOMEM;
433 }
434
435 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
436 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
437 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
438
439 mfc_debug(2, "After setting buffers.\n");
440 return 0;
441 }
442
443 /* Set registers for encoding stream buffer */
444 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
445 unsigned long addr, unsigned int size)
446 {
447 struct s5p_mfc_dev *dev = ctx->dev;
448
449 WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); /* 16B align */
450 WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
451
452 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d",
453 addr, size);
454
455 return 0;
456 }
457
458 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
459 unsigned long y_addr, unsigned long c_addr)
460 {
461 struct s5p_mfc_dev *dev = ctx->dev;
462
463 WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6); /* 256B align */
464 WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
465
466 mfc_debug(2, "enc src y buf addr: 0x%08lx", y_addr);
467 mfc_debug(2, "enc src c buf addr: 0x%08lx", c_addr);
468 }
469
470 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
471 unsigned long *y_addr, unsigned long *c_addr)
472 {
473 struct s5p_mfc_dev *dev = ctx->dev;
474 unsigned long enc_recon_y_addr, enc_recon_c_addr;
475
476 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
477 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
478
479 enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
480 enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
481
482 mfc_debug(2, "recon y addr: 0x%08lx", enc_recon_y_addr);
483 mfc_debug(2, "recon c addr: 0x%08lx", enc_recon_c_addr);
484 }
485
486 /* Set encoding ref & codec buffer */
487 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
488 {
489 struct s5p_mfc_dev *dev = ctx->dev;
490 size_t buf_addr1;
491 int i, buf_size1;
492
493 mfc_debug_enter();
494
495 buf_addr1 = ctx->bank1.dma;
496 buf_size1 = ctx->bank1.size;
497
498 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
499
500 for (i = 0; i < ctx->dpb_count; i++) {
501 WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB_V6 + (4 * i));
502 buf_addr1 += ctx->luma_dpb_size;
503 WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB_V6 + (4 * i));
504 buf_addr1 += ctx->chroma_dpb_size;
505 WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER_V6 + (4 * i));
506 buf_addr1 += ctx->me_buffer_size;
507 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
508 ctx->me_buffer_size);
509 }
510
511 WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
512 WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
513 buf_addr1 += ctx->scratch_buf_size;
514 buf_size1 -= ctx->scratch_buf_size;
515
516 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0_V6);
517 buf_addr1 += ctx->tmv_buffer_size >> 1;
518 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1_V6);
519 buf_addr1 += ctx->tmv_buffer_size >> 1;
520 buf_size1 -= ctx->tmv_buffer_size;
521
522 mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
523 buf_addr1, buf_size1, ctx->dpb_count);
524 if (buf_size1 < 0) {
525 mfc_debug(2, "Not enough memory has been allocated.\n");
526 return -ENOMEM;
527 }
528
529 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
530 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
531 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
532
533 mfc_debug_leave();
534
535 return 0;
536 }
537
538 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
539 {
540 struct s5p_mfc_dev *dev = ctx->dev;
541
542 /* multi-slice control */
543 /* multi-slice MB number or bit size */
544 WRITEL(ctx->slice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
545 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
546 WRITEL(ctx->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
547 } else if (ctx->slice_mode ==
548 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
549 WRITEL(ctx->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
550 } else {
551 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
552 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
553 }
554
555 return 0;
556 }
557
558 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
559 {
560 struct s5p_mfc_dev *dev = ctx->dev;
561 struct s5p_mfc_enc_params *p = &ctx->enc_params;
562 unsigned int reg = 0;
563
564 mfc_debug_enter();
565
566 /* width */
567 WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH_V6); /* 16 align */
568 /* height */
569 WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT_V6); /* 16 align */
570
571 /* cropped width */
572 WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
573 /* cropped height */
574 WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
575 /* cropped offset */
576 WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
577
578 /* pictype : IDR period */
579 reg = 0;
580 reg |= p->gop_size & 0xFFFF;
581 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
582
583 /* multi-slice control */
584 /* multi-slice MB number or bit size */
585 ctx->slice_mode = p->slice_mode;
586 reg = 0;
587 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
588 reg |= (0x1 << 3);
589 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
590 ctx->slice_size.mb = p->slice_mb;
591 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
592 reg |= (0x1 << 3);
593 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
594 ctx->slice_size.bits = p->slice_bit;
595 } else {
596 reg &= ~(0x1 << 3);
597 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
598 }
599
600 s5p_mfc_set_slice_mode(ctx);
601
602 /* cyclic intra refresh */
603 WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE_V6);
604 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
605 if (p->intra_refresh_mb == 0)
606 reg &= ~(0x1 << 4);
607 else
608 reg |= (0x1 << 4);
609 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
610
611 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
612 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
613 reg &= ~(0x1 << 9);
614 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
615
616 /* memory structure cur. frame */
617 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
618 /* 0: Linear, 1: 2D tiled*/
619 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
620 reg &= ~(0x1 << 7);
621 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
622 /* 0: NV12(CbCr), 1: NV21(CrCb) */
623 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
624 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
625 /* 0: Linear, 1: 2D tiled*/
626 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
627 reg &= ~(0x1 << 7);
628 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
629 /* 0: NV12(CbCr), 1: NV21(CrCb) */
630 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
631 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
632 /* 0: Linear, 1: 2D tiled*/
633 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
634 reg |= (0x1 << 7);
635 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
636 /* 0: NV12(CbCr), 1: NV21(CrCb) */
637 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
638 }
639
640 /* memory structure recon. frame */
641 /* 0: Linear, 1: 2D tiled */
642 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
643 reg |= (0x1 << 8);
644 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
645
646 /* padding control & value */
647 WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL_V6);
648 if (p->pad) {
649 reg = 0;
650 /** enable */
651 reg |= (1 << 31);
652 /** cr value */
653 reg |= ((p->pad_cr & 0xFF) << 16);
654 /** cb value */
655 reg |= ((p->pad_cb & 0xFF) << 8);
656 /** y value */
657 reg |= p->pad_luma & 0xFF;
658 WRITEL(reg, S5P_FIMV_E_PADDING_CTRL_V6);
659 }
660
661 /* rate control config. */
662 reg = 0;
663 /* frame-level rate control */
664 reg |= ((p->rc_frame & 0x1) << 9);
665 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
666
667 /* bit rate */
668 if (p->rc_frame)
669 WRITEL(p->rc_bitrate,
670 S5P_FIMV_E_RC_BIT_RATE_V6);
671 else
672 WRITEL(1, S5P_FIMV_E_RC_BIT_RATE_V6);
673
674 /* reaction coefficient */
675 if (p->rc_frame) {
676 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
677 WRITEL(1, S5P_FIMV_E_RC_RPARAM_V6);
678 else /* loose CBR */
679 WRITEL(2, S5P_FIMV_E_RC_RPARAM_V6);
680 }
681
682 /* seq header ctrl */
683 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
684 reg &= ~(0x1 << 2);
685 reg |= ((p->seq_hdr_mode & 0x1) << 2);
686
687 /* frame skip mode */
688 reg &= ~(0x3);
689 reg |= (p->frame_skip_mode & 0x3);
690 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
691
692 /* 'DROP_CONTROL_ENABLE', disable */
693 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
694 reg &= ~(0x1 << 10);
695 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
696
697 /* setting for MV range [16, 256] */
698 reg = 0;
699 reg &= ~(0x3FFF);
700 reg = 256;
701 WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6);
702
703 reg = 0;
704 reg &= ~(0x3FFF);
705 reg = 256;
706 WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6);
707
708 WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6);
709 WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
710 WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE_V6);
711 WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL_V6);
712 WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG_V6);
713
714 WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
715 WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT_V6);
716 WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT_V6);
717
718 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
719 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
720
721 mfc_debug_leave();
722
723 return 0;
724 }
725
726 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
727 {
728 struct s5p_mfc_dev *dev = ctx->dev;
729 struct s5p_mfc_enc_params *p = &ctx->enc_params;
730 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
731 unsigned int reg = 0;
732 int i;
733
734 mfc_debug_enter();
735
736 s5p_mfc_set_enc_params(ctx);
737
738 /* pictype : number of B */
739 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
740 reg &= ~(0x3 << 16);
741 reg |= ((p->num_b_frame & 0x3) << 16);
742 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
743
744 /* profile & level */
745 reg = 0;
746 /** level */
747 reg |= ((p_h264->level & 0xFF) << 8);
748 /** profile - 0 ~ 3 */
749 reg |= p_h264->profile & 0x3F;
750 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
751
752 /* rate control config. */
753 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
754 /** macroblock level rate control */
755 reg &= ~(0x1 << 8);
756 reg |= ((p->rc_mb & 0x1) << 8);
757 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
758 /** frame QP */
759 reg &= ~(0x3F);
760 reg |= p_h264->rc_frame_qp & 0x3F;
761 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
762
763 /* max & min value of QP */
764 reg = 0;
765 /** max QP */
766 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
767 /** min QP */
768 reg |= p_h264->rc_min_qp & 0x3F;
769 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
770
771 /* other QPs */
772 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
773 if (!p->rc_frame && !p->rc_mb) {
774 reg = 0;
775 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
776 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
777 reg |= p_h264->rc_frame_qp & 0x3F;
778 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
779 }
780
781 /* frame rate */
782 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
783 reg = 0;
784 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
785 reg |= p->rc_framerate_denom & 0xFFFF;
786 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
787 }
788
789 /* vbv buffer size */
790 if (p->frame_skip_mode ==
791 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
792 WRITEL(p_h264->cpb_size & 0xFFFF,
793 S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
794
795 if (p->rc_frame)
796 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
797 }
798
799 /* interlace */
800 reg = 0;
801 reg |= ((p_h264->interlace & 0x1) << 3);
802 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
803
804 /* height */
805 if (p_h264->interlace) {
806 WRITEL(ctx->img_height >> 1,
807 S5P_FIMV_E_FRAME_HEIGHT_V6); /* 32 align */
808 /* cropped height */
809 WRITEL(ctx->img_height >> 1,
810 S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
811 }
812
813 /* loop filter ctrl */
814 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
815 reg &= ~(0x3 << 1);
816 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
817 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
818
819 /* loopfilter alpha offset */
820 if (p_h264->loop_filter_alpha < 0) {
821 reg = 0x10;
822 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
823 } else {
824 reg = 0x00;
825 reg |= (p_h264->loop_filter_alpha & 0xF);
826 }
827 WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
828
829 /* loopfilter beta offset */
830 if (p_h264->loop_filter_beta < 0) {
831 reg = 0x10;
832 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
833 } else {
834 reg = 0x00;
835 reg |= (p_h264->loop_filter_beta & 0xF);
836 }
837 WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
838
839 /* entropy coding mode */
840 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
841 reg &= ~(0x1);
842 reg |= p_h264->entropy_mode & 0x1;
843 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
844
845 /* number of ref. picture */
846 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
847 reg &= ~(0x1 << 7);
848 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
849 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
850
851 /* 8x8 transform enable */
852 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
853 reg &= ~(0x3 << 12);
854 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
855 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
856
857 /* macroblock adaptive scaling features */
858 WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG_V6);
859 if (p->rc_mb) {
860 reg = 0;
861 /** dark region */
862 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
863 /** smooth region */
864 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
865 /** static region */
866 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
867 /** high activity region */
868 reg |= p_h264->rc_mb_activity & 0x1;
869 WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG_V6);
870 }
871
872 /* aspect ratio VUI */
873 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
874 reg &= ~(0x1 << 5);
875 reg |= ((p_h264->vui_sar & 0x1) << 5);
876 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
877
878 WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO_V6);
879 WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR_V6);
880 if (p_h264->vui_sar) {
881 /* aspect ration IDC */
882 reg = 0;
883 reg |= p_h264->vui_sar_idc & 0xFF;
884 WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO_V6);
885 if (p_h264->vui_sar_idc == 0xFF) {
886 /* extended SAR */
887 reg = 0;
888 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
889 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
890 WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR_V6);
891 }
892 }
893
894 /* intra picture period for H.264 open GOP */
895 /* control */
896 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
897 reg &= ~(0x1 << 4);
898 reg |= ((p_h264->open_gop & 0x1) << 4);
899 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
900 /* value */
901 WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD_V6);
902 if (p_h264->open_gop) {
903 reg = 0;
904 reg |= p_h264->open_gop_size & 0xFFFF;
905 WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD_V6);
906 }
907
908 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
909 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
910 reg &= ~(0x3 << 9);
911 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
912
913 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
914 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
915 reg &= ~(0x1 << 14);
916 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
917
918 /* ASO */
919 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
920 reg &= ~(0x1 << 6);
921 reg |= ((p_h264->aso & 0x1) << 6);
922 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
923
924 /* hier qp enable */
925 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
926 reg &= ~(0x1 << 8);
927 reg |= ((p_h264->open_gop & 0x1) << 8);
928 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
929 reg = 0;
930 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
931 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
932 reg |= p_h264->hier_qp_layer & 0x7;
933 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
934 /* QP value for each layer */
935 for (i = 0; i < (p_h264->hier_qp_layer & 0x7); i++)
936 WRITEL(p_h264->hier_qp_layer_qp[i],
937 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 +
938 i * 4);
939 }
940 /* number of coding layer should be zero when hierarchical is disable */
941 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
942
943 /* frame packing SEI generation */
944 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
945 reg &= ~(0x1 << 25);
946 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
947 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
948 if (p_h264->sei_frame_packing) {
949 reg = 0;
950 /** current frame0 flag */
951 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
952 /** arrangement type */
953 reg |= p_h264->sei_fp_arrangement_type & 0x3;
954 WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
955 }
956
957 if (p_h264->fmo) {
958 switch (p_h264->fmo_map_type) {
959 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
960 if (p_h264->fmo_slice_grp > 4)
961 p_h264->fmo_slice_grp = 4;
962 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
963 WRITEL(p_h264->fmo_run_len[i] - 1,
964 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 +
965 i * 4);
966 break;
967 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
968 if (p_h264->fmo_slice_grp > 4)
969 p_h264->fmo_slice_grp = 4;
970 break;
971 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
972 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
973 if (p_h264->fmo_slice_grp > 2)
974 p_h264->fmo_slice_grp = 2;
975 WRITEL(p_h264->fmo_chg_dir & 0x1,
976 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
977 /* the valid range is 0 ~ number of macroblocks -1 */
978 WRITEL(p_h264->fmo_chg_rate,
979 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
980 break;
981 default:
982 mfc_err("Unsupported map type for FMO: %d\n",
983 p_h264->fmo_map_type);
984 p_h264->fmo_map_type = 0;
985 p_h264->fmo_slice_grp = 1;
986 break;
987 }
988
989 WRITEL(p_h264->fmo_map_type,
990 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
991 WRITEL(p_h264->fmo_slice_grp - 1,
992 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
993 } else {
994 WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
995 }
996
997 mfc_debug_leave();
998
999 return 0;
1000 }
1001
1002 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1003 {
1004 struct s5p_mfc_dev *dev = ctx->dev;
1005 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1006 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1007 unsigned int reg = 0;
1008
1009 mfc_debug_enter();
1010
1011 s5p_mfc_set_enc_params(ctx);
1012
1013 /* pictype : number of B */
1014 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
1015 reg &= ~(0x3 << 16);
1016 reg |= ((p->num_b_frame & 0x3) << 16);
1017 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
1018
1019 /* profile & level */
1020 reg = 0;
1021 /** level */
1022 reg |= ((p_mpeg4->level & 0xFF) << 8);
1023 /** profile - 0 ~ 1 */
1024 reg |= p_mpeg4->profile & 0x3F;
1025 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1026
1027 /* rate control config. */
1028 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1029 /** macroblock level rate control */
1030 reg &= ~(0x1 << 8);
1031 reg |= ((p->rc_mb & 0x1) << 8);
1032 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1033 /** frame QP */
1034 reg &= ~(0x3F);
1035 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1036 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1037
1038 /* max & min value of QP */
1039 reg = 0;
1040 /** max QP */
1041 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1042 /** min QP */
1043 reg |= p_mpeg4->rc_min_qp & 0x3F;
1044 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1045
1046 /* other QPs */
1047 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1048 if (!p->rc_frame && !p->rc_mb) {
1049 reg = 0;
1050 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1051 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1052 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1053 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1054 }
1055
1056 /* frame rate */
1057 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1058 reg = 0;
1059 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1060 reg |= p->rc_framerate_denom & 0xFFFF;
1061 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1062 }
1063
1064 /* vbv buffer size */
1065 if (p->frame_skip_mode ==
1066 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1067 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1068
1069 if (p->rc_frame)
1070 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1071 }
1072
1073 /* Disable HEC */
1074 WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS_V6);
1075 WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
1076
1077 mfc_debug_leave();
1078
1079 return 0;
1080 }
1081
1082 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1083 {
1084 struct s5p_mfc_dev *dev = ctx->dev;
1085 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1086 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1087 unsigned int reg = 0;
1088
1089 mfc_debug_enter();
1090
1091 s5p_mfc_set_enc_params(ctx);
1092
1093 /* profile & level */
1094 reg = 0;
1095 /** profile */
1096 reg |= (0x1 << 4);
1097 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1098
1099 /* rate control config. */
1100 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1101 /** macroblock level rate control */
1102 reg &= ~(0x1 << 8);
1103 reg |= ((p->rc_mb & 0x1) << 8);
1104 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1105 /** frame QP */
1106 reg &= ~(0x3F);
1107 reg |= p_h263->rc_frame_qp & 0x3F;
1108 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1109
1110 /* max & min value of QP */
1111 reg = 0;
1112 /** max QP */
1113 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1114 /** min QP */
1115 reg |= p_h263->rc_min_qp & 0x3F;
1116 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1117
1118 /* other QPs */
1119 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1120 if (!p->rc_frame && !p->rc_mb) {
1121 reg = 0;
1122 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1123 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1124 reg |= p_h263->rc_frame_qp & 0x3F;
1125 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1126 }
1127
1128 /* frame rate */
1129 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1130 reg = 0;
1131 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1132 reg |= p->rc_framerate_denom & 0xFFFF;
1133 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1134 }
1135
1136 /* vbv buffer size */
1137 if (p->frame_skip_mode ==
1138 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1139 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1140
1141 if (p->rc_frame)
1142 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1143 }
1144
1145 mfc_debug_leave();
1146
1147 return 0;
1148 }
1149
1150 /* Initialize decoding */
1151 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1152 {
1153 struct s5p_mfc_dev *dev = ctx->dev;
1154 unsigned int reg = 0;
1155 int fmo_aso_ctrl = 0;
1156
1157 mfc_debug_enter();
1158 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1159 S5P_FIMV_CH_SEQ_HEADER_V6);
1160 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1161 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1162 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1163 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6));
1164
1165 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1166 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1167
1168 /* When user sets desplay_delay to 0,
1169 * It works as "display_delay enable" and delay set to 0.
1170 * If user wants display_delay disable, It should be
1171 * set to negative value. */
1172 if (ctx->display_delay >= 0) {
1173 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1174 WRITEL(ctx->display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
1175 }
1176 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1177 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1178 mfc_debug(2, "Set loop filter to: %d\n",
1179 ctx->loop_filter_mpeg4);
1180 reg |= (ctx->loop_filter_mpeg4 <<
1181 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1182 }
1183 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1184 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1185
1186 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6);
1187
1188 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1189 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1190 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
1191 else
1192 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
1193
1194 /* sei parse */
1195 WRITEL(ctx->sei_fp_parse & 0x1, S5P_FIMV_D_SEI_ENABLE_V6);
1196
1197 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1198 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1199 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1200
1201 mfc_debug_leave();
1202 return 0;
1203 }
1204
1205 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1206 {
1207 struct s5p_mfc_dev *dev = ctx->dev;
1208
1209 if (flush) {
1210 dev->curr_ctx = ctx->num;
1211 s5p_mfc_clean_ctx_int_flags(ctx);
1212 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1213 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1214 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1215 }
1216 }
1217
1218 /* Decode a single frame */
1219 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1220 enum s5p_mfc_decode_arg last_frame)
1221 {
1222 struct s5p_mfc_dev *dev = ctx->dev;
1223
1224 WRITEL(ctx->dec_dst_flag, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
1225 WRITEL(ctx->slice_interface & 0x1, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
1226
1227 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1228 /* Issue different commands to instance basing on whether it
1229 * is the last frame or not. */
1230 switch (last_frame) {
1231 case 0:
1232 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1233 S5P_FIMV_CH_FRAME_START_V6, NULL);
1234 break;
1235 case 1:
1236 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1237 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1238 break;
1239 default:
1240 mfc_err("Unsupported last frame arg.\n");
1241 return -EINVAL;
1242 }
1243
1244 mfc_debug(2, "Decoding a usual frame.\n");
1245 return 0;
1246 }
1247
1248 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1249 {
1250 struct s5p_mfc_dev *dev = ctx->dev;
1251
1252 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1253 s5p_mfc_set_enc_params_h264(ctx);
1254 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1255 s5p_mfc_set_enc_params_mpeg4(ctx);
1256 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1257 s5p_mfc_set_enc_params_h263(ctx);
1258 else {
1259 mfc_err("Unknown codec for encoding (%x).\n",
1260 ctx->codec_mode);
1261 return -EINVAL;
1262 }
1263
1264 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1265 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1266 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1267
1268 return 0;
1269 }
1270
1271 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1272 {
1273 struct s5p_mfc_dev *dev = ctx->dev;
1274 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1275 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1276 int i;
1277
1278 if (p_h264->aso) {
1279 for (i = 0; i < 8; i++)
1280 WRITEL(p_h264->aso_slice_order[i],
1281 S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 + i * 4);
1282 }
1283 return 0;
1284 }
1285
1286 /* Encode a single frame */
1287 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1288 {
1289 struct s5p_mfc_dev *dev = ctx->dev;
1290
1291 mfc_debug(2, "++\n");
1292
1293 /* memory structure cur. frame */
1294
1295 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1296 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1297
1298 s5p_mfc_set_slice_mode(ctx);
1299
1300 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1301 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1302 S5P_FIMV_CH_FRAME_START_V6, NULL);
1303
1304 mfc_debug(2, "--\n");
1305
1306 return 0;
1307 }
1308
1309 static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1310 {
1311 unsigned long flags;
1312 int new_ctx;
1313 int cnt;
1314
1315 spin_lock_irqsave(&dev->condlock, flags);
1316 mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx,
1317 dev->ctx_work_bits);
1318 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1319 cnt = 0;
1320 while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1321 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1322 cnt++;
1323 if (cnt > MFC_NUM_CONTEXTS) {
1324 /* No contexts to run */
1325 spin_unlock_irqrestore(&dev->condlock, flags);
1326 return -EAGAIN;
1327 }
1328 }
1329 spin_unlock_irqrestore(&dev->condlock, flags);
1330 return new_ctx;
1331 }
1332
1333 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1334 {
1335 struct s5p_mfc_dev *dev = ctx->dev;
1336 struct s5p_mfc_buf *temp_vb;
1337 unsigned long flags;
1338
1339 spin_lock_irqsave(&dev->irqlock, flags);
1340
1341 /* Frames are being decoded */
1342 if (list_empty(&ctx->src_queue)) {
1343 mfc_debug(2, "No src buffers.\n");
1344 spin_unlock_irqrestore(&dev->irqlock, flags);
1345 return;
1346 }
1347 /* Get the next source buffer */
1348 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1349 temp_vb->flags |= MFC_BUF_FLAG_USED;
1350 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1351 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0);
1352 spin_unlock_irqrestore(&dev->irqlock, flags);
1353
1354 dev->curr_ctx = ctx->num;
1355 s5p_mfc_clean_ctx_int_flags(ctx);
1356 s5p_mfc_decode_one_frame_v6(ctx, 1);
1357 }
1358
1359 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1360 {
1361 struct s5p_mfc_dev *dev = ctx->dev;
1362 struct s5p_mfc_buf *temp_vb;
1363 unsigned long flags;
1364 int last_frame = 0;
1365
1366 if (ctx->state == MFCINST_FINISHING) {
1367 last_frame = MFC_DEC_LAST_FRAME;
1368 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1369 dev->curr_ctx = ctx->num;
1370 s5p_mfc_clean_ctx_int_flags(ctx);
1371 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1372 return 0;
1373 }
1374
1375 spin_lock_irqsave(&dev->irqlock, flags);
1376 /* Frames are being decoded */
1377 if (list_empty(&ctx->src_queue)) {
1378 mfc_debug(2, "No src buffers.\n");
1379 spin_unlock_irqrestore(&dev->irqlock, flags);
1380 return -EAGAIN;
1381 }
1382 /* Get the next source buffer */
1383 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1384 temp_vb->flags |= MFC_BUF_FLAG_USED;
1385 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1386 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1387 ctx->consumed_stream,
1388 temp_vb->b->v4l2_planes[0].bytesused);
1389 spin_unlock_irqrestore(&dev->irqlock, flags);
1390
1391 dev->curr_ctx = ctx->num;
1392 s5p_mfc_clean_ctx_int_flags(ctx);
1393 if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1394 last_frame = 1;
1395 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1396 ctx->state = MFCINST_FINISHING;
1397 }
1398 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1399
1400 return 0;
1401 }
1402
1403 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1404 {
1405 struct s5p_mfc_dev *dev = ctx->dev;
1406 unsigned long flags;
1407 struct s5p_mfc_buf *dst_mb;
1408 struct s5p_mfc_buf *src_mb;
1409 unsigned long src_y_addr, src_c_addr, dst_addr;
1410 /*
1411 unsigned int src_y_size, src_c_size;
1412 */
1413 unsigned int dst_size;
1414
1415 spin_lock_irqsave(&dev->irqlock, flags);
1416
1417 if (list_empty(&ctx->src_queue)) {
1418 mfc_debug(2, "no src buffers.\n");
1419 spin_unlock_irqrestore(&dev->irqlock, flags);
1420 return -EAGAIN;
1421 }
1422
1423 if (list_empty(&ctx->dst_queue)) {
1424 mfc_debug(2, "no dst buffers.\n");
1425 spin_unlock_irqrestore(&dev->irqlock, flags);
1426 return -EAGAIN;
1427 }
1428
1429 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1430 src_mb->flags |= MFC_BUF_FLAG_USED;
1431 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
1432 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
1433
1434 mfc_debug(2, "enc src y addr: 0x%08lx", src_y_addr);
1435 mfc_debug(2, "enc src c addr: 0x%08lx", src_c_addr);
1436
1437 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1438
1439 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1440 dst_mb->flags |= MFC_BUF_FLAG_USED;
1441 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1442 dst_size = vb2_plane_size(dst_mb->b, 0);
1443
1444 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1445
1446 spin_unlock_irqrestore(&dev->irqlock, flags);
1447
1448 dev->curr_ctx = ctx->num;
1449 s5p_mfc_clean_ctx_int_flags(ctx);
1450 s5p_mfc_encode_one_frame_v6(ctx);
1451
1452 return 0;
1453 }
1454
1455 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1456 {
1457 struct s5p_mfc_dev *dev = ctx->dev;
1458 unsigned long flags;
1459 struct s5p_mfc_buf *temp_vb;
1460
1461 /* Initializing decoding - parsing header */
1462 spin_lock_irqsave(&dev->irqlock, flags);
1463 mfc_debug(2, "Preparing to init decoding.\n");
1464 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1465 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1466 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1467 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0,
1468 temp_vb->b->v4l2_planes[0].bytesused);
1469 spin_unlock_irqrestore(&dev->irqlock, flags);
1470 dev->curr_ctx = ctx->num;
1471 s5p_mfc_clean_ctx_int_flags(ctx);
1472 s5p_mfc_init_decode_v6(ctx);
1473 }
1474
1475 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1476 {
1477 struct s5p_mfc_dev *dev = ctx->dev;
1478 unsigned long flags;
1479 struct s5p_mfc_buf *dst_mb;
1480 unsigned long dst_addr;
1481 unsigned int dst_size;
1482
1483 spin_lock_irqsave(&dev->irqlock, flags);
1484
1485 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1486 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1487 dst_size = vb2_plane_size(dst_mb->b, 0);
1488 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1489 spin_unlock_irqrestore(&dev->irqlock, flags);
1490 dev->curr_ctx = ctx->num;
1491 s5p_mfc_clean_ctx_int_flags(ctx);
1492 s5p_mfc_init_encode_v6(ctx);
1493 }
1494
1495 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1496 {
1497 struct s5p_mfc_dev *dev = ctx->dev;
1498 int ret;
1499 /* Header was parsed now start processing
1500 * First set the output frame buffers
1501 * s5p_mfc_alloc_dec_buffers(ctx); */
1502
1503 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1504 mfc_err("It seems that not all destionation buffers were\n"
1505 "mmaped.MFC requires that all destination are mmaped\n"
1506 "before starting processing.\n");
1507 return -EAGAIN;
1508 }
1509
1510 dev->curr_ctx = ctx->num;
1511 s5p_mfc_clean_ctx_int_flags(ctx);
1512 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1513 if (ret) {
1514 mfc_err("Failed to alloc frame mem.\n");
1515 ctx->state = MFCINST_ERROR;
1516 }
1517 return ret;
1518 }
1519
1520 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1521 {
1522 struct s5p_mfc_dev *dev = ctx->dev;
1523 int ret;
1524
1525 ret = s5p_mfc_alloc_codec_buffers_v6(ctx);
1526 if (ret) {
1527 mfc_err("Failed to allocate encoding buffers.\n");
1528 return -ENOMEM;
1529 }
1530
1531 /* Header was generated now starting processing
1532 * First set the reference frame buffers
1533 */
1534 if (ctx->capture_state != QUEUE_BUFS_REQUESTED) {
1535 mfc_err("It seems that destionation buffers were not\n"
1536 "requested.MFC requires that header should be generated\n"
1537 "before allocating codec buffer.\n");
1538 return -EAGAIN;
1539 }
1540
1541 dev->curr_ctx = ctx->num;
1542 s5p_mfc_clean_ctx_int_flags(ctx);
1543 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1544 if (ret) {
1545 mfc_err("Failed to alloc frame mem.\n");
1546 ctx->state = MFCINST_ERROR;
1547 }
1548 return ret;
1549 }
1550
1551 /* Try running an operation on hardware */
1552 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1553 {
1554 struct s5p_mfc_ctx *ctx;
1555 int new_ctx;
1556 unsigned int ret = 0;
1557
1558 mfc_debug(1, "Try run dev: %p\n", dev);
1559
1560 /* Check whether hardware is not running */
1561 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1562 /* This is perfectly ok, the scheduled ctx should wait */
1563 mfc_debug(1, "Couldn't lock HW.\n");
1564 return;
1565 }
1566
1567 /* Choose the context to run */
1568 new_ctx = s5p_mfc_get_new_ctx(dev);
1569 if (new_ctx < 0) {
1570 /* No contexts to run */
1571 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1572 mfc_err("Failed to unlock hardware.\n");
1573 return;
1574 }
1575
1576 mfc_debug(1, "No ctx is scheduled to be run.\n");
1577 return;
1578 }
1579
1580 mfc_debug(1, "New context: %d\n", new_ctx);
1581 ctx = dev->ctx[new_ctx];
1582 mfc_debug(1, "Seting new context to %p\n", ctx);
1583 /* Got context to run in ctx */
1584 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1585 ctx->dst_queue_cnt, ctx->dpb_count, ctx->src_queue_cnt);
1586 mfc_debug(1, "ctx->state=%d\n", ctx->state);
1587 /* Last frame has already been sent to MFC
1588 * Now obtaining frames from MFC buffer */
1589
1590 s5p_mfc_clock_on();
1591 if (ctx->type == MFCINST_DECODER) {
1592 switch (ctx->state) {
1593 case MFCINST_FINISHING:
1594 s5p_mfc_run_dec_last_frames(ctx);
1595 break;
1596 case MFCINST_RUNNING:
1597 ret = s5p_mfc_run_dec_frame(ctx);
1598 break;
1599 case MFCINST_INIT:
1600 s5p_mfc_clean_ctx_int_flags(ctx);
1601 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1602 ctx);
1603 break;
1604 case MFCINST_RETURN_INST:
1605 s5p_mfc_clean_ctx_int_flags(ctx);
1606 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1607 ctx);
1608 break;
1609 case MFCINST_GOT_INST:
1610 s5p_mfc_run_init_dec(ctx);
1611 break;
1612 case MFCINST_HEAD_PARSED:
1613 ret = s5p_mfc_run_init_dec_buffers(ctx);
1614 break;
1615 case MFCINST_FLUSH:
1616 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1617 break;
1618 case MFCINST_RES_CHANGE_INIT:
1619 s5p_mfc_run_dec_last_frames(ctx);
1620 break;
1621 case MFCINST_RES_CHANGE_FLUSH:
1622 s5p_mfc_run_dec_last_frames(ctx);
1623 break;
1624 case MFCINST_RES_CHANGE_END:
1625 mfc_debug(2, "Finished remaining frames after resolution change.\n");
1626 ctx->capture_state = QUEUE_FREE;
1627 mfc_debug(2, "Will re-init the codec`.\n");
1628 s5p_mfc_run_init_dec(ctx);
1629 break;
1630 default:
1631 ret = -EAGAIN;
1632 }
1633 } else if (ctx->type == MFCINST_ENCODER) {
1634 switch (ctx->state) {
1635 case MFCINST_FINISHING:
1636 case MFCINST_RUNNING:
1637 ret = s5p_mfc_run_enc_frame(ctx);
1638 break;
1639 case MFCINST_INIT:
1640 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1641 ctx);
1642 break;
1643 case MFCINST_RETURN_INST:
1644 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1645 ctx);
1646 break;
1647 case MFCINST_GOT_INST:
1648 s5p_mfc_run_init_enc(ctx);
1649 break;
1650 case MFCINST_HEAD_PARSED: /* Only for MFC6.x */
1651 ret = s5p_mfc_run_init_enc_buffers(ctx);
1652 break;
1653 default:
1654 ret = -EAGAIN;
1655 }
1656 } else {
1657 mfc_err("invalid context type: %d\n", ctx->type);
1658 ret = -EAGAIN;
1659 }
1660
1661 if (ret) {
1662 /* Free hardware lock */
1663 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1664 mfc_err("Failed to unlock hardware.\n");
1665
1666 /* This is in deed imporant, as no operation has been
1667 * scheduled, reduce the clock count as no one will
1668 * ever do this, because no interrupt related to this try_run
1669 * will ever come from hardware. */
1670 s5p_mfc_clock_off();
1671 }
1672 }
1673
1674
1675 static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1676 {
1677 struct s5p_mfc_buf *b;
1678 int i;
1679
1680 while (!list_empty(lh)) {
1681 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1682 for (i = 0; i < b->b->num_planes; i++)
1683 vb2_set_plane_payload(b->b, i, 0);
1684 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1685 list_del(&b->list);
1686 }
1687 }
1688
1689 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1690 {
1691 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
1692 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT_V6);
1693 }
1694
1695 static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1696 unsigned int ofs)
1697 {
1698 struct s5p_mfc_dev *dev = ctx->dev;
1699
1700 s5p_mfc_clock_on();
1701 WRITEL(data, ofs);
1702 s5p_mfc_clock_off();
1703 }
1704
1705 static unsigned int
1706 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1707 {
1708 struct s5p_mfc_dev *dev = ctx->dev;
1709 int ret;
1710
1711 s5p_mfc_clock_on();
1712 ret = READL(ofs);
1713 s5p_mfc_clock_off();
1714
1715 return ret;
1716 }
1717
1718 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1719 {
1720 return mfc_read(dev, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
1721 }
1722
1723 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1724 {
1725 return mfc_read(dev, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
1726 }
1727
1728 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1729 {
1730 return mfc_read(dev, S5P_FIMV_D_DISPLAY_STATUS_V6);
1731 }
1732
1733 static int s5p_mfc_get_decoded_status_v6(struct s5p_mfc_dev *dev)
1734 {
1735 return mfc_read(dev, S5P_FIMV_D_DECODED_STATUS_V6);
1736 }
1737
1738 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1739 {
1740 return mfc_read(dev, S5P_FIMV_D_DECODED_FRAME_TYPE_V6) &
1741 S5P_FIMV_DECODE_FRAME_MASK_V6;
1742 }
1743
1744 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1745 {
1746 return mfc_read(ctx->dev, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6) &
1747 S5P_FIMV_DECODE_FRAME_MASK_V6;
1748 }
1749
1750 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1751 {
1752 return mfc_read(dev, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
1753 }
1754
1755 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1756 {
1757 return mfc_read(dev, S5P_FIMV_RISC2HOST_CMD_V6) &
1758 S5P_FIMV_RISC2HOST_CMD_MASK;
1759 }
1760
1761 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1762 {
1763 return mfc_read(dev, S5P_FIMV_ERROR_CODE_V6);
1764 }
1765
1766 static int s5p_mfc_err_dec_v6(unsigned int err)
1767 {
1768 return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1769 }
1770
1771 static int s5p_mfc_err_dspl_v6(unsigned int err)
1772 {
1773 return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1774 }
1775
1776 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1777 {
1778 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
1779 }
1780
1781 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1782 {
1783 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
1784 }
1785
1786 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1787 {
1788 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_DPB_V6);
1789 }
1790
1791 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1792 {
1793 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_MV_V6);
1794 }
1795
1796 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1797 {
1798 return mfc_read(dev, S5P_FIMV_RET_INSTANCE_ID_V6);
1799 }
1800
1801 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1802 {
1803 return mfc_read(dev, S5P_FIMV_E_NUM_DPB_V6);
1804 }
1805
1806 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1807 {
1808 return mfc_read(dev, S5P_FIMV_E_STREAM_SIZE_V6);
1809 }
1810
1811 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1812 {
1813 return mfc_read(dev, S5P_FIMV_E_SLICE_TYPE_V6);
1814 }
1815
1816 static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
1817 {
1818 return mfc_read(dev, S5P_FIMV_E_PICTURE_COUNT_V6);
1819 }
1820
1821 static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
1822 {
1823 return mfc_read(ctx->dev, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
1824 }
1825
1826 static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
1827 {
1828 return mfc_read(dev, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
1829 }
1830
1831 static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
1832 {
1833 return mfc_read(dev, S5P_FIMV_D_MVC_VIEW_ID_V6);
1834 }
1835
1836 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
1837 {
1838 return s5p_mfc_read_info_v6(ctx, PIC_TIME_TOP_V6);
1839 }
1840
1841 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
1842 {
1843 return s5p_mfc_read_info_v6(ctx, PIC_TIME_BOT_V6);
1844 }
1845
1846 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
1847 {
1848 return s5p_mfc_read_info_v6(ctx, CROP_INFO_H_V6);
1849 }
1850
1851 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
1852 {
1853 return s5p_mfc_read_info_v6(ctx, CROP_INFO_V_V6);
1854 }
1855
1856 /* Initialize opr function pointers for MFC v6 */
1857 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
1858 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
1859 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
1860 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
1861 .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
1862 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
1863 .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
1864 .alloc_dev_context_buffer =
1865 s5p_mfc_alloc_dev_context_buffer_v6,
1866 .release_dev_context_buffer =
1867 s5p_mfc_release_dev_context_buffer_v6,
1868 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
1869 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
1870 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
1871 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
1872 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
1873 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
1874 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
1875 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
1876 .init_decode = s5p_mfc_init_decode_v6,
1877 .init_encode = s5p_mfc_init_encode_v6,
1878 .encode_one_frame = s5p_mfc_encode_one_frame_v6,
1879 .try_run = s5p_mfc_try_run_v6,
1880 .cleanup_queue = s5p_mfc_cleanup_queue_v6,
1881 .clear_int_flags = s5p_mfc_clear_int_flags_v6,
1882 .write_info = s5p_mfc_write_info_v6,
1883 .read_info = s5p_mfc_read_info_v6,
1884 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
1885 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
1886 .get_dspl_status = s5p_mfc_get_dspl_status_v6,
1887 .get_dec_status = s5p_mfc_get_dec_status_v6,
1888 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
1889 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
1890 .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
1891 .get_int_reason = s5p_mfc_get_int_reason_v6,
1892 .get_int_err = s5p_mfc_get_int_err_v6,
1893 .err_dec = s5p_mfc_err_dec_v6,
1894 .err_dspl = s5p_mfc_err_dspl_v6,
1895 .get_img_width = s5p_mfc_get_img_width_v6,
1896 .get_img_height = s5p_mfc_get_img_height_v6,
1897 .get_dpb_count = s5p_mfc_get_dpb_count_v6,
1898 .get_mv_count = s5p_mfc_get_mv_count_v6,
1899 .get_inst_no = s5p_mfc_get_inst_no_v6,
1900 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
1901 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
1902 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
1903 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
1904 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
1905 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
1906 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
1907 .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
1908 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
1909 .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
1910 .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
1911 };
1912
1913 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
1914 {
1915 return &s5p_mfc_ops_v6;
1916 }
kernel source for telekom puls (alcatel/mediatek)