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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
38 #include <asm/apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
43 #include <asm/gart.h>
44 #include <asm/dma.h>
45
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
49 #include "pci.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 LIST_HEAD(ioapic_map);
76 LIST_HEAD(hpet_map);
77
78 /*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82 static struct protection_domain *pt_domain;
83
84 static struct iommu_ops amd_iommu_ops;
85
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
87 int amd_iommu_max_glx_val = -1;
88
89 static struct dma_map_ops amd_iommu_dma_ops;
90
91 /*
92 * general struct to manage commands send to an IOMMU
93 */
94 struct iommu_cmd {
95 u32 data[4];
96 };
97
98 struct kmem_cache *amd_iommu_irq_cache;
99
100 static void update_domain(struct protection_domain *domain);
101 static int __init alloc_passthrough_domain(void);
102
103 /****************************************************************************
104 *
105 * Helper functions
106 *
107 ****************************************************************************/
108
109 static struct iommu_dev_data *alloc_dev_data(u16 devid)
110 {
111 struct iommu_dev_data *dev_data;
112 unsigned long flags;
113
114 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
115 if (!dev_data)
116 return NULL;
117
118 dev_data->devid = devid;
119 atomic_set(&dev_data->bind, 0);
120
121 spin_lock_irqsave(&dev_data_list_lock, flags);
122 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
123 spin_unlock_irqrestore(&dev_data_list_lock, flags);
124
125 return dev_data;
126 }
127
128 static void free_dev_data(struct iommu_dev_data *dev_data)
129 {
130 unsigned long flags;
131
132 spin_lock_irqsave(&dev_data_list_lock, flags);
133 list_del(&dev_data->dev_data_list);
134 spin_unlock_irqrestore(&dev_data_list_lock, flags);
135
136 if (dev_data->group)
137 iommu_group_put(dev_data->group);
138
139 kfree(dev_data);
140 }
141
142 static struct iommu_dev_data *search_dev_data(u16 devid)
143 {
144 struct iommu_dev_data *dev_data;
145 unsigned long flags;
146
147 spin_lock_irqsave(&dev_data_list_lock, flags);
148 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
149 if (dev_data->devid == devid)
150 goto out_unlock;
151 }
152
153 dev_data = NULL;
154
155 out_unlock:
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 return dev_data;
159 }
160
161 static struct iommu_dev_data *find_dev_data(u16 devid)
162 {
163 struct iommu_dev_data *dev_data;
164
165 dev_data = search_dev_data(devid);
166
167 if (dev_data == NULL)
168 dev_data = alloc_dev_data(devid);
169
170 return dev_data;
171 }
172
173 static inline u16 get_device_id(struct device *dev)
174 {
175 struct pci_dev *pdev = to_pci_dev(dev);
176
177 return PCI_DEVID(pdev->bus->number, pdev->devfn);
178 }
179
180 static struct iommu_dev_data *get_dev_data(struct device *dev)
181 {
182 return dev->archdata.iommu;
183 }
184
185 static bool pci_iommuv2_capable(struct pci_dev *pdev)
186 {
187 static const int caps[] = {
188 PCI_EXT_CAP_ID_ATS,
189 PCI_EXT_CAP_ID_PRI,
190 PCI_EXT_CAP_ID_PASID,
191 };
192 int i, pos;
193
194 for (i = 0; i < 3; ++i) {
195 pos = pci_find_ext_capability(pdev, caps[i]);
196 if (pos == 0)
197 return false;
198 }
199
200 return true;
201 }
202
203 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
204 {
205 struct iommu_dev_data *dev_data;
206
207 dev_data = get_dev_data(&pdev->dev);
208
209 return dev_data->errata & (1 << erratum) ? true : false;
210 }
211
212 /*
213 * In this function the list of preallocated protection domains is traversed to
214 * find the domain for a specific device
215 */
216 static struct dma_ops_domain *find_protection_domain(u16 devid)
217 {
218 struct dma_ops_domain *entry, *ret = NULL;
219 unsigned long flags;
220 u16 alias = amd_iommu_alias_table[devid];
221
222 if (list_empty(&iommu_pd_list))
223 return NULL;
224
225 spin_lock_irqsave(&iommu_pd_list_lock, flags);
226
227 list_for_each_entry(entry, &iommu_pd_list, list) {
228 if (entry->target_dev == devid ||
229 entry->target_dev == alias) {
230 ret = entry;
231 break;
232 }
233 }
234
235 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
236
237 return ret;
238 }
239
240 /*
241 * This function checks if the driver got a valid device from the caller to
242 * avoid dereferencing invalid pointers.
243 */
244 static bool check_device(struct device *dev)
245 {
246 u16 devid;
247
248 if (!dev || !dev->dma_mask)
249 return false;
250
251 /* No device or no PCI device */
252 if (dev->bus != &pci_bus_type)
253 return false;
254
255 devid = get_device_id(dev);
256
257 /* Out of our scope? */
258 if (devid > amd_iommu_last_bdf)
259 return false;
260
261 if (amd_iommu_rlookup_table[devid] == NULL)
262 return false;
263
264 return true;
265 }
266
267 static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
268 {
269 while (!bus->self) {
270 if (!pci_is_root_bus(bus))
271 bus = bus->parent;
272 else
273 return ERR_PTR(-ENODEV);
274 }
275
276 return bus;
277 }
278
279 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
280
281 static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
282 {
283 struct pci_dev *dma_pdev = pdev;
284
285 /* Account for quirked devices */
286 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
287
288 /*
289 * If it's a multifunction device that does not support our
290 * required ACS flags, add to the same group as function 0.
291 */
292 if (dma_pdev->multifunction &&
293 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
294 swap_pci_ref(&dma_pdev,
295 pci_get_slot(dma_pdev->bus,
296 PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
297 0)));
298
299 /*
300 * Devices on the root bus go through the iommu. If that's not us,
301 * find the next upstream device and test ACS up to the root bus.
302 * Finding the next device may require skipping virtual buses.
303 */
304 while (!pci_is_root_bus(dma_pdev->bus)) {
305 struct pci_bus *bus = find_hosted_bus(dma_pdev->bus);
306 if (IS_ERR(bus))
307 break;
308
309 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
310 break;
311
312 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
313 }
314
315 return dma_pdev;
316 }
317
318 static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev)
319 {
320 struct iommu_group *group = iommu_group_get(&pdev->dev);
321 int ret;
322
323 if (!group) {
324 group = iommu_group_alloc();
325 if (IS_ERR(group))
326 return PTR_ERR(group);
327
328 WARN_ON(&pdev->dev != dev);
329 }
330
331 ret = iommu_group_add_device(group, dev);
332 iommu_group_put(group);
333 return ret;
334 }
335
336 static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data,
337 struct device *dev)
338 {
339 if (!dev_data->group) {
340 struct iommu_group *group = iommu_group_alloc();
341 if (IS_ERR(group))
342 return PTR_ERR(group);
343
344 dev_data->group = group;
345 }
346
347 return iommu_group_add_device(dev_data->group, dev);
348 }
349
350 static int init_iommu_group(struct device *dev)
351 {
352 struct iommu_dev_data *dev_data;
353 struct iommu_group *group;
354 struct pci_dev *dma_pdev;
355 int ret;
356
357 group = iommu_group_get(dev);
358 if (group) {
359 iommu_group_put(group);
360 return 0;
361 }
362
363 dev_data = find_dev_data(get_device_id(dev));
364 if (!dev_data)
365 return -ENOMEM;
366
367 if (dev_data->alias_data) {
368 u16 alias;
369 struct pci_bus *bus;
370
371 if (dev_data->alias_data->group)
372 goto use_group;
373
374 /*
375 * If the alias device exists, it's effectively just a first
376 * level quirk for finding the DMA source.
377 */
378 alias = amd_iommu_alias_table[dev_data->devid];
379 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
380 if (dma_pdev) {
381 dma_pdev = get_isolation_root(dma_pdev);
382 goto use_pdev;
383 }
384
385 /*
386 * If the alias is virtual, try to find a parent device
387 * and test whether the IOMMU group is actualy rooted above
388 * the alias. Be careful to also test the parent device if
389 * we think the alias is the root of the group.
390 */
391 bus = pci_find_bus(0, alias >> 8);
392 if (!bus)
393 goto use_group;
394
395 bus = find_hosted_bus(bus);
396 if (IS_ERR(bus) || !bus->self)
397 goto use_group;
398
399 dma_pdev = get_isolation_root(pci_dev_get(bus->self));
400 if (dma_pdev != bus->self || (dma_pdev->multifunction &&
401 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)))
402 goto use_pdev;
403
404 pci_dev_put(dma_pdev);
405 goto use_group;
406 }
407
408 dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev)));
409 use_pdev:
410 ret = use_pdev_iommu_group(dma_pdev, dev);
411 pci_dev_put(dma_pdev);
412 return ret;
413 use_group:
414 return use_dev_data_iommu_group(dev_data->alias_data, dev);
415 }
416
417 static int iommu_init_device(struct device *dev)
418 {
419 struct pci_dev *pdev = to_pci_dev(dev);
420 struct iommu_dev_data *dev_data;
421 u16 alias;
422 int ret;
423
424 if (dev->archdata.iommu)
425 return 0;
426
427 dev_data = find_dev_data(get_device_id(dev));
428 if (!dev_data)
429 return -ENOMEM;
430
431 alias = amd_iommu_alias_table[dev_data->devid];
432 if (alias != dev_data->devid) {
433 struct iommu_dev_data *alias_data;
434
435 alias_data = find_dev_data(alias);
436 if (alias_data == NULL) {
437 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
438 dev_name(dev));
439 free_dev_data(dev_data);
440 return -ENOTSUPP;
441 }
442 dev_data->alias_data = alias_data;
443 }
444
445 ret = init_iommu_group(dev);
446 if (ret)
447 return ret;
448
449 if (pci_iommuv2_capable(pdev)) {
450 struct amd_iommu *iommu;
451
452 iommu = amd_iommu_rlookup_table[dev_data->devid];
453 dev_data->iommu_v2 = iommu->is_iommu_v2;
454 }
455
456 dev->archdata.iommu = dev_data;
457
458 return 0;
459 }
460
461 static void iommu_ignore_device(struct device *dev)
462 {
463 u16 devid, alias;
464
465 devid = get_device_id(dev);
466 alias = amd_iommu_alias_table[devid];
467
468 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
469 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
470
471 amd_iommu_rlookup_table[devid] = NULL;
472 amd_iommu_rlookup_table[alias] = NULL;
473 }
474
475 static void iommu_uninit_device(struct device *dev)
476 {
477 iommu_group_remove_device(dev);
478
479 /*
480 * Nothing to do here - we keep dev_data around for unplugged devices
481 * and reuse it when the device is re-plugged - not doing so would
482 * introduce a ton of races.
483 */
484 }
485
486 void __init amd_iommu_uninit_devices(void)
487 {
488 struct iommu_dev_data *dev_data, *n;
489 struct pci_dev *pdev = NULL;
490
491 for_each_pci_dev(pdev) {
492
493 if (!check_device(&pdev->dev))
494 continue;
495
496 iommu_uninit_device(&pdev->dev);
497 }
498
499 /* Free all of our dev_data structures */
500 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
501 free_dev_data(dev_data);
502 }
503
504 int __init amd_iommu_init_devices(void)
505 {
506 struct pci_dev *pdev = NULL;
507 int ret = 0;
508
509 for_each_pci_dev(pdev) {
510
511 if (!check_device(&pdev->dev))
512 continue;
513
514 ret = iommu_init_device(&pdev->dev);
515 if (ret == -ENOTSUPP)
516 iommu_ignore_device(&pdev->dev);
517 else if (ret)
518 goto out_free;
519 }
520
521 return 0;
522
523 out_free:
524
525 amd_iommu_uninit_devices();
526
527 return ret;
528 }
529 #ifdef CONFIG_AMD_IOMMU_STATS
530
531 /*
532 * Initialization code for statistics collection
533 */
534
535 DECLARE_STATS_COUNTER(compl_wait);
536 DECLARE_STATS_COUNTER(cnt_map_single);
537 DECLARE_STATS_COUNTER(cnt_unmap_single);
538 DECLARE_STATS_COUNTER(cnt_map_sg);
539 DECLARE_STATS_COUNTER(cnt_unmap_sg);
540 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
541 DECLARE_STATS_COUNTER(cnt_free_coherent);
542 DECLARE_STATS_COUNTER(cross_page);
543 DECLARE_STATS_COUNTER(domain_flush_single);
544 DECLARE_STATS_COUNTER(domain_flush_all);
545 DECLARE_STATS_COUNTER(alloced_io_mem);
546 DECLARE_STATS_COUNTER(total_map_requests);
547 DECLARE_STATS_COUNTER(complete_ppr);
548 DECLARE_STATS_COUNTER(invalidate_iotlb);
549 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
550 DECLARE_STATS_COUNTER(pri_requests);
551
552 static struct dentry *stats_dir;
553 static struct dentry *de_fflush;
554
555 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
556 {
557 if (stats_dir == NULL)
558 return;
559
560 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
561 &cnt->value);
562 }
563
564 static void amd_iommu_stats_init(void)
565 {
566 stats_dir = debugfs_create_dir("amd-iommu", NULL);
567 if (stats_dir == NULL)
568 return;
569
570 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
571 &amd_iommu_unmap_flush);
572
573 amd_iommu_stats_add(&compl_wait);
574 amd_iommu_stats_add(&cnt_map_single);
575 amd_iommu_stats_add(&cnt_unmap_single);
576 amd_iommu_stats_add(&cnt_map_sg);
577 amd_iommu_stats_add(&cnt_unmap_sg);
578 amd_iommu_stats_add(&cnt_alloc_coherent);
579 amd_iommu_stats_add(&cnt_free_coherent);
580 amd_iommu_stats_add(&cross_page);
581 amd_iommu_stats_add(&domain_flush_single);
582 amd_iommu_stats_add(&domain_flush_all);
583 amd_iommu_stats_add(&alloced_io_mem);
584 amd_iommu_stats_add(&total_map_requests);
585 amd_iommu_stats_add(&complete_ppr);
586 amd_iommu_stats_add(&invalidate_iotlb);
587 amd_iommu_stats_add(&invalidate_iotlb_all);
588 amd_iommu_stats_add(&pri_requests);
589 }
590
591 #endif
592
593 /****************************************************************************
594 *
595 * Interrupt handling functions
596 *
597 ****************************************************************************/
598
599 static void dump_dte_entry(u16 devid)
600 {
601 int i;
602
603 for (i = 0; i < 4; ++i)
604 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
605 amd_iommu_dev_table[devid].data[i]);
606 }
607
608 static void dump_command(unsigned long phys_addr)
609 {
610 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
611 int i;
612
613 for (i = 0; i < 4; ++i)
614 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
615 }
616
617 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
618 {
619 int type, devid, domid, flags;
620 volatile u32 *event = __evt;
621 int count = 0;
622 u64 address;
623
624 retry:
625 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
626 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
627 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
628 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
629 address = (u64)(((u64)event[3]) << 32) | event[2];
630
631 if (type == 0) {
632 /* Did we hit the erratum? */
633 if (++count == LOOP_TIMEOUT) {
634 pr_err("AMD-Vi: No event written to event log\n");
635 return;
636 }
637 udelay(1);
638 goto retry;
639 }
640
641 printk(KERN_ERR "AMD-Vi: Event logged [");
642
643 switch (type) {
644 case EVENT_TYPE_ILL_DEV:
645 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
646 "address=0x%016llx flags=0x%04x]\n",
647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
648 address, flags);
649 dump_dte_entry(devid);
650 break;
651 case EVENT_TYPE_IO_FAULT:
652 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
653 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
654 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
655 domid, address, flags);
656 break;
657 case EVENT_TYPE_DEV_TAB_ERR:
658 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
659 "address=0x%016llx flags=0x%04x]\n",
660 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
661 address, flags);
662 break;
663 case EVENT_TYPE_PAGE_TAB_ERR:
664 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
665 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
666 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
667 domid, address, flags);
668 break;
669 case EVENT_TYPE_ILL_CMD:
670 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
671 dump_command(address);
672 break;
673 case EVENT_TYPE_CMD_HARD_ERR:
674 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
675 "flags=0x%04x]\n", address, flags);
676 break;
677 case EVENT_TYPE_IOTLB_INV_TO:
678 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
679 "address=0x%016llx]\n",
680 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
681 address);
682 break;
683 case EVENT_TYPE_INV_DEV_REQ:
684 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
685 "address=0x%016llx flags=0x%04x]\n",
686 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
687 address, flags);
688 break;
689 default:
690 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
691 }
692
693 memset(__evt, 0, 4 * sizeof(u32));
694 }
695
696 static void iommu_poll_events(struct amd_iommu *iommu)
697 {
698 u32 head, tail;
699
700 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
701 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
702
703 while (head != tail) {
704 iommu_print_event(iommu, iommu->evt_buf + head);
705 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
706 }
707
708 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
709 }
710
711 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
712 {
713 struct amd_iommu_fault fault;
714
715 INC_STATS_COUNTER(pri_requests);
716
717 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
718 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
719 return;
720 }
721
722 fault.address = raw[1];
723 fault.pasid = PPR_PASID(raw[0]);
724 fault.device_id = PPR_DEVID(raw[0]);
725 fault.tag = PPR_TAG(raw[0]);
726 fault.flags = PPR_FLAGS(raw[0]);
727
728 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
729 }
730
731 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
732 {
733 u32 head, tail;
734
735 if (iommu->ppr_log == NULL)
736 return;
737
738 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
739 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
740
741 while (head != tail) {
742 volatile u64 *raw;
743 u64 entry[2];
744 int i;
745
746 raw = (u64 *)(iommu->ppr_log + head);
747
748 /*
749 * Hardware bug: Interrupt may arrive before the entry is
750 * written to memory. If this happens we need to wait for the
751 * entry to arrive.
752 */
753 for (i = 0; i < LOOP_TIMEOUT; ++i) {
754 if (PPR_REQ_TYPE(raw[0]) != 0)
755 break;
756 udelay(1);
757 }
758
759 /* Avoid memcpy function-call overhead */
760 entry[0] = raw[0];
761 entry[1] = raw[1];
762
763 /*
764 * To detect the hardware bug we need to clear the entry
765 * back to zero.
766 */
767 raw[0] = raw[1] = 0UL;
768
769 /* Update head pointer of hardware ring-buffer */
770 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
771 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
772
773 /* Handle PPR entry */
774 iommu_handle_ppr_entry(iommu, entry);
775
776 /* Refresh ring-buffer information */
777 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
778 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
779 }
780 }
781
782 irqreturn_t amd_iommu_int_thread(int irq, void *data)
783 {
784 struct amd_iommu *iommu = (struct amd_iommu *) data;
785 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
786
787 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
788 /* Enable EVT and PPR interrupts again */
789 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
790 iommu->mmio_base + MMIO_STATUS_OFFSET);
791
792 if (status & MMIO_STATUS_EVT_INT_MASK) {
793 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
794 iommu_poll_events(iommu);
795 }
796
797 if (status & MMIO_STATUS_PPR_INT_MASK) {
798 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
799 iommu_poll_ppr_log(iommu);
800 }
801
802 /*
803 * Hardware bug: ERBT1312
804 * When re-enabling interrupt (by writing 1
805 * to clear the bit), the hardware might also try to set
806 * the interrupt bit in the event status register.
807 * In this scenario, the bit will be set, and disable
808 * subsequent interrupts.
809 *
810 * Workaround: The IOMMU driver should read back the
811 * status register and check if the interrupt bits are cleared.
812 * If not, driver will need to go through the interrupt handler
813 * again and re-clear the bits
814 */
815 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
816 }
817 return IRQ_HANDLED;
818 }
819
820 irqreturn_t amd_iommu_int_handler(int irq, void *data)
821 {
822 return IRQ_WAKE_THREAD;
823 }
824
825 /****************************************************************************
826 *
827 * IOMMU command queuing functions
828 *
829 ****************************************************************************/
830
831 static int wait_on_sem(volatile u64 *sem)
832 {
833 int i = 0;
834
835 while (*sem == 0 && i < LOOP_TIMEOUT) {
836 udelay(1);
837 i += 1;
838 }
839
840 if (i == LOOP_TIMEOUT) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
842 return -EIO;
843 }
844
845 return 0;
846 }
847
848 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
849 struct iommu_cmd *cmd,
850 u32 tail)
851 {
852 u8 *target;
853
854 target = iommu->cmd_buf + tail;
855 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
856
857 /* Copy command to buffer */
858 memcpy(target, cmd, sizeof(*cmd));
859
860 /* Tell the IOMMU about it */
861 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
862 }
863
864 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
865 {
866 WARN_ON(address & 0x7ULL);
867
868 memset(cmd, 0, sizeof(*cmd));
869 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
870 cmd->data[1] = upper_32_bits(__pa(address));
871 cmd->data[2] = 1;
872 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
873 }
874
875 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
876 {
877 memset(cmd, 0, sizeof(*cmd));
878 cmd->data[0] = devid;
879 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
880 }
881
882 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
883 size_t size, u16 domid, int pde)
884 {
885 u64 pages;
886 int s;
887
888 pages = iommu_num_pages(address, size, PAGE_SIZE);
889 s = 0;
890
891 if (pages > 1) {
892 /*
893 * If we have to flush more than one page, flush all
894 * TLB entries for this domain
895 */
896 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
897 s = 1;
898 }
899
900 address &= PAGE_MASK;
901
902 memset(cmd, 0, sizeof(*cmd));
903 cmd->data[1] |= domid;
904 cmd->data[2] = lower_32_bits(address);
905 cmd->data[3] = upper_32_bits(address);
906 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
907 if (s) /* size bit - we flush more than one 4kb page */
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
909 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
910 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
911 }
912
913 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
914 u64 address, size_t size)
915 {
916 u64 pages;
917 int s;
918
919 pages = iommu_num_pages(address, size, PAGE_SIZE);
920 s = 0;
921
922 if (pages > 1) {
923 /*
924 * If we have to flush more than one page, flush all
925 * TLB entries for this domain
926 */
927 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
928 s = 1;
929 }
930
931 address &= PAGE_MASK;
932
933 memset(cmd, 0, sizeof(*cmd));
934 cmd->data[0] = devid;
935 cmd->data[0] |= (qdep & 0xff) << 24;
936 cmd->data[1] = devid;
937 cmd->data[2] = lower_32_bits(address);
938 cmd->data[3] = upper_32_bits(address);
939 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
940 if (s)
941 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
942 }
943
944 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
945 u64 address, bool size)
946 {
947 memset(cmd, 0, sizeof(*cmd));
948
949 address &= ~(0xfffULL);
950
951 cmd->data[0] = pasid & PASID_MASK;
952 cmd->data[1] = domid;
953 cmd->data[2] = lower_32_bits(address);
954 cmd->data[3] = upper_32_bits(address);
955 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
956 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
957 if (size)
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
959 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
960 }
961
962 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
963 int qdep, u64 address, bool size)
964 {
965 memset(cmd, 0, sizeof(*cmd));
966
967 address &= ~(0xfffULL);
968
969 cmd->data[0] = devid;
970 cmd->data[0] |= (pasid & 0xff) << 16;
971 cmd->data[0] |= (qdep & 0xff) << 24;
972 cmd->data[1] = devid;
973 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
974 cmd->data[2] = lower_32_bits(address);
975 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
976 cmd->data[3] = upper_32_bits(address);
977 if (size)
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
979 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
980 }
981
982 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
983 int status, int tag, bool gn)
984 {
985 memset(cmd, 0, sizeof(*cmd));
986
987 cmd->data[0] = devid;
988 if (gn) {
989 cmd->data[1] = pasid & PASID_MASK;
990 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
991 }
992 cmd->data[3] = tag & 0x1ff;
993 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
994
995 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
996 }
997
998 static void build_inv_all(struct iommu_cmd *cmd)
999 {
1000 memset(cmd, 0, sizeof(*cmd));
1001 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1002 }
1003
1004 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1005 {
1006 memset(cmd, 0, sizeof(*cmd));
1007 cmd->data[0] = devid;
1008 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1009 }
1010
1011 /*
1012 * Writes the command to the IOMMUs command buffer and informs the
1013 * hardware about the new command.
1014 */
1015 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1016 struct iommu_cmd *cmd,
1017 bool sync)
1018 {
1019 u32 left, tail, head, next_tail;
1020 unsigned long flags;
1021
1022 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
1023
1024 again:
1025 spin_lock_irqsave(&iommu->lock, flags);
1026
1027 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1028 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1029 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
1030 left = (head - next_tail) % iommu->cmd_buf_size;
1031
1032 if (left <= 0x20) {
1033 struct iommu_cmd sync_cmd;
1034 volatile u64 sem = 0;
1035 int ret;
1036
1037 build_completion_wait(&sync_cmd, (u64)&sem);
1038 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1039
1040 spin_unlock_irqrestore(&iommu->lock, flags);
1041
1042 if ((ret = wait_on_sem(&sem)) != 0)
1043 return ret;
1044
1045 goto again;
1046 }
1047
1048 copy_cmd_to_buffer(iommu, cmd, tail);
1049
1050 /* We need to sync now to make sure all commands are processed */
1051 iommu->need_sync = sync;
1052
1053 spin_unlock_irqrestore(&iommu->lock, flags);
1054
1055 return 0;
1056 }
1057
1058 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1059 {
1060 return iommu_queue_command_sync(iommu, cmd, true);
1061 }
1062
1063 /*
1064 * This function queues a completion wait command into the command
1065 * buffer of an IOMMU
1066 */
1067 static int iommu_completion_wait(struct amd_iommu *iommu)
1068 {
1069 struct iommu_cmd cmd;
1070 volatile u64 sem = 0;
1071 int ret;
1072
1073 if (!iommu->need_sync)
1074 return 0;
1075
1076 build_completion_wait(&cmd, (u64)&sem);
1077
1078 ret = iommu_queue_command_sync(iommu, &cmd, false);
1079 if (ret)
1080 return ret;
1081
1082 return wait_on_sem(&sem);
1083 }
1084
1085 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1086 {
1087 struct iommu_cmd cmd;
1088
1089 build_inv_dte(&cmd, devid);
1090
1091 return iommu_queue_command(iommu, &cmd);
1092 }
1093
1094 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1095 {
1096 u32 devid;
1097
1098 for (devid = 0; devid <= 0xffff; ++devid)
1099 iommu_flush_dte(iommu, devid);
1100
1101 iommu_completion_wait(iommu);
1102 }
1103
1104 /*
1105 * This function uses heavy locking and may disable irqs for some time. But
1106 * this is no issue because it is only called during resume.
1107 */
1108 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1109 {
1110 u32 dom_id;
1111
1112 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1113 struct iommu_cmd cmd;
1114 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1115 dom_id, 1);
1116 iommu_queue_command(iommu, &cmd);
1117 }
1118
1119 iommu_completion_wait(iommu);
1120 }
1121
1122 static void iommu_flush_all(struct amd_iommu *iommu)
1123 {
1124 struct iommu_cmd cmd;
1125
1126 build_inv_all(&cmd);
1127
1128 iommu_queue_command(iommu, &cmd);
1129 iommu_completion_wait(iommu);
1130 }
1131
1132 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1133 {
1134 struct iommu_cmd cmd;
1135
1136 build_inv_irt(&cmd, devid);
1137
1138 iommu_queue_command(iommu, &cmd);
1139 }
1140
1141 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1142 {
1143 u32 devid;
1144
1145 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1146 iommu_flush_irt(iommu, devid);
1147
1148 iommu_completion_wait(iommu);
1149 }
1150
1151 void iommu_flush_all_caches(struct amd_iommu *iommu)
1152 {
1153 if (iommu_feature(iommu, FEATURE_IA)) {
1154 iommu_flush_all(iommu);
1155 } else {
1156 iommu_flush_dte_all(iommu);
1157 iommu_flush_irt_all(iommu);
1158 iommu_flush_tlb_all(iommu);
1159 }
1160 }
1161
1162 /*
1163 * Command send function for flushing on-device TLB
1164 */
1165 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1166 u64 address, size_t size)
1167 {
1168 struct amd_iommu *iommu;
1169 struct iommu_cmd cmd;
1170 int qdep;
1171
1172 qdep = dev_data->ats.qdep;
1173 iommu = amd_iommu_rlookup_table[dev_data->devid];
1174
1175 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1176
1177 return iommu_queue_command(iommu, &cmd);
1178 }
1179
1180 /*
1181 * Command send function for invalidating a device table entry
1182 */
1183 static int device_flush_dte(struct iommu_dev_data *dev_data)
1184 {
1185 struct amd_iommu *iommu;
1186 int ret;
1187
1188 iommu = amd_iommu_rlookup_table[dev_data->devid];
1189
1190 ret = iommu_flush_dte(iommu, dev_data->devid);
1191 if (ret)
1192 return ret;
1193
1194 if (dev_data->ats.enabled)
1195 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1196
1197 return ret;
1198 }
1199
1200 /*
1201 * TLB invalidation function which is called from the mapping functions.
1202 * It invalidates a single PTE if the range to flush is within a single
1203 * page. Otherwise it flushes the whole TLB of the IOMMU.
1204 */
1205 static void __domain_flush_pages(struct protection_domain *domain,
1206 u64 address, size_t size, int pde)
1207 {
1208 struct iommu_dev_data *dev_data;
1209 struct iommu_cmd cmd;
1210 int ret = 0, i;
1211
1212 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1213
1214 for (i = 0; i < amd_iommus_present; ++i) {
1215 if (!domain->dev_iommu[i])
1216 continue;
1217
1218 /*
1219 * Devices of this domain are behind this IOMMU
1220 * We need a TLB flush
1221 */
1222 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1223 }
1224
1225 list_for_each_entry(dev_data, &domain->dev_list, list) {
1226
1227 if (!dev_data->ats.enabled)
1228 continue;
1229
1230 ret |= device_flush_iotlb(dev_data, address, size);
1231 }
1232
1233 WARN_ON(ret);
1234 }
1235
1236 static void domain_flush_pages(struct protection_domain *domain,
1237 u64 address, size_t size)
1238 {
1239 __domain_flush_pages(domain, address, size, 0);
1240 }
1241
1242 /* Flush the whole IO/TLB for a given protection domain */
1243 static void domain_flush_tlb(struct protection_domain *domain)
1244 {
1245 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1246 }
1247
1248 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1249 static void domain_flush_tlb_pde(struct protection_domain *domain)
1250 {
1251 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1252 }
1253
1254 static void domain_flush_complete(struct protection_domain *domain)
1255 {
1256 int i;
1257
1258 for (i = 0; i < amd_iommus_present; ++i) {
1259 if (!domain->dev_iommu[i])
1260 continue;
1261
1262 /*
1263 * Devices of this domain are behind this IOMMU
1264 * We need to wait for completion of all commands.
1265 */
1266 iommu_completion_wait(amd_iommus[i]);
1267 }
1268 }
1269
1270
1271 /*
1272 * This function flushes the DTEs for all devices in domain
1273 */
1274 static void domain_flush_devices(struct protection_domain *domain)
1275 {
1276 struct iommu_dev_data *dev_data;
1277
1278 list_for_each_entry(dev_data, &domain->dev_list, list)
1279 device_flush_dte(dev_data);
1280 }
1281
1282 /****************************************************************************
1283 *
1284 * The functions below are used the create the page table mappings for
1285 * unity mapped regions.
1286 *
1287 ****************************************************************************/
1288
1289 /*
1290 * This function is used to add another level to an IO page table. Adding
1291 * another level increases the size of the address space by 9 bits to a size up
1292 * to 64 bits.
1293 */
1294 static bool increase_address_space(struct protection_domain *domain,
1295 gfp_t gfp)
1296 {
1297 u64 *pte;
1298
1299 if (domain->mode == PAGE_MODE_6_LEVEL)
1300 /* address space already 64 bit large */
1301 return false;
1302
1303 pte = (void *)get_zeroed_page(gfp);
1304 if (!pte)
1305 return false;
1306
1307 *pte = PM_LEVEL_PDE(domain->mode,
1308 virt_to_phys(domain->pt_root));
1309 domain->pt_root = pte;
1310 domain->mode += 1;
1311 domain->updated = true;
1312
1313 return true;
1314 }
1315
1316 static u64 *alloc_pte(struct protection_domain *domain,
1317 unsigned long address,
1318 unsigned long page_size,
1319 u64 **pte_page,
1320 gfp_t gfp)
1321 {
1322 int level, end_lvl;
1323 u64 *pte, *page;
1324
1325 BUG_ON(!is_power_of_2(page_size));
1326
1327 while (address > PM_LEVEL_SIZE(domain->mode))
1328 increase_address_space(domain, gfp);
1329
1330 level = domain->mode - 1;
1331 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1332 address = PAGE_SIZE_ALIGN(address, page_size);
1333 end_lvl = PAGE_SIZE_LEVEL(page_size);
1334
1335 while (level > end_lvl) {
1336 if (!IOMMU_PTE_PRESENT(*pte)) {
1337 page = (u64 *)get_zeroed_page(gfp);
1338 if (!page)
1339 return NULL;
1340 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1341 }
1342
1343 /* No level skipping support yet */
1344 if (PM_PTE_LEVEL(*pte) != level)
1345 return NULL;
1346
1347 level -= 1;
1348
1349 pte = IOMMU_PTE_PAGE(*pte);
1350
1351 if (pte_page && level == end_lvl)
1352 *pte_page = pte;
1353
1354 pte = &pte[PM_LEVEL_INDEX(level, address)];
1355 }
1356
1357 return pte;
1358 }
1359
1360 /*
1361 * This function checks if there is a PTE for a given dma address. If
1362 * there is one, it returns the pointer to it.
1363 */
1364 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1365 {
1366 int level;
1367 u64 *pte;
1368
1369 if (address > PM_LEVEL_SIZE(domain->mode))
1370 return NULL;
1371
1372 level = domain->mode - 1;
1373 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1374
1375 while (level > 0) {
1376
1377 /* Not Present */
1378 if (!IOMMU_PTE_PRESENT(*pte))
1379 return NULL;
1380
1381 /* Large PTE */
1382 if (PM_PTE_LEVEL(*pte) == 0x07) {
1383 unsigned long pte_mask, __pte;
1384
1385 /*
1386 * If we have a series of large PTEs, make
1387 * sure to return a pointer to the first one.
1388 */
1389 pte_mask = PTE_PAGE_SIZE(*pte);
1390 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1391 __pte = ((unsigned long)pte) & pte_mask;
1392
1393 return (u64 *)__pte;
1394 }
1395
1396 /* No level skipping support yet */
1397 if (PM_PTE_LEVEL(*pte) != level)
1398 return NULL;
1399
1400 level -= 1;
1401
1402 /* Walk to the next level */
1403 pte = IOMMU_PTE_PAGE(*pte);
1404 pte = &pte[PM_LEVEL_INDEX(level, address)];
1405 }
1406
1407 return pte;
1408 }
1409
1410 /*
1411 * Generic mapping functions. It maps a physical address into a DMA
1412 * address space. It allocates the page table pages if necessary.
1413 * In the future it can be extended to a generic mapping function
1414 * supporting all features of AMD IOMMU page tables like level skipping
1415 * and full 64 bit address spaces.
1416 */
1417 static int iommu_map_page(struct protection_domain *dom,
1418 unsigned long bus_addr,
1419 unsigned long phys_addr,
1420 int prot,
1421 unsigned long page_size)
1422 {
1423 u64 __pte, *pte;
1424 int i, count;
1425
1426 if (!(prot & IOMMU_PROT_MASK))
1427 return -EINVAL;
1428
1429 bus_addr = PAGE_ALIGN(bus_addr);
1430 phys_addr = PAGE_ALIGN(phys_addr);
1431 count = PAGE_SIZE_PTE_COUNT(page_size);
1432 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1433
1434 for (i = 0; i < count; ++i)
1435 if (IOMMU_PTE_PRESENT(pte[i]))
1436 return -EBUSY;
1437
1438 if (page_size > PAGE_SIZE) {
1439 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1440 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1441 } else
1442 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1443
1444 if (prot & IOMMU_PROT_IR)
1445 __pte |= IOMMU_PTE_IR;
1446 if (prot & IOMMU_PROT_IW)
1447 __pte |= IOMMU_PTE_IW;
1448
1449 for (i = 0; i < count; ++i)
1450 pte[i] = __pte;
1451
1452 update_domain(dom);
1453
1454 return 0;
1455 }
1456
1457 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1458 unsigned long bus_addr,
1459 unsigned long page_size)
1460 {
1461 unsigned long long unmap_size, unmapped;
1462 u64 *pte;
1463
1464 BUG_ON(!is_power_of_2(page_size));
1465
1466 unmapped = 0;
1467
1468 while (unmapped < page_size) {
1469
1470 pte = fetch_pte(dom, bus_addr);
1471
1472 if (!pte) {
1473 /*
1474 * No PTE for this address
1475 * move forward in 4kb steps
1476 */
1477 unmap_size = PAGE_SIZE;
1478 } else if (PM_PTE_LEVEL(*pte) == 0) {
1479 /* 4kb PTE found for this address */
1480 unmap_size = PAGE_SIZE;
1481 *pte = 0ULL;
1482 } else {
1483 int count, i;
1484
1485 /* Large PTE found which maps this address */
1486 unmap_size = PTE_PAGE_SIZE(*pte);
1487
1488 /* Only unmap from the first pte in the page */
1489 if ((unmap_size - 1) & bus_addr)
1490 break;
1491 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1492 for (i = 0; i < count; i++)
1493 pte[i] = 0ULL;
1494 }
1495
1496 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1497 unmapped += unmap_size;
1498 }
1499
1500 BUG_ON(unmapped && !is_power_of_2(unmapped));
1501
1502 return unmapped;
1503 }
1504
1505 /*
1506 * This function checks if a specific unity mapping entry is needed for
1507 * this specific IOMMU.
1508 */
1509 static int iommu_for_unity_map(struct amd_iommu *iommu,
1510 struct unity_map_entry *entry)
1511 {
1512 u16 bdf, i;
1513
1514 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1515 bdf = amd_iommu_alias_table[i];
1516 if (amd_iommu_rlookup_table[bdf] == iommu)
1517 return 1;
1518 }
1519
1520 return 0;
1521 }
1522
1523 /*
1524 * This function actually applies the mapping to the page table of the
1525 * dma_ops domain.
1526 */
1527 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1528 struct unity_map_entry *e)
1529 {
1530 u64 addr;
1531 int ret;
1532
1533 for (addr = e->address_start; addr < e->address_end;
1534 addr += PAGE_SIZE) {
1535 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1536 PAGE_SIZE);
1537 if (ret)
1538 return ret;
1539 /*
1540 * if unity mapping is in aperture range mark the page
1541 * as allocated in the aperture
1542 */
1543 if (addr < dma_dom->aperture_size)
1544 __set_bit(addr >> PAGE_SHIFT,
1545 dma_dom->aperture[0]->bitmap);
1546 }
1547
1548 return 0;
1549 }
1550
1551 /*
1552 * Init the unity mappings for a specific IOMMU in the system
1553 *
1554 * Basically iterates over all unity mapping entries and applies them to
1555 * the default domain DMA of that IOMMU if necessary.
1556 */
1557 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1558 {
1559 struct unity_map_entry *entry;
1560 int ret;
1561
1562 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1563 if (!iommu_for_unity_map(iommu, entry))
1564 continue;
1565 ret = dma_ops_unity_map(iommu->default_dom, entry);
1566 if (ret)
1567 return ret;
1568 }
1569
1570 return 0;
1571 }
1572
1573 /*
1574 * Inits the unity mappings required for a specific device
1575 */
1576 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1577 u16 devid)
1578 {
1579 struct unity_map_entry *e;
1580 int ret;
1581
1582 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1583 if (!(devid >= e->devid_start && devid <= e->devid_end))
1584 continue;
1585 ret = dma_ops_unity_map(dma_dom, e);
1586 if (ret)
1587 return ret;
1588 }
1589
1590 return 0;
1591 }
1592
1593 /****************************************************************************
1594 *
1595 * The next functions belong to the address allocator for the dma_ops
1596 * interface functions. They work like the allocators in the other IOMMU
1597 * drivers. Its basically a bitmap which marks the allocated pages in
1598 * the aperture. Maybe it could be enhanced in the future to a more
1599 * efficient allocator.
1600 *
1601 ****************************************************************************/
1602
1603 /*
1604 * The address allocator core functions.
1605 *
1606 * called with domain->lock held
1607 */
1608
1609 /*
1610 * Used to reserve address ranges in the aperture (e.g. for exclusion
1611 * ranges.
1612 */
1613 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1614 unsigned long start_page,
1615 unsigned int pages)
1616 {
1617 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1618
1619 if (start_page + pages > last_page)
1620 pages = last_page - start_page;
1621
1622 for (i = start_page; i < start_page + pages; ++i) {
1623 int index = i / APERTURE_RANGE_PAGES;
1624 int page = i % APERTURE_RANGE_PAGES;
1625 __set_bit(page, dom->aperture[index]->bitmap);
1626 }
1627 }
1628
1629 /*
1630 * This function is used to add a new aperture range to an existing
1631 * aperture in case of dma_ops domain allocation or address allocation
1632 * failure.
1633 */
1634 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1635 bool populate, gfp_t gfp)
1636 {
1637 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1638 struct amd_iommu *iommu;
1639 unsigned long i, old_size;
1640
1641 #ifdef CONFIG_IOMMU_STRESS
1642 populate = false;
1643 #endif
1644
1645 if (index >= APERTURE_MAX_RANGES)
1646 return -ENOMEM;
1647
1648 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1649 if (!dma_dom->aperture[index])
1650 return -ENOMEM;
1651
1652 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1653 if (!dma_dom->aperture[index]->bitmap)
1654 goto out_free;
1655
1656 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1657
1658 if (populate) {
1659 unsigned long address = dma_dom->aperture_size;
1660 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1661 u64 *pte, *pte_page;
1662
1663 for (i = 0; i < num_ptes; ++i) {
1664 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1665 &pte_page, gfp);
1666 if (!pte)
1667 goto out_free;
1668
1669 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1670
1671 address += APERTURE_RANGE_SIZE / 64;
1672 }
1673 }
1674
1675 old_size = dma_dom->aperture_size;
1676 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1677
1678 /* Reserve address range used for MSI messages */
1679 if (old_size < MSI_ADDR_BASE_LO &&
1680 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1681 unsigned long spage;
1682 int pages;
1683
1684 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1685 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1686
1687 dma_ops_reserve_addresses(dma_dom, spage, pages);
1688 }
1689
1690 /* Initialize the exclusion range if necessary */
1691 for_each_iommu(iommu) {
1692 if (iommu->exclusion_start &&
1693 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1694 && iommu->exclusion_start < dma_dom->aperture_size) {
1695 unsigned long startpage;
1696 int pages = iommu_num_pages(iommu->exclusion_start,
1697 iommu->exclusion_length,
1698 PAGE_SIZE);
1699 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1700 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1701 }
1702 }
1703
1704 /*
1705 * Check for areas already mapped as present in the new aperture
1706 * range and mark those pages as reserved in the allocator. Such
1707 * mappings may already exist as a result of requested unity
1708 * mappings for devices.
1709 */
1710 for (i = dma_dom->aperture[index]->offset;
1711 i < dma_dom->aperture_size;
1712 i += PAGE_SIZE) {
1713 u64 *pte = fetch_pte(&dma_dom->domain, i);
1714 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1715 continue;
1716
1717 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1718 }
1719
1720 update_domain(&dma_dom->domain);
1721
1722 return 0;
1723
1724 out_free:
1725 update_domain(&dma_dom->domain);
1726
1727 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1728
1729 kfree(dma_dom->aperture[index]);
1730 dma_dom->aperture[index] = NULL;
1731
1732 return -ENOMEM;
1733 }
1734
1735 static unsigned long dma_ops_area_alloc(struct device *dev,
1736 struct dma_ops_domain *dom,
1737 unsigned int pages,
1738 unsigned long align_mask,
1739 u64 dma_mask,
1740 unsigned long start)
1741 {
1742 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1743 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1744 int i = start >> APERTURE_RANGE_SHIFT;
1745 unsigned long boundary_size;
1746 unsigned long address = -1;
1747 unsigned long limit;
1748
1749 next_bit >>= PAGE_SHIFT;
1750
1751 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1752 PAGE_SIZE) >> PAGE_SHIFT;
1753
1754 for (;i < max_index; ++i) {
1755 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1756
1757 if (dom->aperture[i]->offset >= dma_mask)
1758 break;
1759
1760 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1761 dma_mask >> PAGE_SHIFT);
1762
1763 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1764 limit, next_bit, pages, 0,
1765 boundary_size, align_mask);
1766 if (address != -1) {
1767 address = dom->aperture[i]->offset +
1768 (address << PAGE_SHIFT);
1769 dom->next_address = address + (pages << PAGE_SHIFT);
1770 break;
1771 }
1772
1773 next_bit = 0;
1774 }
1775
1776 return address;
1777 }
1778
1779 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1780 struct dma_ops_domain *dom,
1781 unsigned int pages,
1782 unsigned long align_mask,
1783 u64 dma_mask)
1784 {
1785 unsigned long address;
1786
1787 #ifdef CONFIG_IOMMU_STRESS
1788 dom->next_address = 0;
1789 dom->need_flush = true;
1790 #endif
1791
1792 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1793 dma_mask, dom->next_address);
1794
1795 if (address == -1) {
1796 dom->next_address = 0;
1797 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1798 dma_mask, 0);
1799 dom->need_flush = true;
1800 }
1801
1802 if (unlikely(address == -1))
1803 address = DMA_ERROR_CODE;
1804
1805 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1806
1807 return address;
1808 }
1809
1810 /*
1811 * The address free function.
1812 *
1813 * called with domain->lock held
1814 */
1815 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1816 unsigned long address,
1817 unsigned int pages)
1818 {
1819 unsigned i = address >> APERTURE_RANGE_SHIFT;
1820 struct aperture_range *range = dom->aperture[i];
1821
1822 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1823
1824 #ifdef CONFIG_IOMMU_STRESS
1825 if (i < 4)
1826 return;
1827 #endif
1828
1829 if (address >= dom->next_address)
1830 dom->need_flush = true;
1831
1832 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1833
1834 bitmap_clear(range->bitmap, address, pages);
1835
1836 }
1837
1838 /****************************************************************************
1839 *
1840 * The next functions belong to the domain allocation. A domain is
1841 * allocated for every IOMMU as the default domain. If device isolation
1842 * is enabled, every device get its own domain. The most important thing
1843 * about domains is the page table mapping the DMA address space they
1844 * contain.
1845 *
1846 ****************************************************************************/
1847
1848 /*
1849 * This function adds a protection domain to the global protection domain list
1850 */
1851 static void add_domain_to_list(struct protection_domain *domain)
1852 {
1853 unsigned long flags;
1854
1855 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1856 list_add(&domain->list, &amd_iommu_pd_list);
1857 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1858 }
1859
1860 /*
1861 * This function removes a protection domain to the global
1862 * protection domain list
1863 */
1864 static void del_domain_from_list(struct protection_domain *domain)
1865 {
1866 unsigned long flags;
1867
1868 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1869 list_del(&domain->list);
1870 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1871 }
1872
1873 static u16 domain_id_alloc(void)
1874 {
1875 unsigned long flags;
1876 int id;
1877
1878 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1879 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1880 BUG_ON(id == 0);
1881 if (id > 0 && id < MAX_DOMAIN_ID)
1882 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1883 else
1884 id = 0;
1885 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1886
1887 return id;
1888 }
1889
1890 static void domain_id_free(int id)
1891 {
1892 unsigned long flags;
1893
1894 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1895 if (id > 0 && id < MAX_DOMAIN_ID)
1896 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1897 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1898 }
1899
1900 static void free_pagetable(struct protection_domain *domain)
1901 {
1902 int i, j;
1903 u64 *p1, *p2, *p3;
1904
1905 p1 = domain->pt_root;
1906
1907 if (!p1)
1908 return;
1909
1910 for (i = 0; i < 512; ++i) {
1911 if (!IOMMU_PTE_PRESENT(p1[i]))
1912 continue;
1913
1914 p2 = IOMMU_PTE_PAGE(p1[i]);
1915 for (j = 0; j < 512; ++j) {
1916 if (!IOMMU_PTE_PRESENT(p2[j]))
1917 continue;
1918 p3 = IOMMU_PTE_PAGE(p2[j]);
1919 free_page((unsigned long)p3);
1920 }
1921
1922 free_page((unsigned long)p2);
1923 }
1924
1925 free_page((unsigned long)p1);
1926
1927 domain->pt_root = NULL;
1928 }
1929
1930 static void free_gcr3_tbl_level1(u64 *tbl)
1931 {
1932 u64 *ptr;
1933 int i;
1934
1935 for (i = 0; i < 512; ++i) {
1936 if (!(tbl[i] & GCR3_VALID))
1937 continue;
1938
1939 ptr = __va(tbl[i] & PAGE_MASK);
1940
1941 free_page((unsigned long)ptr);
1942 }
1943 }
1944
1945 static void free_gcr3_tbl_level2(u64 *tbl)
1946 {
1947 u64 *ptr;
1948 int i;
1949
1950 for (i = 0; i < 512; ++i) {
1951 if (!(tbl[i] & GCR3_VALID))
1952 continue;
1953
1954 ptr = __va(tbl[i] & PAGE_MASK);
1955
1956 free_gcr3_tbl_level1(ptr);
1957 }
1958 }
1959
1960 static void free_gcr3_table(struct protection_domain *domain)
1961 {
1962 if (domain->glx == 2)
1963 free_gcr3_tbl_level2(domain->gcr3_tbl);
1964 else if (domain->glx == 1)
1965 free_gcr3_tbl_level1(domain->gcr3_tbl);
1966 else if (domain->glx != 0)
1967 BUG();
1968
1969 free_page((unsigned long)domain->gcr3_tbl);
1970 }
1971
1972 /*
1973 * Free a domain, only used if something went wrong in the
1974 * allocation path and we need to free an already allocated page table
1975 */
1976 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1977 {
1978 int i;
1979
1980 if (!dom)
1981 return;
1982
1983 del_domain_from_list(&dom->domain);
1984
1985 free_pagetable(&dom->domain);
1986
1987 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1988 if (!dom->aperture[i])
1989 continue;
1990 free_page((unsigned long)dom->aperture[i]->bitmap);
1991 kfree(dom->aperture[i]);
1992 }
1993
1994 if (dom->domain.id)
1995 domain_id_free(dom->domain.id);
1996
1997 kfree(dom);
1998 }
1999
2000 /*
2001 * Allocates a new protection domain usable for the dma_ops functions.
2002 * It also initializes the page table and the address allocator data
2003 * structures required for the dma_ops interface
2004 */
2005 static struct dma_ops_domain *dma_ops_domain_alloc(void)
2006 {
2007 struct dma_ops_domain *dma_dom;
2008
2009 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2010 if (!dma_dom)
2011 return NULL;
2012
2013 spin_lock_init(&dma_dom->domain.lock);
2014
2015 dma_dom->domain.id = domain_id_alloc();
2016 if (dma_dom->domain.id == 0)
2017 goto free_dma_dom;
2018 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2019 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2020 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2021 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2022 dma_dom->domain.priv = dma_dom;
2023 if (!dma_dom->domain.pt_root)
2024 goto free_dma_dom;
2025
2026 dma_dom->need_flush = false;
2027 dma_dom->target_dev = 0xffff;
2028
2029 add_domain_to_list(&dma_dom->domain);
2030
2031 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2032 goto free_dma_dom;
2033
2034 /*
2035 * mark the first page as allocated so we never return 0 as
2036 * a valid dma-address. So we can use 0 as error value
2037 */
2038 dma_dom->aperture[0]->bitmap[0] = 1;
2039 dma_dom->next_address = 0;
2040
2041
2042 return dma_dom;
2043
2044 free_dma_dom:
2045 dma_ops_domain_free(dma_dom);
2046
2047 return NULL;
2048 }
2049
2050 /*
2051 * little helper function to check whether a given protection domain is a
2052 * dma_ops domain
2053 */
2054 static bool dma_ops_domain(struct protection_domain *domain)
2055 {
2056 return domain->flags & PD_DMA_OPS_MASK;
2057 }
2058
2059 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2060 {
2061 u64 pte_root = 0;
2062 u64 flags = 0;
2063
2064 if (domain->mode != PAGE_MODE_NONE)
2065 pte_root = virt_to_phys(domain->pt_root);
2066
2067 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2068 << DEV_ENTRY_MODE_SHIFT;
2069 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2070
2071 flags = amd_iommu_dev_table[devid].data[1];
2072
2073 if (ats)
2074 flags |= DTE_FLAG_IOTLB;
2075
2076 if (domain->flags & PD_IOMMUV2_MASK) {
2077 u64 gcr3 = __pa(domain->gcr3_tbl);
2078 u64 glx = domain->glx;
2079 u64 tmp;
2080
2081 pte_root |= DTE_FLAG_GV;
2082 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2083
2084 /* First mask out possible old values for GCR3 table */
2085 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2086 flags &= ~tmp;
2087
2088 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2089 flags &= ~tmp;
2090
2091 /* Encode GCR3 table into DTE */
2092 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2093 pte_root |= tmp;
2094
2095 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2096 flags |= tmp;
2097
2098 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2099 flags |= tmp;
2100 }
2101
2102 flags &= ~(0xffffUL);
2103 flags |= domain->id;
2104
2105 amd_iommu_dev_table[devid].data[1] = flags;
2106 amd_iommu_dev_table[devid].data[0] = pte_root;
2107 }
2108
2109 static void clear_dte_entry(u16 devid)
2110 {
2111 /* remove entry from the device table seen by the hardware */
2112 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2113 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2114
2115 amd_iommu_apply_erratum_63(devid);
2116 }
2117
2118 static void do_attach(struct iommu_dev_data *dev_data,
2119 struct protection_domain *domain)
2120 {
2121 struct amd_iommu *iommu;
2122 bool ats;
2123
2124 iommu = amd_iommu_rlookup_table[dev_data->devid];
2125 ats = dev_data->ats.enabled;
2126
2127 /* Update data structures */
2128 dev_data->domain = domain;
2129 list_add(&dev_data->list, &domain->dev_list);
2130 set_dte_entry(dev_data->devid, domain, ats);
2131
2132 /* Do reference counting */
2133 domain->dev_iommu[iommu->index] += 1;
2134 domain->dev_cnt += 1;
2135
2136 /* Flush the DTE entry */
2137 device_flush_dte(dev_data);
2138 }
2139
2140 static void do_detach(struct iommu_dev_data *dev_data)
2141 {
2142 struct amd_iommu *iommu;
2143
2144 iommu = amd_iommu_rlookup_table[dev_data->devid];
2145
2146 /* decrease reference counters */
2147 dev_data->domain->dev_iommu[iommu->index] -= 1;
2148 dev_data->domain->dev_cnt -= 1;
2149
2150 /* Update data structures */
2151 dev_data->domain = NULL;
2152 list_del(&dev_data->list);
2153 clear_dte_entry(dev_data->devid);
2154
2155 /* Flush the DTE entry */
2156 device_flush_dte(dev_data);
2157 }
2158
2159 /*
2160 * If a device is not yet associated with a domain, this function does
2161 * assigns it visible for the hardware
2162 */
2163 static int __attach_device(struct iommu_dev_data *dev_data,
2164 struct protection_domain *domain)
2165 {
2166 int ret;
2167
2168 /* lock domain */
2169 spin_lock(&domain->lock);
2170
2171 if (dev_data->alias_data != NULL) {
2172 struct iommu_dev_data *alias_data = dev_data->alias_data;
2173
2174 /* Some sanity checks */
2175 ret = -EBUSY;
2176 if (alias_data->domain != NULL &&
2177 alias_data->domain != domain)
2178 goto out_unlock;
2179
2180 if (dev_data->domain != NULL &&
2181 dev_data->domain != domain)
2182 goto out_unlock;
2183
2184 /* Do real assignment */
2185 if (alias_data->domain == NULL)
2186 do_attach(alias_data, domain);
2187
2188 atomic_inc(&alias_data->bind);
2189 }
2190
2191 if (dev_data->domain == NULL)
2192 do_attach(dev_data, domain);
2193
2194 atomic_inc(&dev_data->bind);
2195
2196 ret = 0;
2197
2198 out_unlock:
2199
2200 /* ready */
2201 spin_unlock(&domain->lock);
2202
2203 return ret;
2204 }
2205
2206
2207 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2208 {
2209 pci_disable_ats(pdev);
2210 pci_disable_pri(pdev);
2211 pci_disable_pasid(pdev);
2212 }
2213
2214 /* FIXME: Change generic reset-function to do the same */
2215 static int pri_reset_while_enabled(struct pci_dev *pdev)
2216 {
2217 u16 control;
2218 int pos;
2219
2220 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2221 if (!pos)
2222 return -EINVAL;
2223
2224 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2225 control |= PCI_PRI_CTRL_RESET;
2226 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2227
2228 return 0;
2229 }
2230
2231 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2232 {
2233 bool reset_enable;
2234 int reqs, ret;
2235
2236 /* FIXME: Hardcode number of outstanding requests for now */
2237 reqs = 32;
2238 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2239 reqs = 1;
2240 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2241
2242 /* Only allow access to user-accessible pages */
2243 ret = pci_enable_pasid(pdev, 0);
2244 if (ret)
2245 goto out_err;
2246
2247 /* First reset the PRI state of the device */
2248 ret = pci_reset_pri(pdev);
2249 if (ret)
2250 goto out_err;
2251
2252 /* Enable PRI */
2253 ret = pci_enable_pri(pdev, reqs);
2254 if (ret)
2255 goto out_err;
2256
2257 if (reset_enable) {
2258 ret = pri_reset_while_enabled(pdev);
2259 if (ret)
2260 goto out_err;
2261 }
2262
2263 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2264 if (ret)
2265 goto out_err;
2266
2267 return 0;
2268
2269 out_err:
2270 pci_disable_pri(pdev);
2271 pci_disable_pasid(pdev);
2272
2273 return ret;
2274 }
2275
2276 /* FIXME: Move this to PCI code */
2277 #define PCI_PRI_TLP_OFF (1 << 15)
2278
2279 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2280 {
2281 u16 status;
2282 int pos;
2283
2284 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2285 if (!pos)
2286 return false;
2287
2288 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2289
2290 return (status & PCI_PRI_TLP_OFF) ? true : false;
2291 }
2292
2293 /*
2294 * If a device is not yet associated with a domain, this function
2295 * assigns it visible for the hardware
2296 */
2297 static int attach_device(struct device *dev,
2298 struct protection_domain *domain)
2299 {
2300 struct pci_dev *pdev = to_pci_dev(dev);
2301 struct iommu_dev_data *dev_data;
2302 unsigned long flags;
2303 int ret;
2304
2305 dev_data = get_dev_data(dev);
2306
2307 if (domain->flags & PD_IOMMUV2_MASK) {
2308 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2309 return -EINVAL;
2310
2311 if (pdev_iommuv2_enable(pdev) != 0)
2312 return -EINVAL;
2313
2314 dev_data->ats.enabled = true;
2315 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2316 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2317 } else if (amd_iommu_iotlb_sup &&
2318 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2319 dev_data->ats.enabled = true;
2320 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2321 }
2322
2323 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2324 ret = __attach_device(dev_data, domain);
2325 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2326
2327 /*
2328 * We might boot into a crash-kernel here. The crashed kernel
2329 * left the caches in the IOMMU dirty. So we have to flush
2330 * here to evict all dirty stuff.
2331 */
2332 domain_flush_tlb_pde(domain);
2333
2334 return ret;
2335 }
2336
2337 /*
2338 * Removes a device from a protection domain (unlocked)
2339 */
2340 static void __detach_device(struct iommu_dev_data *dev_data)
2341 {
2342 struct protection_domain *domain;
2343 unsigned long flags;
2344
2345 BUG_ON(!dev_data->domain);
2346
2347 domain = dev_data->domain;
2348
2349 spin_lock_irqsave(&domain->lock, flags);
2350
2351 if (dev_data->alias_data != NULL) {
2352 struct iommu_dev_data *alias_data = dev_data->alias_data;
2353
2354 if (atomic_dec_and_test(&alias_data->bind))
2355 do_detach(alias_data);
2356 }
2357
2358 if (atomic_dec_and_test(&dev_data->bind))
2359 do_detach(dev_data);
2360
2361 spin_unlock_irqrestore(&domain->lock, flags);
2362
2363 /*
2364 * If we run in passthrough mode the device must be assigned to the
2365 * passthrough domain if it is detached from any other domain.
2366 * Make sure we can deassign from the pt_domain itself.
2367 */
2368 if (dev_data->passthrough &&
2369 (dev_data->domain == NULL && domain != pt_domain))
2370 __attach_device(dev_data, pt_domain);
2371 }
2372
2373 /*
2374 * Removes a device from a protection domain (with devtable_lock held)
2375 */
2376 static void detach_device(struct device *dev)
2377 {
2378 struct protection_domain *domain;
2379 struct iommu_dev_data *dev_data;
2380 unsigned long flags;
2381
2382 dev_data = get_dev_data(dev);
2383 domain = dev_data->domain;
2384
2385 /* lock device table */
2386 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2387 __detach_device(dev_data);
2388 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2389
2390 if (domain->flags & PD_IOMMUV2_MASK)
2391 pdev_iommuv2_disable(to_pci_dev(dev));
2392 else if (dev_data->ats.enabled)
2393 pci_disable_ats(to_pci_dev(dev));
2394
2395 dev_data->ats.enabled = false;
2396 }
2397
2398 /*
2399 * Find out the protection domain structure for a given PCI device. This
2400 * will give us the pointer to the page table root for example.
2401 */
2402 static struct protection_domain *domain_for_device(struct device *dev)
2403 {
2404 struct iommu_dev_data *dev_data;
2405 struct protection_domain *dom = NULL;
2406 unsigned long flags;
2407
2408 dev_data = get_dev_data(dev);
2409
2410 if (dev_data->domain)
2411 return dev_data->domain;
2412
2413 if (dev_data->alias_data != NULL) {
2414 struct iommu_dev_data *alias_data = dev_data->alias_data;
2415
2416 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2417 if (alias_data->domain != NULL) {
2418 __attach_device(dev_data, alias_data->domain);
2419 dom = alias_data->domain;
2420 }
2421 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2422 }
2423
2424 return dom;
2425 }
2426
2427 static int device_change_notifier(struct notifier_block *nb,
2428 unsigned long action, void *data)
2429 {
2430 struct dma_ops_domain *dma_domain;
2431 struct protection_domain *domain;
2432 struct iommu_dev_data *dev_data;
2433 struct device *dev = data;
2434 struct amd_iommu *iommu;
2435 unsigned long flags;
2436 u16 devid;
2437
2438 if (!check_device(dev))
2439 return 0;
2440
2441 devid = get_device_id(dev);
2442 iommu = amd_iommu_rlookup_table[devid];
2443 dev_data = get_dev_data(dev);
2444
2445 switch (action) {
2446 case BUS_NOTIFY_UNBOUND_DRIVER:
2447
2448 domain = domain_for_device(dev);
2449
2450 if (!domain)
2451 goto out;
2452 if (dev_data->passthrough)
2453 break;
2454 detach_device(dev);
2455 break;
2456 case BUS_NOTIFY_ADD_DEVICE:
2457
2458 iommu_init_device(dev);
2459
2460 /*
2461 * dev_data is still NULL and
2462 * got initialized in iommu_init_device
2463 */
2464 dev_data = get_dev_data(dev);
2465
2466 if (iommu_pass_through || dev_data->iommu_v2) {
2467 dev_data->passthrough = true;
2468 attach_device(dev, pt_domain);
2469 break;
2470 }
2471
2472 domain = domain_for_device(dev);
2473
2474 /* allocate a protection domain if a device is added */
2475 dma_domain = find_protection_domain(devid);
2476 if (!dma_domain) {
2477 dma_domain = dma_ops_domain_alloc();
2478 if (!dma_domain)
2479 goto out;
2480 dma_domain->target_dev = devid;
2481
2482 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2483 list_add_tail(&dma_domain->list, &iommu_pd_list);
2484 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2485 }
2486
2487 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2488
2489 break;
2490 case BUS_NOTIFY_DEL_DEVICE:
2491
2492 iommu_uninit_device(dev);
2493
2494 default:
2495 goto out;
2496 }
2497
2498 iommu_completion_wait(iommu);
2499
2500 out:
2501 return 0;
2502 }
2503
2504 static struct notifier_block device_nb = {
2505 .notifier_call = device_change_notifier,
2506 };
2507
2508 void amd_iommu_init_notifier(void)
2509 {
2510 bus_register_notifier(&pci_bus_type, &device_nb);
2511 }
2512
2513 /*****************************************************************************
2514 *
2515 * The next functions belong to the dma_ops mapping/unmapping code.
2516 *
2517 *****************************************************************************/
2518
2519 /*
2520 * In the dma_ops path we only have the struct device. This function
2521 * finds the corresponding IOMMU, the protection domain and the
2522 * requestor id for a given device.
2523 * If the device is not yet associated with a domain this is also done
2524 * in this function.
2525 */
2526 static struct protection_domain *get_domain(struct device *dev)
2527 {
2528 struct protection_domain *domain;
2529 struct dma_ops_domain *dma_dom;
2530 u16 devid = get_device_id(dev);
2531
2532 if (!check_device(dev))
2533 return ERR_PTR(-EINVAL);
2534
2535 domain = domain_for_device(dev);
2536 if (domain != NULL && !dma_ops_domain(domain))
2537 return ERR_PTR(-EBUSY);
2538
2539 if (domain != NULL)
2540 return domain;
2541
2542 /* Device not bound yet - bind it */
2543 dma_dom = find_protection_domain(devid);
2544 if (!dma_dom)
2545 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2546 attach_device(dev, &dma_dom->domain);
2547 DUMP_printk("Using protection domain %d for device %s\n",
2548 dma_dom->domain.id, dev_name(dev));
2549
2550 return &dma_dom->domain;
2551 }
2552
2553 static void update_device_table(struct protection_domain *domain)
2554 {
2555 struct iommu_dev_data *dev_data;
2556
2557 list_for_each_entry(dev_data, &domain->dev_list, list) {
2558 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2559
2560 if (dev_data->alias_data == NULL)
2561 continue;
2562
2563 /* There is an alias, update device table entry for it */
2564 set_dte_entry(dev_data->alias_data->devid, domain,
2565 dev_data->alias_data->ats.enabled);
2566 }
2567 }
2568
2569 static void update_domain(struct protection_domain *domain)
2570 {
2571 if (!domain->updated)
2572 return;
2573
2574 update_device_table(domain);
2575
2576 domain_flush_devices(domain);
2577 domain_flush_tlb_pde(domain);
2578
2579 domain->updated = false;
2580 }
2581
2582 /*
2583 * This function fetches the PTE for a given address in the aperture
2584 */
2585 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2586 unsigned long address)
2587 {
2588 struct aperture_range *aperture;
2589 u64 *pte, *pte_page;
2590
2591 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2592 if (!aperture)
2593 return NULL;
2594
2595 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2596 if (!pte) {
2597 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2598 GFP_ATOMIC);
2599 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2600 } else
2601 pte += PM_LEVEL_INDEX(0, address);
2602
2603 update_domain(&dom->domain);
2604
2605 return pte;
2606 }
2607
2608 /*
2609 * This is the generic map function. It maps one 4kb page at paddr to
2610 * the given address in the DMA address space for the domain.
2611 */
2612 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2613 unsigned long address,
2614 phys_addr_t paddr,
2615 int direction)
2616 {
2617 u64 *pte, __pte;
2618
2619 WARN_ON(address > dom->aperture_size);
2620
2621 paddr &= PAGE_MASK;
2622
2623 pte = dma_ops_get_pte(dom, address);
2624 if (!pte)
2625 return DMA_ERROR_CODE;
2626
2627 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2628
2629 if (direction == DMA_TO_DEVICE)
2630 __pte |= IOMMU_PTE_IR;
2631 else if (direction == DMA_FROM_DEVICE)
2632 __pte |= IOMMU_PTE_IW;
2633 else if (direction == DMA_BIDIRECTIONAL)
2634 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2635
2636 WARN_ON(*pte);
2637
2638 *pte = __pte;
2639
2640 return (dma_addr_t)address;
2641 }
2642
2643 /*
2644 * The generic unmapping function for on page in the DMA address space.
2645 */
2646 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2647 unsigned long address)
2648 {
2649 struct aperture_range *aperture;
2650 u64 *pte;
2651
2652 if (address >= dom->aperture_size)
2653 return;
2654
2655 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2656 if (!aperture)
2657 return;
2658
2659 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2660 if (!pte)
2661 return;
2662
2663 pte += PM_LEVEL_INDEX(0, address);
2664
2665 WARN_ON(!*pte);
2666
2667 *pte = 0ULL;
2668 }
2669
2670 /*
2671 * This function contains common code for mapping of a physically
2672 * contiguous memory region into DMA address space. It is used by all
2673 * mapping functions provided with this IOMMU driver.
2674 * Must be called with the domain lock held.
2675 */
2676 static dma_addr_t __map_single(struct device *dev,
2677 struct dma_ops_domain *dma_dom,
2678 phys_addr_t paddr,
2679 size_t size,
2680 int dir,
2681 bool align,
2682 u64 dma_mask)
2683 {
2684 dma_addr_t offset = paddr & ~PAGE_MASK;
2685 dma_addr_t address, start, ret;
2686 unsigned int pages;
2687 unsigned long align_mask = 0;
2688 int i;
2689
2690 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2691 paddr &= PAGE_MASK;
2692
2693 INC_STATS_COUNTER(total_map_requests);
2694
2695 if (pages > 1)
2696 INC_STATS_COUNTER(cross_page);
2697
2698 if (align)
2699 align_mask = (1UL << get_order(size)) - 1;
2700
2701 retry:
2702 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2703 dma_mask);
2704 if (unlikely(address == DMA_ERROR_CODE)) {
2705 /*
2706 * setting next_address here will let the address
2707 * allocator only scan the new allocated range in the
2708 * first run. This is a small optimization.
2709 */
2710 dma_dom->next_address = dma_dom->aperture_size;
2711
2712 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2713 goto out;
2714
2715 /*
2716 * aperture was successfully enlarged by 128 MB, try
2717 * allocation again
2718 */
2719 goto retry;
2720 }
2721
2722 start = address;
2723 for (i = 0; i < pages; ++i) {
2724 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2725 if (ret == DMA_ERROR_CODE)
2726 goto out_unmap;
2727
2728 paddr += PAGE_SIZE;
2729 start += PAGE_SIZE;
2730 }
2731 address += offset;
2732
2733 ADD_STATS_COUNTER(alloced_io_mem, size);
2734
2735 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2736 domain_flush_tlb(&dma_dom->domain);
2737 dma_dom->need_flush = false;
2738 } else if (unlikely(amd_iommu_np_cache))
2739 domain_flush_pages(&dma_dom->domain, address, size);
2740
2741 out:
2742 return address;
2743
2744 out_unmap:
2745
2746 for (--i; i >= 0; --i) {
2747 start -= PAGE_SIZE;
2748 dma_ops_domain_unmap(dma_dom, start);
2749 }
2750
2751 dma_ops_free_addresses(dma_dom, address, pages);
2752
2753 return DMA_ERROR_CODE;
2754 }
2755
2756 /*
2757 * Does the reverse of the __map_single function. Must be called with
2758 * the domain lock held too
2759 */
2760 static void __unmap_single(struct dma_ops_domain *dma_dom,
2761 dma_addr_t dma_addr,
2762 size_t size,
2763 int dir)
2764 {
2765 dma_addr_t flush_addr;
2766 dma_addr_t i, start;
2767 unsigned int pages;
2768
2769 if ((dma_addr == DMA_ERROR_CODE) ||
2770 (dma_addr + size > dma_dom->aperture_size))
2771 return;
2772
2773 flush_addr = dma_addr;
2774 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2775 dma_addr &= PAGE_MASK;
2776 start = dma_addr;
2777
2778 for (i = 0; i < pages; ++i) {
2779 dma_ops_domain_unmap(dma_dom, start);
2780 start += PAGE_SIZE;
2781 }
2782
2783 SUB_STATS_COUNTER(alloced_io_mem, size);
2784
2785 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2786
2787 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2788 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2789 dma_dom->need_flush = false;
2790 }
2791 }
2792
2793 /*
2794 * The exported map_single function for dma_ops.
2795 */
2796 static dma_addr_t map_page(struct device *dev, struct page *page,
2797 unsigned long offset, size_t size,
2798 enum dma_data_direction dir,
2799 struct dma_attrs *attrs)
2800 {
2801 unsigned long flags;
2802 struct protection_domain *domain;
2803 dma_addr_t addr;
2804 u64 dma_mask;
2805 phys_addr_t paddr = page_to_phys(page) + offset;
2806
2807 INC_STATS_COUNTER(cnt_map_single);
2808
2809 domain = get_domain(dev);
2810 if (PTR_ERR(domain) == -EINVAL)
2811 return (dma_addr_t)paddr;
2812 else if (IS_ERR(domain))
2813 return DMA_ERROR_CODE;
2814
2815 dma_mask = *dev->dma_mask;
2816
2817 spin_lock_irqsave(&domain->lock, flags);
2818
2819 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2820 dma_mask);
2821 if (addr == DMA_ERROR_CODE)
2822 goto out;
2823
2824 domain_flush_complete(domain);
2825
2826 out:
2827 spin_unlock_irqrestore(&domain->lock, flags);
2828
2829 return addr;
2830 }
2831
2832 /*
2833 * The exported unmap_single function for dma_ops.
2834 */
2835 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2836 enum dma_data_direction dir, struct dma_attrs *attrs)
2837 {
2838 unsigned long flags;
2839 struct protection_domain *domain;
2840
2841 INC_STATS_COUNTER(cnt_unmap_single);
2842
2843 domain = get_domain(dev);
2844 if (IS_ERR(domain))
2845 return;
2846
2847 spin_lock_irqsave(&domain->lock, flags);
2848
2849 __unmap_single(domain->priv, dma_addr, size, dir);
2850
2851 domain_flush_complete(domain);
2852
2853 spin_unlock_irqrestore(&domain->lock, flags);
2854 }
2855
2856 /*
2857 * The exported map_sg function for dma_ops (handles scatter-gather
2858 * lists).
2859 */
2860 static int map_sg(struct device *dev, struct scatterlist *sglist,
2861 int nelems, enum dma_data_direction dir,
2862 struct dma_attrs *attrs)
2863 {
2864 unsigned long flags;
2865 struct protection_domain *domain;
2866 int i;
2867 struct scatterlist *s;
2868 phys_addr_t paddr;
2869 int mapped_elems = 0;
2870 u64 dma_mask;
2871
2872 INC_STATS_COUNTER(cnt_map_sg);
2873
2874 domain = get_domain(dev);
2875 if (IS_ERR(domain))
2876 return 0;
2877
2878 dma_mask = *dev->dma_mask;
2879
2880 spin_lock_irqsave(&domain->lock, flags);
2881
2882 for_each_sg(sglist, s, nelems, i) {
2883 paddr = sg_phys(s);
2884
2885 s->dma_address = __map_single(dev, domain->priv,
2886 paddr, s->length, dir, false,
2887 dma_mask);
2888
2889 if (s->dma_address) {
2890 s->dma_length = s->length;
2891 mapped_elems++;
2892 } else
2893 goto unmap;
2894 }
2895
2896 domain_flush_complete(domain);
2897
2898 out:
2899 spin_unlock_irqrestore(&domain->lock, flags);
2900
2901 return mapped_elems;
2902 unmap:
2903 for_each_sg(sglist, s, mapped_elems, i) {
2904 if (s->dma_address)
2905 __unmap_single(domain->priv, s->dma_address,
2906 s->dma_length, dir);
2907 s->dma_address = s->dma_length = 0;
2908 }
2909
2910 mapped_elems = 0;
2911
2912 goto out;
2913 }
2914
2915 /*
2916 * The exported map_sg function for dma_ops (handles scatter-gather
2917 * lists).
2918 */
2919 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2920 int nelems, enum dma_data_direction dir,
2921 struct dma_attrs *attrs)
2922 {
2923 unsigned long flags;
2924 struct protection_domain *domain;
2925 struct scatterlist *s;
2926 int i;
2927
2928 INC_STATS_COUNTER(cnt_unmap_sg);
2929
2930 domain = get_domain(dev);
2931 if (IS_ERR(domain))
2932 return;
2933
2934 spin_lock_irqsave(&domain->lock, flags);
2935
2936 for_each_sg(sglist, s, nelems, i) {
2937 __unmap_single(domain->priv, s->dma_address,
2938 s->dma_length, dir);
2939 s->dma_address = s->dma_length = 0;
2940 }
2941
2942 domain_flush_complete(domain);
2943
2944 spin_unlock_irqrestore(&domain->lock, flags);
2945 }
2946
2947 /*
2948 * The exported alloc_coherent function for dma_ops.
2949 */
2950 static void *alloc_coherent(struct device *dev, size_t size,
2951 dma_addr_t *dma_addr, gfp_t flag,
2952 struct dma_attrs *attrs)
2953 {
2954 unsigned long flags;
2955 void *virt_addr;
2956 struct protection_domain *domain;
2957 phys_addr_t paddr;
2958 u64 dma_mask = dev->coherent_dma_mask;
2959
2960 INC_STATS_COUNTER(cnt_alloc_coherent);
2961
2962 domain = get_domain(dev);
2963 if (PTR_ERR(domain) == -EINVAL) {
2964 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2965 *dma_addr = __pa(virt_addr);
2966 return virt_addr;
2967 } else if (IS_ERR(domain))
2968 return NULL;
2969
2970 dma_mask = dev->coherent_dma_mask;
2971 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2972 flag |= __GFP_ZERO;
2973
2974 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2975 if (!virt_addr)
2976 return NULL;
2977
2978 paddr = virt_to_phys(virt_addr);
2979
2980 if (!dma_mask)
2981 dma_mask = *dev->dma_mask;
2982
2983 spin_lock_irqsave(&domain->lock, flags);
2984
2985 *dma_addr = __map_single(dev, domain->priv, paddr,
2986 size, DMA_BIDIRECTIONAL, true, dma_mask);
2987
2988 if (*dma_addr == DMA_ERROR_CODE) {
2989 spin_unlock_irqrestore(&domain->lock, flags);
2990 goto out_free;
2991 }
2992
2993 domain_flush_complete(domain);
2994
2995 spin_unlock_irqrestore(&domain->lock, flags);
2996
2997 return virt_addr;
2998
2999 out_free:
3000
3001 free_pages((unsigned long)virt_addr, get_order(size));
3002
3003 return NULL;
3004 }
3005
3006 /*
3007 * The exported free_coherent function for dma_ops.
3008 */
3009 static void free_coherent(struct device *dev, size_t size,
3010 void *virt_addr, dma_addr_t dma_addr,
3011 struct dma_attrs *attrs)
3012 {
3013 unsigned long flags;
3014 struct protection_domain *domain;
3015
3016 INC_STATS_COUNTER(cnt_free_coherent);
3017
3018 domain = get_domain(dev);
3019 if (IS_ERR(domain))
3020 goto free_mem;
3021
3022 spin_lock_irqsave(&domain->lock, flags);
3023
3024 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
3025
3026 domain_flush_complete(domain);
3027
3028 spin_unlock_irqrestore(&domain->lock, flags);
3029
3030 free_mem:
3031 free_pages((unsigned long)virt_addr, get_order(size));
3032 }
3033
3034 /*
3035 * This function is called by the DMA layer to find out if we can handle a
3036 * particular device. It is part of the dma_ops.
3037 */
3038 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3039 {
3040 return check_device(dev);
3041 }
3042
3043 /*
3044 * The function for pre-allocating protection domains.
3045 *
3046 * If the driver core informs the DMA layer if a driver grabs a device
3047 * we don't need to preallocate the protection domains anymore.
3048 * For now we have to.
3049 */
3050 static void __init prealloc_protection_domains(void)
3051 {
3052 struct iommu_dev_data *dev_data;
3053 struct dma_ops_domain *dma_dom;
3054 struct pci_dev *dev = NULL;
3055 u16 devid;
3056
3057 for_each_pci_dev(dev) {
3058
3059 /* Do we handle this device? */
3060 if (!check_device(&dev->dev))
3061 continue;
3062
3063 dev_data = get_dev_data(&dev->dev);
3064 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3065 /* Make sure passthrough domain is allocated */
3066 alloc_passthrough_domain();
3067 dev_data->passthrough = true;
3068 attach_device(&dev->dev, pt_domain);
3069 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3070 dev_name(&dev->dev));
3071 }
3072
3073 /* Is there already any domain for it? */
3074 if (domain_for_device(&dev->dev))
3075 continue;
3076
3077 devid = get_device_id(&dev->dev);
3078
3079 dma_dom = dma_ops_domain_alloc();
3080 if (!dma_dom)
3081 continue;
3082 init_unity_mappings_for_device(dma_dom, devid);
3083 dma_dom->target_dev = devid;
3084
3085 attach_device(&dev->dev, &dma_dom->domain);
3086
3087 list_add_tail(&dma_dom->list, &iommu_pd_list);
3088 }
3089 }
3090
3091 static struct dma_map_ops amd_iommu_dma_ops = {
3092 .alloc = alloc_coherent,
3093 .free = free_coherent,
3094 .map_page = map_page,
3095 .unmap_page = unmap_page,
3096 .map_sg = map_sg,
3097 .unmap_sg = unmap_sg,
3098 .dma_supported = amd_iommu_dma_supported,
3099 };
3100
3101 static unsigned device_dma_ops_init(void)
3102 {
3103 struct iommu_dev_data *dev_data;
3104 struct pci_dev *pdev = NULL;
3105 unsigned unhandled = 0;
3106
3107 for_each_pci_dev(pdev) {
3108 if (!check_device(&pdev->dev)) {
3109
3110 iommu_ignore_device(&pdev->dev);
3111
3112 unhandled += 1;
3113 continue;
3114 }
3115
3116 dev_data = get_dev_data(&pdev->dev);
3117
3118 if (!dev_data->passthrough)
3119 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3120 else
3121 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3122 }
3123
3124 return unhandled;
3125 }
3126
3127 /*
3128 * The function which clues the AMD IOMMU driver into dma_ops.
3129 */
3130
3131 void __init amd_iommu_init_api(void)
3132 {
3133 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3134 }
3135
3136 int __init amd_iommu_init_dma_ops(void)
3137 {
3138 struct amd_iommu *iommu;
3139 int ret, unhandled;
3140
3141 /*
3142 * first allocate a default protection domain for every IOMMU we
3143 * found in the system. Devices not assigned to any other
3144 * protection domain will be assigned to the default one.
3145 */
3146 for_each_iommu(iommu) {
3147 iommu->default_dom = dma_ops_domain_alloc();
3148 if (iommu->default_dom == NULL)
3149 return -ENOMEM;
3150 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3151 ret = iommu_init_unity_mappings(iommu);
3152 if (ret)
3153 goto free_domains;
3154 }
3155
3156 /*
3157 * Pre-allocate the protection domains for each device.
3158 */
3159 prealloc_protection_domains();
3160
3161 iommu_detected = 1;
3162 swiotlb = 0;
3163
3164 /* Make the driver finally visible to the drivers */
3165 unhandled = device_dma_ops_init();
3166 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3167 /* There are unhandled devices - initialize swiotlb for them */
3168 swiotlb = 1;
3169 }
3170
3171 amd_iommu_stats_init();
3172
3173 if (amd_iommu_unmap_flush)
3174 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3175 else
3176 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3177
3178 return 0;
3179
3180 free_domains:
3181
3182 for_each_iommu(iommu) {
3183 dma_ops_domain_free(iommu->default_dom);
3184 }
3185
3186 return ret;
3187 }
3188
3189 /*****************************************************************************
3190 *
3191 * The following functions belong to the exported interface of AMD IOMMU
3192 *
3193 * This interface allows access to lower level functions of the IOMMU
3194 * like protection domain handling and assignement of devices to domains
3195 * which is not possible with the dma_ops interface.
3196 *
3197 *****************************************************************************/
3198
3199 static void cleanup_domain(struct protection_domain *domain)
3200 {
3201 struct iommu_dev_data *entry;
3202 unsigned long flags;
3203
3204 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3205
3206 while (!list_empty(&domain->dev_list)) {
3207 entry = list_first_entry(&domain->dev_list,
3208 struct iommu_dev_data, list);
3209 __detach_device(entry);
3210 atomic_set(&entry->bind, 0);
3211 }
3212
3213 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3214 }
3215
3216 static void protection_domain_free(struct protection_domain *domain)
3217 {
3218 if (!domain)
3219 return;
3220
3221 del_domain_from_list(domain);
3222
3223 if (domain->id)
3224 domain_id_free(domain->id);
3225
3226 kfree(domain);
3227 }
3228
3229 static struct protection_domain *protection_domain_alloc(void)
3230 {
3231 struct protection_domain *domain;
3232
3233 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3234 if (!domain)
3235 return NULL;
3236
3237 spin_lock_init(&domain->lock);
3238 mutex_init(&domain->api_lock);
3239 domain->id = domain_id_alloc();
3240 if (!domain->id)
3241 goto out_err;
3242 INIT_LIST_HEAD(&domain->dev_list);
3243
3244 add_domain_to_list(domain);
3245
3246 return domain;
3247
3248 out_err:
3249 kfree(domain);
3250
3251 return NULL;
3252 }
3253
3254 static int __init alloc_passthrough_domain(void)
3255 {
3256 if (pt_domain != NULL)
3257 return 0;
3258
3259 /* allocate passthrough domain */
3260 pt_domain = protection_domain_alloc();
3261 if (!pt_domain)
3262 return -ENOMEM;
3263
3264 pt_domain->mode = PAGE_MODE_NONE;
3265
3266 return 0;
3267 }
3268 static int amd_iommu_domain_init(struct iommu_domain *dom)
3269 {
3270 struct protection_domain *domain;
3271
3272 domain = protection_domain_alloc();
3273 if (!domain)
3274 goto out_free;
3275
3276 domain->mode = PAGE_MODE_3_LEVEL;
3277 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3278 if (!domain->pt_root)
3279 goto out_free;
3280
3281 domain->iommu_domain = dom;
3282
3283 dom->priv = domain;
3284
3285 dom->geometry.aperture_start = 0;
3286 dom->geometry.aperture_end = ~0ULL;
3287 dom->geometry.force_aperture = true;
3288
3289 return 0;
3290
3291 out_free:
3292 protection_domain_free(domain);
3293
3294 return -ENOMEM;
3295 }
3296
3297 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3298 {
3299 struct protection_domain *domain = dom->priv;
3300
3301 if (!domain)
3302 return;
3303
3304 if (domain->dev_cnt > 0)
3305 cleanup_domain(domain);
3306
3307 BUG_ON(domain->dev_cnt != 0);
3308
3309 if (domain->mode != PAGE_MODE_NONE)
3310 free_pagetable(domain);
3311
3312 if (domain->flags & PD_IOMMUV2_MASK)
3313 free_gcr3_table(domain);
3314
3315 protection_domain_free(domain);
3316
3317 dom->priv = NULL;
3318 }
3319
3320 static void amd_iommu_detach_device(struct iommu_domain *dom,
3321 struct device *dev)
3322 {
3323 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3324 struct amd_iommu *iommu;
3325 u16 devid;
3326
3327 if (!check_device(dev))
3328 return;
3329
3330 devid = get_device_id(dev);
3331
3332 if (dev_data->domain != NULL)
3333 detach_device(dev);
3334
3335 iommu = amd_iommu_rlookup_table[devid];
3336 if (!iommu)
3337 return;
3338
3339 iommu_completion_wait(iommu);
3340 }
3341
3342 static int amd_iommu_attach_device(struct iommu_domain *dom,
3343 struct device *dev)
3344 {
3345 struct protection_domain *domain = dom->priv;
3346 struct iommu_dev_data *dev_data;
3347 struct amd_iommu *iommu;
3348 int ret;
3349
3350 if (!check_device(dev))
3351 return -EINVAL;
3352
3353 dev_data = dev->archdata.iommu;
3354
3355 iommu = amd_iommu_rlookup_table[dev_data->devid];
3356 if (!iommu)
3357 return -EINVAL;
3358
3359 if (dev_data->domain)
3360 detach_device(dev);
3361
3362 ret = attach_device(dev, domain);
3363
3364 iommu_completion_wait(iommu);
3365
3366 return ret;
3367 }
3368
3369 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3370 phys_addr_t paddr, size_t page_size, int iommu_prot)
3371 {
3372 struct protection_domain *domain = dom->priv;
3373 int prot = 0;
3374 int ret;
3375
3376 if (domain->mode == PAGE_MODE_NONE)
3377 return -EINVAL;
3378
3379 if (iommu_prot & IOMMU_READ)
3380 prot |= IOMMU_PROT_IR;
3381 if (iommu_prot & IOMMU_WRITE)
3382 prot |= IOMMU_PROT_IW;
3383
3384 mutex_lock(&domain->api_lock);
3385 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3386 mutex_unlock(&domain->api_lock);
3387
3388 return ret;
3389 }
3390
3391 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3392 size_t page_size)
3393 {
3394 struct protection_domain *domain = dom->priv;
3395 size_t unmap_size;
3396
3397 if (domain->mode == PAGE_MODE_NONE)
3398 return -EINVAL;
3399
3400 mutex_lock(&domain->api_lock);
3401 unmap_size = iommu_unmap_page(domain, iova, page_size);
3402 mutex_unlock(&domain->api_lock);
3403
3404 domain_flush_tlb_pde(domain);
3405 domain_flush_complete(domain);
3406
3407 return unmap_size;
3408 }
3409
3410 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3411 dma_addr_t iova)
3412 {
3413 struct protection_domain *domain = dom->priv;
3414 unsigned long offset_mask;
3415 phys_addr_t paddr;
3416 u64 *pte, __pte;
3417
3418 if (domain->mode == PAGE_MODE_NONE)
3419 return iova;
3420
3421 pte = fetch_pte(domain, iova);
3422
3423 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3424 return 0;
3425
3426 if (PM_PTE_LEVEL(*pte) == 0)
3427 offset_mask = PAGE_SIZE - 1;
3428 else
3429 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3430
3431 __pte = *pte & PM_ADDR_MASK;
3432 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3433
3434 return paddr;
3435 }
3436
3437 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3438 unsigned long cap)
3439 {
3440 switch (cap) {
3441 case IOMMU_CAP_CACHE_COHERENCY:
3442 return 1;
3443 case IOMMU_CAP_INTR_REMAP:
3444 return irq_remapping_enabled;
3445 }
3446
3447 return 0;
3448 }
3449
3450 static struct iommu_ops amd_iommu_ops = {
3451 .domain_init = amd_iommu_domain_init,
3452 .domain_destroy = amd_iommu_domain_destroy,
3453 .attach_dev = amd_iommu_attach_device,
3454 .detach_dev = amd_iommu_detach_device,
3455 .map = amd_iommu_map,
3456 .unmap = amd_iommu_unmap,
3457 .iova_to_phys = amd_iommu_iova_to_phys,
3458 .domain_has_cap = amd_iommu_domain_has_cap,
3459 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3460 };
3461
3462 /*****************************************************************************
3463 *
3464 * The next functions do a basic initialization of IOMMU for pass through
3465 * mode
3466 *
3467 * In passthrough mode the IOMMU is initialized and enabled but not used for
3468 * DMA-API translation.
3469 *
3470 *****************************************************************************/
3471
3472 int __init amd_iommu_init_passthrough(void)
3473 {
3474 struct iommu_dev_data *dev_data;
3475 struct pci_dev *dev = NULL;
3476 struct amd_iommu *iommu;
3477 u16 devid;
3478 int ret;
3479
3480 ret = alloc_passthrough_domain();
3481 if (ret)
3482 return ret;
3483
3484 for_each_pci_dev(dev) {
3485 if (!check_device(&dev->dev))
3486 continue;
3487
3488 dev_data = get_dev_data(&dev->dev);
3489 dev_data->passthrough = true;
3490
3491 devid = get_device_id(&dev->dev);
3492
3493 iommu = amd_iommu_rlookup_table[devid];
3494 if (!iommu)
3495 continue;
3496
3497 attach_device(&dev->dev, pt_domain);
3498 }
3499
3500 amd_iommu_stats_init();
3501
3502 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3503
3504 return 0;
3505 }
3506
3507 /* IOMMUv2 specific functions */
3508 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3509 {
3510 return atomic_notifier_chain_register(&ppr_notifier, nb);
3511 }
3512 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3513
3514 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3515 {
3516 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3517 }
3518 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3519
3520 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3521 {
3522 struct protection_domain *domain = dom->priv;
3523 unsigned long flags;
3524
3525 spin_lock_irqsave(&domain->lock, flags);
3526
3527 /* Update data structure */
3528 domain->mode = PAGE_MODE_NONE;
3529 domain->updated = true;
3530
3531 /* Make changes visible to IOMMUs */
3532 update_domain(domain);
3533
3534 /* Page-table is not visible to IOMMU anymore, so free it */
3535 free_pagetable(domain);
3536
3537 spin_unlock_irqrestore(&domain->lock, flags);
3538 }
3539 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3540
3541 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3542 {
3543 struct protection_domain *domain = dom->priv;
3544 unsigned long flags;
3545 int levels, ret;
3546
3547 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3548 return -EINVAL;
3549
3550 /* Number of GCR3 table levels required */
3551 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3552 levels += 1;
3553
3554 if (levels > amd_iommu_max_glx_val)
3555 return -EINVAL;
3556
3557 spin_lock_irqsave(&domain->lock, flags);
3558
3559 /*
3560 * Save us all sanity checks whether devices already in the
3561 * domain support IOMMUv2. Just force that the domain has no
3562 * devices attached when it is switched into IOMMUv2 mode.
3563 */
3564 ret = -EBUSY;
3565 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3566 goto out;
3567
3568 ret = -ENOMEM;
3569 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3570 if (domain->gcr3_tbl == NULL)
3571 goto out;
3572
3573 domain->glx = levels;
3574 domain->flags |= PD_IOMMUV2_MASK;
3575 domain->updated = true;
3576
3577 update_domain(domain);
3578
3579 ret = 0;
3580
3581 out:
3582 spin_unlock_irqrestore(&domain->lock, flags);
3583
3584 return ret;
3585 }
3586 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3587
3588 static int __flush_pasid(struct protection_domain *domain, int pasid,
3589 u64 address, bool size)
3590 {
3591 struct iommu_dev_data *dev_data;
3592 struct iommu_cmd cmd;
3593 int i, ret;
3594
3595 if (!(domain->flags & PD_IOMMUV2_MASK))
3596 return -EINVAL;
3597
3598 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3599
3600 /*
3601 * IOMMU TLB needs to be flushed before Device TLB to
3602 * prevent device TLB refill from IOMMU TLB
3603 */
3604 for (i = 0; i < amd_iommus_present; ++i) {
3605 if (domain->dev_iommu[i] == 0)
3606 continue;
3607
3608 ret = iommu_queue_command(amd_iommus[i], &cmd);
3609 if (ret != 0)
3610 goto out;
3611 }
3612
3613 /* Wait until IOMMU TLB flushes are complete */
3614 domain_flush_complete(domain);
3615
3616 /* Now flush device TLBs */
3617 list_for_each_entry(dev_data, &domain->dev_list, list) {
3618 struct amd_iommu *iommu;
3619 int qdep;
3620
3621 BUG_ON(!dev_data->ats.enabled);
3622
3623 qdep = dev_data->ats.qdep;
3624 iommu = amd_iommu_rlookup_table[dev_data->devid];
3625
3626 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3627 qdep, address, size);
3628
3629 ret = iommu_queue_command(iommu, &cmd);
3630 if (ret != 0)
3631 goto out;
3632 }
3633
3634 /* Wait until all device TLBs are flushed */
3635 domain_flush_complete(domain);
3636
3637 ret = 0;
3638
3639 out:
3640
3641 return ret;
3642 }
3643
3644 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3645 u64 address)
3646 {
3647 INC_STATS_COUNTER(invalidate_iotlb);
3648
3649 return __flush_pasid(domain, pasid, address, false);
3650 }
3651
3652 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3653 u64 address)
3654 {
3655 struct protection_domain *domain = dom->priv;
3656 unsigned long flags;
3657 int ret;
3658
3659 spin_lock_irqsave(&domain->lock, flags);
3660 ret = __amd_iommu_flush_page(domain, pasid, address);
3661 spin_unlock_irqrestore(&domain->lock, flags);
3662
3663 return ret;
3664 }
3665 EXPORT_SYMBOL(amd_iommu_flush_page);
3666
3667 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3668 {
3669 INC_STATS_COUNTER(invalidate_iotlb_all);
3670
3671 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3672 true);
3673 }
3674
3675 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3676 {
3677 struct protection_domain *domain = dom->priv;
3678 unsigned long flags;
3679 int ret;
3680
3681 spin_lock_irqsave(&domain->lock, flags);
3682 ret = __amd_iommu_flush_tlb(domain, pasid);
3683 spin_unlock_irqrestore(&domain->lock, flags);
3684
3685 return ret;
3686 }
3687 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3688
3689 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3690 {
3691 int index;
3692 u64 *pte;
3693
3694 while (true) {
3695
3696 index = (pasid >> (9 * level)) & 0x1ff;
3697 pte = &root[index];
3698
3699 if (level == 0)
3700 break;
3701
3702 if (!(*pte & GCR3_VALID)) {
3703 if (!alloc)
3704 return NULL;
3705
3706 root = (void *)get_zeroed_page(GFP_ATOMIC);
3707 if (root == NULL)
3708 return NULL;
3709
3710 *pte = __pa(root) | GCR3_VALID;
3711 }
3712
3713 root = __va(*pte & PAGE_MASK);
3714
3715 level -= 1;
3716 }
3717
3718 return pte;
3719 }
3720
3721 static int __set_gcr3(struct protection_domain *domain, int pasid,
3722 unsigned long cr3)
3723 {
3724 u64 *pte;
3725
3726 if (domain->mode != PAGE_MODE_NONE)
3727 return -EINVAL;
3728
3729 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3730 if (pte == NULL)
3731 return -ENOMEM;
3732
3733 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3734
3735 return __amd_iommu_flush_tlb(domain, pasid);
3736 }
3737
3738 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3739 {
3740 u64 *pte;
3741
3742 if (domain->mode != PAGE_MODE_NONE)
3743 return -EINVAL;
3744
3745 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3746 if (pte == NULL)
3747 return 0;
3748
3749 *pte = 0;
3750
3751 return __amd_iommu_flush_tlb(domain, pasid);
3752 }
3753
3754 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3755 unsigned long cr3)
3756 {
3757 struct protection_domain *domain = dom->priv;
3758 unsigned long flags;
3759 int ret;
3760
3761 spin_lock_irqsave(&domain->lock, flags);
3762 ret = __set_gcr3(domain, pasid, cr3);
3763 spin_unlock_irqrestore(&domain->lock, flags);
3764
3765 return ret;
3766 }
3767 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3768
3769 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3770 {
3771 struct protection_domain *domain = dom->priv;
3772 unsigned long flags;
3773 int ret;
3774
3775 spin_lock_irqsave(&domain->lock, flags);
3776 ret = __clear_gcr3(domain, pasid);
3777 spin_unlock_irqrestore(&domain->lock, flags);
3778
3779 return ret;
3780 }
3781 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3782
3783 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3784 int status, int tag)
3785 {
3786 struct iommu_dev_data *dev_data;
3787 struct amd_iommu *iommu;
3788 struct iommu_cmd cmd;
3789
3790 INC_STATS_COUNTER(complete_ppr);
3791
3792 dev_data = get_dev_data(&pdev->dev);
3793 iommu = amd_iommu_rlookup_table[dev_data->devid];
3794
3795 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3796 tag, dev_data->pri_tlp);
3797
3798 return iommu_queue_command(iommu, &cmd);
3799 }
3800 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3801
3802 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3803 {
3804 struct protection_domain *domain;
3805
3806 domain = get_domain(&pdev->dev);
3807 if (IS_ERR(domain))
3808 return NULL;
3809
3810 /* Only return IOMMUv2 domains */
3811 if (!(domain->flags & PD_IOMMUV2_MASK))
3812 return NULL;
3813
3814 return domain->iommu_domain;
3815 }
3816 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3817
3818 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3819 {
3820 struct iommu_dev_data *dev_data;
3821
3822 if (!amd_iommu_v2_supported())
3823 return;
3824
3825 dev_data = get_dev_data(&pdev->dev);
3826 dev_data->errata |= (1 << erratum);
3827 }
3828 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3829
3830 int amd_iommu_device_info(struct pci_dev *pdev,
3831 struct amd_iommu_device_info *info)
3832 {
3833 int max_pasids;
3834 int pos;
3835
3836 if (pdev == NULL || info == NULL)
3837 return -EINVAL;
3838
3839 if (!amd_iommu_v2_supported())
3840 return -EINVAL;
3841
3842 memset(info, 0, sizeof(*info));
3843
3844 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3845 if (pos)
3846 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3847
3848 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3849 if (pos)
3850 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3851
3852 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3853 if (pos) {
3854 int features;
3855
3856 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3857 max_pasids = min(max_pasids, (1 << 20));
3858
3859 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3860 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3861
3862 features = pci_pasid_features(pdev);
3863 if (features & PCI_PASID_CAP_EXEC)
3864 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3865 if (features & PCI_PASID_CAP_PRIV)
3866 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3867 }
3868
3869 return 0;
3870 }
3871 EXPORT_SYMBOL(amd_iommu_device_info);
3872
3873 #ifdef CONFIG_IRQ_REMAP
3874
3875 /*****************************************************************************
3876 *
3877 * Interrupt Remapping Implementation
3878 *
3879 *****************************************************************************/
3880
3881 union irte {
3882 u32 val;
3883 struct {
3884 u32 valid : 1,
3885 no_fault : 1,
3886 int_type : 3,
3887 rq_eoi : 1,
3888 dm : 1,
3889 rsvd_1 : 1,
3890 destination : 8,
3891 vector : 8,
3892 rsvd_2 : 8;
3893 } fields;
3894 };
3895
3896 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3897 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3898 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3899 #define DTE_IRQ_REMAP_ENABLE 1ULL
3900
3901 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3902 {
3903 u64 dte;
3904
3905 dte = amd_iommu_dev_table[devid].data[2];
3906 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3907 dte |= virt_to_phys(table->table);
3908 dte |= DTE_IRQ_REMAP_INTCTL;
3909 dte |= DTE_IRQ_TABLE_LEN;
3910 dte |= DTE_IRQ_REMAP_ENABLE;
3911
3912 amd_iommu_dev_table[devid].data[2] = dte;
3913 }
3914
3915 #define IRTE_ALLOCATED (~1U)
3916
3917 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3918 {
3919 struct irq_remap_table *table = NULL;
3920 struct amd_iommu *iommu;
3921 unsigned long flags;
3922 u16 alias;
3923
3924 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3925
3926 iommu = amd_iommu_rlookup_table[devid];
3927 if (!iommu)
3928 goto out_unlock;
3929
3930 table = irq_lookup_table[devid];
3931 if (table)
3932 goto out;
3933
3934 alias = amd_iommu_alias_table[devid];
3935 table = irq_lookup_table[alias];
3936 if (table) {
3937 irq_lookup_table[devid] = table;
3938 set_dte_irq_entry(devid, table);
3939 iommu_flush_dte(iommu, devid);
3940 goto out;
3941 }
3942
3943 /* Nothing there yet, allocate new irq remapping table */
3944 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3945 if (!table)
3946 goto out;
3947
3948 /* Initialize table spin-lock */
3949 spin_lock_init(&table->lock);
3950
3951 if (ioapic)
3952 /* Keep the first 32 indexes free for IOAPIC interrupts */
3953 table->min_index = 32;
3954
3955 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3956 if (!table->table) {
3957 kfree(table);
3958 table = NULL;
3959 goto out;
3960 }
3961
3962 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3963
3964 if (ioapic) {
3965 int i;
3966
3967 for (i = 0; i < 32; ++i)
3968 table->table[i] = IRTE_ALLOCATED;
3969 }
3970
3971 irq_lookup_table[devid] = table;
3972 set_dte_irq_entry(devid, table);
3973 iommu_flush_dte(iommu, devid);
3974 if (devid != alias) {
3975 irq_lookup_table[alias] = table;
3976 set_dte_irq_entry(alias, table);
3977 iommu_flush_dte(iommu, alias);
3978 }
3979
3980 out:
3981 iommu_completion_wait(iommu);
3982
3983 out_unlock:
3984 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3985
3986 return table;
3987 }
3988
3989 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3990 {
3991 struct irq_remap_table *table;
3992 unsigned long flags;
3993 int index, c;
3994
3995 table = get_irq_table(devid, false);
3996 if (!table)
3997 return -ENODEV;
3998
3999 spin_lock_irqsave(&table->lock, flags);
4000
4001 /* Scan table for free entries */
4002 for (c = 0, index = table->min_index;
4003 index < MAX_IRQS_PER_TABLE;
4004 ++index) {
4005 if (table->table[index] == 0)
4006 c += 1;
4007 else
4008 c = 0;
4009
4010 if (c == count) {
4011 struct irq_2_irte *irte_info;
4012
4013 for (; c != 0; --c)
4014 table->table[index - c + 1] = IRTE_ALLOCATED;
4015
4016 index -= count - 1;
4017
4018 cfg->remapped = 1;
4019 irte_info = &cfg->irq_2_irte;
4020 irte_info->devid = devid;
4021 irte_info->index = index;
4022
4023 goto out;
4024 }
4025 }
4026
4027 index = -ENOSPC;
4028
4029 out:
4030 spin_unlock_irqrestore(&table->lock, flags);
4031
4032 return index;
4033 }
4034
4035 static int get_irte(u16 devid, int index, union irte *irte)
4036 {
4037 struct irq_remap_table *table;
4038 unsigned long flags;
4039
4040 table = get_irq_table(devid, false);
4041 if (!table)
4042 return -ENOMEM;
4043
4044 spin_lock_irqsave(&table->lock, flags);
4045 irte->val = table->table[index];
4046 spin_unlock_irqrestore(&table->lock, flags);
4047
4048 return 0;
4049 }
4050
4051 static int modify_irte(u16 devid, int index, union irte irte)
4052 {
4053 struct irq_remap_table *table;
4054 struct amd_iommu *iommu;
4055 unsigned long flags;
4056
4057 iommu = amd_iommu_rlookup_table[devid];
4058 if (iommu == NULL)
4059 return -EINVAL;
4060
4061 table = get_irq_table(devid, false);
4062 if (!table)
4063 return -ENOMEM;
4064
4065 spin_lock_irqsave(&table->lock, flags);
4066 table->table[index] = irte.val;
4067 spin_unlock_irqrestore(&table->lock, flags);
4068
4069 iommu_flush_irt(iommu, devid);
4070 iommu_completion_wait(iommu);
4071
4072 return 0;
4073 }
4074
4075 static void free_irte(u16 devid, int index)
4076 {
4077 struct irq_remap_table *table;
4078 struct amd_iommu *iommu;
4079 unsigned long flags;
4080
4081 iommu = amd_iommu_rlookup_table[devid];
4082 if (iommu == NULL)
4083 return;
4084
4085 table = get_irq_table(devid, false);
4086 if (!table)
4087 return;
4088
4089 spin_lock_irqsave(&table->lock, flags);
4090 table->table[index] = 0;
4091 spin_unlock_irqrestore(&table->lock, flags);
4092
4093 iommu_flush_irt(iommu, devid);
4094 iommu_completion_wait(iommu);
4095 }
4096
4097 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4098 unsigned int destination, int vector,
4099 struct io_apic_irq_attr *attr)
4100 {
4101 struct irq_remap_table *table;
4102 struct irq_2_irte *irte_info;
4103 struct irq_cfg *cfg;
4104 union irte irte;
4105 int ioapic_id;
4106 int index;
4107 int devid;
4108 int ret;
4109
4110 cfg = irq_get_chip_data(irq);
4111 if (!cfg)
4112 return -EINVAL;
4113
4114 irte_info = &cfg->irq_2_irte;
4115 ioapic_id = mpc_ioapic_id(attr->ioapic);
4116 devid = get_ioapic_devid(ioapic_id);
4117
4118 if (devid < 0)
4119 return devid;
4120
4121 table = get_irq_table(devid, true);
4122 if (table == NULL)
4123 return -ENOMEM;
4124
4125 index = attr->ioapic_pin;
4126
4127 /* Setup IRQ remapping info */
4128 cfg->remapped = 1;
4129 irte_info->devid = devid;
4130 irte_info->index = index;
4131
4132 /* Setup IRTE for IOMMU */
4133 irte.val = 0;
4134 irte.fields.vector = vector;
4135 irte.fields.int_type = apic->irq_delivery_mode;
4136 irte.fields.destination = destination;
4137 irte.fields.dm = apic->irq_dest_mode;
4138 irte.fields.valid = 1;
4139
4140 ret = modify_irte(devid, index, irte);
4141 if (ret)
4142 return ret;
4143
4144 /* Setup IOAPIC entry */
4145 memset(entry, 0, sizeof(*entry));
4146
4147 entry->vector = index;
4148 entry->mask = 0;
4149 entry->trigger = attr->trigger;
4150 entry->polarity = attr->polarity;
4151
4152 /*
4153 * Mask level triggered irqs.
4154 */
4155 if (attr->trigger)
4156 entry->mask = 1;
4157
4158 return 0;
4159 }
4160
4161 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4162 bool force)
4163 {
4164 struct irq_2_irte *irte_info;
4165 unsigned int dest, irq;
4166 struct irq_cfg *cfg;
4167 union irte irte;
4168 int err;
4169
4170 if (!config_enabled(CONFIG_SMP))
4171 return -1;
4172
4173 cfg = data->chip_data;
4174 irq = data->irq;
4175 irte_info = &cfg->irq_2_irte;
4176
4177 if (!cpumask_intersects(mask, cpu_online_mask))
4178 return -EINVAL;
4179
4180 if (get_irte(irte_info->devid, irte_info->index, &irte))
4181 return -EBUSY;
4182
4183 if (assign_irq_vector(irq, cfg, mask))
4184 return -EBUSY;
4185
4186 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4187 if (err) {
4188 if (assign_irq_vector(irq, cfg, data->affinity))
4189 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4190 return err;
4191 }
4192
4193 irte.fields.vector = cfg->vector;
4194 irte.fields.destination = dest;
4195
4196 modify_irte(irte_info->devid, irte_info->index, irte);
4197
4198 if (cfg->move_in_progress)
4199 send_cleanup_vector(cfg);
4200
4201 cpumask_copy(data->affinity, mask);
4202
4203 return 0;
4204 }
4205
4206 static int free_irq(int irq)
4207 {
4208 struct irq_2_irte *irte_info;
4209 struct irq_cfg *cfg;
4210
4211 cfg = irq_get_chip_data(irq);
4212 if (!cfg)
4213 return -EINVAL;
4214
4215 irte_info = &cfg->irq_2_irte;
4216
4217 free_irte(irte_info->devid, irte_info->index);
4218
4219 return 0;
4220 }
4221
4222 static void compose_msi_msg(struct pci_dev *pdev,
4223 unsigned int irq, unsigned int dest,
4224 struct msi_msg *msg, u8 hpet_id)
4225 {
4226 struct irq_2_irte *irte_info;
4227 struct irq_cfg *cfg;
4228 union irte irte;
4229
4230 cfg = irq_get_chip_data(irq);
4231 if (!cfg)
4232 return;
4233
4234 irte_info = &cfg->irq_2_irte;
4235
4236 irte.val = 0;
4237 irte.fields.vector = cfg->vector;
4238 irte.fields.int_type = apic->irq_delivery_mode;
4239 irte.fields.destination = dest;
4240 irte.fields.dm = apic->irq_dest_mode;
4241 irte.fields.valid = 1;
4242
4243 modify_irte(irte_info->devid, irte_info->index, irte);
4244
4245 msg->address_hi = MSI_ADDR_BASE_HI;
4246 msg->address_lo = MSI_ADDR_BASE_LO;
4247 msg->data = irte_info->index;
4248 }
4249
4250 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4251 {
4252 struct irq_cfg *cfg;
4253 int index;
4254 u16 devid;
4255
4256 if (!pdev)
4257 return -EINVAL;
4258
4259 cfg = irq_get_chip_data(irq);
4260 if (!cfg)
4261 return -EINVAL;
4262
4263 devid = get_device_id(&pdev->dev);
4264 index = alloc_irq_index(cfg, devid, nvec);
4265
4266 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4267 }
4268
4269 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4270 int index, int offset)
4271 {
4272 struct irq_2_irte *irte_info;
4273 struct irq_cfg *cfg;
4274 u16 devid;
4275
4276 if (!pdev)
4277 return -EINVAL;
4278
4279 cfg = irq_get_chip_data(irq);
4280 if (!cfg)
4281 return -EINVAL;
4282
4283 if (index >= MAX_IRQS_PER_TABLE)
4284 return 0;
4285
4286 devid = get_device_id(&pdev->dev);
4287 irte_info = &cfg->irq_2_irte;
4288
4289 cfg->remapped = 1;
4290 irte_info->devid = devid;
4291 irte_info->index = index + offset;
4292
4293 return 0;
4294 }
4295
4296 static int setup_hpet_msi(unsigned int irq, unsigned int id)
4297 {
4298 struct irq_2_irte *irte_info;
4299 struct irq_cfg *cfg;
4300 int index, devid;
4301
4302 cfg = irq_get_chip_data(irq);
4303 if (!cfg)
4304 return -EINVAL;
4305
4306 irte_info = &cfg->irq_2_irte;
4307 devid = get_hpet_devid(id);
4308 if (devid < 0)
4309 return devid;
4310
4311 index = alloc_irq_index(cfg, devid, 1);
4312 if (index < 0)
4313 return index;
4314
4315 cfg->remapped = 1;
4316 irte_info->devid = devid;
4317 irte_info->index = index;
4318
4319 return 0;
4320 }
4321
4322 struct irq_remap_ops amd_iommu_irq_ops = {
4323 .supported = amd_iommu_supported,
4324 .prepare = amd_iommu_prepare,
4325 .enable = amd_iommu_enable,
4326 .disable = amd_iommu_disable,
4327 .reenable = amd_iommu_reenable,
4328 .enable_faulting = amd_iommu_enable_faulting,
4329 .setup_ioapic_entry = setup_ioapic_entry,
4330 .set_affinity = set_affinity,
4331 .free_irq = free_irq,
4332 .compose_msi_msg = compose_msi_msg,
4333 .msi_alloc_irq = msi_alloc_irq,
4334 .msi_setup_irq = msi_setup_irq,
4335 .setup_hpet_msi = setup_hpet_msi,
4336 };
4337 #endif
kernel source for telekom puls (alcatel/mediatek)