2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/module.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/mwait.h>
68 #define INTEL_IDLE_VERSION "0.4"
69 #define PREFIX "intel_idle: "
71 static struct cpuidle_driver intel_idle_driver
= {
74 .en_core_tk_irqen
= 1,
76 /* intel_idle.max_cstate=0 disables driver */
77 static int max_cstate
= CPUIDLE_STATE_MAX
- 1;
79 static unsigned int mwait_substates
;
81 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
82 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
83 static unsigned int lapic_timer_reliable_states
= (1 << 1); /* Default to only C1 */
86 struct cpuidle_state
*state_table
;
89 * Hardware C-state auto-demotion may not always be optimal.
90 * Indicate which enable bits to clear here.
92 unsigned long auto_demotion_disable_flags
;
93 bool disable_promotion_to_c1e
;
96 static const struct idle_cpu
*icpu
;
97 static struct cpuidle_device __percpu
*intel_idle_cpuidle_devices
;
98 static int intel_idle(struct cpuidle_device
*dev
,
99 struct cpuidle_driver
*drv
, int index
);
100 static int intel_idle_cpu_init(int cpu
);
102 static struct cpuidle_state
*cpuidle_state_table
;
105 * Set this flag for states where the HW flushes the TLB for us
106 * and so we don't need cross-calls to keep it consistent.
107 * If this flag is set, SW flushes the TLB, so even if the
108 * HW doesn't do the flushing, this flag is safe to use.
110 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
113 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
114 * the C-state (top nibble) and sub-state (bottom nibble)
115 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
117 * We store the hint at the top of our "flags" for each state.
119 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
120 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
123 * States are indexed by the cstate number,
124 * which is also the index into the MWAIT hint array.
125 * Thus C0 is a dummy.
127 static struct cpuidle_state nehalem_cstates
[CPUIDLE_STATE_MAX
] = {
130 .desc
= "MWAIT 0x00",
131 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
133 .target_residency
= 6,
134 .enter
= &intel_idle
},
137 .desc
= "MWAIT 0x01",
138 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
140 .target_residency
= 20,
141 .enter
= &intel_idle
},
144 .desc
= "MWAIT 0x10",
145 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
147 .target_residency
= 80,
148 .enter
= &intel_idle
},
151 .desc
= "MWAIT 0x20",
152 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
154 .target_residency
= 800,
155 .enter
= &intel_idle
},
160 static struct cpuidle_state snb_cstates
[CPUIDLE_STATE_MAX
] = {
163 .desc
= "MWAIT 0x00",
164 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
166 .target_residency
= 2,
167 .enter
= &intel_idle
},
170 .desc
= "MWAIT 0x01",
171 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
173 .target_residency
= 20,
174 .enter
= &intel_idle
},
177 .desc
= "MWAIT 0x10",
178 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
180 .target_residency
= 211,
181 .enter
= &intel_idle
},
184 .desc
= "MWAIT 0x20",
185 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
187 .target_residency
= 345,
188 .enter
= &intel_idle
},
191 .desc
= "MWAIT 0x30",
192 .flags
= MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
194 .target_residency
= 345,
195 .enter
= &intel_idle
},
200 static struct cpuidle_state ivb_cstates
[CPUIDLE_STATE_MAX
] = {
203 .desc
= "MWAIT 0x00",
204 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
206 .target_residency
= 1,
207 .enter
= &intel_idle
},
210 .desc
= "MWAIT 0x01",
211 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
213 .target_residency
= 20,
214 .enter
= &intel_idle
},
217 .desc
= "MWAIT 0x10",
218 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
220 .target_residency
= 156,
221 .enter
= &intel_idle
},
224 .desc
= "MWAIT 0x20",
225 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
227 .target_residency
= 300,
228 .enter
= &intel_idle
},
231 .desc
= "MWAIT 0x30",
232 .flags
= MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
234 .target_residency
= 300,
235 .enter
= &intel_idle
},
240 static struct cpuidle_state hsw_cstates
[CPUIDLE_STATE_MAX
] = {
243 .desc
= "MWAIT 0x00",
244 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
246 .target_residency
= 2,
247 .enter
= &intel_idle
},
250 .desc
= "MWAIT 0x01",
251 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
253 .target_residency
= 20,
254 .enter
= &intel_idle
},
257 .desc
= "MWAIT 0x10",
258 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
260 .target_residency
= 100,
261 .enter
= &intel_idle
},
264 .desc
= "MWAIT 0x20",
265 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
267 .target_residency
= 400,
268 .enter
= &intel_idle
},
271 .desc
= "MWAIT 0x32",
272 .flags
= MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
274 .target_residency
= 500,
275 .enter
= &intel_idle
},
280 static struct cpuidle_state atom_cstates
[CPUIDLE_STATE_MAX
] = {
283 .desc
= "MWAIT 0x00",
284 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
286 .target_residency
= 20,
287 .enter
= &intel_idle
},
290 .desc
= "MWAIT 0x10",
291 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
,
293 .target_residency
= 80,
294 .enter
= &intel_idle
},
297 .desc
= "MWAIT 0x30",
298 .flags
= MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
300 .target_residency
= 400,
301 .enter
= &intel_idle
},
304 .desc
= "MWAIT 0x52",
305 .flags
= MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
307 .target_residency
= 560,
308 .enter
= &intel_idle
},
315 * @dev: cpuidle_device
316 * @drv: cpuidle driver
317 * @index: index of cpuidle state
319 * Must be called under local_irq_disable().
321 static int intel_idle(struct cpuidle_device
*dev
,
322 struct cpuidle_driver
*drv
, int index
)
324 unsigned long ecx
= 1; /* break on interrupt flag */
325 struct cpuidle_state
*state
= &drv
->states
[index
];
326 unsigned long eax
= flg2MWAIT(state
->flags
);
328 int cpu
= smp_processor_id();
330 cstate
= (((eax
) >> MWAIT_SUBSTATE_SIZE
) & MWAIT_CSTATE_MASK
) + 1;
333 * leave_mm() to avoid costly and often unnecessary wakeups
334 * for flushing the user TLB's associated with the active mm.
336 if (state
->flags
& CPUIDLE_FLAG_TLB_FLUSHED
)
339 if (!(lapic_timer_reliable_states
& (1 << (cstate
))))
340 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
342 stop_critical_timings();
343 if (!need_resched()) {
345 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
351 start_critical_timings();
353 if (!(lapic_timer_reliable_states
& (1 << (cstate
))))
354 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
359 static void __setup_broadcast_timer(void *arg
)
361 unsigned long reason
= (unsigned long)arg
;
362 int cpu
= smp_processor_id();
365 CLOCK_EVT_NOTIFY_BROADCAST_ON
: CLOCK_EVT_NOTIFY_BROADCAST_OFF
;
367 clockevents_notify(reason
, &cpu
);
370 static int cpu_hotplug_notify(struct notifier_block
*n
,
371 unsigned long action
, void *hcpu
)
373 int hotcpu
= (unsigned long)hcpu
;
374 struct cpuidle_device
*dev
;
376 switch (action
& 0xf) {
379 if (lapic_timer_reliable_states
!= LAPIC_TIMER_ALWAYS_RELIABLE
)
380 smp_call_function_single(hotcpu
, __setup_broadcast_timer
,
384 * Some systems can hotplug a cpu at runtime after
385 * the kernel has booted, we have to initialize the
386 * driver in this case
388 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, hotcpu
);
389 if (!dev
->registered
)
390 intel_idle_cpu_init(hotcpu
);
397 static struct notifier_block cpu_hotplug_notifier
= {
398 .notifier_call
= cpu_hotplug_notify
,
401 static void auto_demotion_disable(void *dummy
)
403 unsigned long long msr_bits
;
405 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL
, msr_bits
);
406 msr_bits
&= ~(icpu
->auto_demotion_disable_flags
);
407 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL
, msr_bits
);
409 static void c1e_promotion_disable(void *dummy
)
411 unsigned long long msr_bits
;
413 rdmsrl(MSR_IA32_POWER_CTL
, msr_bits
);
415 wrmsrl(MSR_IA32_POWER_CTL
, msr_bits
);
418 static const struct idle_cpu idle_cpu_nehalem
= {
419 .state_table
= nehalem_cstates
,
420 .auto_demotion_disable_flags
= NHM_C1_AUTO_DEMOTE
| NHM_C3_AUTO_DEMOTE
,
421 .disable_promotion_to_c1e
= true,
424 static const struct idle_cpu idle_cpu_atom
= {
425 .state_table
= atom_cstates
,
428 static const struct idle_cpu idle_cpu_lincroft
= {
429 .state_table
= atom_cstates
,
430 .auto_demotion_disable_flags
= ATM_LNC_C6_AUTO_DEMOTE
,
433 static const struct idle_cpu idle_cpu_snb
= {
434 .state_table
= snb_cstates
,
435 .disable_promotion_to_c1e
= true,
438 static const struct idle_cpu idle_cpu_ivb
= {
439 .state_table
= ivb_cstates
,
440 .disable_promotion_to_c1e
= true,
443 static const struct idle_cpu idle_cpu_hsw
= {
444 .state_table
= hsw_cstates
,
445 .disable_promotion_to_c1e
= true,
448 #define ICPU(model, cpu) \
449 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
451 static const struct x86_cpu_id intel_idle_ids
[] = {
452 ICPU(0x1a, idle_cpu_nehalem
),
453 ICPU(0x1e, idle_cpu_nehalem
),
454 ICPU(0x1f, idle_cpu_nehalem
),
455 ICPU(0x25, idle_cpu_nehalem
),
456 ICPU(0x2c, idle_cpu_nehalem
),
457 ICPU(0x2e, idle_cpu_nehalem
),
458 ICPU(0x1c, idle_cpu_atom
),
459 ICPU(0x26, idle_cpu_lincroft
),
460 ICPU(0x2f, idle_cpu_nehalem
),
461 ICPU(0x2a, idle_cpu_snb
),
462 ICPU(0x2d, idle_cpu_snb
),
463 ICPU(0x3a, idle_cpu_ivb
),
464 ICPU(0x3e, idle_cpu_ivb
),
465 ICPU(0x3c, idle_cpu_hsw
),
466 ICPU(0x3f, idle_cpu_hsw
),
467 ICPU(0x45, idle_cpu_hsw
),
470 MODULE_DEVICE_TABLE(x86cpu
, intel_idle_ids
);
475 static int intel_idle_probe(void)
477 unsigned int eax
, ebx
, ecx
;
478 const struct x86_cpu_id
*id
;
480 if (max_cstate
== 0) {
481 pr_debug(PREFIX
"disabled\n");
485 id
= x86_match_cpu(intel_idle_ids
);
487 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
488 boot_cpu_data
.x86
== 6)
489 pr_debug(PREFIX
"does not run on family %d model %d\n",
490 boot_cpu_data
.x86
, boot_cpu_data
.x86_model
);
494 if (boot_cpu_data
.cpuid_level
< CPUID_MWAIT_LEAF
)
497 cpuid(CPUID_MWAIT_LEAF
, &eax
, &ebx
, &ecx
, &mwait_substates
);
499 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
) ||
500 !(ecx
& CPUID5_ECX_INTERRUPT_BREAK
) ||
504 pr_debug(PREFIX
"MWAIT substates: 0x%x\n", mwait_substates
);
506 icpu
= (const struct idle_cpu
*)id
->driver_data
;
507 cpuidle_state_table
= icpu
->state_table
;
509 if (boot_cpu_has(X86_FEATURE_ARAT
)) /* Always Reliable APIC Timer */
510 lapic_timer_reliable_states
= LAPIC_TIMER_ALWAYS_RELIABLE
;
512 on_each_cpu(__setup_broadcast_timer
, (void *)true, 1);
514 pr_debug(PREFIX
"v" INTEL_IDLE_VERSION
515 " model 0x%X\n", boot_cpu_data
.x86_model
);
517 pr_debug(PREFIX
"lapic_timer_reliable_states 0x%x\n",
518 lapic_timer_reliable_states
);
523 * intel_idle_cpuidle_devices_uninit()
524 * unregister, free cpuidle_devices
526 static void intel_idle_cpuidle_devices_uninit(void)
529 struct cpuidle_device
*dev
;
531 for_each_online_cpu(i
) {
532 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, i
);
533 cpuidle_unregister_device(dev
);
536 free_percpu(intel_idle_cpuidle_devices
);
540 * intel_idle_cpuidle_driver_init()
541 * allocate, initialize cpuidle_states
543 static int intel_idle_cpuidle_driver_init(void)
546 struct cpuidle_driver
*drv
= &intel_idle_driver
;
548 drv
->state_count
= 1;
550 for (cstate
= 0; cstate
< CPUIDLE_STATE_MAX
; ++cstate
) {
551 int num_substates
, mwait_hint
, mwait_cstate
, mwait_substate
;
553 if (cpuidle_state_table
[cstate
].enter
== NULL
)
556 if (cstate
+ 1 > max_cstate
) {
557 printk(PREFIX
"max_cstate %d reached\n",
562 mwait_hint
= flg2MWAIT(cpuidle_state_table
[cstate
].flags
);
563 mwait_cstate
= MWAIT_HINT2CSTATE(mwait_hint
);
564 mwait_substate
= MWAIT_HINT2SUBSTATE(mwait_hint
);
566 /* does the state exist in CPUID.MWAIT? */
567 num_substates
= (mwait_substates
>> ((mwait_cstate
+ 1) * 4))
568 & MWAIT_SUBSTATE_MASK
;
570 /* if sub-state in table is not enumerated by CPUID */
571 if ((mwait_substate
+ 1) > num_substates
)
574 if (((mwait_cstate
+ 1) > 2) &&
575 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
576 mark_tsc_unstable("TSC halts in idle"
577 " states deeper than C2");
579 drv
->states
[drv
->state_count
] = /* structure copy */
580 cpuidle_state_table
[cstate
];
582 drv
->state_count
+= 1;
585 if (icpu
->auto_demotion_disable_flags
)
586 on_each_cpu(auto_demotion_disable
, NULL
, 1);
588 if (icpu
->disable_promotion_to_c1e
) /* each-cpu is redundant */
589 on_each_cpu(c1e_promotion_disable
, NULL
, 1);
596 * intel_idle_cpu_init()
597 * allocate, initialize, register cpuidle_devices
598 * @cpu: cpu/core to initialize
600 static int intel_idle_cpu_init(int cpu
)
603 struct cpuidle_device
*dev
;
605 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, cpu
);
607 dev
->state_count
= 1;
609 for (cstate
= 0; cstate
< CPUIDLE_STATE_MAX
; ++cstate
) {
610 int num_substates
, mwait_hint
, mwait_cstate
, mwait_substate
;
612 if (cpuidle_state_table
[cstate
].enter
== NULL
)
615 if (cstate
+ 1 > max_cstate
) {
616 printk(PREFIX
"max_cstate %d reached\n", max_cstate
);
620 mwait_hint
= flg2MWAIT(cpuidle_state_table
[cstate
].flags
);
621 mwait_cstate
= MWAIT_HINT2CSTATE(mwait_hint
);
622 mwait_substate
= MWAIT_HINT2SUBSTATE(mwait_hint
);
624 /* does the state exist in CPUID.MWAIT? */
625 num_substates
= (mwait_substates
>> ((mwait_cstate
+ 1) * 4))
626 & MWAIT_SUBSTATE_MASK
;
628 /* if sub-state in table is not enumerated by CPUID */
629 if ((mwait_substate
+ 1) > num_substates
)
632 dev
->state_count
+= 1;
637 if (cpuidle_register_device(dev
)) {
638 pr_debug(PREFIX
"cpuidle_register_device %d failed!\n", cpu
);
639 intel_idle_cpuidle_devices_uninit();
643 if (icpu
->auto_demotion_disable_flags
)
644 smp_call_function_single(cpu
, auto_demotion_disable
, NULL
, 1);
649 static int __init
intel_idle_init(void)
653 /* Do not load intel_idle at all for now if idle= is passed */
654 if (boot_option_idle_override
!= IDLE_NO_OVERRIDE
)
657 retval
= intel_idle_probe();
661 intel_idle_cpuidle_driver_init();
662 retval
= cpuidle_register_driver(&intel_idle_driver
);
664 struct cpuidle_driver
*drv
= cpuidle_get_driver();
665 printk(KERN_DEBUG PREFIX
"intel_idle yielding to %s",
666 drv
? drv
->name
: "none");
670 intel_idle_cpuidle_devices
= alloc_percpu(struct cpuidle_device
);
671 if (intel_idle_cpuidle_devices
== NULL
)
674 for_each_online_cpu(i
) {
675 retval
= intel_idle_cpu_init(i
);
677 cpuidle_unregister_driver(&intel_idle_driver
);
681 register_cpu_notifier(&cpu_hotplug_notifier
);
686 static void __exit
intel_idle_exit(void)
688 intel_idle_cpuidle_devices_uninit();
689 cpuidle_unregister_driver(&intel_idle_driver
);
692 if (lapic_timer_reliable_states
!= LAPIC_TIMER_ALWAYS_RELIABLE
)
693 on_each_cpu(__setup_broadcast_timer
, (void *)false, 1);
694 unregister_cpu_notifier(&cpu_hotplug_notifier
);
699 module_init(intel_idle_init
);
700 module_exit(intel_idle_exit
);
702 module_param(max_cstate
, int, 0444);
704 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
705 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION
);
706 MODULE_LICENSE("GPL");