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ARM: mxs: icoll: Fix interrupts gpio bank 0
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61
62 Features supported by this driver:
63 Software PEC no
64 Hardware PEC yes
65 Block buffer yes
66 Block process call transaction no
67 I2C block read transaction yes (doesn't use the block buffer)
68 Slave mode no
69 Interrupt processing yes
70
71 See the file Documentation/i2c/busses/i2c-i801 for details.
72 */
73
74 #include <linux/interrupt.h>
75 #include <linux/module.h>
76 #include <linux/pci.h>
77 #include <linux/kernel.h>
78 #include <linux/stddef.h>
79 #include <linux/delay.h>
80 #include <linux/ioport.h>
81 #include <linux/init.h>
82 #include <linux/i2c.h>
83 #include <linux/acpi.h>
84 #include <linux/io.h>
85 #include <linux/dmi.h>
86 #include <linux/slab.h>
87 #include <linux/wait.h>
88 #include <linux/err.h>
89 #include <linux/of_i2c.h>
90
91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
92 defined CONFIG_DMI
93 #include <linux/gpio.h>
94 #include <linux/i2c-mux-gpio.h>
95 #include <linux/platform_device.h>
96 #endif
97
98 /* I801 SMBus address offsets */
99 #define SMBHSTSTS(p) (0 + (p)->smba)
100 #define SMBHSTCNT(p) (2 + (p)->smba)
101 #define SMBHSTCMD(p) (3 + (p)->smba)
102 #define SMBHSTADD(p) (4 + (p)->smba)
103 #define SMBHSTDAT0(p) (5 + (p)->smba)
104 #define SMBHSTDAT1(p) (6 + (p)->smba)
105 #define SMBBLKDAT(p) (7 + (p)->smba)
106 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
107 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
108 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
109
110 /* PCI Address Constants */
111 #define SMBBAR 4
112 #define SMBPCISTS 0x006
113 #define SMBHSTCFG 0x040
114
115 /* Host status bits for SMBPCISTS */
116 #define SMBPCISTS_INTS 0x08
117
118 /* Host configuration bits for SMBHSTCFG */
119 #define SMBHSTCFG_HST_EN 1
120 #define SMBHSTCFG_SMB_SMI_EN 2
121 #define SMBHSTCFG_I2C_EN 4
122
123 /* Auxiliary control register bits, ICH4+ only */
124 #define SMBAUXCTL_CRC 1
125 #define SMBAUXCTL_E32B 2
126
127 /* Other settings */
128 #define MAX_RETRIES 400
129
130 /* I801 command constants */
131 #define I801_QUICK 0x00
132 #define I801_BYTE 0x04
133 #define I801_BYTE_DATA 0x08
134 #define I801_WORD_DATA 0x0C
135 #define I801_PROC_CALL 0x10 /* unimplemented */
136 #define I801_BLOCK_DATA 0x14
137 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
138
139 /* I801 Host Control register bits */
140 #define SMBHSTCNT_INTREN 0x01
141 #define SMBHSTCNT_KILL 0x02
142 #define SMBHSTCNT_LAST_BYTE 0x20
143 #define SMBHSTCNT_START 0x40
144 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
145
146 /* I801 Hosts Status register bits */
147 #define SMBHSTSTS_BYTE_DONE 0x80
148 #define SMBHSTSTS_INUSE_STS 0x40
149 #define SMBHSTSTS_SMBALERT_STS 0x20
150 #define SMBHSTSTS_FAILED 0x10
151 #define SMBHSTSTS_BUS_ERR 0x08
152 #define SMBHSTSTS_DEV_ERR 0x04
153 #define SMBHSTSTS_INTR 0x02
154 #define SMBHSTSTS_HOST_BUSY 0x01
155
156 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
157 SMBHSTSTS_DEV_ERR)
158
159 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
160 STATUS_ERROR_FLAGS)
161
162 /* Older devices have their ID defined in <linux/pci_ids.h> */
163 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
164 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
165 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
166 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
169 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
170 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
171 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
172 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
173 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
174 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
175 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
176 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
177 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
178 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
179
180 struct i801_mux_config {
181 char *gpio_chip;
182 unsigned values[3];
183 int n_values;
184 unsigned classes[3];
185 unsigned gpios[2]; /* Relative to gpio_chip->base */
186 int n_gpios;
187 };
188
189 struct i801_priv {
190 struct i2c_adapter adapter;
191 unsigned long smba;
192 unsigned char original_hstcfg;
193 struct pci_dev *pci_dev;
194 unsigned int features;
195
196 /* isr processing */
197 wait_queue_head_t waitq;
198 u8 status;
199
200 /* Command state used by isr for byte-by-byte block transactions */
201 u8 cmd;
202 bool is_read;
203 int count;
204 int len;
205 u8 *data;
206
207 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
208 defined CONFIG_DMI
209 const struct i801_mux_config *mux_drvdata;
210 struct platform_device *mux_pdev;
211 #endif
212 };
213
214 static struct pci_driver i801_driver;
215
216 #define FEATURE_SMBUS_PEC (1 << 0)
217 #define FEATURE_BLOCK_BUFFER (1 << 1)
218 #define FEATURE_BLOCK_PROC (1 << 2)
219 #define FEATURE_I2C_BLOCK_READ (1 << 3)
220 #define FEATURE_IRQ (1 << 4)
221 /* Not really a feature, but it's convenient to handle it as such */
222 #define FEATURE_IDF (1 << 15)
223
224 static const char *i801_feature_names[] = {
225 "SMBus PEC",
226 "Block buffer",
227 "Block process call",
228 "I2C block read",
229 "Interrupt",
230 };
231
232 static unsigned int disable_features;
233 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
234 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
235
236 /* Make sure the SMBus host is ready to start transmitting.
237 Return 0 if it is, -EBUSY if it is not. */
238 static int i801_check_pre(struct i801_priv *priv)
239 {
240 int status;
241
242 status = inb_p(SMBHSTSTS(priv));
243 if (status & SMBHSTSTS_HOST_BUSY) {
244 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
245 return -EBUSY;
246 }
247
248 status &= STATUS_FLAGS;
249 if (status) {
250 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
251 status);
252 outb_p(status, SMBHSTSTS(priv));
253 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
254 if (status) {
255 dev_err(&priv->pci_dev->dev,
256 "Failed clearing status flags (%02x)\n",
257 status);
258 return -EBUSY;
259 }
260 }
261
262 return 0;
263 }
264
265 /*
266 * Convert the status register to an error code, and clear it.
267 * Note that status only contains the bits we want to clear, not the
268 * actual register value.
269 */
270 static int i801_check_post(struct i801_priv *priv, int status)
271 {
272 int result = 0;
273
274 /*
275 * If the SMBus is still busy, we give up
276 * Note: This timeout condition only happens when using polling
277 * transactions. For interrupt operation, NAK/timeout is indicated by
278 * DEV_ERR.
279 */
280 if (unlikely(status < 0)) {
281 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
282 /* try to stop the current command */
283 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
284 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
285 SMBHSTCNT(priv));
286 usleep_range(1000, 2000);
287 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
288 SMBHSTCNT(priv));
289
290 /* Check if it worked */
291 status = inb_p(SMBHSTSTS(priv));
292 if ((status & SMBHSTSTS_HOST_BUSY) ||
293 !(status & SMBHSTSTS_FAILED))
294 dev_err(&priv->pci_dev->dev,
295 "Failed terminating the transaction\n");
296 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
297 return -ETIMEDOUT;
298 }
299
300 if (status & SMBHSTSTS_FAILED) {
301 result = -EIO;
302 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
303 }
304 if (status & SMBHSTSTS_DEV_ERR) {
305 result = -ENXIO;
306 dev_dbg(&priv->pci_dev->dev, "No response\n");
307 }
308 if (status & SMBHSTSTS_BUS_ERR) {
309 result = -EAGAIN;
310 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
311 }
312
313 /* Clear status flags except BYTE_DONE, to be cleared by caller */
314 outb_p(status, SMBHSTSTS(priv));
315
316 return result;
317 }
318
319 /* Wait for BUSY being cleared and either INTR or an error flag being set */
320 static int i801_wait_intr(struct i801_priv *priv)
321 {
322 int timeout = 0;
323 int status;
324
325 /* We will always wait for a fraction of a second! */
326 do {
327 usleep_range(250, 500);
328 status = inb_p(SMBHSTSTS(priv));
329 } while (((status & SMBHSTSTS_HOST_BUSY) ||
330 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
331 (timeout++ < MAX_RETRIES));
332
333 if (timeout > MAX_RETRIES) {
334 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
335 return -ETIMEDOUT;
336 }
337 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
338 }
339
340 /* Wait for either BYTE_DONE or an error flag being set */
341 static int i801_wait_byte_done(struct i801_priv *priv)
342 {
343 int timeout = 0;
344 int status;
345
346 /* We will always wait for a fraction of a second! */
347 do {
348 usleep_range(250, 500);
349 status = inb_p(SMBHSTSTS(priv));
350 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
351 (timeout++ < MAX_RETRIES));
352
353 if (timeout > MAX_RETRIES) {
354 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
355 return -ETIMEDOUT;
356 }
357 return status & STATUS_ERROR_FLAGS;
358 }
359
360 static int i801_transaction(struct i801_priv *priv, int xact)
361 {
362 int status;
363 int result;
364
365 result = i801_check_pre(priv);
366 if (result < 0)
367 return result;
368
369 if (priv->features & FEATURE_IRQ) {
370 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
371 SMBHSTCNT(priv));
372 wait_event(priv->waitq, (status = priv->status));
373 priv->status = 0;
374 return i801_check_post(priv, status);
375 }
376
377 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
378 * SMBSCMD are passed in xact */
379 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
380
381 status = i801_wait_intr(priv);
382 return i801_check_post(priv, status);
383 }
384
385 static int i801_block_transaction_by_block(struct i801_priv *priv,
386 union i2c_smbus_data *data,
387 char read_write, int hwpec)
388 {
389 int i, len;
390 int status;
391
392 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
393
394 /* Use 32-byte buffer to process this transaction */
395 if (read_write == I2C_SMBUS_WRITE) {
396 len = data->block[0];
397 outb_p(len, SMBHSTDAT0(priv));
398 for (i = 0; i < len; i++)
399 outb_p(data->block[i+1], SMBBLKDAT(priv));
400 }
401
402 status = i801_transaction(priv, I801_BLOCK_DATA |
403 (hwpec ? SMBHSTCNT_PEC_EN : 0));
404 if (status)
405 return status;
406
407 if (read_write == I2C_SMBUS_READ) {
408 len = inb_p(SMBHSTDAT0(priv));
409 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
410 return -EPROTO;
411
412 data->block[0] = len;
413 for (i = 0; i < len; i++)
414 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
415 }
416 return 0;
417 }
418
419 static void i801_isr_byte_done(struct i801_priv *priv)
420 {
421 if (priv->is_read) {
422 /* For SMBus block reads, length is received with first byte */
423 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
424 (priv->count == 0)) {
425 priv->len = inb_p(SMBHSTDAT0(priv));
426 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
427 dev_err(&priv->pci_dev->dev,
428 "Illegal SMBus block read size %d\n",
429 priv->len);
430 /* FIXME: Recover */
431 priv->len = I2C_SMBUS_BLOCK_MAX;
432 } else {
433 dev_dbg(&priv->pci_dev->dev,
434 "SMBus block read size is %d\n",
435 priv->len);
436 }
437 priv->data[-1] = priv->len;
438 }
439
440 /* Read next byte */
441 if (priv->count < priv->len)
442 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
443 else
444 dev_dbg(&priv->pci_dev->dev,
445 "Discarding extra byte on block read\n");
446
447 /* Set LAST_BYTE for last byte of read transaction */
448 if (priv->count == priv->len - 1)
449 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
450 SMBHSTCNT(priv));
451 } else if (priv->count < priv->len - 1) {
452 /* Write next byte, except for IRQ after last byte */
453 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
454 }
455
456 /* Clear BYTE_DONE to continue with next byte */
457 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
458 }
459
460 /*
461 * There are two kinds of interrupts:
462 *
463 * 1) i801 signals transaction completion with one of these interrupts:
464 * INTR - Success
465 * DEV_ERR - Invalid command, NAK or communication timeout
466 * BUS_ERR - SMI# transaction collision
467 * FAILED - transaction was canceled due to a KILL request
468 * When any of these occur, update ->status and wake up the waitq.
469 * ->status must be cleared before kicking off the next transaction.
470 *
471 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
472 * occurs for each byte of a byte-by-byte to prepare the next byte.
473 */
474 static irqreturn_t i801_isr(int irq, void *dev_id)
475 {
476 struct i801_priv *priv = dev_id;
477 u16 pcists;
478 u8 status;
479
480 /* Confirm this is our interrupt */
481 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
482 if (!(pcists & SMBPCISTS_INTS))
483 return IRQ_NONE;
484
485 status = inb_p(SMBHSTSTS(priv));
486 if (status != 0x42)
487 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
488
489 if (status & SMBHSTSTS_BYTE_DONE)
490 i801_isr_byte_done(priv);
491
492 /*
493 * Clear irq sources and report transaction result.
494 * ->status must be cleared before the next transaction is started.
495 */
496 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
497 if (status) {
498 outb_p(status, SMBHSTSTS(priv));
499 priv->status |= status;
500 wake_up(&priv->waitq);
501 }
502
503 return IRQ_HANDLED;
504 }
505
506 /*
507 * For "byte-by-byte" block transactions:
508 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
509 * I2C read uses cmd=I801_I2C_BLOCK_DATA
510 */
511 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
512 union i2c_smbus_data *data,
513 char read_write, int command,
514 int hwpec)
515 {
516 int i, len;
517 int smbcmd;
518 int status;
519 int result;
520
521 result = i801_check_pre(priv);
522 if (result < 0)
523 return result;
524
525 len = data->block[0];
526
527 if (read_write == I2C_SMBUS_WRITE) {
528 outb_p(len, SMBHSTDAT0(priv));
529 outb_p(data->block[1], SMBBLKDAT(priv));
530 }
531
532 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
533 read_write == I2C_SMBUS_READ)
534 smbcmd = I801_I2C_BLOCK_DATA;
535 else
536 smbcmd = I801_BLOCK_DATA;
537
538 if (priv->features & FEATURE_IRQ) {
539 priv->is_read = (read_write == I2C_SMBUS_READ);
540 if (len == 1 && priv->is_read)
541 smbcmd |= SMBHSTCNT_LAST_BYTE;
542 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
543 priv->len = len;
544 priv->count = 0;
545 priv->data = &data->block[1];
546
547 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
548 wait_event(priv->waitq, (status = priv->status));
549 priv->status = 0;
550 return i801_check_post(priv, status);
551 }
552
553 for (i = 1; i <= len; i++) {
554 if (i == len && read_write == I2C_SMBUS_READ)
555 smbcmd |= SMBHSTCNT_LAST_BYTE;
556 outb_p(smbcmd, SMBHSTCNT(priv));
557
558 if (i == 1)
559 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
560 SMBHSTCNT(priv));
561
562 status = i801_wait_byte_done(priv);
563 if (status)
564 goto exit;
565
566 if (i == 1 && read_write == I2C_SMBUS_READ
567 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
568 len = inb_p(SMBHSTDAT0(priv));
569 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
570 dev_err(&priv->pci_dev->dev,
571 "Illegal SMBus block read size %d\n",
572 len);
573 /* Recover */
574 while (inb_p(SMBHSTSTS(priv)) &
575 SMBHSTSTS_HOST_BUSY)
576 outb_p(SMBHSTSTS_BYTE_DONE,
577 SMBHSTSTS(priv));
578 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
579 return -EPROTO;
580 }
581 data->block[0] = len;
582 }
583
584 /* Retrieve/store value in SMBBLKDAT */
585 if (read_write == I2C_SMBUS_READ)
586 data->block[i] = inb_p(SMBBLKDAT(priv));
587 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
588 outb_p(data->block[i+1], SMBBLKDAT(priv));
589
590 /* signals SMBBLKDAT ready */
591 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
592 }
593
594 status = i801_wait_intr(priv);
595 exit:
596 return i801_check_post(priv, status);
597 }
598
599 static int i801_set_block_buffer_mode(struct i801_priv *priv)
600 {
601 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
602 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
603 return -EIO;
604 return 0;
605 }
606
607 /* Block transaction function */
608 static int i801_block_transaction(struct i801_priv *priv,
609 union i2c_smbus_data *data, char read_write,
610 int command, int hwpec)
611 {
612 int result = 0;
613 unsigned char hostc;
614
615 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
616 if (read_write == I2C_SMBUS_WRITE) {
617 /* set I2C_EN bit in configuration register */
618 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
619 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
620 hostc | SMBHSTCFG_I2C_EN);
621 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
622 dev_err(&priv->pci_dev->dev,
623 "I2C block read is unsupported!\n");
624 return -EOPNOTSUPP;
625 }
626 }
627
628 if (read_write == I2C_SMBUS_WRITE
629 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
630 if (data->block[0] < 1)
631 data->block[0] = 1;
632 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
633 data->block[0] = I2C_SMBUS_BLOCK_MAX;
634 } else {
635 data->block[0] = 32; /* max for SMBus block reads */
636 }
637
638 /* Experience has shown that the block buffer can only be used for
639 SMBus (not I2C) block transactions, even though the datasheet
640 doesn't mention this limitation. */
641 if ((priv->features & FEATURE_BLOCK_BUFFER)
642 && command != I2C_SMBUS_I2C_BLOCK_DATA
643 && i801_set_block_buffer_mode(priv) == 0)
644 result = i801_block_transaction_by_block(priv, data,
645 read_write, hwpec);
646 else
647 result = i801_block_transaction_byte_by_byte(priv, data,
648 read_write,
649 command, hwpec);
650
651 if (command == I2C_SMBUS_I2C_BLOCK_DATA
652 && read_write == I2C_SMBUS_WRITE) {
653 /* restore saved configuration register value */
654 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
655 }
656 return result;
657 }
658
659 /* Return negative errno on error. */
660 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
661 unsigned short flags, char read_write, u8 command,
662 int size, union i2c_smbus_data *data)
663 {
664 int hwpec;
665 int block = 0;
666 int ret, xact = 0;
667 struct i801_priv *priv = i2c_get_adapdata(adap);
668
669 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
670 && size != I2C_SMBUS_QUICK
671 && size != I2C_SMBUS_I2C_BLOCK_DATA;
672
673 switch (size) {
674 case I2C_SMBUS_QUICK:
675 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
676 SMBHSTADD(priv));
677 xact = I801_QUICK;
678 break;
679 case I2C_SMBUS_BYTE:
680 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
681 SMBHSTADD(priv));
682 if (read_write == I2C_SMBUS_WRITE)
683 outb_p(command, SMBHSTCMD(priv));
684 xact = I801_BYTE;
685 break;
686 case I2C_SMBUS_BYTE_DATA:
687 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
688 SMBHSTADD(priv));
689 outb_p(command, SMBHSTCMD(priv));
690 if (read_write == I2C_SMBUS_WRITE)
691 outb_p(data->byte, SMBHSTDAT0(priv));
692 xact = I801_BYTE_DATA;
693 break;
694 case I2C_SMBUS_WORD_DATA:
695 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
696 SMBHSTADD(priv));
697 outb_p(command, SMBHSTCMD(priv));
698 if (read_write == I2C_SMBUS_WRITE) {
699 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
700 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
701 }
702 xact = I801_WORD_DATA;
703 break;
704 case I2C_SMBUS_BLOCK_DATA:
705 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
706 SMBHSTADD(priv));
707 outb_p(command, SMBHSTCMD(priv));
708 block = 1;
709 break;
710 case I2C_SMBUS_I2C_BLOCK_DATA:
711 /* NB: page 240 of ICH5 datasheet shows that the R/#W
712 * bit should be cleared here, even when reading */
713 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
714 if (read_write == I2C_SMBUS_READ) {
715 /* NB: page 240 of ICH5 datasheet also shows
716 * that DATA1 is the cmd field when reading */
717 outb_p(command, SMBHSTDAT1(priv));
718 } else
719 outb_p(command, SMBHSTCMD(priv));
720 block = 1;
721 break;
722 default:
723 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
724 size);
725 return -EOPNOTSUPP;
726 }
727
728 if (hwpec) /* enable/disable hardware PEC */
729 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
730 else
731 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
732 SMBAUXCTL(priv));
733
734 if (block)
735 ret = i801_block_transaction(priv, data, read_write, size,
736 hwpec);
737 else
738 ret = i801_transaction(priv, xact);
739
740 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
741 time, so we forcibly disable it after every transaction. Turn off
742 E32B for the same reason. */
743 if (hwpec || block)
744 outb_p(inb_p(SMBAUXCTL(priv)) &
745 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
746
747 if (block)
748 return ret;
749 if (ret)
750 return ret;
751 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
752 return 0;
753
754 switch (xact & 0x7f) {
755 case I801_BYTE: /* Result put in SMBHSTDAT0 */
756 case I801_BYTE_DATA:
757 data->byte = inb_p(SMBHSTDAT0(priv));
758 break;
759 case I801_WORD_DATA:
760 data->word = inb_p(SMBHSTDAT0(priv)) +
761 (inb_p(SMBHSTDAT1(priv)) << 8);
762 break;
763 }
764 return 0;
765 }
766
767
768 static u32 i801_func(struct i2c_adapter *adapter)
769 {
770 struct i801_priv *priv = i2c_get_adapdata(adapter);
771
772 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
773 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
774 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
775 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
776 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
777 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
778 }
779
780 static const struct i2c_algorithm smbus_algorithm = {
781 .smbus_xfer = i801_access,
782 .functionality = i801_func,
783 };
784
785 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
786 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
787 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
788 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
789 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
790 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
791 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
792 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
794 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
816 { 0, }
817 };
818
819 MODULE_DEVICE_TABLE(pci, i801_ids);
820
821 #if defined CONFIG_X86 && defined CONFIG_DMI
822 static unsigned char apanel_addr;
823
824 /* Scan the system ROM for the signature "FJKEYINF" */
825 static __init const void __iomem *bios_signature(const void __iomem *bios)
826 {
827 ssize_t offset;
828 const unsigned char signature[] = "FJKEYINF";
829
830 for (offset = 0; offset < 0x10000; offset += 0x10) {
831 if (check_signature(bios + offset, signature,
832 sizeof(signature)-1))
833 return bios + offset;
834 }
835 return NULL;
836 }
837
838 static void __init input_apanel_init(void)
839 {
840 void __iomem *bios;
841 const void __iomem *p;
842
843 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
844 p = bios_signature(bios);
845 if (p) {
846 /* just use the first address */
847 apanel_addr = readb(p + 8 + 3) >> 1;
848 }
849 iounmap(bios);
850 }
851
852 struct dmi_onboard_device_info {
853 const char *name;
854 u8 type;
855 unsigned short i2c_addr;
856 const char *i2c_type;
857 };
858
859 static const struct dmi_onboard_device_info dmi_devices[] = {
860 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
861 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
862 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
863 };
864
865 static void dmi_check_onboard_device(u8 type, const char *name,
866 struct i2c_adapter *adap)
867 {
868 int i;
869 struct i2c_board_info info;
870
871 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
872 /* & ~0x80, ignore enabled/disabled bit */
873 if ((type & ~0x80) != dmi_devices[i].type)
874 continue;
875 if (strcasecmp(name, dmi_devices[i].name))
876 continue;
877
878 memset(&info, 0, sizeof(struct i2c_board_info));
879 info.addr = dmi_devices[i].i2c_addr;
880 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
881 i2c_new_device(adap, &info);
882 break;
883 }
884 }
885
886 /* We use our own function to check for onboard devices instead of
887 dmi_find_device() as some buggy BIOS's have the devices we are interested
888 in marked as disabled */
889 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
890 {
891 int i, count;
892
893 if (dm->type != 10)
894 return;
895
896 count = (dm->length - sizeof(struct dmi_header)) / 2;
897 for (i = 0; i < count; i++) {
898 const u8 *d = (char *)(dm + 1) + (i * 2);
899 const char *name = ((char *) dm) + dm->length;
900 u8 type = d[0];
901 u8 s = d[1];
902
903 if (!s)
904 continue;
905 s--;
906 while (s > 0 && name[0]) {
907 name += strlen(name) + 1;
908 s--;
909 }
910 if (name[0] == 0) /* Bogus string reference */
911 continue;
912
913 dmi_check_onboard_device(type, name, adap);
914 }
915 }
916
917 /* Register optional slaves */
918 static void i801_probe_optional_slaves(struct i801_priv *priv)
919 {
920 /* Only register slaves on main SMBus channel */
921 if (priv->features & FEATURE_IDF)
922 return;
923
924 if (apanel_addr) {
925 struct i2c_board_info info;
926
927 memset(&info, 0, sizeof(struct i2c_board_info));
928 info.addr = apanel_addr;
929 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
930 i2c_new_device(&priv->adapter, &info);
931 }
932
933 if (dmi_name_in_vendors("FUJITSU"))
934 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
935 }
936 #else
937 static void __init input_apanel_init(void) {}
938 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
939 #endif /* CONFIG_X86 && CONFIG_DMI */
940
941 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
942 defined CONFIG_DMI
943 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
944 .gpio_chip = "gpio_ich",
945 .values = { 0x02, 0x03 },
946 .n_values = 2,
947 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
948 .gpios = { 52, 53 },
949 .n_gpios = 2,
950 };
951
952 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
953 .gpio_chip = "gpio_ich",
954 .values = { 0x02, 0x03, 0x01 },
955 .n_values = 3,
956 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
957 .gpios = { 52, 53 },
958 .n_gpios = 2,
959 };
960
961 static const struct dmi_system_id mux_dmi_table[] = {
962 {
963 .matches = {
964 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
965 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
966 },
967 .driver_data = &i801_mux_config_asus_z8_d12,
968 },
969 {
970 .matches = {
971 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
972 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
973 },
974 .driver_data = &i801_mux_config_asus_z8_d12,
975 },
976 {
977 .matches = {
978 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
979 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
980 },
981 .driver_data = &i801_mux_config_asus_z8_d12,
982 },
983 {
984 .matches = {
985 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
986 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
987 },
988 .driver_data = &i801_mux_config_asus_z8_d12,
989 },
990 {
991 .matches = {
992 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
993 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
994 },
995 .driver_data = &i801_mux_config_asus_z8_d12,
996 },
997 {
998 .matches = {
999 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1000 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1001 },
1002 .driver_data = &i801_mux_config_asus_z8_d12,
1003 },
1004 {
1005 .matches = {
1006 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1007 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1008 },
1009 .driver_data = &i801_mux_config_asus_z8_d18,
1010 },
1011 {
1012 .matches = {
1013 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1014 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1015 },
1016 .driver_data = &i801_mux_config_asus_z8_d18,
1017 },
1018 {
1019 .matches = {
1020 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1021 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1022 },
1023 .driver_data = &i801_mux_config_asus_z8_d12,
1024 },
1025 { }
1026 };
1027
1028 /* Setup multiplexing if needed */
1029 static int i801_add_mux(struct i801_priv *priv)
1030 {
1031 struct device *dev = &priv->adapter.dev;
1032 const struct i801_mux_config *mux_config;
1033 struct i2c_mux_gpio_platform_data gpio_data;
1034 int err;
1035
1036 if (!priv->mux_drvdata)
1037 return 0;
1038 mux_config = priv->mux_drvdata;
1039
1040 /* Prepare the platform data */
1041 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1042 gpio_data.parent = priv->adapter.nr;
1043 gpio_data.values = mux_config->values;
1044 gpio_data.n_values = mux_config->n_values;
1045 gpio_data.classes = mux_config->classes;
1046 gpio_data.gpio_chip = mux_config->gpio_chip;
1047 gpio_data.gpios = mux_config->gpios;
1048 gpio_data.n_gpios = mux_config->n_gpios;
1049 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1050
1051 /* Register the mux device */
1052 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1053 PLATFORM_DEVID_AUTO, &gpio_data,
1054 sizeof(struct i2c_mux_gpio_platform_data));
1055 if (IS_ERR(priv->mux_pdev)) {
1056 err = PTR_ERR(priv->mux_pdev);
1057 priv->mux_pdev = NULL;
1058 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1059 return err;
1060 }
1061
1062 return 0;
1063 }
1064
1065 static void i801_del_mux(struct i801_priv *priv)
1066 {
1067 if (priv->mux_pdev)
1068 platform_device_unregister(priv->mux_pdev);
1069 }
1070
1071 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1072 {
1073 const struct dmi_system_id *id;
1074 const struct i801_mux_config *mux_config;
1075 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1076 int i;
1077
1078 id = dmi_first_match(mux_dmi_table);
1079 if (id) {
1080 /* Remove branch classes from trunk */
1081 mux_config = id->driver_data;
1082 for (i = 0; i < mux_config->n_values; i++)
1083 class &= ~mux_config->classes[i];
1084
1085 /* Remember for later */
1086 priv->mux_drvdata = mux_config;
1087 }
1088
1089 return class;
1090 }
1091 #else
1092 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1093 static inline void i801_del_mux(struct i801_priv *priv) { }
1094
1095 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1096 {
1097 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1098 }
1099 #endif
1100
1101 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1102 {
1103 unsigned char temp;
1104 int err, i;
1105 struct i801_priv *priv;
1106
1107 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1108 if (!priv)
1109 return -ENOMEM;
1110
1111 i2c_set_adapdata(&priv->adapter, priv);
1112 priv->adapter.owner = THIS_MODULE;
1113 priv->adapter.class = i801_get_adapter_class(priv);
1114 priv->adapter.algo = &smbus_algorithm;
1115
1116 priv->pci_dev = dev;
1117 switch (dev->device) {
1118 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1119 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1120 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1121 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1122 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1123 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1124 priv->features |= FEATURE_IDF;
1125 /* fall through */
1126 default:
1127 priv->features |= FEATURE_I2C_BLOCK_READ;
1128 priv->features |= FEATURE_IRQ;
1129 /* fall through */
1130 case PCI_DEVICE_ID_INTEL_82801DB_3:
1131 priv->features |= FEATURE_SMBUS_PEC;
1132 priv->features |= FEATURE_BLOCK_BUFFER;
1133 /* fall through */
1134 case PCI_DEVICE_ID_INTEL_82801CA_3:
1135 case PCI_DEVICE_ID_INTEL_82801BA_2:
1136 case PCI_DEVICE_ID_INTEL_82801AB_3:
1137 case PCI_DEVICE_ID_INTEL_82801AA_3:
1138 break;
1139 }
1140
1141 /* Disable features on user request */
1142 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1143 if (priv->features & disable_features & (1 << i))
1144 dev_notice(&dev->dev, "%s disabled by user\n",
1145 i801_feature_names[i]);
1146 }
1147 priv->features &= ~disable_features;
1148
1149 err = pci_enable_device(dev);
1150 if (err) {
1151 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1152 err);
1153 goto exit;
1154 }
1155
1156 /* Determine the address of the SMBus area */
1157 priv->smba = pci_resource_start(dev, SMBBAR);
1158 if (!priv->smba) {
1159 dev_err(&dev->dev, "SMBus base address uninitialized, "
1160 "upgrade BIOS\n");
1161 err = -ENODEV;
1162 goto exit;
1163 }
1164
1165 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1166 if (err) {
1167 err = -ENODEV;
1168 goto exit;
1169 }
1170
1171 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1172 if (err) {
1173 dev_err(&dev->dev, "Failed to request SMBus region "
1174 "0x%lx-0x%Lx\n", priv->smba,
1175 (unsigned long long)pci_resource_end(dev, SMBBAR));
1176 goto exit;
1177 }
1178
1179 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1180 priv->original_hstcfg = temp;
1181 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1182 if (!(temp & SMBHSTCFG_HST_EN)) {
1183 dev_info(&dev->dev, "Enabling SMBus device\n");
1184 temp |= SMBHSTCFG_HST_EN;
1185 }
1186 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1187
1188 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1189 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1190 /* Disable SMBus interrupt feature if SMBus using SMI# */
1191 priv->features &= ~FEATURE_IRQ;
1192 }
1193
1194 /* Clear special mode bits */
1195 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1196 outb_p(inb_p(SMBAUXCTL(priv)) &
1197 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1198
1199 if (priv->features & FEATURE_IRQ) {
1200 init_waitqueue_head(&priv->waitq);
1201
1202 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1203 i801_driver.name, priv);
1204 if (err) {
1205 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1206 dev->irq, err);
1207 goto exit_release;
1208 }
1209 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1210 }
1211
1212 /* set up the sysfs linkage to our parent device */
1213 priv->adapter.dev.parent = &dev->dev;
1214
1215 /* Retry up to 3 times on lost arbitration */
1216 priv->adapter.retries = 3;
1217
1218 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1219 "SMBus I801 adapter at %04lx", priv->smba);
1220 err = i2c_add_adapter(&priv->adapter);
1221 if (err) {
1222 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1223 goto exit_free_irq;
1224 }
1225
1226 of_i2c_register_devices(&priv->adapter);
1227 i801_probe_optional_slaves(priv);
1228 /* We ignore errors - multiplexing is optional */
1229 i801_add_mux(priv);
1230
1231 pci_set_drvdata(dev, priv);
1232
1233 return 0;
1234
1235 exit_free_irq:
1236 if (priv->features & FEATURE_IRQ)
1237 free_irq(dev->irq, priv);
1238 exit_release:
1239 pci_release_region(dev, SMBBAR);
1240 exit:
1241 kfree(priv);
1242 return err;
1243 }
1244
1245 static void i801_remove(struct pci_dev *dev)
1246 {
1247 struct i801_priv *priv = pci_get_drvdata(dev);
1248
1249 i801_del_mux(priv);
1250 i2c_del_adapter(&priv->adapter);
1251 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1252
1253 if (priv->features & FEATURE_IRQ)
1254 free_irq(dev->irq, priv);
1255 pci_release_region(dev, SMBBAR);
1256
1257 kfree(priv);
1258 /*
1259 * do not call pci_disable_device(dev) since it can cause hard hangs on
1260 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1261 */
1262 }
1263
1264 #ifdef CONFIG_PM
1265 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1266 {
1267 struct i801_priv *priv = pci_get_drvdata(dev);
1268
1269 pci_save_state(dev);
1270 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1271 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1272 return 0;
1273 }
1274
1275 static int i801_resume(struct pci_dev *dev)
1276 {
1277 pci_set_power_state(dev, PCI_D0);
1278 pci_restore_state(dev);
1279 return pci_enable_device(dev);
1280 }
1281 #else
1282 #define i801_suspend NULL
1283 #define i801_resume NULL
1284 #endif
1285
1286 static struct pci_driver i801_driver = {
1287 .name = "i801_smbus",
1288 .id_table = i801_ids,
1289 .probe = i801_probe,
1290 .remove = i801_remove,
1291 .suspend = i801_suspend,
1292 .resume = i801_resume,
1293 };
1294
1295 static int __init i2c_i801_init(void)
1296 {
1297 if (dmi_name_in_vendors("FUJITSU"))
1298 input_apanel_init();
1299 return pci_register_driver(&i801_driver);
1300 }
1301
1302 static void __exit i2c_i801_exit(void)
1303 {
1304 pci_unregister_driver(&i801_driver);
1305 }
1306
1307 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
1308 "Jean Delvare <khali@linux-fr.org>");
1309 MODULE_DESCRIPTION("I801 SMBus driver");
1310 MODULE_LICENSE("GPL");
1311
1312 module_init(i2c_i801_init);
1313 module_exit(i2c_i801_exit);
kernel source for telekom puls (alcatel/mediatek)