2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/acpi.h>
40 /* If you boot an IGP board with a discrete card as the primary,
41 * the IGP rom is not accessible via the rom bar as the IGP rom is
42 * part of the system bios. On boot, the system bios puts a
43 * copy of the igp rom at the start of vram if a discrete card is
46 static bool igp_read_bios_from_vram(struct radeon_device
*rdev
)
48 uint8_t __iomem
*bios
;
49 resource_size_t vram_base
;
50 resource_size_t size
= 256 * 1024; /* ??? */
52 if (!(rdev
->flags
& RADEON_IS_IGP
))
53 if (!radeon_card_posted(rdev
))
57 vram_base
= pci_resource_start(rdev
->pdev
, 0);
58 bios
= ioremap(vram_base
, size
);
63 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
67 rdev
->bios
= kmalloc(size
, GFP_KERNEL
);
68 if (rdev
->bios
== NULL
) {
72 memcpy_fromio(rdev
->bios
, bios
, size
);
77 static bool radeon_read_bios(struct radeon_device
*rdev
)
79 uint8_t __iomem
*bios
;
83 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
84 bios
= pci_map_rom(rdev
->pdev
, &size
);
89 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
90 pci_unmap_rom(rdev
->pdev
, bios
);
93 rdev
->bios
= kmemdup(bios
, size
, GFP_KERNEL
);
94 if (rdev
->bios
== NULL
) {
95 pci_unmap_rom(rdev
->pdev
, bios
);
98 pci_unmap_rom(rdev
->pdev
, bios
);
102 static bool radeon_read_platform_bios(struct radeon_device
*rdev
)
104 uint8_t __iomem
*bios
;
109 bios
= pci_platform_rom(rdev
->pdev
, &size
);
114 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
117 rdev
->bios
= kmemdup(bios
, size
, GFP_KERNEL
);
118 if (rdev
->bios
== NULL
) {
126 /* ATRM is used to get the BIOS on the discrete cards in
129 /* retrieve the ROM in 4k blocks */
130 #define ATRM_BIOS_PAGE 4096
132 * radeon_atrm_call - fetch a chunk of the vbios
134 * @atrm_handle: acpi ATRM handle
135 * @bios: vbios image pointer
136 * @offset: offset of vbios image data to fetch
137 * @len: length of vbios image data to fetch
139 * Executes ATRM to fetch a chunk of the discrete
140 * vbios image on PX systems (all asics).
141 * Returns the length of the buffer fetched.
143 static int radeon_atrm_call(acpi_handle atrm_handle
, uint8_t *bios
,
147 union acpi_object atrm_arg_elements
[2], *obj
;
148 struct acpi_object_list atrm_arg
;
149 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
152 atrm_arg
.pointer
= &atrm_arg_elements
[0];
154 atrm_arg_elements
[0].type
= ACPI_TYPE_INTEGER
;
155 atrm_arg_elements
[0].integer
.value
= offset
;
157 atrm_arg_elements
[1].type
= ACPI_TYPE_INTEGER
;
158 atrm_arg_elements
[1].integer
.value
= len
;
160 status
= acpi_evaluate_object(atrm_handle
, NULL
, &atrm_arg
, &buffer
);
161 if (ACPI_FAILURE(status
)) {
162 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status
));
166 obj
= (union acpi_object
*)buffer
.pointer
;
167 memcpy(bios
+offset
, obj
->buffer
.pointer
, obj
->buffer
.length
);
168 len
= obj
->buffer
.length
;
169 kfree(buffer
.pointer
);
173 static bool radeon_atrm_get_bios(struct radeon_device
*rdev
)
176 int size
= 256 * 1024;
178 struct pci_dev
*pdev
= NULL
;
179 acpi_handle dhandle
, atrm_handle
;
183 /* ATRM is for the discrete card only */
184 if (rdev
->flags
& RADEON_IS_IGP
)
187 while ((pdev
= pci_get_class(PCI_CLASS_DISPLAY_VGA
<< 8, pdev
)) != NULL
) {
188 dhandle
= DEVICE_ACPI_HANDLE(&pdev
->dev
);
192 status
= acpi_get_handle(dhandle
, "ATRM", &atrm_handle
);
193 if (!ACPI_FAILURE(status
)) {
202 rdev
->bios
= kmalloc(size
, GFP_KERNEL
);
204 DRM_ERROR("Unable to allocate bios\n");
208 for (i
= 0; i
< size
/ ATRM_BIOS_PAGE
; i
++) {
209 ret
= radeon_atrm_call(atrm_handle
,
211 (i
* ATRM_BIOS_PAGE
),
213 if (ret
< ATRM_BIOS_PAGE
)
217 if (i
== 0 || rdev
->bios
[0] != 0x55 || rdev
->bios
[1] != 0xaa) {
224 static inline bool radeon_atrm_get_bios(struct radeon_device
*rdev
)
230 static bool ni_read_disabled_bios(struct radeon_device
*rdev
)
235 u32 vga_render_control
;
239 bus_cntl
= RREG32(R600_BUS_CNTL
);
240 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
241 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
242 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
243 rom_cntl
= RREG32(R600_ROM_CNTL
);
246 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
247 /* Disable VGA mode */
248 WREG32(AVIVO_D1VGA_CONTROL
,
249 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
250 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
251 WREG32(AVIVO_D2VGA_CONTROL
,
252 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
253 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
254 WREG32(AVIVO_VGA_RENDER_CONTROL
,
255 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
256 WREG32(R600_ROM_CNTL
, rom_cntl
| R600_SCK_OVERWRITE
);
258 r
= radeon_read_bios(rdev
);
261 WREG32(R600_BUS_CNTL
, bus_cntl
);
262 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
263 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
264 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
265 WREG32(R600_ROM_CNTL
, rom_cntl
);
269 static bool r700_read_disabled_bios(struct radeon_device
*rdev
)
271 uint32_t viph_control
;
273 uint32_t d1vga_control
;
274 uint32_t d2vga_control
;
275 uint32_t vga_render_control
;
277 uint32_t cg_spll_func_cntl
= 0;
278 uint32_t cg_spll_status
;
281 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
282 bus_cntl
= RREG32(R600_BUS_CNTL
);
283 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
284 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
285 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
286 rom_cntl
= RREG32(R600_ROM_CNTL
);
289 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
291 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
292 /* Disable VGA mode */
293 WREG32(AVIVO_D1VGA_CONTROL
,
294 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
295 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
296 WREG32(AVIVO_D2VGA_CONTROL
,
297 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
298 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
299 WREG32(AVIVO_VGA_RENDER_CONTROL
,
300 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
302 if (rdev
->family
== CHIP_RV730
) {
303 cg_spll_func_cntl
= RREG32(R600_CG_SPLL_FUNC_CNTL
);
305 /* enable bypass mode */
306 WREG32(R600_CG_SPLL_FUNC_CNTL
, (cg_spll_func_cntl
|
307 R600_SPLL_BYPASS_EN
));
309 /* wait for SPLL_CHG_STATUS to change to 1 */
311 while (!(cg_spll_status
& R600_SPLL_CHG_STATUS
))
312 cg_spll_status
= RREG32(R600_CG_SPLL_STATUS
);
314 WREG32(R600_ROM_CNTL
, (rom_cntl
& ~R600_SCK_OVERWRITE
));
316 WREG32(R600_ROM_CNTL
, (rom_cntl
| R600_SCK_OVERWRITE
));
318 r
= radeon_read_bios(rdev
);
321 if (rdev
->family
== CHIP_RV730
) {
322 WREG32(R600_CG_SPLL_FUNC_CNTL
, cg_spll_func_cntl
);
324 /* wait for SPLL_CHG_STATUS to change to 1 */
326 while (!(cg_spll_status
& R600_SPLL_CHG_STATUS
))
327 cg_spll_status
= RREG32(R600_CG_SPLL_STATUS
);
329 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
330 WREG32(R600_BUS_CNTL
, bus_cntl
);
331 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
332 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
333 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
334 WREG32(R600_ROM_CNTL
, rom_cntl
);
338 static bool r600_read_disabled_bios(struct radeon_device
*rdev
)
340 uint32_t viph_control
;
342 uint32_t d1vga_control
;
343 uint32_t d2vga_control
;
344 uint32_t vga_render_control
;
346 uint32_t general_pwrmgt
;
347 uint32_t low_vid_lower_gpio_cntl
;
348 uint32_t medium_vid_lower_gpio_cntl
;
349 uint32_t high_vid_lower_gpio_cntl
;
350 uint32_t ctxsw_vid_lower_gpio_cntl
;
351 uint32_t lower_gpio_enable
;
354 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
355 bus_cntl
= RREG32(R600_BUS_CNTL
);
356 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
357 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
358 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
359 rom_cntl
= RREG32(R600_ROM_CNTL
);
360 general_pwrmgt
= RREG32(R600_GENERAL_PWRMGT
);
361 low_vid_lower_gpio_cntl
= RREG32(R600_LOW_VID_LOWER_GPIO_CNTL
);
362 medium_vid_lower_gpio_cntl
= RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
);
363 high_vid_lower_gpio_cntl
= RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
);
364 ctxsw_vid_lower_gpio_cntl
= RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
);
365 lower_gpio_enable
= RREG32(R600_LOWER_GPIO_ENABLE
);
368 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
370 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
371 /* Disable VGA mode */
372 WREG32(AVIVO_D1VGA_CONTROL
,
373 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
374 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
375 WREG32(AVIVO_D2VGA_CONTROL
,
376 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
377 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
378 WREG32(AVIVO_VGA_RENDER_CONTROL
,
379 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
381 WREG32(R600_ROM_CNTL
,
382 ((rom_cntl
& ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK
) |
383 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT
) |
384 R600_SCK_OVERWRITE
));
386 WREG32(R600_GENERAL_PWRMGT
, (general_pwrmgt
& ~R600_OPEN_DRAIN_PADS
));
387 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL
,
388 (low_vid_lower_gpio_cntl
& ~0x400));
389 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
,
390 (medium_vid_lower_gpio_cntl
& ~0x400));
391 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
,
392 (high_vid_lower_gpio_cntl
& ~0x400));
393 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
,
394 (ctxsw_vid_lower_gpio_cntl
& ~0x400));
395 WREG32(R600_LOWER_GPIO_ENABLE
, (lower_gpio_enable
| 0x400));
397 r
= radeon_read_bios(rdev
);
400 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
401 WREG32(R600_BUS_CNTL
, bus_cntl
);
402 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
403 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
404 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
405 WREG32(R600_ROM_CNTL
, rom_cntl
);
406 WREG32(R600_GENERAL_PWRMGT
, general_pwrmgt
);
407 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL
, low_vid_lower_gpio_cntl
);
408 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
, medium_vid_lower_gpio_cntl
);
409 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
, high_vid_lower_gpio_cntl
);
410 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
, ctxsw_vid_lower_gpio_cntl
);
411 WREG32(R600_LOWER_GPIO_ENABLE
, lower_gpio_enable
);
415 static bool avivo_read_disabled_bios(struct radeon_device
*rdev
)
417 uint32_t seprom_cntl1
;
418 uint32_t viph_control
;
420 uint32_t d1vga_control
;
421 uint32_t d2vga_control
;
422 uint32_t vga_render_control
;
425 uint32_t gpiopad_mask
;
428 seprom_cntl1
= RREG32(RADEON_SEPROM_CNTL1
);
429 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
430 bus_cntl
= RREG32(RV370_BUS_CNTL
);
431 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
432 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
433 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
434 gpiopad_a
= RREG32(RADEON_GPIOPAD_A
);
435 gpiopad_en
= RREG32(RADEON_GPIOPAD_EN
);
436 gpiopad_mask
= RREG32(RADEON_GPIOPAD_MASK
);
438 WREG32(RADEON_SEPROM_CNTL1
,
439 ((seprom_cntl1
& ~RADEON_SCK_PRESCALE_MASK
) |
440 (0xc << RADEON_SCK_PRESCALE_SHIFT
)));
441 WREG32(RADEON_GPIOPAD_A
, 0);
442 WREG32(RADEON_GPIOPAD_EN
, 0);
443 WREG32(RADEON_GPIOPAD_MASK
, 0);
446 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
449 WREG32(RV370_BUS_CNTL
, (bus_cntl
& ~RV370_BUS_BIOS_DIS_ROM
));
451 /* Disable VGA mode */
452 WREG32(AVIVO_D1VGA_CONTROL
,
453 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
454 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
455 WREG32(AVIVO_D2VGA_CONTROL
,
456 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
457 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
458 WREG32(AVIVO_VGA_RENDER_CONTROL
,
459 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
461 r
= radeon_read_bios(rdev
);
464 WREG32(RADEON_SEPROM_CNTL1
, seprom_cntl1
);
465 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
466 WREG32(RV370_BUS_CNTL
, bus_cntl
);
467 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
468 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
469 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
470 WREG32(RADEON_GPIOPAD_A
, gpiopad_a
);
471 WREG32(RADEON_GPIOPAD_EN
, gpiopad_en
);
472 WREG32(RADEON_GPIOPAD_MASK
, gpiopad_mask
);
476 static bool legacy_read_disabled_bios(struct radeon_device
*rdev
)
478 uint32_t seprom_cntl1
;
479 uint32_t viph_control
;
481 uint32_t crtc_gen_cntl
;
482 uint32_t crtc2_gen_cntl
;
483 uint32_t crtc_ext_cntl
;
484 uint32_t fp2_gen_cntl
;
487 seprom_cntl1
= RREG32(RADEON_SEPROM_CNTL1
);
488 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
489 if (rdev
->flags
& RADEON_IS_PCIE
)
490 bus_cntl
= RREG32(RV370_BUS_CNTL
);
492 bus_cntl
= RREG32(RADEON_BUS_CNTL
);
493 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
495 crtc_ext_cntl
= RREG32(RADEON_CRTC_EXT_CNTL
);
498 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
499 fp2_gen_cntl
= RREG32(RADEON_FP2_GEN_CNTL
);
502 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
503 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
506 WREG32(RADEON_SEPROM_CNTL1
,
507 ((seprom_cntl1
& ~RADEON_SCK_PRESCALE_MASK
) |
508 (0xc << RADEON_SCK_PRESCALE_SHIFT
)));
511 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
514 if (rdev
->flags
& RADEON_IS_PCIE
)
515 WREG32(RV370_BUS_CNTL
, (bus_cntl
& ~RV370_BUS_BIOS_DIS_ROM
));
517 WREG32(RADEON_BUS_CNTL
, (bus_cntl
& ~RADEON_BUS_BIOS_DIS_ROM
));
519 /* Turn off mem requests and CRTC for both controllers */
520 WREG32(RADEON_CRTC_GEN_CNTL
,
521 ((crtc_gen_cntl
& ~RADEON_CRTC_EN
) |
522 (RADEON_CRTC_DISP_REQ_EN_B
|
523 RADEON_CRTC_EXT_DISP_EN
)));
524 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
525 WREG32(RADEON_CRTC2_GEN_CNTL
,
526 ((crtc2_gen_cntl
& ~RADEON_CRTC2_EN
) |
527 RADEON_CRTC2_DISP_REQ_EN_B
));
530 WREG32(RADEON_CRTC_EXT_CNTL
,
531 ((crtc_ext_cntl
& ~RADEON_CRTC_CRT_ON
) |
532 (RADEON_CRTC_SYNC_TRISTAT
|
533 RADEON_CRTC_DISPLAY_DIS
)));
535 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
536 WREG32(RADEON_FP2_GEN_CNTL
, (fp2_gen_cntl
& ~RADEON_FP2_ON
));
539 r
= radeon_read_bios(rdev
);
542 WREG32(RADEON_SEPROM_CNTL1
, seprom_cntl1
);
543 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
544 if (rdev
->flags
& RADEON_IS_PCIE
)
545 WREG32(RV370_BUS_CNTL
, bus_cntl
);
547 WREG32(RADEON_BUS_CNTL
, bus_cntl
);
548 WREG32(RADEON_CRTC_GEN_CNTL
, crtc_gen_cntl
);
549 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
550 WREG32(RADEON_CRTC2_GEN_CNTL
, crtc2_gen_cntl
);
552 WREG32(RADEON_CRTC_EXT_CNTL
, crtc_ext_cntl
);
553 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
554 WREG32(RADEON_FP2_GEN_CNTL
, fp2_gen_cntl
);
559 static bool radeon_read_disabled_bios(struct radeon_device
*rdev
)
561 if (rdev
->flags
& RADEON_IS_IGP
)
562 return igp_read_bios_from_vram(rdev
);
563 else if (rdev
->family
>= CHIP_BARTS
)
564 return ni_read_disabled_bios(rdev
);
565 else if (rdev
->family
>= CHIP_RV770
)
566 return r700_read_disabled_bios(rdev
);
567 else if (rdev
->family
>= CHIP_R600
)
568 return r600_read_disabled_bios(rdev
);
569 else if (rdev
->family
>= CHIP_RS600
)
570 return avivo_read_disabled_bios(rdev
);
572 return legacy_read_disabled_bios(rdev
);
576 static bool radeon_acpi_vfct_bios(struct radeon_device
*rdev
)
579 struct acpi_table_header
*hdr
;
581 UEFI_ACPI_VFCT
*vfct
;
582 GOP_VBIOS_CONTENT
*vbios
;
583 VFCT_IMAGE_HEADER
*vhdr
;
585 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr
, &tbl_size
)))
587 if (tbl_size
< sizeof(UEFI_ACPI_VFCT
)) {
588 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
592 vfct
= (UEFI_ACPI_VFCT
*)hdr
;
593 if (vfct
->VBIOSImageOffset
+ sizeof(VFCT_IMAGE_HEADER
) > tbl_size
) {
594 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
598 vbios
= (GOP_VBIOS_CONTENT
*)((char *)hdr
+ vfct
->VBIOSImageOffset
);
599 vhdr
= &vbios
->VbiosHeader
;
600 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
601 vhdr
->PCIBus
, vhdr
->PCIDevice
, vhdr
->PCIFunction
,
602 vhdr
->VendorID
, vhdr
->DeviceID
, vhdr
->ImageLength
);
604 if (vhdr
->PCIBus
!= rdev
->pdev
->bus
->number
||
605 vhdr
->PCIDevice
!= PCI_SLOT(rdev
->pdev
->devfn
) ||
606 vhdr
->PCIFunction
!= PCI_FUNC(rdev
->pdev
->devfn
) ||
607 vhdr
->VendorID
!= rdev
->pdev
->vendor
||
608 vhdr
->DeviceID
!= rdev
->pdev
->device
) {
609 DRM_INFO("ACPI VFCT table is not for this card\n");
613 if (vfct
->VBIOSImageOffset
+ sizeof(VFCT_IMAGE_HEADER
) + vhdr
->ImageLength
> tbl_size
) {
614 DRM_ERROR("ACPI VFCT image truncated\n");
618 rdev
->bios
= kmemdup(&vbios
->VbiosContent
, vhdr
->ImageLength
, GFP_KERNEL
);
625 static inline bool radeon_acpi_vfct_bios(struct radeon_device
*rdev
)
631 bool radeon_get_bios(struct radeon_device
*rdev
)
636 r
= radeon_atrm_get_bios(rdev
);
638 r
= radeon_acpi_vfct_bios(rdev
);
640 r
= igp_read_bios_from_vram(rdev
);
642 r
= radeon_read_bios(rdev
);
644 r
= radeon_read_disabled_bios(rdev
);
647 r
= radeon_read_platform_bios(rdev
);
649 if (r
== false || rdev
->bios
== NULL
) {
650 DRM_ERROR("Unable to locate a BIOS ROM\n");
654 if (rdev
->bios
[0] != 0x55 || rdev
->bios
[1] != 0xaa) {
655 printk("BIOS signature incorrect %x %x\n", rdev
->bios
[0], rdev
->bios
[1]);
660 if (RBIOS8(tmp
+ 0x14) != 0x0) {
661 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
665 rdev
->bios_header_start
= RBIOS16(0x48);
666 if (!rdev
->bios_header_start
) {
669 tmp
= rdev
->bios_header_start
+ 4;
670 if (!memcmp(rdev
->bios
+ tmp
, "ATOM", 4) ||
671 !memcmp(rdev
->bios
+ tmp
, "MOTA", 4)) {
672 rdev
->is_atom_bios
= true;
674 rdev
->is_atom_bios
= false;
677 DRM_DEBUG("%sBIOS detected\n", rdev
->is_atom_bios
? "ATOM" : "COM");