2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device
*rdev
);
41 void evergreen_fini(struct radeon_device
*rdev
);
43 /* get temperature in millidegrees */
44 u32
evergreen_get_temp(struct radeon_device
*rdev
)
46 u32 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
52 else if ((temp
>> 9) & 1)
55 actual_temp
= (temp
>> 1) & 0xff;
57 return actual_temp
* 1000;
60 void evergreen_pm_misc(struct radeon_device
*rdev
)
62 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
63 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
64 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
65 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
67 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
68 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
69 radeon_atom_set_voltage(rdev
, voltage
->voltage
);
70 rdev
->pm
.current_vddc
= voltage
->voltage
;
71 DRM_DEBUG("Setting: v: %d\n", voltage
->voltage
);
76 void evergreen_pm_prepare(struct radeon_device
*rdev
)
78 struct drm_device
*ddev
= rdev
->ddev
;
79 struct drm_crtc
*crtc
;
80 struct radeon_crtc
*radeon_crtc
;
83 /* disable any active CRTCs */
84 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
85 radeon_crtc
= to_radeon_crtc(crtc
);
86 if (radeon_crtc
->enabled
) {
87 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
88 tmp
|= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
89 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
94 void evergreen_pm_finish(struct radeon_device
*rdev
)
96 struct drm_device
*ddev
= rdev
->ddev
;
97 struct drm_crtc
*crtc
;
98 struct radeon_crtc
*radeon_crtc
;
101 /* enable any active CRTCs */
102 list_for_each_entry(crtc
, &ddev
->mode_config
.crtc_list
, head
) {
103 radeon_crtc
= to_radeon_crtc(crtc
);
104 if (radeon_crtc
->enabled
) {
105 tmp
= RREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
);
106 tmp
&= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE
;
107 WREG32(EVERGREEN_CRTC_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
112 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
114 bool connected
= false;
118 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
122 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
126 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
130 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
134 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
138 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
148 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
149 enum radeon_hpd_id hpd
)
152 bool connected
= evergreen_hpd_sense(rdev
, hpd
);
156 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
158 tmp
&= ~DC_HPDx_INT_POLARITY
;
160 tmp
|= DC_HPDx_INT_POLARITY
;
161 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
164 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
166 tmp
&= ~DC_HPDx_INT_POLARITY
;
168 tmp
|= DC_HPDx_INT_POLARITY
;
169 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
172 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
174 tmp
&= ~DC_HPDx_INT_POLARITY
;
176 tmp
|= DC_HPDx_INT_POLARITY
;
177 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
180 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
182 tmp
&= ~DC_HPDx_INT_POLARITY
;
184 tmp
|= DC_HPDx_INT_POLARITY
;
185 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
188 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
190 tmp
&= ~DC_HPDx_INT_POLARITY
;
192 tmp
|= DC_HPDx_INT_POLARITY
;
193 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
196 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
198 tmp
&= ~DC_HPDx_INT_POLARITY
;
200 tmp
|= DC_HPDx_INT_POLARITY
;
201 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
208 void evergreen_hpd_init(struct radeon_device
*rdev
)
210 struct drm_device
*dev
= rdev
->ddev
;
211 struct drm_connector
*connector
;
212 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) |
213 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN
;
215 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
216 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
217 switch (radeon_connector
->hpd
.hpd
) {
219 WREG32(DC_HPD1_CONTROL
, tmp
);
220 rdev
->irq
.hpd
[0] = true;
223 WREG32(DC_HPD2_CONTROL
, tmp
);
224 rdev
->irq
.hpd
[1] = true;
227 WREG32(DC_HPD3_CONTROL
, tmp
);
228 rdev
->irq
.hpd
[2] = true;
231 WREG32(DC_HPD4_CONTROL
, tmp
);
232 rdev
->irq
.hpd
[3] = true;
235 WREG32(DC_HPD5_CONTROL
, tmp
);
236 rdev
->irq
.hpd
[4] = true;
239 WREG32(DC_HPD6_CONTROL
, tmp
);
240 rdev
->irq
.hpd
[5] = true;
246 if (rdev
->irq
.installed
)
247 evergreen_irq_set(rdev
);
250 void evergreen_hpd_fini(struct radeon_device
*rdev
)
252 struct drm_device
*dev
= rdev
->ddev
;
253 struct drm_connector
*connector
;
255 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
256 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
257 switch (radeon_connector
->hpd
.hpd
) {
259 WREG32(DC_HPD1_CONTROL
, 0);
260 rdev
->irq
.hpd
[0] = false;
263 WREG32(DC_HPD2_CONTROL
, 0);
264 rdev
->irq
.hpd
[1] = false;
267 WREG32(DC_HPD3_CONTROL
, 0);
268 rdev
->irq
.hpd
[2] = false;
271 WREG32(DC_HPD4_CONTROL
, 0);
272 rdev
->irq
.hpd
[3] = false;
275 WREG32(DC_HPD5_CONTROL
, 0);
276 rdev
->irq
.hpd
[4] = false;
279 WREG32(DC_HPD6_CONTROL
, 0);
280 rdev
->irq
.hpd
[5] = false;
288 /* watermark setup */
290 static u32
evergreen_line_buffer_adjust(struct radeon_device
*rdev
,
291 struct radeon_crtc
*radeon_crtc
,
292 struct drm_display_mode
*mode
,
293 struct drm_display_mode
*other_mode
)
298 * There are 3 line buffers, each one shared by 2 display controllers.
299 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
300 * the display controllers. The paritioning is done via one of four
301 * preset allocations specified in bits 2:0:
302 * first display controller
303 * 0 - first half of lb (3840 * 2)
304 * 1 - first 3/4 of lb (5760 * 2)
305 * 2 - whole lb (7680 * 2)
306 * 3 - first 1/4 of lb (1920 * 2)
307 * second display controller
308 * 4 - second half of lb (3840 * 2)
309 * 5 - second 3/4 of lb (5760 * 2)
310 * 6 - whole lb (7680 * 2)
311 * 7 - last 1/4 of lb (1920 * 2)
313 if (mode
&& other_mode
) {
314 if (mode
->hdisplay
> other_mode
->hdisplay
) {
315 if (mode
->hdisplay
> 2560)
319 } else if (other_mode
->hdisplay
> mode
->hdisplay
) {
320 if (other_mode
->hdisplay
> 2560)
331 /* second controller of the pair uses second half of the lb */
332 if (radeon_crtc
->crtc_id
% 2)
334 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
, tmp
);
353 static u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
)
355 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
357 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
370 struct evergreen_wm_params
{
371 u32 dram_channels
; /* number of dram channels */
372 u32 yclk
; /* bandwidth per dram data pin in kHz */
373 u32 sclk
; /* engine clock in kHz */
374 u32 disp_clk
; /* display clock in kHz */
375 u32 src_width
; /* viewport width */
376 u32 active_time
; /* active display time in ns */
377 u32 blank_time
; /* blank time in ns */
378 bool interlaced
; /* mode is interlaced */
379 fixed20_12 vsc
; /* vertical scale ratio */
380 u32 num_heads
; /* number of active crtcs */
381 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
382 u32 lb_size
; /* line buffer allocated to pipe */
383 u32 vtaps
; /* vertical scaler taps */
386 static u32
evergreen_dram_bandwidth(struct evergreen_wm_params
*wm
)
388 /* Calculate DRAM Bandwidth and the part allocated to display. */
389 fixed20_12 dram_efficiency
; /* 0.7 */
390 fixed20_12 yclk
, dram_channels
, bandwidth
;
393 a
.full
= dfixed_const(1000);
394 yclk
.full
= dfixed_const(wm
->yclk
);
395 yclk
.full
= dfixed_div(yclk
, a
);
396 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
397 a
.full
= dfixed_const(10);
398 dram_efficiency
.full
= dfixed_const(7);
399 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
400 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
401 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
403 return dfixed_trunc(bandwidth
);
406 static u32
evergreen_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
408 /* Calculate DRAM Bandwidth and the part allocated to display. */
409 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
410 fixed20_12 yclk
, dram_channels
, bandwidth
;
413 a
.full
= dfixed_const(1000);
414 yclk
.full
= dfixed_const(wm
->yclk
);
415 yclk
.full
= dfixed_div(yclk
, a
);
416 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
417 a
.full
= dfixed_const(10);
418 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
419 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
420 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
421 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
423 return dfixed_trunc(bandwidth
);
426 static u32
evergreen_data_return_bandwidth(struct evergreen_wm_params
*wm
)
428 /* Calculate the display Data return Bandwidth */
429 fixed20_12 return_efficiency
; /* 0.8 */
430 fixed20_12 sclk
, bandwidth
;
433 a
.full
= dfixed_const(1000);
434 sclk
.full
= dfixed_const(wm
->sclk
);
435 sclk
.full
= dfixed_div(sclk
, a
);
436 a
.full
= dfixed_const(10);
437 return_efficiency
.full
= dfixed_const(8);
438 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
439 a
.full
= dfixed_const(32);
440 bandwidth
.full
= dfixed_mul(a
, sclk
);
441 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
443 return dfixed_trunc(bandwidth
);
446 static u32
evergreen_dmif_request_bandwidth(struct evergreen_wm_params
*wm
)
448 /* Calculate the DMIF Request Bandwidth */
449 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
450 fixed20_12 disp_clk
, bandwidth
;
453 a
.full
= dfixed_const(1000);
454 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
455 disp_clk
.full
= dfixed_div(disp_clk
, a
);
456 a
.full
= dfixed_const(10);
457 disp_clk_request_efficiency
.full
= dfixed_const(8);
458 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
459 a
.full
= dfixed_const(32);
460 bandwidth
.full
= dfixed_mul(a
, disp_clk
);
461 bandwidth
.full
= dfixed_mul(bandwidth
, disp_clk_request_efficiency
);
463 return dfixed_trunc(bandwidth
);
466 static u32
evergreen_available_bandwidth(struct evergreen_wm_params
*wm
)
468 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
469 u32 dram_bandwidth
= evergreen_dram_bandwidth(wm
);
470 u32 data_return_bandwidth
= evergreen_data_return_bandwidth(wm
);
471 u32 dmif_req_bandwidth
= evergreen_dmif_request_bandwidth(wm
);
473 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
476 static u32
evergreen_average_bandwidth(struct evergreen_wm_params
*wm
)
478 /* Calculate the display mode Average Bandwidth
479 * DisplayMode should contain the source and destination dimensions,
483 fixed20_12 line_time
;
484 fixed20_12 src_width
;
485 fixed20_12 bandwidth
;
488 a
.full
= dfixed_const(1000);
489 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
490 line_time
.full
= dfixed_div(line_time
, a
);
491 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
492 src_width
.full
= dfixed_const(wm
->src_width
);
493 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
494 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
495 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
497 return dfixed_trunc(bandwidth
);
500 static u32
evergreen_latency_watermark(struct evergreen_wm_params
*wm
)
502 /* First calcualte the latency in ns */
503 u32 mc_latency
= 2000; /* 2000 ns. */
504 u32 available_bandwidth
= evergreen_available_bandwidth(wm
);
505 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
506 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
507 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
508 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
509 (wm
->num_heads
* cursor_line_pair_return_time
);
510 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
511 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
514 if (wm
->num_heads
== 0)
517 a
.full
= dfixed_const(2);
518 b
.full
= dfixed_const(1);
519 if ((wm
->vsc
.full
> a
.full
) ||
520 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
522 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
523 max_src_lines_per_dst_line
= 4;
525 max_src_lines_per_dst_line
= 2;
527 a
.full
= dfixed_const(available_bandwidth
);
528 b
.full
= dfixed_const(wm
->num_heads
);
529 a
.full
= dfixed_div(a
, b
);
531 b
.full
= dfixed_const(1000);
532 c
.full
= dfixed_const(wm
->disp_clk
);
533 b
.full
= dfixed_div(c
, b
);
534 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
535 b
.full
= dfixed_mul(b
, c
);
537 lb_fill_bw
= min(dfixed_trunc(a
), dfixed_trunc(b
));
539 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
540 b
.full
= dfixed_const(1000);
541 c
.full
= dfixed_const(lb_fill_bw
);
542 b
.full
= dfixed_div(c
, b
);
543 a
.full
= dfixed_div(a
, b
);
544 line_fill_time
= dfixed_trunc(a
);
546 if (line_fill_time
< wm
->active_time
)
549 return latency
+ (line_fill_time
- wm
->active_time
);
553 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params
*wm
)
555 if (evergreen_average_bandwidth(wm
) <=
556 (evergreen_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
562 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params
*wm
)
564 if (evergreen_average_bandwidth(wm
) <=
565 (evergreen_available_bandwidth(wm
) / wm
->num_heads
))
571 static bool evergreen_check_latency_hiding(struct evergreen_wm_params
*wm
)
573 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
574 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
575 u32 latency_tolerant_lines
;
579 a
.full
= dfixed_const(1);
580 if (wm
->vsc
.full
> a
.full
)
581 latency_tolerant_lines
= 1;
583 if (lb_partitions
<= (wm
->vtaps
+ 1))
584 latency_tolerant_lines
= 1;
586 latency_tolerant_lines
= 2;
589 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
591 if (evergreen_latency_watermark(wm
) <= latency_hiding
)
597 static void evergreen_program_watermarks(struct radeon_device
*rdev
,
598 struct radeon_crtc
*radeon_crtc
,
599 u32 lb_size
, u32 num_heads
)
601 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
602 struct evergreen_wm_params wm
;
605 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
606 u32 priority_a_mark
= 0, priority_b_mark
= 0;
607 u32 priority_a_cnt
= PRIORITY_OFF
;
608 u32 priority_b_cnt
= PRIORITY_OFF
;
609 u32 pipe_offset
= radeon_crtc
->crtc_id
* 16;
610 u32 tmp
, arb_control3
;
613 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
614 pixel_period
= 1000000 / (u32
)mode
->clock
;
615 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
619 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
620 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
621 wm
.disp_clk
= mode
->clock
;
622 wm
.src_width
= mode
->crtc_hdisplay
;
623 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
624 wm
.blank_time
= line_time
- wm
.active_time
;
625 wm
.interlaced
= false;
626 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
627 wm
.interlaced
= true;
628 wm
.vsc
= radeon_crtc
->vsc
;
630 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
632 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
633 wm
.lb_size
= lb_size
;
634 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
635 wm
.num_heads
= num_heads
;
637 /* set for high clocks */
638 latency_watermark_a
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
639 /* set for low clocks */
640 /* wm.yclk = low clk; wm.sclk = low clk */
641 latency_watermark_b
= min(evergreen_latency_watermark(&wm
), (u32
)65535);
643 /* possibly force display priority to high */
644 /* should really do this at mode validation time... */
645 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
646 !evergreen_average_bandwidth_vs_available_bandwidth(&wm
) ||
647 !evergreen_check_latency_hiding(&wm
) ||
648 (rdev
->disp_priority
== 2)) {
649 DRM_INFO("force priority to high\n");
650 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
651 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
654 a
.full
= dfixed_const(1000);
655 b
.full
= dfixed_const(mode
->clock
);
656 b
.full
= dfixed_div(b
, a
);
657 c
.full
= dfixed_const(latency_watermark_a
);
658 c
.full
= dfixed_mul(c
, b
);
659 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
660 c
.full
= dfixed_div(c
, a
);
661 a
.full
= dfixed_const(16);
662 c
.full
= dfixed_div(c
, a
);
663 priority_a_mark
= dfixed_trunc(c
);
664 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
666 a
.full
= dfixed_const(1000);
667 b
.full
= dfixed_const(mode
->clock
);
668 b
.full
= dfixed_div(b
, a
);
669 c
.full
= dfixed_const(latency_watermark_b
);
670 c
.full
= dfixed_mul(c
, b
);
671 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
672 c
.full
= dfixed_div(c
, a
);
673 a
.full
= dfixed_const(16);
674 c
.full
= dfixed_div(c
, a
);
675 priority_b_mark
= dfixed_trunc(c
);
676 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
680 arb_control3
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
682 tmp
&= ~LATENCY_WATERMARK_MASK(3);
683 tmp
|= LATENCY_WATERMARK_MASK(1);
684 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
685 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
686 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
687 LATENCY_HIGH_WATERMARK(line_time
)));
689 tmp
= RREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
);
690 tmp
&= ~LATENCY_WATERMARK_MASK(3);
691 tmp
|= LATENCY_WATERMARK_MASK(2);
692 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, tmp
);
693 WREG32(PIPE0_LATENCY_CONTROL
+ pipe_offset
,
694 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
695 LATENCY_HIGH_WATERMARK(line_time
)));
696 /* restore original selection */
697 WREG32(PIPE0_ARBITRATION_CONTROL3
+ pipe_offset
, arb_control3
);
699 /* write the priority marks */
700 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
701 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
705 void evergreen_bandwidth_update(struct radeon_device
*rdev
)
707 struct drm_display_mode
*mode0
= NULL
;
708 struct drm_display_mode
*mode1
= NULL
;
709 u32 num_heads
= 0, lb_size
;
712 radeon_update_display_priority(rdev
);
714 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
715 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
718 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
719 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
720 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
721 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
722 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
723 lb_size
= evergreen_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
724 evergreen_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
728 static int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
)
733 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
735 tmp
= RREG32(SRBM_STATUS
) & 0x1F00;
746 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
751 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
752 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
754 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
755 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
757 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
767 int evergreen_pcie_gart_enable(struct radeon_device
*rdev
)
772 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
773 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
776 r
= radeon_gart_table_vram_pin(rdev
);
779 radeon_gart_restore(rdev
);
781 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
782 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
783 EFFECTIVE_L2_QUEUE_SIZE(7));
784 WREG32(VM_L2_CNTL2
, 0);
785 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
786 /* Setup TLB control */
787 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
788 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
789 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
790 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
791 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
792 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
793 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
794 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
795 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
796 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
797 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
798 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
799 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
800 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
801 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
802 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
803 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
804 (u32
)(rdev
->dummy_page
.addr
>> 12));
805 WREG32(VM_CONTEXT1_CNTL
, 0);
807 evergreen_pcie_gart_tlb_flush(rdev
);
808 rdev
->gart
.ready
= true;
812 void evergreen_pcie_gart_disable(struct radeon_device
*rdev
)
817 /* Disable all tables */
818 WREG32(VM_CONTEXT0_CNTL
, 0);
819 WREG32(VM_CONTEXT1_CNTL
, 0);
822 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
823 EFFECTIVE_L2_QUEUE_SIZE(7));
824 WREG32(VM_L2_CNTL2
, 0);
825 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
826 /* Setup TLB control */
827 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
828 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
829 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
830 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
831 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
832 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
833 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
834 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
835 if (rdev
->gart
.table
.vram
.robj
) {
836 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
837 if (likely(r
== 0)) {
838 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
839 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
840 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
845 void evergreen_pcie_gart_fini(struct radeon_device
*rdev
)
847 evergreen_pcie_gart_disable(rdev
);
848 radeon_gart_table_vram_free(rdev
);
849 radeon_gart_fini(rdev
);
853 void evergreen_agp_enable(struct radeon_device
*rdev
)
858 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
859 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
860 EFFECTIVE_L2_QUEUE_SIZE(7));
861 WREG32(VM_L2_CNTL2
, 0);
862 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
863 /* Setup TLB control */
864 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
865 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
866 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
867 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
868 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
869 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
870 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
871 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
872 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
873 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
874 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
875 WREG32(VM_CONTEXT0_CNTL
, 0);
876 WREG32(VM_CONTEXT1_CNTL
, 0);
879 static void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
881 save
->vga_control
[0] = RREG32(D1VGA_CONTROL
);
882 save
->vga_control
[1] = RREG32(D2VGA_CONTROL
);
883 save
->vga_control
[2] = RREG32(EVERGREEN_D3VGA_CONTROL
);
884 save
->vga_control
[3] = RREG32(EVERGREEN_D4VGA_CONTROL
);
885 save
->vga_control
[4] = RREG32(EVERGREEN_D5VGA_CONTROL
);
886 save
->vga_control
[5] = RREG32(EVERGREEN_D6VGA_CONTROL
);
887 save
->vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
888 save
->vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
889 save
->crtc_control
[0] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
890 save
->crtc_control
[1] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
891 save
->crtc_control
[2] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
892 save
->crtc_control
[3] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
893 save
->crtc_control
[4] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
894 save
->crtc_control
[5] = RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
897 WREG32(VGA_RENDER_CONTROL
, 0);
898 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
899 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
900 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
901 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
902 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
903 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
904 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
905 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
906 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
907 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
908 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
909 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
910 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
911 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
912 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
913 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
914 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
915 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
917 WREG32(D1VGA_CONTROL
, 0);
918 WREG32(D2VGA_CONTROL
, 0);
919 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
920 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
921 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
922 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
925 static void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
)
927 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
928 upper_32_bits(rdev
->mc
.vram_start
));
929 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
930 upper_32_bits(rdev
->mc
.vram_start
));
931 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
932 (u32
)rdev
->mc
.vram_start
);
933 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
,
934 (u32
)rdev
->mc
.vram_start
);
936 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
937 upper_32_bits(rdev
->mc
.vram_start
));
938 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
939 upper_32_bits(rdev
->mc
.vram_start
));
940 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
941 (u32
)rdev
->mc
.vram_start
);
942 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
,
943 (u32
)rdev
->mc
.vram_start
);
945 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
946 upper_32_bits(rdev
->mc
.vram_start
));
947 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
948 upper_32_bits(rdev
->mc
.vram_start
));
949 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
950 (u32
)rdev
->mc
.vram_start
);
951 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
,
952 (u32
)rdev
->mc
.vram_start
);
954 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
955 upper_32_bits(rdev
->mc
.vram_start
));
956 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
957 upper_32_bits(rdev
->mc
.vram_start
));
958 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
959 (u32
)rdev
->mc
.vram_start
);
960 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
,
961 (u32
)rdev
->mc
.vram_start
);
963 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
964 upper_32_bits(rdev
->mc
.vram_start
));
965 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
966 upper_32_bits(rdev
->mc
.vram_start
));
967 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
968 (u32
)rdev
->mc
.vram_start
);
969 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
,
970 (u32
)rdev
->mc
.vram_start
);
972 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
973 upper_32_bits(rdev
->mc
.vram_start
));
974 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
975 upper_32_bits(rdev
->mc
.vram_start
));
976 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
977 (u32
)rdev
->mc
.vram_start
);
978 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
,
979 (u32
)rdev
->mc
.vram_start
);
981 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(rdev
->mc
.vram_start
));
982 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
983 /* Unlock host access */
984 WREG32(VGA_HDP_CONTROL
, save
->vga_hdp_control
);
986 /* Restore video state */
987 WREG32(D1VGA_CONTROL
, save
->vga_control
[0]);
988 WREG32(D2VGA_CONTROL
, save
->vga_control
[1]);
989 WREG32(EVERGREEN_D3VGA_CONTROL
, save
->vga_control
[2]);
990 WREG32(EVERGREEN_D4VGA_CONTROL
, save
->vga_control
[3]);
991 WREG32(EVERGREEN_D5VGA_CONTROL
, save
->vga_control
[4]);
992 WREG32(EVERGREEN_D6VGA_CONTROL
, save
->vga_control
[5]);
993 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 1);
994 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 1);
995 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 1);
996 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 1);
997 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 1);
998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 1);
999 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, save
->crtc_control
[0]);
1000 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, save
->crtc_control
[1]);
1001 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, save
->crtc_control
[2]);
1002 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, save
->crtc_control
[3]);
1003 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, save
->crtc_control
[4]);
1004 WREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, save
->crtc_control
[5]);
1005 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1006 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
1011 WREG32(VGA_RENDER_CONTROL
, save
->vga_render_control
);
1014 static void evergreen_mc_program(struct radeon_device
*rdev
)
1016 struct evergreen_mc_save save
;
1020 /* Initialize HDP */
1021 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1022 WREG32((0x2c14 + j
), 0x00000000);
1023 WREG32((0x2c18 + j
), 0x00000000);
1024 WREG32((0x2c1c + j
), 0x00000000);
1025 WREG32((0x2c20 + j
), 0x00000000);
1026 WREG32((0x2c24 + j
), 0x00000000);
1028 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1030 evergreen_mc_stop(rdev
, &save
);
1031 if (evergreen_mc_wait_for_idle(rdev
)) {
1032 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1034 /* Lockout access through VGA aperture*/
1035 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1036 /* Update configuration */
1037 if (rdev
->flags
& RADEON_IS_AGP
) {
1038 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1039 /* VRAM before AGP */
1040 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1041 rdev
->mc
.vram_start
>> 12);
1042 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1043 rdev
->mc
.gtt_end
>> 12);
1045 /* VRAM after AGP */
1046 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1047 rdev
->mc
.gtt_start
>> 12);
1048 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1049 rdev
->mc
.vram_end
>> 12);
1052 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1053 rdev
->mc
.vram_start
>> 12);
1054 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1055 rdev
->mc
.vram_end
>> 12);
1057 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
1058 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1059 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1060 WREG32(MC_VM_FB_LOCATION
, tmp
);
1061 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1062 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
1063 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1064 if (rdev
->flags
& RADEON_IS_AGP
) {
1065 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
1066 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
1067 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1069 WREG32(MC_VM_AGP_BASE
, 0);
1070 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1071 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1073 if (evergreen_mc_wait_for_idle(rdev
)) {
1074 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1076 evergreen_mc_resume(rdev
, &save
);
1077 /* we need to own VRAM, so turn off the VGA renderer here
1078 * to stop it overwriting our objects */
1079 rv515_vga_render_disable(rdev
);
1086 static int evergreen_cp_load_microcode(struct radeon_device
*rdev
)
1088 const __be32
*fw_data
;
1091 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1095 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| (15 << 8) | (3 << 0));
1097 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1098 WREG32(CP_PFP_UCODE_ADDR
, 0);
1099 for (i
= 0; i
< EVERGREEN_PFP_UCODE_SIZE
; i
++)
1100 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1101 WREG32(CP_PFP_UCODE_ADDR
, 0);
1103 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1104 WREG32(CP_ME_RAM_WADDR
, 0);
1105 for (i
= 0; i
< EVERGREEN_PM4_UCODE_SIZE
; i
++)
1106 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1108 WREG32(CP_PFP_UCODE_ADDR
, 0);
1109 WREG32(CP_ME_RAM_WADDR
, 0);
1110 WREG32(CP_ME_RAM_RADDR
, 0);
1114 static int evergreen_cp_start(struct radeon_device
*rdev
)
1119 r
= radeon_ring_lock(rdev
, 7);
1121 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1124 radeon_ring_write(rdev
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1125 radeon_ring_write(rdev
, 0x1);
1126 radeon_ring_write(rdev
, 0x0);
1127 radeon_ring_write(rdev
, rdev
->config
.evergreen
.max_hw_contexts
- 1);
1128 radeon_ring_write(rdev
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1129 radeon_ring_write(rdev
, 0);
1130 radeon_ring_write(rdev
, 0);
1131 radeon_ring_unlock_commit(rdev
);
1134 WREG32(CP_ME_CNTL
, cp_me
);
1136 r
= radeon_ring_lock(rdev
, evergreen_default_size
+ 15);
1138 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1142 /* setup clear context state */
1143 radeon_ring_write(rdev
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1144 radeon_ring_write(rdev
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1146 for (i
= 0; i
< evergreen_default_size
; i
++)
1147 radeon_ring_write(rdev
, evergreen_default_state
[i
]);
1149 radeon_ring_write(rdev
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1150 radeon_ring_write(rdev
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1152 /* set clear context state */
1153 radeon_ring_write(rdev
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1154 radeon_ring_write(rdev
, 0);
1156 /* SQ_VTX_BASE_VTX_LOC */
1157 radeon_ring_write(rdev
, 0xc0026f00);
1158 radeon_ring_write(rdev
, 0x00000000);
1159 radeon_ring_write(rdev
, 0x00000000);
1160 radeon_ring_write(rdev
, 0x00000000);
1163 radeon_ring_write(rdev
, 0xc0036f00);
1164 radeon_ring_write(rdev
, 0x00000bc4);
1165 radeon_ring_write(rdev
, 0xffffffff);
1166 radeon_ring_write(rdev
, 0xffffffff);
1167 radeon_ring_write(rdev
, 0xffffffff);
1169 radeon_ring_unlock_commit(rdev
);
1174 int evergreen_cp_resume(struct radeon_device
*rdev
)
1180 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1181 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1186 RREG32(GRBM_SOFT_RESET
);
1188 WREG32(GRBM_SOFT_RESET
, 0);
1189 RREG32(GRBM_SOFT_RESET
);
1191 /* Set ring buffer size */
1192 rb_bufsz
= drm_order(rdev
->cp
.ring_size
/ 8);
1193 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1195 tmp
|= BUF_SWAP_32BIT
;
1197 WREG32(CP_RB_CNTL
, tmp
);
1198 WREG32(CP_SEM_WAIT_TIMER
, 0x4);
1200 /* Set the write pointer delay */
1201 WREG32(CP_RB_WPTR_DELAY
, 0);
1203 /* Initialize the ring buffer's read and write pointers */
1204 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1205 WREG32(CP_RB_RPTR_WR
, 0);
1206 WREG32(CP_RB_WPTR
, 0);
1208 /* set the wb address wether it's enabled or not */
1209 WREG32(CP_RB_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC);
1210 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
1211 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1213 if (rdev
->wb
.enabled
)
1214 WREG32(SCRATCH_UMSK
, 0xff);
1216 tmp
|= RB_NO_UPDATE
;
1217 WREG32(SCRATCH_UMSK
, 0);
1221 WREG32(CP_RB_CNTL
, tmp
);
1223 WREG32(CP_RB_BASE
, rdev
->cp
.gpu_addr
>> 8);
1224 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1226 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
1227 rdev
->cp
.wptr
= RREG32(CP_RB_WPTR
);
1229 evergreen_cp_start(rdev
);
1230 rdev
->cp
.ready
= true;
1231 r
= radeon_ring_test(rdev
);
1233 rdev
->cp
.ready
= false;
1242 static u32
evergreen_get_tile_pipe_to_backend_map(struct radeon_device
*rdev
,
1245 u32 backend_disable_mask
)
1247 u32 backend_map
= 0;
1248 u32 enabled_backends_mask
= 0;
1249 u32 enabled_backends_count
= 0;
1251 u32 swizzle_pipe
[EVERGREEN_MAX_PIPES
];
1252 u32 cur_backend
= 0;
1254 bool force_no_swizzle
;
1256 if (num_tile_pipes
> EVERGREEN_MAX_PIPES
)
1257 num_tile_pipes
= EVERGREEN_MAX_PIPES
;
1258 if (num_tile_pipes
< 1)
1260 if (num_backends
> EVERGREEN_MAX_BACKENDS
)
1261 num_backends
= EVERGREEN_MAX_BACKENDS
;
1262 if (num_backends
< 1)
1265 for (i
= 0; i
< EVERGREEN_MAX_BACKENDS
; ++i
) {
1266 if (((backend_disable_mask
>> i
) & 1) == 0) {
1267 enabled_backends_mask
|= (1 << i
);
1268 ++enabled_backends_count
;
1270 if (enabled_backends_count
== num_backends
)
1274 if (enabled_backends_count
== 0) {
1275 enabled_backends_mask
= 1;
1276 enabled_backends_count
= 1;
1279 if (enabled_backends_count
!= num_backends
)
1280 num_backends
= enabled_backends_count
;
1282 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * EVERGREEN_MAX_PIPES
);
1283 switch (rdev
->family
) {
1286 force_no_swizzle
= false;
1292 force_no_swizzle
= true;
1295 if (force_no_swizzle
) {
1296 bool last_backend_enabled
= false;
1298 force_no_swizzle
= false;
1299 for (i
= 0; i
< EVERGREEN_MAX_BACKENDS
; ++i
) {
1300 if (((enabled_backends_mask
>> i
) & 1) == 1) {
1301 if (last_backend_enabled
)
1302 force_no_swizzle
= true;
1303 last_backend_enabled
= true;
1305 last_backend_enabled
= false;
1309 switch (num_tile_pipes
) {
1314 DRM_ERROR("odd number of pipes!\n");
1317 swizzle_pipe
[0] = 0;
1318 swizzle_pipe
[1] = 1;
1321 if (force_no_swizzle
) {
1322 swizzle_pipe
[0] = 0;
1323 swizzle_pipe
[1] = 1;
1324 swizzle_pipe
[2] = 2;
1325 swizzle_pipe
[3] = 3;
1327 swizzle_pipe
[0] = 0;
1328 swizzle_pipe
[1] = 2;
1329 swizzle_pipe
[2] = 1;
1330 swizzle_pipe
[3] = 3;
1334 if (force_no_swizzle
) {
1335 swizzle_pipe
[0] = 0;
1336 swizzle_pipe
[1] = 1;
1337 swizzle_pipe
[2] = 2;
1338 swizzle_pipe
[3] = 3;
1339 swizzle_pipe
[4] = 4;
1340 swizzle_pipe
[5] = 5;
1342 swizzle_pipe
[0] = 0;
1343 swizzle_pipe
[1] = 2;
1344 swizzle_pipe
[2] = 4;
1345 swizzle_pipe
[3] = 1;
1346 swizzle_pipe
[4] = 3;
1347 swizzle_pipe
[5] = 5;
1351 if (force_no_swizzle
) {
1352 swizzle_pipe
[0] = 0;
1353 swizzle_pipe
[1] = 1;
1354 swizzle_pipe
[2] = 2;
1355 swizzle_pipe
[3] = 3;
1356 swizzle_pipe
[4] = 4;
1357 swizzle_pipe
[5] = 5;
1358 swizzle_pipe
[6] = 6;
1359 swizzle_pipe
[7] = 7;
1361 swizzle_pipe
[0] = 0;
1362 swizzle_pipe
[1] = 2;
1363 swizzle_pipe
[2] = 4;
1364 swizzle_pipe
[3] = 6;
1365 swizzle_pipe
[4] = 1;
1366 swizzle_pipe
[5] = 3;
1367 swizzle_pipe
[6] = 5;
1368 swizzle_pipe
[7] = 7;
1373 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1374 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1375 cur_backend
= (cur_backend
+ 1) % EVERGREEN_MAX_BACKENDS
;
1377 backend_map
|= (((cur_backend
& 0xf) << (swizzle_pipe
[cur_pipe
] * 4)));
1379 cur_backend
= (cur_backend
+ 1) % EVERGREEN_MAX_BACKENDS
;
1385 static void evergreen_gpu_init(struct radeon_device
*rdev
)
1387 u32 cc_rb_backend_disable
= 0;
1388 u32 cc_gc_shader_pipe_config
;
1389 u32 gb_addr_config
= 0;
1390 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1396 u32 sq_lds_resource_mgmt
;
1397 u32 sq_gpr_resource_mgmt_1
;
1398 u32 sq_gpr_resource_mgmt_2
;
1399 u32 sq_gpr_resource_mgmt_3
;
1400 u32 sq_thread_resource_mgmt
;
1401 u32 sq_thread_resource_mgmt_2
;
1402 u32 sq_stack_resource_mgmt_1
;
1403 u32 sq_stack_resource_mgmt_2
;
1404 u32 sq_stack_resource_mgmt_3
;
1405 u32 vgt_cache_invalidation
;
1406 u32 hdp_host_path_cntl
;
1407 int i
, j
, num_shader_engines
, ps_thread_count
;
1409 switch (rdev
->family
) {
1412 rdev
->config
.evergreen
.num_ses
= 2;
1413 rdev
->config
.evergreen
.max_pipes
= 4;
1414 rdev
->config
.evergreen
.max_tile_pipes
= 8;
1415 rdev
->config
.evergreen
.max_simds
= 10;
1416 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1417 rdev
->config
.evergreen
.max_gprs
= 256;
1418 rdev
->config
.evergreen
.max_threads
= 248;
1419 rdev
->config
.evergreen
.max_gs_threads
= 32;
1420 rdev
->config
.evergreen
.max_stack_entries
= 512;
1421 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1422 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1423 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1424 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1425 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1426 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1428 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1429 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1430 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1433 rdev
->config
.evergreen
.num_ses
= 1;
1434 rdev
->config
.evergreen
.max_pipes
= 4;
1435 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1436 rdev
->config
.evergreen
.max_simds
= 10;
1437 rdev
->config
.evergreen
.max_backends
= 4 * rdev
->config
.evergreen
.num_ses
;
1438 rdev
->config
.evergreen
.max_gprs
= 256;
1439 rdev
->config
.evergreen
.max_threads
= 248;
1440 rdev
->config
.evergreen
.max_gs_threads
= 32;
1441 rdev
->config
.evergreen
.max_stack_entries
= 512;
1442 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1443 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1444 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1445 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1446 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1447 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1449 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1450 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1451 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1454 rdev
->config
.evergreen
.num_ses
= 1;
1455 rdev
->config
.evergreen
.max_pipes
= 4;
1456 rdev
->config
.evergreen
.max_tile_pipes
= 4;
1457 rdev
->config
.evergreen
.max_simds
= 5;
1458 rdev
->config
.evergreen
.max_backends
= 2 * rdev
->config
.evergreen
.num_ses
;
1459 rdev
->config
.evergreen
.max_gprs
= 256;
1460 rdev
->config
.evergreen
.max_threads
= 248;
1461 rdev
->config
.evergreen
.max_gs_threads
= 32;
1462 rdev
->config
.evergreen
.max_stack_entries
= 256;
1463 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1464 rdev
->config
.evergreen
.sx_max_export_size
= 256;
1465 rdev
->config
.evergreen
.sx_max_export_pos_size
= 64;
1466 rdev
->config
.evergreen
.sx_max_export_smx_size
= 192;
1467 rdev
->config
.evergreen
.max_hw_contexts
= 8;
1468 rdev
->config
.evergreen
.sq_num_cf_insts
= 2;
1470 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x100;
1471 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1472 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1476 rdev
->config
.evergreen
.num_ses
= 1;
1477 rdev
->config
.evergreen
.max_pipes
= 2;
1478 rdev
->config
.evergreen
.max_tile_pipes
= 2;
1479 rdev
->config
.evergreen
.max_simds
= 2;
1480 rdev
->config
.evergreen
.max_backends
= 1 * rdev
->config
.evergreen
.num_ses
;
1481 rdev
->config
.evergreen
.max_gprs
= 256;
1482 rdev
->config
.evergreen
.max_threads
= 192;
1483 rdev
->config
.evergreen
.max_gs_threads
= 16;
1484 rdev
->config
.evergreen
.max_stack_entries
= 256;
1485 rdev
->config
.evergreen
.sx_num_of_sets
= 4;
1486 rdev
->config
.evergreen
.sx_max_export_size
= 128;
1487 rdev
->config
.evergreen
.sx_max_export_pos_size
= 32;
1488 rdev
->config
.evergreen
.sx_max_export_smx_size
= 96;
1489 rdev
->config
.evergreen
.max_hw_contexts
= 4;
1490 rdev
->config
.evergreen
.sq_num_cf_insts
= 1;
1492 rdev
->config
.evergreen
.sc_prim_fifo_size
= 0x40;
1493 rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
= 0x30;
1494 rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
= 0x130;
1498 /* Initialize HDP */
1499 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1500 WREG32((0x2c14 + j
), 0x00000000);
1501 WREG32((0x2c18 + j
), 0x00000000);
1502 WREG32((0x2c1c + j
), 0x00000000);
1503 WREG32((0x2c20 + j
), 0x00000000);
1504 WREG32((0x2c24 + j
), 0x00000000);
1507 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1509 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & ~2;
1511 cc_gc_shader_pipe_config
|=
1512 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK
<< rdev
->config
.evergreen
.max_pipes
)
1513 & EVERGREEN_MAX_PIPES_MASK
);
1514 cc_gc_shader_pipe_config
|=
1515 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK
<< rdev
->config
.evergreen
.max_simds
)
1516 & EVERGREEN_MAX_SIMDS_MASK
);
1518 cc_rb_backend_disable
=
1519 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK
<< rdev
->config
.evergreen
.max_backends
)
1520 & EVERGREEN_MAX_BACKENDS_MASK
);
1523 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1524 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1526 switch (rdev
->config
.evergreen
.max_tile_pipes
) {
1529 gb_addr_config
|= NUM_PIPES(0);
1532 gb_addr_config
|= NUM_PIPES(1);
1535 gb_addr_config
|= NUM_PIPES(2);
1538 gb_addr_config
|= NUM_PIPES(3);
1542 gb_addr_config
|= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1543 gb_addr_config
|= BANK_INTERLEAVE_SIZE(0);
1544 gb_addr_config
|= NUM_SHADER_ENGINES(rdev
->config
.evergreen
.num_ses
- 1);
1545 gb_addr_config
|= SHADER_ENGINE_TILE_SIZE(1);
1546 gb_addr_config
|= NUM_GPUS(0); /* Hemlock? */
1547 gb_addr_config
|= MULTI_GPU_TILE_SIZE(2);
1549 if (((mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
) > 2)
1550 gb_addr_config
|= ROW_SIZE(2);
1552 gb_addr_config
|= ROW_SIZE((mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
);
1554 if (rdev
->ddev
->pdev
->device
== 0x689e) {
1557 u8 efuse_box_bit_131_124
;
1559 WREG32(RCU_IND_INDEX
, 0x204);
1560 efuse_straps_4
= RREG32(RCU_IND_DATA
);
1561 WREG32(RCU_IND_INDEX
, 0x203);
1562 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1563 efuse_box_bit_131_124
= (u8
)(((efuse_straps_4
& 0xf) << 4) | ((efuse_straps_3
& 0xf0000000) >> 28));
1565 switch(efuse_box_bit_131_124
) {
1567 gb_backend_map
= 0x76543210;
1570 gb_backend_map
= 0x77553311;
1573 gb_backend_map
= 0x77553300;
1576 gb_backend_map
= 0x77552211;
1579 gb_backend_map
= 0x77443300;
1582 gb_backend_map
= 0x66552211;
1585 gb_backend_map
= 0x77552200;
1588 gb_backend_map
= 0x66442200;
1591 gb_backend_map
= 0x66553311;
1594 DRM_ERROR("bad backend map, using default\n");
1596 evergreen_get_tile_pipe_to_backend_map(rdev
,
1597 rdev
->config
.evergreen
.max_tile_pipes
,
1598 rdev
->config
.evergreen
.max_backends
,
1599 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1600 rdev
->config
.evergreen
.max_backends
) &
1601 EVERGREEN_MAX_BACKENDS_MASK
));
1604 } else if (rdev
->ddev
->pdev
->device
== 0x68b9) {
1606 u8 efuse_box_bit_127_124
;
1608 WREG32(RCU_IND_INDEX
, 0x203);
1609 efuse_straps_3
= RREG32(RCU_IND_DATA
);
1610 efuse_box_bit_127_124
= (u8
)((efuse_straps_3
& 0xF0000000) >> 28);
1612 switch(efuse_box_bit_127_124
) {
1614 gb_backend_map
= 0x00003210;
1620 gb_backend_map
= 0x00003311;
1623 DRM_ERROR("bad backend map, using default\n");
1625 evergreen_get_tile_pipe_to_backend_map(rdev
,
1626 rdev
->config
.evergreen
.max_tile_pipes
,
1627 rdev
->config
.evergreen
.max_backends
,
1628 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1629 rdev
->config
.evergreen
.max_backends
) &
1630 EVERGREEN_MAX_BACKENDS_MASK
));
1634 switch (rdev
->family
) {
1637 gb_backend_map
= 0x66442200;
1640 gb_backend_map
= 0x00006420;
1644 evergreen_get_tile_pipe_to_backend_map(rdev
,
1645 rdev
->config
.evergreen
.max_tile_pipes
,
1646 rdev
->config
.evergreen
.max_backends
,
1647 ((EVERGREEN_MAX_BACKENDS_MASK
<<
1648 rdev
->config
.evergreen
.max_backends
) &
1649 EVERGREEN_MAX_BACKENDS_MASK
));
1653 rdev
->config
.evergreen
.tile_config
= gb_addr_config
;
1654 WREG32(GB_BACKEND_MAP
, gb_backend_map
);
1655 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1656 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1657 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1659 num_shader_engines
= ((RREG32(GB_ADDR_CONFIG
) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1660 grbm_gfx_index
= INSTANCE_BROADCAST_WRITES
;
1662 for (i
= 0; i
< rdev
->config
.evergreen
.num_ses
; i
++) {
1663 u32 rb
= cc_rb_backend_disable
| (0xf0 << 16);
1664 u32 sp
= cc_gc_shader_pipe_config
;
1665 u32 gfx
= grbm_gfx_index
| SE_INDEX(i
);
1667 if (i
== num_shader_engines
) {
1668 rb
|= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK
);
1669 sp
|= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK
);
1672 WREG32(GRBM_GFX_INDEX
, gfx
);
1673 WREG32(RLC_GFX_INDEX
, gfx
);
1675 WREG32(CC_RB_BACKEND_DISABLE
, rb
);
1676 WREG32(CC_SYS_RB_BACKEND_DISABLE
, rb
);
1677 WREG32(GC_USER_RB_BACKEND_DISABLE
, rb
);
1678 WREG32(CC_GC_SHADER_PIPE_CONFIG
, sp
);
1681 grbm_gfx_index
|= SE_BROADCAST_WRITES
;
1682 WREG32(GRBM_GFX_INDEX
, grbm_gfx_index
);
1683 WREG32(RLC_GFX_INDEX
, grbm_gfx_index
);
1685 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
1686 WREG32(CGTS_TCC_DISABLE
, 0);
1687 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
1688 WREG32(CGTS_USER_TCC_DISABLE
, 0);
1690 /* set HW defaults for 3D engine */
1691 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
1692 ROQ_IB2_START(0x2b)));
1694 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
1696 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
1701 sx_debug_1
= RREG32(SX_DEBUG_1
);
1702 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
1703 WREG32(SX_DEBUG_1
, sx_debug_1
);
1706 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
1707 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
1708 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.evergreen
.sx_num_of_sets
);
1709 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
1711 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_size
/ 4) - 1) |
1712 POSITION_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_pos_size
/ 4) - 1) |
1713 SMX_BUFFER_SIZE((rdev
->config
.evergreen
.sx_max_export_smx_size
/ 4) - 1)));
1715 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.evergreen
.sc_prim_fifo_size
) |
1716 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_hiz_tile_fifo_size
) |
1717 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.evergreen
.sc_earlyz_tile_fifo_size
)));
1719 WREG32(VGT_NUM_INSTANCES
, 1);
1720 WREG32(SPI_CONFIG_CNTL
, 0);
1721 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
1722 WREG32(CP_PERFMON_CNTL
, 0);
1724 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.evergreen
.sq_num_cf_insts
) |
1725 FETCH_FIFO_HIWATER(0x4) |
1726 DONE_FIFO_HIWATER(0xe0) |
1727 ALU_UPDATE_FIFO_HIWATER(0x8)));
1729 sq_config
= RREG32(SQ_CONFIG
);
1730 sq_config
&= ~(PS_PRIO(3) |
1734 sq_config
|= (VC_ENABLE
|
1741 if (rdev
->family
== CHIP_CEDAR
)
1742 /* no vertex cache */
1743 sq_config
&= ~VC_ENABLE
;
1745 sq_lds_resource_mgmt
= RREG32(SQ_LDS_RESOURCE_MGMT
);
1747 sq_gpr_resource_mgmt_1
= NUM_PS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2))* 12 / 32);
1748 sq_gpr_resource_mgmt_1
|= NUM_VS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 6 / 32);
1749 sq_gpr_resource_mgmt_1
|= NUM_CLAUSE_TEMP_GPRS(4);
1750 sq_gpr_resource_mgmt_2
= NUM_GS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1751 sq_gpr_resource_mgmt_2
|= NUM_ES_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 4 / 32);
1752 sq_gpr_resource_mgmt_3
= NUM_HS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1753 sq_gpr_resource_mgmt_3
|= NUM_LS_GPRS((rdev
->config
.evergreen
.max_gprs
- (4 * 2)) * 3 / 32);
1755 if (rdev
->family
== CHIP_CEDAR
)
1756 ps_thread_count
= 96;
1758 ps_thread_count
= 128;
1760 sq_thread_resource_mgmt
= NUM_PS_THREADS(ps_thread_count
);
1761 sq_thread_resource_mgmt
|= NUM_VS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1762 sq_thread_resource_mgmt
|= NUM_GS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1763 sq_thread_resource_mgmt
|= NUM_ES_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1764 sq_thread_resource_mgmt_2
= NUM_HS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1765 sq_thread_resource_mgmt_2
|= NUM_LS_THREADS((((rdev
->config
.evergreen
.max_threads
- ps_thread_count
) / 6) / 8) * 8);
1767 sq_stack_resource_mgmt_1
= NUM_PS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1768 sq_stack_resource_mgmt_1
|= NUM_VS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1769 sq_stack_resource_mgmt_2
= NUM_GS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1770 sq_stack_resource_mgmt_2
|= NUM_ES_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1771 sq_stack_resource_mgmt_3
= NUM_HS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1772 sq_stack_resource_mgmt_3
|= NUM_LS_STACK_ENTRIES((rdev
->config
.evergreen
.max_stack_entries
* 1) / 6);
1774 WREG32(SQ_CONFIG
, sq_config
);
1775 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1776 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1777 WREG32(SQ_GPR_RESOURCE_MGMT_3
, sq_gpr_resource_mgmt_3
);
1778 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1779 WREG32(SQ_THREAD_RESOURCE_MGMT_2
, sq_thread_resource_mgmt_2
);
1780 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1781 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1782 WREG32(SQ_STACK_RESOURCE_MGMT_3
, sq_stack_resource_mgmt_3
);
1783 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
1784 WREG32(SQ_LDS_RESOURCE_MGMT
, sq_lds_resource_mgmt
);
1786 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
1787 FORCE_EOV_MAX_REZ_CNT(255)));
1789 if (rdev
->family
== CHIP_CEDAR
)
1790 vgt_cache_invalidation
= CACHE_INVALIDATION(TC_ONLY
);
1792 vgt_cache_invalidation
= CACHE_INVALIDATION(VC_AND_TC
);
1793 vgt_cache_invalidation
|= AUTO_INVLD_EN(ES_AND_GS_AUTO
);
1794 WREG32(VGT_CACHE_INVALIDATION
, vgt_cache_invalidation
);
1796 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1797 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1799 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
1800 WREG32(VGT_OUT_DEALLOC_CNTL
, 16);
1802 WREG32(CB_PERF_CTR0_SEL_0
, 0);
1803 WREG32(CB_PERF_CTR0_SEL_1
, 0);
1804 WREG32(CB_PERF_CTR1_SEL_0
, 0);
1805 WREG32(CB_PERF_CTR1_SEL_1
, 0);
1806 WREG32(CB_PERF_CTR2_SEL_0
, 0);
1807 WREG32(CB_PERF_CTR2_SEL_1
, 0);
1808 WREG32(CB_PERF_CTR3_SEL_0
, 0);
1809 WREG32(CB_PERF_CTR3_SEL_1
, 0);
1811 /* clear render buffer base addresses */
1812 WREG32(CB_COLOR0_BASE
, 0);
1813 WREG32(CB_COLOR1_BASE
, 0);
1814 WREG32(CB_COLOR2_BASE
, 0);
1815 WREG32(CB_COLOR3_BASE
, 0);
1816 WREG32(CB_COLOR4_BASE
, 0);
1817 WREG32(CB_COLOR5_BASE
, 0);
1818 WREG32(CB_COLOR6_BASE
, 0);
1819 WREG32(CB_COLOR7_BASE
, 0);
1820 WREG32(CB_COLOR8_BASE
, 0);
1821 WREG32(CB_COLOR9_BASE
, 0);
1822 WREG32(CB_COLOR10_BASE
, 0);
1823 WREG32(CB_COLOR11_BASE
, 0);
1825 /* set the shader const cache sizes to 0 */
1826 for (i
= SQ_ALU_CONST_BUFFER_SIZE_PS_0
; i
< 0x28200; i
+= 4)
1828 for (i
= SQ_ALU_CONST_BUFFER_SIZE_HS_0
; i
< 0x29000; i
+= 4)
1831 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
1832 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1834 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
1840 int evergreen_mc_init(struct radeon_device
*rdev
)
1843 int chansize
, numchan
;
1845 /* Get VRAM informations */
1846 rdev
->mc
.vram_is_ddr
= true;
1847 tmp
= RREG32(MC_ARB_RAMCFG
);
1848 if (tmp
& CHANSIZE_OVERRIDE
) {
1850 } else if (tmp
& CHANSIZE_MASK
) {
1855 tmp
= RREG32(MC_SHARED_CHMAP
);
1856 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1871 rdev
->mc
.vram_width
= numchan
* chansize
;
1872 /* Could aper size report 0 ? */
1873 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1874 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1875 /* Setup GPU memory space */
1876 /* size in MB on evergreen */
1877 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
1878 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
1879 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1880 rdev
->mc
.active_vram_size
= rdev
->mc
.visible_vram_size
;
1881 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1882 radeon_update_bandwidth_info(rdev
);
1887 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
)
1889 /* FIXME: implement for evergreen */
1893 static int evergreen_gpu_soft_reset(struct radeon_device
*rdev
)
1895 struct evergreen_mc_save save
;
1899 dev_info(rdev
->dev
, "GPU softreset \n");
1900 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
1901 RREG32(GRBM_STATUS
));
1902 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
1903 RREG32(GRBM_STATUS_SE0
));
1904 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
1905 RREG32(GRBM_STATUS_SE1
));
1906 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
1907 RREG32(SRBM_STATUS
));
1908 evergreen_mc_stop(rdev
, &save
);
1909 if (evergreen_mc_wait_for_idle(rdev
)) {
1910 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1912 /* Disable CP parsing/prefetching */
1913 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
1915 /* reset all the gfx blocks */
1916 grbm_reset
= (SOFT_RESET_CP
|
1929 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
1930 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
1931 (void)RREG32(GRBM_SOFT_RESET
);
1933 WREG32(GRBM_SOFT_RESET
, 0);
1934 (void)RREG32(GRBM_SOFT_RESET
);
1936 /* reset all the system blocks */
1937 srbm_reset
= SRBM_SOFT_RESET_ALL_MASK
;
1939 dev_info(rdev
->dev
, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset
);
1940 WREG32(SRBM_SOFT_RESET
, srbm_reset
);
1941 (void)RREG32(SRBM_SOFT_RESET
);
1943 WREG32(SRBM_SOFT_RESET
, 0);
1944 (void)RREG32(SRBM_SOFT_RESET
);
1945 /* Wait a little for things to settle down */
1947 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
1948 RREG32(GRBM_STATUS
));
1949 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
1950 RREG32(GRBM_STATUS_SE0
));
1951 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
1952 RREG32(GRBM_STATUS_SE1
));
1953 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
1954 RREG32(SRBM_STATUS
));
1955 /* After reset we need to reinit the asic as GPU often endup in an
1958 atom_asic_init(rdev
->mode_info
.atom_context
);
1959 evergreen_mc_resume(rdev
, &save
);
1963 int evergreen_asic_reset(struct radeon_device
*rdev
)
1965 return evergreen_gpu_soft_reset(rdev
);
1970 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
1974 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
1976 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
1978 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
1980 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
1982 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
1984 return RREG32(CRTC_STATUS_FRAME_COUNT
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
1990 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
)
1994 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
1995 WREG32(GRBM_INT_CNTL
, 0);
1996 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
1997 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
1998 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
1999 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2000 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2001 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2003 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
2004 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
2005 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
2006 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
2007 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
2008 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
2010 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2011 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2013 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2014 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2015 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2016 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2017 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2018 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2019 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2020 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2021 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2022 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2023 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2024 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2028 int evergreen_irq_set(struct radeon_device
*rdev
)
2030 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2031 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
2032 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
2033 u32 grbm_int_cntl
= 0;
2035 if (!rdev
->irq
.installed
) {
2036 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2039 /* don't enable anything if the ih is disabled */
2040 if (!rdev
->ih
.enabled
) {
2041 r600_disable_interrupts(rdev
);
2042 /* force the active interrupt state to all disabled */
2043 evergreen_disable_interrupt_state(rdev
);
2047 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2048 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2049 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2050 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2051 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2052 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2054 if (rdev
->irq
.sw_int
) {
2055 DRM_DEBUG("evergreen_irq_set: sw int\n");
2056 cp_int_cntl
|= RB_INT_ENABLE
;
2057 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
2059 if (rdev
->irq
.crtc_vblank_int
[0]) {
2060 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2061 crtc1
|= VBLANK_INT_MASK
;
2063 if (rdev
->irq
.crtc_vblank_int
[1]) {
2064 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2065 crtc2
|= VBLANK_INT_MASK
;
2067 if (rdev
->irq
.crtc_vblank_int
[2]) {
2068 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2069 crtc3
|= VBLANK_INT_MASK
;
2071 if (rdev
->irq
.crtc_vblank_int
[3]) {
2072 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2073 crtc4
|= VBLANK_INT_MASK
;
2075 if (rdev
->irq
.crtc_vblank_int
[4]) {
2076 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2077 crtc5
|= VBLANK_INT_MASK
;
2079 if (rdev
->irq
.crtc_vblank_int
[5]) {
2080 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2081 crtc6
|= VBLANK_INT_MASK
;
2083 if (rdev
->irq
.hpd
[0]) {
2084 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2085 hpd1
|= DC_HPDx_INT_EN
;
2087 if (rdev
->irq
.hpd
[1]) {
2088 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2089 hpd2
|= DC_HPDx_INT_EN
;
2091 if (rdev
->irq
.hpd
[2]) {
2092 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2093 hpd3
|= DC_HPDx_INT_EN
;
2095 if (rdev
->irq
.hpd
[3]) {
2096 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2097 hpd4
|= DC_HPDx_INT_EN
;
2099 if (rdev
->irq
.hpd
[4]) {
2100 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2101 hpd5
|= DC_HPDx_INT_EN
;
2103 if (rdev
->irq
.hpd
[5]) {
2104 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2105 hpd6
|= DC_HPDx_INT_EN
;
2107 if (rdev
->irq
.gui_idle
) {
2108 DRM_DEBUG("gui idle\n");
2109 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
2112 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2113 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
2115 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
2116 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
2117 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
2118 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
2119 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
2120 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
2122 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2123 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2124 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2125 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2126 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2127 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2132 static inline void evergreen_irq_ack(struct radeon_device
*rdev
,
2135 u32
*disp_int_cont2
,
2136 u32
*disp_int_cont3
,
2137 u32
*disp_int_cont4
,
2138 u32
*disp_int_cont5
)
2142 *disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2143 *disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2144 *disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
2145 *disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
2146 *disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
2147 *disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
2149 if (*disp_int
& LB_D1_VBLANK_INTERRUPT
)
2150 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
2151 if (*disp_int
& LB_D1_VLINE_INTERRUPT
)
2152 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
2154 if (*disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
2155 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
2156 if (*disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
2157 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
2159 if (*disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
2160 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
2161 if (*disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
2162 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
2164 if (*disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
2165 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
2166 if (*disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
2167 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
2169 if (*disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
2170 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
2171 if (*disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
2172 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
2174 if (*disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
2175 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
2176 if (*disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
2177 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
2179 if (*disp_int
& DC_HPD1_INTERRUPT
) {
2180 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
2181 tmp
|= DC_HPDx_INT_ACK
;
2182 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2184 if (*disp_int_cont
& DC_HPD2_INTERRUPT
) {
2185 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
2186 tmp
|= DC_HPDx_INT_ACK
;
2187 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2189 if (*disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2190 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
2191 tmp
|= DC_HPDx_INT_ACK
;
2192 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2194 if (*disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2195 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
2196 tmp
|= DC_HPDx_INT_ACK
;
2197 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2199 if (*disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2200 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2201 tmp
|= DC_HPDx_INT_ACK
;
2202 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2204 if (*disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2205 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2206 tmp
|= DC_HPDx_INT_ACK
;
2207 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2211 void evergreen_irq_disable(struct radeon_device
*rdev
)
2213 u32 disp_int
, disp_int_cont
, disp_int_cont2
;
2214 u32 disp_int_cont3
, disp_int_cont4
, disp_int_cont5
;
2216 r600_disable_interrupts(rdev
);
2217 /* Wait and acknowledge irq */
2219 evergreen_irq_ack(rdev
, &disp_int
, &disp_int_cont
, &disp_int_cont2
,
2220 &disp_int_cont3
, &disp_int_cont4
, &disp_int_cont5
);
2221 evergreen_disable_interrupt_state(rdev
);
2224 static void evergreen_irq_suspend(struct radeon_device
*rdev
)
2226 evergreen_irq_disable(rdev
);
2227 r600_rlc_stop(rdev
);
2230 static inline u32
evergreen_get_ih_wptr(struct radeon_device
*rdev
)
2234 if (rdev
->wb
.enabled
)
2235 wptr
= rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4];
2237 wptr
= RREG32(IH_RB_WPTR
);
2239 if (wptr
& RB_OVERFLOW
) {
2240 /* When a ring buffer overflow happen start parsing interrupt
2241 * from the last not overwritten vector (wptr + 16). Hopefully
2242 * this should allow us to catchup.
2244 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2245 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
2246 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
2247 tmp
= RREG32(IH_RB_CNTL
);
2248 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
2249 WREG32(IH_RB_CNTL
, tmp
);
2251 return (wptr
& rdev
->ih
.ptr_mask
);
2254 int evergreen_irq_process(struct radeon_device
*rdev
)
2256 u32 wptr
= evergreen_get_ih_wptr(rdev
);
2257 u32 rptr
= rdev
->ih
.rptr
;
2258 u32 src_id
, src_data
;
2260 u32 disp_int
, disp_int_cont
, disp_int_cont2
;
2261 u32 disp_int_cont3
, disp_int_cont4
, disp_int_cont5
;
2262 unsigned long flags
;
2263 bool queue_hotplug
= false;
2265 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
2266 if (!rdev
->ih
.enabled
)
2269 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
2272 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2275 if (rdev
->shutdown
) {
2276 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2281 /* display interrupts */
2282 evergreen_irq_ack(rdev
, &disp_int
, &disp_int_cont
, &disp_int_cont2
,
2283 &disp_int_cont3
, &disp_int_cont4
, &disp_int_cont5
);
2285 rdev
->ih
.wptr
= wptr
;
2286 while (rptr
!= wptr
) {
2287 /* wptr/rptr are in bytes! */
2288 ring_index
= rptr
/ 4;
2289 src_id
= rdev
->ih
.ring
[ring_index
] & 0xff;
2290 src_data
= rdev
->ih
.ring
[ring_index
+ 1] & 0xfffffff;
2293 case 1: /* D1 vblank/vline */
2295 case 0: /* D1 vblank */
2296 if (disp_int
& LB_D1_VBLANK_INTERRUPT
) {
2297 drm_handle_vblank(rdev
->ddev
, 0);
2298 wake_up(&rdev
->irq
.vblank_queue
);
2299 disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
2300 DRM_DEBUG("IH: D1 vblank\n");
2303 case 1: /* D1 vline */
2304 if (disp_int
& LB_D1_VLINE_INTERRUPT
) {
2305 disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
2306 DRM_DEBUG("IH: D1 vline\n");
2310 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2314 case 2: /* D2 vblank/vline */
2316 case 0: /* D2 vblank */
2317 if (disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
2318 drm_handle_vblank(rdev
->ddev
, 1);
2319 wake_up(&rdev
->irq
.vblank_queue
);
2320 disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
2321 DRM_DEBUG("IH: D2 vblank\n");
2324 case 1: /* D2 vline */
2325 if (disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
2326 disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
2327 DRM_DEBUG("IH: D2 vline\n");
2331 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2335 case 3: /* D3 vblank/vline */
2337 case 0: /* D3 vblank */
2338 if (disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
2339 drm_handle_vblank(rdev
->ddev
, 2);
2340 wake_up(&rdev
->irq
.vblank_queue
);
2341 disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
2342 DRM_DEBUG("IH: D3 vblank\n");
2345 case 1: /* D3 vline */
2346 if (disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
2347 disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
2348 DRM_DEBUG("IH: D3 vline\n");
2352 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2356 case 4: /* D4 vblank/vline */
2358 case 0: /* D4 vblank */
2359 if (disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
2360 drm_handle_vblank(rdev
->ddev
, 3);
2361 wake_up(&rdev
->irq
.vblank_queue
);
2362 disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
2363 DRM_DEBUG("IH: D4 vblank\n");
2366 case 1: /* D4 vline */
2367 if (disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
2368 disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
2369 DRM_DEBUG("IH: D4 vline\n");
2373 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2377 case 5: /* D5 vblank/vline */
2379 case 0: /* D5 vblank */
2380 if (disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
2381 drm_handle_vblank(rdev
->ddev
, 4);
2382 wake_up(&rdev
->irq
.vblank_queue
);
2383 disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
2384 DRM_DEBUG("IH: D5 vblank\n");
2387 case 1: /* D5 vline */
2388 if (disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
2389 disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
2390 DRM_DEBUG("IH: D5 vline\n");
2394 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2398 case 6: /* D6 vblank/vline */
2400 case 0: /* D6 vblank */
2401 if (disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
2402 drm_handle_vblank(rdev
->ddev
, 5);
2403 wake_up(&rdev
->irq
.vblank_queue
);
2404 disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
2405 DRM_DEBUG("IH: D6 vblank\n");
2408 case 1: /* D6 vline */
2409 if (disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
2410 disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
2411 DRM_DEBUG("IH: D6 vline\n");
2415 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2419 case 42: /* HPD hotplug */
2422 if (disp_int
& DC_HPD1_INTERRUPT
) {
2423 disp_int
&= ~DC_HPD1_INTERRUPT
;
2424 queue_hotplug
= true;
2425 DRM_DEBUG("IH: HPD1\n");
2429 if (disp_int_cont
& DC_HPD2_INTERRUPT
) {
2430 disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
2431 queue_hotplug
= true;
2432 DRM_DEBUG("IH: HPD2\n");
2436 if (disp_int_cont2
& DC_HPD3_INTERRUPT
) {
2437 disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
2438 queue_hotplug
= true;
2439 DRM_DEBUG("IH: HPD3\n");
2443 if (disp_int_cont3
& DC_HPD4_INTERRUPT
) {
2444 disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
2445 queue_hotplug
= true;
2446 DRM_DEBUG("IH: HPD4\n");
2450 if (disp_int_cont4
& DC_HPD5_INTERRUPT
) {
2451 disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
2452 queue_hotplug
= true;
2453 DRM_DEBUG("IH: HPD5\n");
2457 if (disp_int_cont5
& DC_HPD6_INTERRUPT
) {
2458 disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
2459 queue_hotplug
= true;
2460 DRM_DEBUG("IH: HPD6\n");
2464 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2468 case 176: /* CP_INT in ring buffer */
2469 case 177: /* CP_INT in IB1 */
2470 case 178: /* CP_INT in IB2 */
2471 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
2472 radeon_fence_process(rdev
);
2474 case 181: /* CP EOP event */
2475 DRM_DEBUG("IH: CP EOP\n");
2476 radeon_fence_process(rdev
);
2478 case 233: /* GUI IDLE */
2479 DRM_DEBUG("IH: CP EOP\n");
2480 rdev
->pm
.gui_idle
= true;
2481 wake_up(&rdev
->irq
.idle_queue
);
2484 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2488 /* wptr/rptr are in bytes! */
2490 rptr
&= rdev
->ih
.ptr_mask
;
2492 /* make sure wptr hasn't changed while processing */
2493 wptr
= evergreen_get_ih_wptr(rdev
);
2494 if (wptr
!= rdev
->ih
.wptr
)
2497 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
2498 rdev
->ih
.rptr
= rptr
;
2499 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
2500 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2504 static int evergreen_startup(struct radeon_device
*rdev
)
2508 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
2509 r
= r600_init_microcode(rdev
);
2511 DRM_ERROR("Failed to load firmware!\n");
2516 evergreen_mc_program(rdev
);
2517 if (rdev
->flags
& RADEON_IS_AGP
) {
2518 evergreen_agp_enable(rdev
);
2520 r
= evergreen_pcie_gart_enable(rdev
);
2524 evergreen_gpu_init(rdev
);
2526 r
= evergreen_blit_init(rdev
);
2528 evergreen_blit_fini(rdev
);
2529 rdev
->asic
->copy
= NULL
;
2530 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
2533 /* allocate wb buffer */
2534 r
= radeon_wb_init(rdev
);
2539 r
= r600_irq_init(rdev
);
2541 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2542 radeon_irq_kms_fini(rdev
);
2545 evergreen_irq_set(rdev
);
2547 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
2550 r
= evergreen_cp_load_microcode(rdev
);
2553 r
= evergreen_cp_resume(rdev
);
2560 int evergreen_resume(struct radeon_device
*rdev
)
2564 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2565 * posting will perform necessary task to bring back GPU into good
2569 atom_asic_init(rdev
->mode_info
.atom_context
);
2571 r
= evergreen_startup(rdev
);
2573 DRM_ERROR("r600 startup failed on resume\n");
2577 r
= r600_ib_test(rdev
);
2579 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
2587 int evergreen_suspend(struct radeon_device
*rdev
)
2591 /* FIXME: we should wait for ring to be empty */
2593 rdev
->cp
.ready
= false;
2594 evergreen_irq_suspend(rdev
);
2595 radeon_wb_disable(rdev
);
2596 evergreen_pcie_gart_disable(rdev
);
2598 /* unpin shaders bo */
2599 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
2600 if (likely(r
== 0)) {
2601 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
2602 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
2608 int evergreen_copy_blit(struct radeon_device
*rdev
,
2609 uint64_t src_offset
, uint64_t dst_offset
,
2610 unsigned num_pages
, struct radeon_fence
*fence
)
2614 mutex_lock(&rdev
->r600_blit
.mutex
);
2615 rdev
->r600_blit
.vb_ib
= NULL
;
2616 r
= evergreen_blit_prepare_copy(rdev
, num_pages
* RADEON_GPU_PAGE_SIZE
);
2618 if (rdev
->r600_blit
.vb_ib
)
2619 radeon_ib_free(rdev
, &rdev
->r600_blit
.vb_ib
);
2620 mutex_unlock(&rdev
->r600_blit
.mutex
);
2623 evergreen_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_pages
* RADEON_GPU_PAGE_SIZE
);
2624 evergreen_blit_done_copy(rdev
, fence
);
2625 mutex_unlock(&rdev
->r600_blit
.mutex
);
2629 static bool evergreen_card_posted(struct radeon_device
*rdev
)
2633 /* first check CRTCs */
2634 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
2635 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
) |
2636 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
2637 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
) |
2638 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
2639 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
2640 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
2643 /* then check MEM_SIZE, in case the crtcs are off */
2644 if (RREG32(CONFIG_MEMSIZE
))
2650 /* Plan is to move initialization in that function and use
2651 * helper function so that radeon_device_init pretty much
2652 * do nothing more than calling asic specific function. This
2653 * should also allow to remove a bunch of callback function
2656 int evergreen_init(struct radeon_device
*rdev
)
2660 r
= radeon_dummy_page_init(rdev
);
2663 /* This don't do much */
2664 r
= radeon_gem_init(rdev
);
2668 if (!radeon_get_bios(rdev
)) {
2669 if (ASIC_IS_AVIVO(rdev
))
2672 /* Must be an ATOMBIOS */
2673 if (!rdev
->is_atom_bios
) {
2674 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
2677 r
= radeon_atombios_init(rdev
);
2680 /* Post card if necessary */
2681 if (!evergreen_card_posted(rdev
)) {
2683 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2686 DRM_INFO("GPU not posted. posting now...\n");
2687 atom_asic_init(rdev
->mode_info
.atom_context
);
2689 /* Initialize scratch registers */
2690 r600_scratch_init(rdev
);
2691 /* Initialize surface registers */
2692 radeon_surface_init(rdev
);
2693 /* Initialize clocks */
2694 radeon_get_clock_info(rdev
->ddev
);
2696 r
= radeon_fence_driver_init(rdev
);
2699 /* initialize AGP */
2700 if (rdev
->flags
& RADEON_IS_AGP
) {
2701 r
= radeon_agp_init(rdev
);
2703 radeon_agp_disable(rdev
);
2705 /* initialize memory controller */
2706 r
= evergreen_mc_init(rdev
);
2709 /* Memory manager */
2710 r
= radeon_bo_init(rdev
);
2714 r
= radeon_irq_kms_init(rdev
);
2718 rdev
->cp
.ring_obj
= NULL
;
2719 r600_ring_init(rdev
, 1024 * 1024);
2721 rdev
->ih
.ring_obj
= NULL
;
2722 r600_ih_ring_init(rdev
, 64 * 1024);
2724 r
= r600_pcie_gart_init(rdev
);
2728 rdev
->accel_working
= true;
2729 r
= evergreen_startup(rdev
);
2731 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2733 r600_irq_fini(rdev
);
2734 radeon_wb_fini(rdev
);
2735 radeon_irq_kms_fini(rdev
);
2736 evergreen_pcie_gart_fini(rdev
);
2737 rdev
->accel_working
= false;
2739 if (rdev
->accel_working
) {
2740 r
= radeon_ib_pool_init(rdev
);
2742 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r
);
2743 rdev
->accel_working
= false;
2745 r
= r600_ib_test(rdev
);
2747 DRM_ERROR("radeon: failed testing IB (%d).\n", r
);
2748 rdev
->accel_working
= false;
2754 void evergreen_fini(struct radeon_device
*rdev
)
2756 evergreen_blit_fini(rdev
);
2758 r600_irq_fini(rdev
);
2759 radeon_wb_fini(rdev
);
2760 radeon_irq_kms_fini(rdev
);
2761 evergreen_pcie_gart_fini(rdev
);
2762 radeon_gem_fini(rdev
);
2763 radeon_fence_driver_fini(rdev
);
2764 radeon_agp_fini(rdev
);
2765 radeon_bo_fini(rdev
);
2766 radeon_atombios_fini(rdev
);
2769 radeon_dummy_page_fini(rdev
);