drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27
  28 #include "nv50.h"
  29
  30 int
  31 nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
  32 {
  33         const u32 hoff = (head * 0x800);
  34
  35         if (!(data & NV84_DISP_SOR_HDMI_PWR_STATE_ON)) {
  36                 nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000);
  37                 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
  38                 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
  39                 return 0;
  40         }
  41
  42         /* AVI InfoFrame */
  43         nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
  44         nv_wr32(priv, 0x616528 + hoff, 0x000d0282);
  45         nv_wr32(priv, 0x61652c + hoff, 0x0000006f);
  46         nv_wr32(priv, 0x616530 + hoff, 0x00000000);
  47         nv_wr32(priv, 0x616534 + hoff, 0x00000000);
  48         nv_wr32(priv, 0x616538 + hoff, 0x00000000);
  49         nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001);
  50
  51         /* Audio InfoFrame */
  52         nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
  53         nv_wr32(priv, 0x616508 + hoff, 0x000a0184);
  54         nv_wr32(priv, 0x61650c + hoff, 0x00000071);
  55         nv_wr32(priv, 0x616510 + hoff, 0x00000000);
  56         nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
  57
  58         /* ??? */
  59         nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
  60         nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
  61         nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
  62
  63         /* HDMI_CTRL */
  64         nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, data | 0x1f000000 /* ??? */);
  65         return 0;
  66 }