drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 struct gmbus_port {
  38         const char *name;
  39         int reg;
  40 };
  41
  42 static const struct gmbus_port gmbus_ports[] = {
  43         { "ssc", GPIOB },
  44         { "vga", GPIOA },
  45         { "panel", GPIOC },
  46         { "dpc", GPIOD },
  47         { "dpb", GPIOE },
  48         { "dpd", GPIOF },
  49 };
  50
  51 /* Intel GPIO access functions */
  52
  53 #define I2C_RISEFALL_TIME 10
  54
  55 static inline struct intel_gmbus *
  56 to_intel_gmbus(struct i2c_adapter *i2c)
  57 {
  58         return container_of(i2c, struct intel_gmbus, adapter);
  59 }
  60
  61 void
  62 intel_i2c_reset(struct drm_device *dev)
  63 {
  64         struct drm_i915_private *dev_priv = dev->dev_private;
  65         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
  66         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
  67 }
  68
  69 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  70 {
  71         u32 val;
  72
  73         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  74         if (!IS_PINEVIEW(dev_priv->dev))
  75                 return;
  76
  77         val = I915_READ(DSPCLK_GATE_D);
  78         if (enable)
  79                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  80         else
  81                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  82         I915_WRITE(DSPCLK_GATE_D, val);
  83 }
  84
  85 static u32 get_reserved(struct intel_gmbus *bus)
  86 {
  87         struct drm_i915_private *dev_priv = bus->dev_priv;
  88         struct drm_device *dev = dev_priv->dev;
  89         u32 reserved = 0;
  90
  91         /* On most chips, these bits must be preserved in software. */
  92         if (!IS_I830(dev) && !IS_845G(dev))
  93                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
  94                                              (GPIO_DATA_PULLUP_DISABLE |
  95                                               GPIO_CLOCK_PULLUP_DISABLE);
  96
  97         return reserved;
  98 }
  99
 100 static int get_clock(void *data)
 101 {
 102         struct intel_gmbus *bus = data;
 103         struct drm_i915_private *dev_priv = bus->dev_priv;
 104         u32 reserved = get_reserved(bus);
 105         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 106         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 107         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 108 }
 109
 110 static int get_data(void *data)
 111 {
 112         struct intel_gmbus *bus = data;
 113         struct drm_i915_private *dev_priv = bus->dev_priv;
 114         u32 reserved = get_reserved(bus);
 115         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 116         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 117         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 118 }
 119
 120 static void set_clock(void *data, int state_high)
 121 {
 122         struct intel_gmbus *bus = data;
 123         struct drm_i915_private *dev_priv = bus->dev_priv;
 124         u32 reserved = get_reserved(bus);
 125         u32 clock_bits;
 126
 127         if (state_high)
 128                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 129         else
 130                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 131                         GPIO_CLOCK_VAL_MASK;
 132
 133         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 134         POSTING_READ(bus->gpio_reg);
 135 }
 136
 137 static void set_data(void *data, int state_high)
 138 {
 139         struct intel_gmbus *bus = data;
 140         struct drm_i915_private *dev_priv = bus->dev_priv;
 141         u32 reserved = get_reserved(bus);
 142         u32 data_bits;
 143
 144         if (state_high)
 145                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 146         else
 147                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 148                         GPIO_DATA_VAL_MASK;
 149
 150         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 151         POSTING_READ(bus->gpio_reg);
 152 }
 153
 154 static int
 155 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 156 {
 157         struct intel_gmbus *bus = container_of(adapter,
 158                                                struct intel_gmbus,
 159                                                adapter);
 160         struct drm_i915_private *dev_priv = bus->dev_priv;
 161
 162         intel_i2c_reset(dev_priv->dev);
 163         intel_i2c_quirk_set(dev_priv, true);
 164         set_data(bus, 1);
 165         set_clock(bus, 1);
 166         udelay(I2C_RISEFALL_TIME);
 167         return 0;
 168 }
 169
 170 static void
 171 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 172 {
 173         struct intel_gmbus *bus = container_of(adapter,
 174                                                struct intel_gmbus,
 175                                                adapter);
 176         struct drm_i915_private *dev_priv = bus->dev_priv;
 177
 178         set_data(bus, 1);
 179         set_clock(bus, 1);
 180         intel_i2c_quirk_set(dev_priv, false);
 181 }
 182
 183 static void
 184 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
 185 {
 186         struct drm_i915_private *dev_priv = bus->dev_priv;
 187         struct i2c_algo_bit_data *algo;
 188
 189         algo = &bus->bit_algo;
 190
 191         /* -1 to map pin pair to gmbus index */
 192         bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
 193
 194         bus->adapter.algo_data = algo;
 195         algo->setsda = set_data;
 196         algo->setscl = set_clock;
 197         algo->getsda = get_data;
 198         algo->getscl = get_clock;
 199         algo->pre_xfer = intel_gpio_pre_xfer;
 200         algo->post_xfer = intel_gpio_post_xfer;
 201         algo->udelay = I2C_RISEFALL_TIME;
 202         algo->timeout = usecs_to_jiffies(2200);
 203         algo->data = bus;
 204 }
 205
 206 /*
 207  * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
 208  * mode. This results in spurious interrupt warnings if the legacy irq no. is
 209  * shared with another device. The kernel then disables that interrupt source
 210  * and so prevents the other device from working properly.
 211  */
 212 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
 213 static int
 214 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 215                      u32 gmbus2_status,
 216                      u32 gmbus4_irq_en)
 217 {
 218         int i;
 219         int reg_offset = dev_priv->gpio_mmio_base;
 220         u32 gmbus2 = 0;
 221         DEFINE_WAIT(wait);
 222
 223         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 224                 gmbus4_irq_en = 0;
 225
 226         /* Important: The hw handles only the first bit, so set only one! Since
 227          * we also need to check for NAKs besides the hw ready/idle signal, we
 228          * need to wake up periodically and check that ourselves. */
 229         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 230
 231         for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {
 232                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 233                                 TASK_UNINTERRUPTIBLE);
 234
 235                 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
 236                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 237                         break;
 238
 239                 schedule_timeout(1);
 240         }
 241         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 242
 243         I915_WRITE(GMBUS4 + reg_offset, 0);
 244
 245         if (gmbus2 & GMBUS_SATOER)
 246                 return -ENXIO;
 247         if (gmbus2 & gmbus2_status)
 248                 return 0;
 249         return -ETIMEDOUT;
 250 }
 251
 252 static int
 253 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 254 {
 255         int ret;
 256         int reg_offset = dev_priv->gpio_mmio_base;
 257
 258 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
 259
 260         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 261                 return wait_for(C, 10);
 262
 263         /* Important: The hw handles only the first bit, so set only one! */
 264         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
 265
 266         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
 267
 268         I915_WRITE(GMBUS4 + reg_offset, 0);
 269
 270         if (ret)
 271                 return 0;
 272         else
 273                 return -ETIMEDOUT;
 274 #undef C
 275 }
 276
 277 static int
 278 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 279                 u32 gmbus1_index)
 280 {
 281         int reg_offset = dev_priv->gpio_mmio_base;
 282         u16 len = msg->len;
 283         u8 *buf = msg->buf;
 284
 285         I915_WRITE(GMBUS1 + reg_offset,
 286                    gmbus1_index |
 287                    GMBUS_CYCLE_WAIT |
 288                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 289                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 290                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 291         while (len) {
 292                 int ret;
 293                 u32 val, loop = 0;
 294
 295                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 296                                            GMBUS_HW_RDY_EN);
 297                 if (ret)
 298                         return ret;
 299
 300                 val = I915_READ(GMBUS3 + reg_offset);
 301                 do {
 302                         *buf++ = val & 0xff;
 303                         val >>= 8;
 304                 } while (--len && ++loop < 4);
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int
 311 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 312 {
 313         int reg_offset = dev_priv->gpio_mmio_base;
 314         u16 len = msg->len;
 315         u8 *buf = msg->buf;
 316         u32 val, loop;
 317
 318         val = loop = 0;
 319         while (len && loop < 4) {
 320                 val |= *buf++ << (8 * loop++);
 321                 len -= 1;
 322         }
 323
 324         I915_WRITE(GMBUS3 + reg_offset, val);
 325         I915_WRITE(GMBUS1 + reg_offset,
 326                    GMBUS_CYCLE_WAIT |
 327                    (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
 328                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 329                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 330         while (len) {
 331                 int ret;
 332
 333                 val = loop = 0;
 334                 do {
 335                         val |= *buf++ << (8 * loop);
 336                 } while (--len && ++loop < 4);
 337
 338                 I915_WRITE(GMBUS3 + reg_offset, val);
 339
 340                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 341                                            GMBUS_HW_RDY_EN);
 342                 if (ret)
 343                         return ret;
 344         }
 345         return 0;
 346 }
 347
 348 /*
 349  * The gmbus controller can combine a 1 or 2 byte write with a read that
 350  * immediately follows it by using an "INDEX" cycle.
 351  */
 352 static bool
 353 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 354 {
 355         return (i + 1 < num &&
 356                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
 357                 (msgs[i + 1].flags & I2C_M_RD));
 358 }
 359
 360 static int
 361 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 362 {
 363         int reg_offset = dev_priv->gpio_mmio_base;
 364         u32 gmbus1_index = 0;
 365         u32 gmbus5 = 0;
 366         int ret;
 367
 368         if (msgs[0].len == 2)
 369                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 370                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 371         if (msgs[0].len == 1)
 372                 gmbus1_index = GMBUS_CYCLE_INDEX |
 373                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 374
 375         /* GMBUS5 holds 16-bit index */
 376         if (gmbus5)
 377                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
 378
 379         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 380
 381         /* Clear GMBUS5 after each index transfer */
 382         if (gmbus5)
 383                 I915_WRITE(GMBUS5 + reg_offset, 0);
 384
 385         return ret;
 386 }
 387
 388 static int
 389 gmbus_xfer(struct i2c_adapter *adapter,
 390            struct i2c_msg *msgs,
 391            int num)
 392 {
 393         struct intel_gmbus *bus = container_of(adapter,
 394                                                struct intel_gmbus,
 395                                                adapter);
 396         struct drm_i915_private *dev_priv = bus->dev_priv;
 397         int i, reg_offset;
 398         int ret = 0;
 399
 400         mutex_lock(&dev_priv->gmbus_mutex);
 401
 402         if (bus->force_bit) {
 403                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 404                 goto out;
 405         }
 406
 407         reg_offset = dev_priv->gpio_mmio_base;
 408
 409         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 410
 411         for (i = 0; i < num; i++) {
 412                 if (gmbus_is_index_read(msgs, i, num)) {
 413                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 414                         i += 1;  /* set i to the index of the read xfer */
 415                 } else if (msgs[i].flags & I2C_M_RD) {
 416                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 417                 } else {
 418                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 419                 }
 420
 421                 if (ret == -ETIMEDOUT)
 422                         goto timeout;
 423                 if (ret == -ENXIO)
 424                         goto clear_err;
 425
 426                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
 427                                            GMBUS_HW_WAIT_EN);
 428                 if (ret == -ENXIO)
 429                         goto clear_err;
 430                 if (ret)
 431                         goto timeout;
 432         }
 433
 434         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 435          * a STOP on the very first cycle. To simplify the code we
 436          * unconditionally generate the STOP condition with an additional gmbus
 437          * cycle. */
 438         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 439
 440         /* Mark the GMBUS interface as disabled after waiting for idle.
 441          * We will re-enable it at the start of the next xfer,
 442          * till then let it sleep.
 443          */
 444         if (gmbus_wait_idle(dev_priv)) {
 445                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 446                          adapter->name);
 447                 ret = -ETIMEDOUT;
 448         }
 449         I915_WRITE(GMBUS0 + reg_offset, 0);
 450         ret = ret ?: i;
 451         goto out;
 452
 453 clear_err:
 454         /*
 455          * Wait for bus to IDLE before clearing NAK.
 456          * If we clear the NAK while bus is still active, then it will stay
 457          * active and the next transaction may fail.
 458          *
 459          * If no ACK is received during the address phase of a transaction, the
 460          * adapter must report -ENXIO. It is not clear what to return if no ACK
 461          * is received at other times. But we have to be careful to not return
 462          * spurious -ENXIO because that will prevent i2c and drm edid functions
 463          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 464          * timing out seems to happen when there _is_ a ddc chip present, but
 465          * it's slow responding and only answers on the 2nd retry.
 466          */
 467         ret = -ENXIO;
 468         if (gmbus_wait_idle(dev_priv)) {
 469                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 470                               adapter->name);
 471                 ret = -ETIMEDOUT;
 472         }
 473
 474         /* Toggle the Software Clear Interrupt bit. This has the effect
 475          * of resetting the GMBUS controller and so clearing the
 476          * BUS_ERROR raised by the slave's NAK.
 477          */
 478         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 479         I915_WRITE(GMBUS1 + reg_offset, 0);
 480         I915_WRITE(GMBUS0 + reg_offset, 0);
 481
 482         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 483                          adapter->name, msgs[i].addr,
 484                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 485
 486         goto out;
 487
 488 timeout:
 489         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 490                  bus->adapter.name, bus->reg0 & 0xff);
 491         I915_WRITE(GMBUS0 + reg_offset, 0);
 492
 493         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 494         bus->force_bit = 1;
 495         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 496
 497 out:
 498         mutex_unlock(&dev_priv->gmbus_mutex);
 499         return ret;
 500 }
 501
 502 static u32 gmbus_func(struct i2c_adapter *adapter)
 503 {
 504         return i2c_bit_algo.functionality(adapter) &
 505                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 506                 /* I2C_FUNC_10BIT_ADDR | */
 507                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 508                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 509 }
 510
 511 static const struct i2c_algorithm gmbus_algorithm = {
 512         .master_xfer    = gmbus_xfer,
 513         .functionality  = gmbus_func
 514 };
 515
 516 /**
 517  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 518  * @dev: DRM device
 519  */
 520 int intel_setup_gmbus(struct drm_device *dev)
 521 {
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         int ret, i;
 524
 525         if (HAS_PCH_NOP(dev))
 526                 return 0;
 527         else if (HAS_PCH_SPLIT(dev))
 528                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 529         else if (IS_VALLEYVIEW(dev))
 530                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 531         else
 532                 dev_priv->gpio_mmio_base = 0;
 533
 534         mutex_init(&dev_priv->gmbus_mutex);
 535         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 536
 537         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 538                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 539                 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
 540
 541                 bus->adapter.owner = THIS_MODULE;
 542                 bus->adapter.class = I2C_CLASS_DDC;
 543                 snprintf(bus->adapter.name,
 544                          sizeof(bus->adapter.name),
 545                          "i915 gmbus %s",
 546                          gmbus_ports[i].name);
 547
 548                 bus->adapter.dev.parent = &dev->pdev->dev;
 549                 bus->dev_priv = dev_priv;
 550
 551                 bus->adapter.algo = &gmbus_algorithm;
 552
 553                 /* By default use a conservative clock rate */
 554                 bus->reg0 = port | GMBUS_RATE_100KHZ;
 555
 556                 /* gmbus seems to be broken on i830 */
 557                 if (IS_I830(dev))
 558                         bus->force_bit = 1;
 559
 560                 intel_gpio_setup(bus, port);
 561
 562                 ret = i2c_add_adapter(&bus->adapter);
 563                 if (ret)
 564                         goto err;
 565         }
 566
 567         intel_i2c_reset(dev_priv->dev);
 568
 569         return 0;
 570
 571 err:
 572         while (--i) {
 573                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 574                 i2c_del_adapter(&bus->adapter);
 575         }
 576         return ret;
 577 }
 578
 579 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 580                                             unsigned port)
 581 {
 582         WARN_ON(!intel_gmbus_is_port_valid(port));
 583         /* -1 to map pin pair to gmbus index */
 584         return (intel_gmbus_is_port_valid(port)) ?
 585                 &dev_priv->gmbus[port - 1].adapter : NULL;
 586 }
 587
 588 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 589 {
 590         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 591
 592         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 593 }
 594
 595 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 596 {
 597         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 598
 599         bus->force_bit += force_bit ? 1 : -1;
 600         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
 601                       force_bit ? "en" : "dis", adapter->name,
 602                       bus->force_bit);
 603 }
 604
 605 void intel_teardown_gmbus(struct drm_device *dev)
 606 {
 607         struct drm_i915_private *dev_priv = dev->dev_private;
 608         int i;
 609
 610         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 611                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 612                 i2c_del_adapter(&bus->adapter);
 613         }
 614 }