2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll
)(const intel_limit_t
*limit
,
88 struct drm_crtc
*crtc
,
89 int target
, int refclk
,
90 intel_clock_t
*match_clock
,
91 intel_clock_t
*best_clock
);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 WARN_ON(!HAS_PCH_SPLIT(dev
));
104 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
108 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
109 int target
, int refclk
, intel_clock_t
*match_clock
,
110 intel_clock_t
*best_clock
);
112 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
117 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
118 int target
, int refclk
, intel_clock_t
*match_clock
,
119 intel_clock_t
*best_clock
);
121 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
122 int target
, int refclk
, intel_clock_t
*match_clock
,
123 intel_clock_t
*best_clock
);
126 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
127 int target
, int refclk
, intel_clock_t
*match_clock
,
128 intel_clock_t
*best_clock
);
130 static inline u32
/* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 2, .max
= 33 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 4, .p2_fast
= 2 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i8xx_lvds
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 930000, .max
= 1400000 },
157 .n
= { .min
= 3, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 1, .max
= 6 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 14, .p2_fast
= 7 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_sdvo
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 8, .max
= 18 },
174 .m2
= { .min
= 3, .max
= 7 },
175 .p
= { .min
= 5, .max
= 80 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 200000,
178 .p2_slow
= 10, .p2_fast
= 5 },
179 .find_pll
= intel_find_best_PLL
,
182 static const intel_limit_t intel_limits_i9xx_lvds
= {
183 .dot
= { .min
= 20000, .max
= 400000 },
184 .vco
= { .min
= 1400000, .max
= 2800000 },
185 .n
= { .min
= 1, .max
= 6 },
186 .m
= { .min
= 70, .max
= 120 },
187 .m1
= { .min
= 8, .max
= 18 },
188 .m2
= { .min
= 3, .max
= 7 },
189 .p
= { .min
= 7, .max
= 98 },
190 .p1
= { .min
= 1, .max
= 8 },
191 .p2
= { .dot_limit
= 112000,
192 .p2_slow
= 14, .p2_fast
= 7 },
193 .find_pll
= intel_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_sdvo
= {
198 .dot
= { .min
= 25000, .max
= 270000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 17, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 10, .max
= 30 },
205 .p1
= { .min
= 1, .max
= 3},
206 .p2
= { .dot_limit
= 270000,
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_hdmi
= {
214 .dot
= { .min
= 22000, .max
= 400000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 16, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 5, .max
= 80 },
221 .p1
= { .min
= 1, .max
= 8},
222 .p2
= { .dot_limit
= 165000,
223 .p2_slow
= 10, .p2_fast
= 5 },
224 .find_pll
= intel_g4x_find_best_PLL
,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
228 .dot
= { .min
= 20000, .max
= 115000 },
229 .vco
= { .min
= 1750000, .max
= 3500000 },
230 .n
= { .min
= 1, .max
= 3 },
231 .m
= { .min
= 104, .max
= 138 },
232 .m1
= { .min
= 17, .max
= 23 },
233 .m2
= { .min
= 5, .max
= 11 },
234 .p
= { .min
= 28, .max
= 112 },
235 .p1
= { .min
= 2, .max
= 8 },
236 .p2
= { .dot_limit
= 0,
237 .p2_slow
= 14, .p2_fast
= 14
239 .find_pll
= intel_g4x_find_best_PLL
,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
243 .dot
= { .min
= 80000, .max
= 224000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 14, .max
= 42 },
250 .p1
= { .min
= 2, .max
= 6 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 7, .p2_fast
= 7
254 .find_pll
= intel_g4x_find_best_PLL
,
257 static const intel_limit_t intel_limits_g4x_display_port
= {
258 .dot
= { .min
= 161670, .max
= 227000 },
259 .vco
= { .min
= 1750000, .max
= 3500000},
260 .n
= { .min
= 1, .max
= 2 },
261 .m
= { .min
= 97, .max
= 108 },
262 .m1
= { .min
= 0x10, .max
= 0x12 },
263 .m2
= { .min
= 0x05, .max
= 0x06 },
264 .p
= { .min
= 10, .max
= 20 },
265 .p1
= { .min
= 1, .max
= 2},
266 .p2
= { .dot_limit
= 0,
267 .p2_slow
= 10, .p2_fast
= 10 },
268 .find_pll
= intel_find_pll_g4x_dp
,
271 static const intel_limit_t intel_limits_pineview_sdvo
= {
272 .dot
= { .min
= 20000, .max
= 400000},
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n
= { .min
= 3, .max
= 6 },
276 .m
= { .min
= 2, .max
= 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 5, .max
= 80 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 200000,
283 .p2_slow
= 10, .p2_fast
= 5 },
284 .find_pll
= intel_find_best_PLL
,
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
298 .find_pll
= intel_find_best_PLL
,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 5 },
310 .m
= { .min
= 79, .max
= 127 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 5, .max
= 80 },
314 .p1
= { .min
= 1, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 10, .p2_fast
= 5 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 118 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 28, .max
= 112 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 14, .p2_fast
= 14 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 3 },
338 .m
= { .min
= 79, .max
= 127 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 14, .max
= 56 },
342 .p1
= { .min
= 2, .max
= 8 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 7, .p2_fast
= 7 },
345 .find_pll
= intel_g4x_find_best_PLL
,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000 },
366 .n
= { .min
= 1, .max
= 3 },
367 .m
= { .min
= 79, .max
= 126 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 14, .max
= 42 },
371 .p1
= { .min
= 2, .max
= 6 },
372 .p2
= { .dot_limit
= 225000,
373 .p2_slow
= 7, .p2_fast
= 7 },
374 .find_pll
= intel_g4x_find_best_PLL
,
377 static const intel_limit_t intel_limits_ironlake_display_port
= {
378 .dot
= { .min
= 25000, .max
= 350000 },
379 .vco
= { .min
= 1760000, .max
= 3510000},
380 .n
= { .min
= 1, .max
= 2 },
381 .m
= { .min
= 81, .max
= 90 },
382 .m1
= { .min
= 12, .max
= 22 },
383 .m2
= { .min
= 5, .max
= 9 },
384 .p
= { .min
= 10, .max
= 20 },
385 .p1
= { .min
= 1, .max
= 2},
386 .p2
= { .dot_limit
= 0,
387 .p2_slow
= 10, .p2_fast
= 10 },
388 .find_pll
= intel_find_pll_ironlake_dp
,
391 static const intel_limit_t intel_limits_vlv_dac
= {
392 .dot
= { .min
= 25000, .max
= 270000 },
393 .vco
= { .min
= 4000000, .max
= 6000000 },
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 22, .max
= 450 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_hdmi
= {
406 .dot
= { .min
= 20000, .max
= 165000 },
407 .vco
= { .min
= 4000000, .max
= 5994000},
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 60, .max
= 300 }, /* guess */
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 static const intel_limit_t intel_limits_vlv_dp
= {
420 .dot
= { .min
= 25000, .max
= 270000 },
421 .vco
= { .min
= 4000000, .max
= 6000000 },
422 .n
= { .min
= 1, .max
= 7 },
423 .m
= { .min
= 22, .max
= 450 },
424 .m1
= { .min
= 2, .max
= 3 },
425 .m2
= { .min
= 11, .max
= 156 },
426 .p
= { .min
= 10, .max
= 30 },
427 .p1
= { .min
= 2, .max
= 3 },
428 .p2
= { .dot_limit
= 270000,
429 .p2_slow
= 2, .p2_fast
= 20 },
430 .find_pll
= intel_vlv_find_best_pll
,
433 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
435 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG
, reg
);
443 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA
);
453 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
456 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA
, val
);
464 I915_WRITE(DPIO_REG
, reg
);
465 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device
*dev
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL
, 0);
477 POSTING_READ(DPIO_CTL
);
478 I915_WRITE(DPIO_CTL
, 1);
479 POSTING_READ(DPIO_CTL
);
482 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
485 struct drm_device
*dev
= crtc
->dev
;
486 const intel_limit_t
*limit
;
488 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
489 if (intel_is_dual_link_lvds(dev
)) {
490 if (refclk
== 100000)
491 limit
= &intel_limits_ironlake_dual_lvds_100m
;
493 limit
= &intel_limits_ironlake_dual_lvds
;
495 if (refclk
== 100000)
496 limit
= &intel_limits_ironlake_single_lvds_100m
;
498 limit
= &intel_limits_ironlake_single_lvds
;
500 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
501 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
502 limit
= &intel_limits_ironlake_display_port
;
504 limit
= &intel_limits_ironlake_dac
;
509 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
511 struct drm_device
*dev
= crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
515 if (intel_is_dual_link_lvds(dev
))
516 limit
= &intel_limits_g4x_dual_channel_lvds
;
518 limit
= &intel_limits_g4x_single_channel_lvds
;
519 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
520 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
521 limit
= &intel_limits_g4x_hdmi
;
522 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
523 limit
= &intel_limits_g4x_sdvo
;
524 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
525 limit
= &intel_limits_g4x_display_port
;
526 } else /* The option is for other outputs */
527 limit
= &intel_limits_i9xx_sdvo
;
532 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
534 struct drm_device
*dev
= crtc
->dev
;
535 const intel_limit_t
*limit
;
537 if (HAS_PCH_SPLIT(dev
))
538 limit
= intel_ironlake_limit(crtc
, refclk
);
539 else if (IS_G4X(dev
)) {
540 limit
= intel_g4x_limit(crtc
);
541 } else if (IS_PINEVIEW(dev
)) {
542 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
543 limit
= &intel_limits_pineview_lvds
;
545 limit
= &intel_limits_pineview_sdvo
;
546 } else if (IS_VALLEYVIEW(dev
)) {
547 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
548 limit
= &intel_limits_vlv_dac
;
549 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
550 limit
= &intel_limits_vlv_hdmi
;
552 limit
= &intel_limits_vlv_dp
;
553 } else if (!IS_GEN2(dev
)) {
554 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
555 limit
= &intel_limits_i9xx_lvds
;
557 limit
= &intel_limits_i9xx_sdvo
;
559 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
560 limit
= &intel_limits_i8xx_lvds
;
562 limit
= &intel_limits_i8xx_dvo
;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
570 clock
->m
= clock
->m2
+ 2;
571 clock
->p
= clock
->p1
* clock
->p2
;
572 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
573 clock
->dot
= clock
->vco
/ clock
->p
;
576 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
578 if (IS_PINEVIEW(dev
)) {
579 pineview_clock(refclk
, clock
);
582 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
583 clock
->p
= clock
->p1
* clock
->p2
;
584 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
585 clock
->dot
= clock
->vco
/ clock
->p
;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
593 struct drm_device
*dev
= crtc
->dev
;
594 struct intel_encoder
*encoder
;
596 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
597 if (encoder
->type
== type
)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device
*dev
,
610 const intel_limit_t
*limit
,
611 const intel_clock_t
*clock
)
613 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
616 INTELPllInvalid("p out of range\n");
617 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
625 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
626 INTELPllInvalid("n out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
640 int target
, int refclk
, intel_clock_t
*match_clock
,
641 intel_clock_t
*best_clock
)
644 struct drm_device
*dev
= crtc
->dev
;
648 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 clock
.p2
= limit
->p2
.p2_fast
;
657 clock
.p2
= limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 clock
.p2
= limit
->p2
.p2_slow
;
662 clock
.p2
= limit
->p2
.p2_fast
;
665 memset(best_clock
, 0, sizeof(*best_clock
));
667 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
669 for (clock
.m2
= limit
->m2
.min
;
670 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
671 /* m1 is always 0 in Pineview */
672 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
674 for (clock
.n
= limit
->n
.min
;
675 clock
.n
<= limit
->n
.max
; clock
.n
++) {
676 for (clock
.p1
= limit
->p1
.min
;
677 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
680 intel_clock(dev
, refclk
, &clock
);
681 if (!intel_PLL_is_valid(dev
, limit
,
685 clock
.p
!= match_clock
->p
)
688 this_err
= abs(clock
.dot
- target
);
689 if (this_err
< err
) {
698 return (err
!= target
);
702 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
703 int target
, int refclk
, intel_clock_t
*match_clock
,
704 intel_clock_t
*best_clock
)
706 struct drm_device
*dev
= crtc
->dev
;
710 /* approximately equals target * 0.00585 */
711 int err_most
= (target
>> 8) + (target
>> 9);
714 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (HAS_PCH_SPLIT(dev
))
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
733 max_n
= limit
->n
.max
;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock
.m1
= limit
->m1
.max
;
738 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
739 for (clock
.m2
= limit
->m2
.max
;
740 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
741 for (clock
.p1
= limit
->p1
.max
;
742 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
745 intel_clock(dev
, refclk
, &clock
);
746 if (!intel_PLL_is_valid(dev
, limit
,
750 clock
.p
!= match_clock
->p
)
753 this_err
= abs(clock
.dot
- target
);
754 if (this_err
< err_most
) {
768 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
769 int target
, int refclk
, intel_clock_t
*match_clock
,
770 intel_clock_t
*best_clock
)
772 struct drm_device
*dev
= crtc
->dev
;
775 if (target
< 200000) {
788 intel_clock(dev
, refclk
, &clock
);
789 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
796 int target
, int refclk
, intel_clock_t
*match_clock
,
797 intel_clock_t
*best_clock
)
800 if (target
< 200000) {
813 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
814 clock
.p
= (clock
.p1
* clock
.p2
);
815 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
817 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
821 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
822 int target
, int refclk
, intel_clock_t
*match_clock
,
823 intel_clock_t
*best_clock
)
825 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
827 u32 updrate
, minupdate
, fracbits
, p
;
828 unsigned long bestppm
, ppm
, absppm
;
832 dotclk
= target
* 1000;
835 fastclk
= dotclk
/ (2*100);
839 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
840 bestm1
= bestm2
= bestp1
= bestp2
= 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
844 updrate
= refclk
/ n
;
845 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
846 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
852 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
853 refclk
) / (2*refclk
));
856 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
857 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
858 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
859 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
863 if (absppm
< bestppm
- 10) {
880 best_clock
->n
= bestn
;
881 best_clock
->m1
= bestm1
;
882 best_clock
->m2
= bestm2
;
883 best_clock
->p1
= bestp1
;
884 best_clock
->p2
= bestp2
;
889 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
892 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
895 return intel_crtc
->config
.cpu_transcoder
;
898 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
903 frame
= I915_READ(frame_reg
);
905 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 int pipestat_reg
= PIPESTAT(pipe
);
922 if (INTEL_INFO(dev
)->gen
>= 5) {
923 ironlake_wait_for_vblank(dev
, pipe
);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg
,
941 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg
) &
945 PIPE_VBLANK_INTERRUPT_STATUS
,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (INTEL_INFO(dev
)->gen
>= 4) {
974 int reg
= PIPECONF(cpu_transcoder
);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line
, line_mask
;
982 int reg
= PIPEDSL(pipe
);
983 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
986 line_mask
= DSL_LINEMASK_GEN2
;
988 line_mask
= DSL_LINEMASK_GEN3
;
990 /* Wait for the display line to settle */
992 last_line
= I915_READ(reg
) & line_mask
;
994 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
995 time_after(timeout
, jiffies
));
996 if (time_after(jiffies
, timeout
))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1009 struct intel_digital_port
*port
)
1013 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1014 switch(port
->port
) {
1016 bit
= SDE_PORTB_HOTPLUG
;
1019 bit
= SDE_PORTC_HOTPLUG
;
1022 bit
= SDE_PORTD_HOTPLUG
;
1028 switch(port
->port
) {
1030 bit
= SDE_PORTB_HOTPLUG_CPT
;
1033 bit
= SDE_PORTC_HOTPLUG_CPT
;
1036 bit
= SDE_PORTD_HOTPLUG_CPT
;
1043 return I915_READ(SDEISR
) & bit
;
1046 static const char *state_string(bool enabled
)
1048 return enabled
? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private
*dev_priv
,
1053 enum pipe pipe
, bool state
)
1060 val
= I915_READ(reg
);
1061 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1062 WARN(cur_state
!= state
,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state
), state_string(cur_state
));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1071 struct intel_pch_pll
*pll
,
1072 struct intel_crtc
*crtc
,
1078 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1087 val
= I915_READ(pll
->pll_reg
);
1088 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1089 WARN(cur_state
!= state
,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1097 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1098 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1099 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state
, crtc
->pipe
, pch_dpll
)) {
1102 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1103 WARN(cur_state
!= state
,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll
->pll_reg
== _PCH_DPLL_B
,
1106 state_string(state
),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
->dev
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1130 reg
= FDI_TX_CTL(pipe
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& FDI_TX_ENABLE
);
1134 WARN(cur_state
!= state
,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state
), state_string(cur_state
));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv
->info
->gen
== 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
->dev
))
1172 reg
= FDI_TX_CTL(pipe
);
1173 val
= I915_READ(reg
);
1174 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1183 reg
= FDI_RX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1191 int pp_reg
, lvds_reg
;
1193 enum pipe panel_pipe
= PIPE_A
;
1196 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1197 pp_reg
= PCH_PP_CONTROL
;
1198 lvds_reg
= PCH_LVDS
;
1200 pp_reg
= PP_CONTROL
;
1204 val
= I915_READ(pp_reg
);
1205 if (!(val
& PANEL_POWER_ON
) ||
1206 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1209 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1210 panel_pipe
= PIPE_B
;
1212 WARN(panel_pipe
== pipe
&& locked
,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1223 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1230 if (!intel_using_power_well(dev_priv
->dev
) &&
1231 cpu_transcoder
!= TRANSCODER_EDP
) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv
->dev
) || IS_VALLEYVIEW(dev_priv
->dev
)) {
1271 reg
= DSPCNTR(pipe
);
1272 val
= I915_READ(reg
);
1273 WARN((val
& DISPLAY_PLANE_ENABLE
),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i
= 0; i
< 2; i
++) {
1282 val
= I915_READ(reg
);
1283 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1284 DISPPLANE_SEL_PIPE_SHIFT
;
1285 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i
), pipe_name(pipe
));
1291 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1297 if (!IS_VALLEYVIEW(dev_priv
->dev
))
1300 /* Need to check both planes against the pipe */
1301 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1302 reg
= SPCNTR(pipe
, i
);
1303 val
= I915_READ(reg
);
1304 WARN((val
& SP_ENABLE
),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe
* 2 + i
, pipe_name(pipe
));
1310 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1315 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1320 val
= I915_READ(PCH_DREF_CONTROL
);
1321 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1322 DREF_SUPERSPREAD_SOURCE_MASK
));
1323 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1326 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1333 reg
= TRANSCONF(pipe
);
1334 val
= I915_READ(reg
);
1335 enabled
= !!(val
& TRANS_ENABLE
);
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1341 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1342 enum pipe pipe
, u32 port_sel
, u32 val
)
1344 if ((val
& DP_PORT_EN
) == 0)
1347 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1348 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1349 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1350 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1353 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1359 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1360 enum pipe pipe
, u32 val
)
1362 if ((val
& SDVO_ENABLE
) == 0)
1365 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1366 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1369 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1375 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1376 enum pipe pipe
, u32 val
)
1378 if ((val
& LVDS_PORT_EN
) == 0)
1381 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1382 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1385 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1391 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1392 enum pipe pipe
, u32 val
)
1394 if ((val
& ADPA_DAC_ENABLE
) == 0)
1396 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1397 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1400 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1406 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1407 enum pipe pipe
, int reg
, u32 port_sel
)
1409 u32 val
= I915_READ(reg
);
1410 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412 reg
, pipe_name(pipe
));
1414 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1415 && (val
& DP_PIPEB_SELECT
),
1416 "IBX PCH dp port still using transcoder B\n");
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1420 enum pipe pipe
, int reg
)
1422 u32 val
= I915_READ(reg
);
1423 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425 reg
, pipe_name(pipe
));
1427 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1428 && (val
& SDVO_PIPE_B_SELECT
),
1429 "IBX PCH hdmi port still using transcoder B\n");
1432 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1438 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1439 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1440 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1443 val
= I915_READ(reg
);
1444 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
1449 val
= I915_READ(reg
);
1450 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1454 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1455 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1456 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1468 * Note! This is for pre-ILK only.
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1472 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1477 /* No really, not for ILK+ */
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1482 assert_panel_unlocked(dev_priv
, pipe
);
1485 val
= I915_READ(reg
);
1486 val
|= DPLL_VCO_ENABLE
;
1488 /* We do this three times for luck */
1489 I915_WRITE(reg
, val
);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg
, val
);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg
, val
);
1497 udelay(150); /* wait for warmup */
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1507 * Note! This is for pre-ILK only.
1509 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv
, pipe
);
1522 val
= I915_READ(reg
);
1523 val
&= ~DPLL_VCO_ENABLE
;
1524 I915_WRITE(reg
, val
);
1530 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1531 enum intel_sbi_destination destination
)
1535 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1537 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1543 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1544 I915_WRITE(SBI_DATA
, value
);
1546 if (destination
== SBI_ICLK
)
1547 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1549 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1550 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1552 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1560 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1561 enum intel_sbi_destination destination
)
1564 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1566 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
1572 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1574 if (destination
== SBI_ICLK
)
1575 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1577 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1578 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1580 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1586 return I915_READ(SBI_DATA
);
1590 * ironlake_enable_pch_pll - enable PCH PLL
1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1597 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1599 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1600 struct intel_pch_pll
*pll
;
1604 /* PCH PLLs only available on ILK, SNB and IVB */
1605 BUG_ON(dev_priv
->info
->gen
< 5);
1606 pll
= intel_crtc
->pch_pll
;
1610 if (WARN_ON(pll
->refcount
== 0))
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll
->pll_reg
, pll
->active
, pll
->on
,
1615 intel_crtc
->base
.base
.id
);
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv
);
1620 if (pll
->active
++ && pll
->on
) {
1621 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1628 val
= I915_READ(reg
);
1629 val
|= DPLL_VCO_ENABLE
;
1630 I915_WRITE(reg
, val
);
1637 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1639 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1640 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv
->info
->gen
< 5);
1649 if (WARN_ON(pll
->refcount
== 0))
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll
->pll_reg
, pll
->active
, pll
->on
,
1654 intel_crtc
->base
.base
.id
);
1656 if (WARN_ON(pll
->active
== 0)) {
1657 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1661 if (--pll
->active
) {
1662 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1672 val
= I915_READ(reg
);
1673 val
&= ~DPLL_VCO_ENABLE
;
1674 I915_WRITE(reg
, val
);
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1684 struct drm_device
*dev
= dev_priv
->dev
;
1685 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1686 uint32_t reg
, val
, pipeconf_val
;
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv
->info
->gen
< 5);
1691 /* Make sure PCH DPLL is enabled */
1692 assert_pch_pll_enabled(dev_priv
,
1693 to_intel_crtc(crtc
)->pch_pll
,
1694 to_intel_crtc(crtc
));
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv
, pipe
);
1698 assert_fdi_rx_enabled(dev_priv
, pipe
);
1700 if (HAS_PCH_CPT(dev
)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg
= TRANS_CHICKEN2(pipe
);
1704 val
= I915_READ(reg
);
1705 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1706 I915_WRITE(reg
, val
);
1709 reg
= TRANSCONF(pipe
);
1710 val
= I915_READ(reg
);
1711 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1713 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1718 val
&= ~PIPECONF_BPC_MASK
;
1719 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1722 val
&= ~TRANS_INTERLACE_MASK
;
1723 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1724 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1725 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1726 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1728 val
|= TRANS_INTERLACED
;
1730 val
|= TRANS_PROGRESSIVE
;
1732 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1733 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1738 enum transcoder cpu_transcoder
)
1740 u32 val
, pipeconf_val
;
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv
->info
->gen
< 5);
1745 /* FDI must be feeding us bits for PCH ports */
1746 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1747 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1749 /* Workaround: set timing override bit. */
1750 val
= I915_READ(_TRANSA_CHICKEN2
);
1751 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1752 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1755 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1757 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1758 PIPECONF_INTERLACED_ILK
)
1759 val
|= TRANS_INTERLACED
;
1761 val
|= TRANS_PROGRESSIVE
;
1763 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1764 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1771 struct drm_device
*dev
= dev_priv
->dev
;
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv
, pipe
);
1776 assert_fdi_rx_disabled(dev_priv
, pipe
);
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv
, pipe
);
1781 reg
= TRANSCONF(pipe
);
1782 val
= I915_READ(reg
);
1783 val
&= ~TRANS_ENABLE
;
1784 I915_WRITE(reg
, val
);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1789 if (!HAS_PCH_IBX(dev
)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg
= TRANS_CHICKEN2(pipe
);
1792 val
= I915_READ(reg
);
1793 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1794 I915_WRITE(reg
, val
);
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1802 val
= I915_READ(_TRANSACONF
);
1803 val
&= ~TRANS_ENABLE
;
1804 I915_WRITE(_TRANSACONF
, val
);
1805 /* wait for PCH transcoder off, transcoder state */
1806 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
1809 /* Workaround: clear timing override bit. */
1810 val
= I915_READ(_TRANSA_CHICKEN2
);
1811 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1812 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1816 * intel_enable_pipe - enable a pipe, asserting requirements
1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1824 * @pipe should be %PIPE_A or %PIPE_B.
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1829 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1832 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1834 enum pipe pch_transcoder
;
1838 if (HAS_PCH_LPT(dev_priv
->dev
))
1839 pch_transcoder
= TRANSCODER_A
;
1841 pch_transcoder
= pipe
;
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1848 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1849 assert_pll_enabled(dev_priv
, pipe
);
1852 /* if driving the PCH, we need FDI enabled */
1853 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1854 assert_fdi_tx_pll_enabled(dev_priv
,
1855 (enum pipe
) cpu_transcoder
);
1857 /* FIXME: assert CPU port conditions for SNB+ */
1860 reg
= PIPECONF(cpu_transcoder
);
1861 val
= I915_READ(reg
);
1862 if (val
& PIPECONF_ENABLE
)
1865 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1866 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1870 * intel_disable_pipe - disable a pipe, asserting requirements
1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1877 * @pipe should be %PIPE_A or %PIPE_B.
1879 * Will wait until the pipe has shut down before returning.
1881 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1884 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1893 assert_planes_disabled(dev_priv
, pipe
);
1894 assert_sprites_disabled(dev_priv
, pipe
);
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1900 reg
= PIPECONF(cpu_transcoder
);
1901 val
= I915_READ(reg
);
1902 if ((val
& PIPECONF_ENABLE
) == 0)
1905 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1906 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1913 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1916 if (dev_priv
->info
->gen
>= 4)
1917 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1919 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1930 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1931 enum plane plane
, enum pipe pipe
)
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv
, pipe
);
1939 reg
= DSPCNTR(plane
);
1940 val
= I915_READ(reg
);
1941 if (val
& DISPLAY_PLANE_ENABLE
)
1944 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1945 intel_flush_display_plane(dev_priv
, plane
);
1946 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1955 * Disable @plane; should be an independent operation.
1957 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1958 enum plane plane
, enum pipe pipe
)
1963 reg
= DSPCNTR(plane
);
1964 val
= I915_READ(reg
);
1965 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1968 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1969 intel_flush_display_plane(dev_priv
, plane
);
1970 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1973 static bool need_vtd_wa(struct drm_device
*dev
)
1975 #ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1983 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1984 struct drm_i915_gem_object
*obj
,
1985 struct intel_ring_buffer
*pipelined
)
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1991 switch (obj
->tiling_mode
) {
1992 case I915_TILING_NONE
:
1993 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1994 alignment
= 128 * 1024;
1995 else if (INTEL_INFO(dev
)->gen
>= 4)
1996 alignment
= 4 * 1024;
1998 alignment
= 64 * 1024;
2001 /* pin() will align the object as required by fence */
2005 /* Despite that we check this in framebuffer_init userspace can
2006 * screw us over and change the tiling after the fact. Only
2007 * pinned buffers can't change their tiling. */
2008 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2014 /* Note that the w/a also requires 64 PTE of padding following the
2015 * bo. We currently fill all unused PTE with the shadow page and so
2016 * we should always have valid PTE following the scanout preventing
2019 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2020 alignment
= 256 * 1024;
2022 dev_priv
->mm
.interruptible
= false;
2023 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2025 goto err_interruptible
;
2027 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2028 * fence, whereas 965+ only requires a fence if using
2029 * framebuffer compression. For simplicity, we always install
2030 * a fence as the cost is not that onerous.
2032 ret
= i915_gem_object_get_fence(obj
);
2036 i915_gem_object_pin_fence(obj
);
2038 dev_priv
->mm
.interruptible
= true;
2042 i915_gem_object_unpin(obj
);
2044 dev_priv
->mm
.interruptible
= true;
2048 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2050 i915_gem_object_unpin_fence(obj
);
2051 i915_gem_object_unpin(obj
);
2054 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2055 * is assumed to be a power-of-two. */
2056 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2057 unsigned int tiling_mode
,
2061 if (tiling_mode
!= I915_TILING_NONE
) {
2062 unsigned int tile_rows
, tiles
;
2067 tiles
= *x
/ (512/cpp
);
2070 return tile_rows
* pitch
* 8 + tiles
* 4096;
2072 unsigned int offset
;
2074 offset
= *y
* pitch
+ *x
* cpp
;
2076 *x
= (offset
& 4095) / cpp
;
2077 return offset
& -4096;
2081 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2084 struct drm_device
*dev
= crtc
->dev
;
2085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2087 struct intel_framebuffer
*intel_fb
;
2088 struct drm_i915_gem_object
*obj
;
2089 int plane
= intel_crtc
->plane
;
2090 unsigned long linear_offset
;
2099 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2103 intel_fb
= to_intel_framebuffer(fb
);
2104 obj
= intel_fb
->obj
;
2106 reg
= DSPCNTR(plane
);
2107 dspcntr
= I915_READ(reg
);
2108 /* Mask out pixel format bits in case we change it */
2109 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2110 switch (fb
->pixel_format
) {
2112 dspcntr
|= DISPPLANE_8BPP
;
2114 case DRM_FORMAT_XRGB1555
:
2115 case DRM_FORMAT_ARGB1555
:
2116 dspcntr
|= DISPPLANE_BGRX555
;
2118 case DRM_FORMAT_RGB565
:
2119 dspcntr
|= DISPPLANE_BGRX565
;
2121 case DRM_FORMAT_XRGB8888
:
2122 case DRM_FORMAT_ARGB8888
:
2123 dspcntr
|= DISPPLANE_BGRX888
;
2125 case DRM_FORMAT_XBGR8888
:
2126 case DRM_FORMAT_ABGR8888
:
2127 dspcntr
|= DISPPLANE_RGBX888
;
2129 case DRM_FORMAT_XRGB2101010
:
2130 case DRM_FORMAT_ARGB2101010
:
2131 dspcntr
|= DISPPLANE_BGRX101010
;
2133 case DRM_FORMAT_XBGR2101010
:
2134 case DRM_FORMAT_ABGR2101010
:
2135 dspcntr
|= DISPPLANE_RGBX101010
;
2141 if (INTEL_INFO(dev
)->gen
>= 4) {
2142 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2143 dspcntr
|= DISPPLANE_TILED
;
2145 dspcntr
&= ~DISPPLANE_TILED
;
2148 I915_WRITE(reg
, dspcntr
);
2150 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2152 if (INTEL_INFO(dev
)->gen
>= 4) {
2153 intel_crtc
->dspaddr_offset
=
2154 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2155 fb
->bits_per_pixel
/ 8,
2157 linear_offset
-= intel_crtc
->dspaddr_offset
;
2159 intel_crtc
->dspaddr_offset
= linear_offset
;
2162 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2163 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2164 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2165 if (INTEL_INFO(dev
)->gen
>= 4) {
2166 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2167 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2168 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2169 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2171 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2177 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2178 struct drm_framebuffer
*fb
, int x
, int y
)
2180 struct drm_device
*dev
= crtc
->dev
;
2181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2183 struct intel_framebuffer
*intel_fb
;
2184 struct drm_i915_gem_object
*obj
;
2185 int plane
= intel_crtc
->plane
;
2186 unsigned long linear_offset
;
2196 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2200 intel_fb
= to_intel_framebuffer(fb
);
2201 obj
= intel_fb
->obj
;
2203 reg
= DSPCNTR(plane
);
2204 dspcntr
= I915_READ(reg
);
2205 /* Mask out pixel format bits in case we change it */
2206 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2207 switch (fb
->pixel_format
) {
2209 dspcntr
|= DISPPLANE_8BPP
;
2211 case DRM_FORMAT_RGB565
:
2212 dspcntr
|= DISPPLANE_BGRX565
;
2214 case DRM_FORMAT_XRGB8888
:
2215 case DRM_FORMAT_ARGB8888
:
2216 dspcntr
|= DISPPLANE_BGRX888
;
2218 case DRM_FORMAT_XBGR8888
:
2219 case DRM_FORMAT_ABGR8888
:
2220 dspcntr
|= DISPPLANE_RGBX888
;
2222 case DRM_FORMAT_XRGB2101010
:
2223 case DRM_FORMAT_ARGB2101010
:
2224 dspcntr
|= DISPPLANE_BGRX101010
;
2226 case DRM_FORMAT_XBGR2101010
:
2227 case DRM_FORMAT_ABGR2101010
:
2228 dspcntr
|= DISPPLANE_RGBX101010
;
2234 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2235 dspcntr
|= DISPPLANE_TILED
;
2237 dspcntr
&= ~DISPPLANE_TILED
;
2240 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2242 I915_WRITE(reg
, dspcntr
);
2244 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2245 intel_crtc
->dspaddr_offset
=
2246 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2247 fb
->bits_per_pixel
/ 8,
2249 linear_offset
-= intel_crtc
->dspaddr_offset
;
2251 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2252 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2253 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2254 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2255 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2256 if (IS_HASWELL(dev
)) {
2257 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2259 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2260 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2267 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2269 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2270 int x
, int y
, enum mode_set_atomic state
)
2272 struct drm_device
*dev
= crtc
->dev
;
2273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 if (dev_priv
->display
.disable_fbc
)
2276 dev_priv
->display
.disable_fbc(dev
);
2277 intel_increase_pllclock(crtc
);
2279 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2282 void intel_display_handle_reset(struct drm_device
*dev
)
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 struct drm_crtc
*crtc
;
2288 * Flips in the rings have been nuked by the reset,
2289 * so complete all pending flips so that user space
2290 * will get its events and not get stuck.
2292 * Also update the base address of all primary
2293 * planes to the the last fb to make sure we're
2294 * showing the correct fb after a reset.
2296 * Need to make two loops over the crtcs so that we
2297 * don't try to grab a crtc mutex before the
2298 * pending_flip_queue really got woken up.
2301 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2302 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2303 enum plane plane
= intel_crtc
->plane
;
2305 intel_prepare_page_flip(dev
, plane
);
2306 intel_finish_page_flip_plane(dev
, plane
);
2309 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2312 mutex_lock(&crtc
->mutex
);
2313 if (intel_crtc
->active
)
2314 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2316 mutex_unlock(&crtc
->mutex
);
2321 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2323 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2324 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2325 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2328 /* Big Hammer, we also need to ensure that any pending
2329 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2330 * current scanout is retired before unpinning the old
2333 * This should only fail upon a hung GPU, in which case we
2334 * can safely continue.
2336 dev_priv
->mm
.interruptible
= false;
2337 ret
= i915_gem_object_finish_gpu(obj
);
2338 dev_priv
->mm
.interruptible
= was_interruptible
;
2343 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2345 struct drm_device
*dev
= crtc
->dev
;
2346 struct drm_i915_master_private
*master_priv
;
2347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2349 if (!dev
->primary
->master
)
2352 master_priv
= dev
->primary
->master
->driver_priv
;
2353 if (!master_priv
->sarea_priv
)
2356 switch (intel_crtc
->pipe
) {
2358 master_priv
->sarea_priv
->pipeA_x
= x
;
2359 master_priv
->sarea_priv
->pipeA_y
= y
;
2362 master_priv
->sarea_priv
->pipeB_x
= x
;
2363 master_priv
->sarea_priv
->pipeB_y
= y
;
2371 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2372 struct drm_framebuffer
*fb
)
2374 struct drm_device
*dev
= crtc
->dev
;
2375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2376 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2377 struct drm_framebuffer
*old_fb
;
2382 DRM_ERROR("No FB bound\n");
2386 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2387 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2389 INTEL_INFO(dev
)->num_pipes
);
2393 mutex_lock(&dev
->struct_mutex
);
2394 ret
= intel_pin_and_fence_fb_obj(dev
,
2395 to_intel_framebuffer(fb
)->obj
,
2398 mutex_unlock(&dev
->struct_mutex
);
2399 DRM_ERROR("pin & fence failed\n");
2403 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2405 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2406 mutex_unlock(&dev
->struct_mutex
);
2407 DRM_ERROR("failed to update base address\n");
2417 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2418 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2421 intel_update_fbc(dev
);
2422 mutex_unlock(&dev
->struct_mutex
);
2424 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2429 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2431 struct drm_device
*dev
= crtc
->dev
;
2432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2434 int pipe
= intel_crtc
->pipe
;
2437 /* enable normal train */
2438 reg
= FDI_TX_CTL(pipe
);
2439 temp
= I915_READ(reg
);
2440 if (IS_IVYBRIDGE(dev
)) {
2441 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2442 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2444 temp
&= ~FDI_LINK_TRAIN_NONE
;
2445 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2447 I915_WRITE(reg
, temp
);
2449 reg
= FDI_RX_CTL(pipe
);
2450 temp
= I915_READ(reg
);
2451 if (HAS_PCH_CPT(dev
)) {
2452 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2453 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2455 temp
&= ~FDI_LINK_TRAIN_NONE
;
2456 temp
|= FDI_LINK_TRAIN_NONE
;
2458 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2460 /* wait one idle pattern time */
2464 /* IVB wants error correction enabled */
2465 if (IS_IVYBRIDGE(dev
))
2466 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2467 FDI_FE_ERRC_ENABLE
);
2470 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2473 struct intel_crtc
*pipe_B_crtc
=
2474 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2475 struct intel_crtc
*pipe_C_crtc
=
2476 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2479 /* When everything is off disable fdi C so that we could enable fdi B
2480 * with all lanes. XXX: This misses the case where a pipe is not using
2481 * any pch resources and so doesn't need any fdi lanes. */
2482 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2486 temp
= I915_READ(SOUTH_CHICKEN1
);
2487 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2488 DRM_DEBUG_KMS("disabling fdi C rx\n");
2489 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2493 /* The FDI link training functions for ILK/Ibexpeak. */
2494 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2496 struct drm_device
*dev
= crtc
->dev
;
2497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2499 int pipe
= intel_crtc
->pipe
;
2500 int plane
= intel_crtc
->plane
;
2501 u32 reg
, temp
, tries
;
2503 /* FDI needs bits from pipe & plane first */
2504 assert_pipe_enabled(dev_priv
, pipe
);
2505 assert_plane_enabled(dev_priv
, plane
);
2507 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 reg
= FDI_RX_IMR(pipe
);
2510 temp
= I915_READ(reg
);
2511 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2512 temp
&= ~FDI_RX_BIT_LOCK
;
2513 I915_WRITE(reg
, temp
);
2517 /* enable CPU FDI TX and PCH FDI RX */
2518 reg
= FDI_TX_CTL(pipe
);
2519 temp
= I915_READ(reg
);
2521 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2522 temp
&= ~FDI_LINK_TRAIN_NONE
;
2523 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2524 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2526 reg
= FDI_RX_CTL(pipe
);
2527 temp
= I915_READ(reg
);
2528 temp
&= ~FDI_LINK_TRAIN_NONE
;
2529 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2530 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2535 /* Ironlake workaround, enable clock pointer after FDI enable*/
2536 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2537 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2538 FDI_RX_PHASE_SYNC_POINTER_EN
);
2540 reg
= FDI_RX_IIR(pipe
);
2541 for (tries
= 0; tries
< 5; tries
++) {
2542 temp
= I915_READ(reg
);
2543 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2545 if ((temp
& FDI_RX_BIT_LOCK
)) {
2546 DRM_DEBUG_KMS("FDI train 1 done.\n");
2547 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2552 DRM_ERROR("FDI train 1 fail!\n");
2555 reg
= FDI_TX_CTL(pipe
);
2556 temp
= I915_READ(reg
);
2557 temp
&= ~FDI_LINK_TRAIN_NONE
;
2558 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2559 I915_WRITE(reg
, temp
);
2561 reg
= FDI_RX_CTL(pipe
);
2562 temp
= I915_READ(reg
);
2563 temp
&= ~FDI_LINK_TRAIN_NONE
;
2564 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2565 I915_WRITE(reg
, temp
);
2570 reg
= FDI_RX_IIR(pipe
);
2571 for (tries
= 0; tries
< 5; tries
++) {
2572 temp
= I915_READ(reg
);
2573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2575 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2576 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2582 DRM_ERROR("FDI train 2 fail!\n");
2584 DRM_DEBUG_KMS("FDI train done\n");
2588 static const int snb_b_fdi_train_param
[] = {
2589 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2590 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2591 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2592 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2595 /* The FDI link training functions for SNB/Cougarpoint. */
2596 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2598 struct drm_device
*dev
= crtc
->dev
;
2599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2600 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2601 int pipe
= intel_crtc
->pipe
;
2602 u32 reg
, temp
, i
, retry
;
2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606 reg
= FDI_RX_IMR(pipe
);
2607 temp
= I915_READ(reg
);
2608 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2609 temp
&= ~FDI_RX_BIT_LOCK
;
2610 I915_WRITE(reg
, temp
);
2615 /* enable CPU FDI TX and PCH FDI RX */
2616 reg
= FDI_TX_CTL(pipe
);
2617 temp
= I915_READ(reg
);
2619 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2620 temp
&= ~FDI_LINK_TRAIN_NONE
;
2621 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2622 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2624 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2625 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2627 I915_WRITE(FDI_RX_MISC(pipe
),
2628 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2630 reg
= FDI_RX_CTL(pipe
);
2631 temp
= I915_READ(reg
);
2632 if (HAS_PCH_CPT(dev
)) {
2633 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2634 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2636 temp
&= ~FDI_LINK_TRAIN_NONE
;
2637 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2639 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2644 for (i
= 0; i
< 4; i
++) {
2645 reg
= FDI_TX_CTL(pipe
);
2646 temp
= I915_READ(reg
);
2647 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2648 temp
|= snb_b_fdi_train_param
[i
];
2649 I915_WRITE(reg
, temp
);
2654 for (retry
= 0; retry
< 5; retry
++) {
2655 reg
= FDI_RX_IIR(pipe
);
2656 temp
= I915_READ(reg
);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2658 if (temp
& FDI_RX_BIT_LOCK
) {
2659 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2660 DRM_DEBUG_KMS("FDI train 1 done.\n");
2669 DRM_ERROR("FDI train 1 fail!\n");
2672 reg
= FDI_TX_CTL(pipe
);
2673 temp
= I915_READ(reg
);
2674 temp
&= ~FDI_LINK_TRAIN_NONE
;
2675 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2677 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2679 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2681 I915_WRITE(reg
, temp
);
2683 reg
= FDI_RX_CTL(pipe
);
2684 temp
= I915_READ(reg
);
2685 if (HAS_PCH_CPT(dev
)) {
2686 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2687 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2689 temp
&= ~FDI_LINK_TRAIN_NONE
;
2690 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2692 I915_WRITE(reg
, temp
);
2697 for (i
= 0; i
< 4; i
++) {
2698 reg
= FDI_TX_CTL(pipe
);
2699 temp
= I915_READ(reg
);
2700 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2701 temp
|= snb_b_fdi_train_param
[i
];
2702 I915_WRITE(reg
, temp
);
2707 for (retry
= 0; retry
< 5; retry
++) {
2708 reg
= FDI_RX_IIR(pipe
);
2709 temp
= I915_READ(reg
);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2711 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2712 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2713 DRM_DEBUG_KMS("FDI train 2 done.\n");
2722 DRM_ERROR("FDI train 2 fail!\n");
2724 DRM_DEBUG_KMS("FDI train done.\n");
2727 /* Manual link training for Ivy Bridge A0 parts */
2728 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2730 struct drm_device
*dev
= crtc
->dev
;
2731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2732 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2733 int pipe
= intel_crtc
->pipe
;
2736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2738 reg
= FDI_RX_IMR(pipe
);
2739 temp
= I915_READ(reg
);
2740 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2741 temp
&= ~FDI_RX_BIT_LOCK
;
2742 I915_WRITE(reg
, temp
);
2747 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2748 I915_READ(FDI_RX_IIR(pipe
)));
2750 /* enable CPU FDI TX and PCH FDI RX */
2751 reg
= FDI_TX_CTL(pipe
);
2752 temp
= I915_READ(reg
);
2754 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2755 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2756 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2757 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2758 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2759 temp
|= FDI_COMPOSITE_SYNC
;
2760 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2762 I915_WRITE(FDI_RX_MISC(pipe
),
2763 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2765 reg
= FDI_RX_CTL(pipe
);
2766 temp
= I915_READ(reg
);
2767 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2768 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2769 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2770 temp
|= FDI_COMPOSITE_SYNC
;
2771 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2776 for (i
= 0; i
< 4; i
++) {
2777 reg
= FDI_TX_CTL(pipe
);
2778 temp
= I915_READ(reg
);
2779 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2780 temp
|= snb_b_fdi_train_param
[i
];
2781 I915_WRITE(reg
, temp
);
2786 reg
= FDI_RX_IIR(pipe
);
2787 temp
= I915_READ(reg
);
2788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2790 if (temp
& FDI_RX_BIT_LOCK
||
2791 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2792 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2793 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2798 DRM_ERROR("FDI train 1 fail!\n");
2801 reg
= FDI_TX_CTL(pipe
);
2802 temp
= I915_READ(reg
);
2803 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2804 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2805 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2806 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2807 I915_WRITE(reg
, temp
);
2809 reg
= FDI_RX_CTL(pipe
);
2810 temp
= I915_READ(reg
);
2811 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2812 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2813 I915_WRITE(reg
, temp
);
2818 for (i
= 0; i
< 4; i
++) {
2819 reg
= FDI_TX_CTL(pipe
);
2820 temp
= I915_READ(reg
);
2821 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2822 temp
|= snb_b_fdi_train_param
[i
];
2823 I915_WRITE(reg
, temp
);
2828 reg
= FDI_RX_IIR(pipe
);
2829 temp
= I915_READ(reg
);
2830 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2832 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2833 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2834 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2839 DRM_ERROR("FDI train 2 fail!\n");
2841 DRM_DEBUG_KMS("FDI train done.\n");
2844 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2846 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2848 int pipe
= intel_crtc
->pipe
;
2852 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2853 reg
= FDI_RX_CTL(pipe
);
2854 temp
= I915_READ(reg
);
2855 temp
&= ~((0x7 << 19) | (0x7 << 16));
2856 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2857 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2858 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2863 /* Switch from Rawclk to PCDclk */
2864 temp
= I915_READ(reg
);
2865 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2870 /* Enable CPU FDI TX PLL, always on for Ironlake */
2871 reg
= FDI_TX_CTL(pipe
);
2872 temp
= I915_READ(reg
);
2873 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2874 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2881 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2883 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2885 int pipe
= intel_crtc
->pipe
;
2888 /* Switch from PCDclk to Rawclk */
2889 reg
= FDI_RX_CTL(pipe
);
2890 temp
= I915_READ(reg
);
2891 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2893 /* Disable CPU FDI TX PLL */
2894 reg
= FDI_TX_CTL(pipe
);
2895 temp
= I915_READ(reg
);
2896 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2901 reg
= FDI_RX_CTL(pipe
);
2902 temp
= I915_READ(reg
);
2903 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2905 /* Wait for the clocks to turn off. */
2910 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2912 struct drm_device
*dev
= crtc
->dev
;
2913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2914 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2915 int pipe
= intel_crtc
->pipe
;
2918 /* disable CPU FDI tx and PCH FDI rx */
2919 reg
= FDI_TX_CTL(pipe
);
2920 temp
= I915_READ(reg
);
2921 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2924 reg
= FDI_RX_CTL(pipe
);
2925 temp
= I915_READ(reg
);
2926 temp
&= ~(0x7 << 16);
2927 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2928 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2933 /* Ironlake workaround, disable clock pointer after downing FDI */
2934 if (HAS_PCH_IBX(dev
)) {
2935 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2938 /* still set train pattern 1 */
2939 reg
= FDI_TX_CTL(pipe
);
2940 temp
= I915_READ(reg
);
2941 temp
&= ~FDI_LINK_TRAIN_NONE
;
2942 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2943 I915_WRITE(reg
, temp
);
2945 reg
= FDI_RX_CTL(pipe
);
2946 temp
= I915_READ(reg
);
2947 if (HAS_PCH_CPT(dev
)) {
2948 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2949 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2951 temp
&= ~FDI_LINK_TRAIN_NONE
;
2952 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2954 /* BPC in FDI rx is consistent with that in PIPECONF */
2955 temp
&= ~(0x07 << 16);
2956 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2957 I915_WRITE(reg
, temp
);
2963 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2965 struct drm_device
*dev
= crtc
->dev
;
2966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2968 unsigned long flags
;
2971 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2972 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2975 spin_lock_irqsave(&dev
->event_lock
, flags
);
2976 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2977 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2982 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2984 struct drm_device
*dev
= crtc
->dev
;
2985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2987 if (crtc
->fb
== NULL
)
2990 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2992 wait_event(dev_priv
->pending_flip_queue
,
2993 !intel_crtc_has_pending_flip(crtc
));
2995 mutex_lock(&dev
->struct_mutex
);
2996 intel_finish_fb(crtc
->fb
);
2997 mutex_unlock(&dev
->struct_mutex
);
3000 /* Program iCLKIP clock to the desired frequency */
3001 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3003 struct drm_device
*dev
= crtc
->dev
;
3004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3005 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3008 mutex_lock(&dev_priv
->dpio_lock
);
3010 /* It is necessary to ungate the pixclk gate prior to programming
3011 * the divisors, and gate it back when it is done.
3013 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3015 /* Disable SSCCTL */
3016 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3017 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022 if (crtc
->mode
.clock
== 20000) {
3027 /* The iCLK virtual clock root frequency is in MHz,
3028 * but the crtc->mode.clock in in KHz. To get the divisors,
3029 * it is necessary to divide one by another, so we
3030 * convert the virtual clock precision to KHz here for higher
3033 u32 iclk_virtual_root_freq
= 172800 * 1000;
3034 u32 iclk_pi_range
= 64;
3035 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3037 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3038 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3039 pi_value
= desired_divisor
% iclk_pi_range
;
3042 divsel
= msb_divisor_value
- 2;
3043 phaseinc
= pi_value
;
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3059 /* Program SSCDIVINTPHASE6 */
3060 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3061 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3062 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3063 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3064 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3065 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3066 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3067 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3069 /* Program SSCAUXDIV */
3070 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3071 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3073 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3075 /* Enable modulator and associated divider */
3076 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3077 temp
&= ~SBI_SSCCTL_DISABLE
;
3078 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3080 /* Wait for initialization time */
3083 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3085 mutex_unlock(&dev_priv
->dpio_lock
);
3089 * Enable PCH resources required for PCH ports:
3091 * - FDI training & RX/TX
3092 * - update transcoder timings
3093 * - DP transcoding bits
3096 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3098 struct drm_device
*dev
= crtc
->dev
;
3099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3101 int pipe
= intel_crtc
->pipe
;
3104 assert_transcoder_disabled(dev_priv
, pipe
);
3106 /* Write the TU size bits before fdi link training, so that error
3107 * detection works. */
3108 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3109 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3111 /* For PCH output, training FDI link */
3112 dev_priv
->display
.fdi_link_train(crtc
);
3114 /* XXX: pch pll's can be enabled any time before we enable the PCH
3115 * transcoder, and we actually should do this to not upset any PCH
3116 * transcoder that already use the clock when we share it.
3118 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3119 * unconditionally resets the pll - we need that to have the right LVDS
3120 * enable sequence. */
3121 ironlake_enable_pch_pll(intel_crtc
);
3123 if (HAS_PCH_CPT(dev
)) {
3126 temp
= I915_READ(PCH_DPLL_SEL
);
3130 temp
|= TRANSA_DPLL_ENABLE
;
3131 sel
= TRANSA_DPLLB_SEL
;
3134 temp
|= TRANSB_DPLL_ENABLE
;
3135 sel
= TRANSB_DPLLB_SEL
;
3138 temp
|= TRANSC_DPLL_ENABLE
;
3139 sel
= TRANSC_DPLLB_SEL
;
3142 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3146 I915_WRITE(PCH_DPLL_SEL
, temp
);
3149 /* set transcoder timing, panel must allow it */
3150 assert_panel_unlocked(dev_priv
, pipe
);
3151 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3152 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3153 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3155 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3156 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3157 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3158 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3160 intel_fdi_normal_train(crtc
);
3162 /* For PCH DP, enable TRANS_DP_CTL */
3163 if (HAS_PCH_CPT(dev
) &&
3164 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3165 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3166 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3167 reg
= TRANS_DP_CTL(pipe
);
3168 temp
= I915_READ(reg
);
3169 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3170 TRANS_DP_SYNC_MASK
|
3172 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3173 TRANS_DP_ENH_FRAMING
);
3174 temp
|= bpc
<< 9; /* same format but at 11:9 */
3176 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3177 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3178 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3179 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3181 switch (intel_trans_dp_port_sel(crtc
)) {
3183 temp
|= TRANS_DP_PORT_SEL_B
;
3186 temp
|= TRANS_DP_PORT_SEL_C
;
3189 temp
|= TRANS_DP_PORT_SEL_D
;
3195 I915_WRITE(reg
, temp
);
3198 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3201 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3203 struct drm_device
*dev
= crtc
->dev
;
3204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3205 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3206 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3208 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3210 lpt_program_iclkip(crtc
);
3212 /* Set transcoder timing. */
3213 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3214 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3215 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3217 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3218 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3219 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3220 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3222 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3225 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3227 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3232 if (pll
->refcount
== 0) {
3233 WARN(1, "bad PCH PLL refcount\n");
3238 intel_crtc
->pch_pll
= NULL
;
3241 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3243 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3244 struct intel_pch_pll
*pll
;
3247 pll
= intel_crtc
->pch_pll
;
3249 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3250 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3254 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3255 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256 i
= intel_crtc
->pipe
;
3257 pll
= &dev_priv
->pch_plls
[i
];
3259 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3260 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3265 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3266 pll
= &dev_priv
->pch_plls
[i
];
3268 /* Only want to check enabled timings first */
3269 if (pll
->refcount
== 0)
3272 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3273 fp
== I915_READ(pll
->fp0_reg
)) {
3274 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3275 intel_crtc
->base
.base
.id
,
3276 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3282 /* Ok no matching timings, maybe there's a free one? */
3283 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3284 pll
= &dev_priv
->pch_plls
[i
];
3285 if (pll
->refcount
== 0) {
3286 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3287 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3295 intel_crtc
->pch_pll
= pll
;
3297 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3298 prepare
: /* separate function? */
3299 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3301 /* Wait for the clocks to stabilize before rewriting the regs */
3302 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3303 POSTING_READ(pll
->pll_reg
);
3306 I915_WRITE(pll
->fp0_reg
, fp
);
3307 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3312 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3315 int dslreg
= PIPEDSL(pipe
);
3318 temp
= I915_READ(dslreg
);
3320 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3321 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3322 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3326 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3328 struct drm_device
*dev
= crtc
->dev
;
3329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3331 struct intel_encoder
*encoder
;
3332 int pipe
= intel_crtc
->pipe
;
3333 int plane
= intel_crtc
->plane
;
3336 WARN_ON(!crtc
->enabled
);
3338 if (intel_crtc
->active
)
3341 intel_crtc
->active
= true;
3342 intel_update_watermarks(dev
);
3344 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3345 temp
= I915_READ(PCH_LVDS
);
3346 if ((temp
& LVDS_PORT_EN
) == 0)
3347 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3351 if (intel_crtc
->config
.has_pch_encoder
) {
3352 /* Note: FDI PLL enabling _must_ be done before we enable the
3353 * cpu pipes, hence this is separate from all the other fdi/pch
3355 ironlake_fdi_pll_enable(intel_crtc
);
3357 assert_fdi_tx_disabled(dev_priv
, pipe
);
3358 assert_fdi_rx_disabled(dev_priv
, pipe
);
3361 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3362 if (encoder
->pre_enable
)
3363 encoder
->pre_enable(encoder
);
3365 /* Enable panel fitting for LVDS */
3366 if (dev_priv
->pch_pf_size
&&
3367 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3368 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3369 /* Force use of hard-coded filter coefficients
3370 * as some pre-programmed values are broken,
3373 if (IS_IVYBRIDGE(dev
))
3374 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3375 PF_PIPE_SEL_IVB(pipe
));
3377 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3378 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3379 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3383 * On ILK+ LUT must be loaded before the pipe is running but with
3386 intel_crtc_load_lut(crtc
);
3388 intel_enable_pipe(dev_priv
, pipe
,
3389 intel_crtc
->config
.has_pch_encoder
);
3390 intel_enable_plane(dev_priv
, plane
, pipe
);
3392 if (intel_crtc
->config
.has_pch_encoder
)
3393 ironlake_pch_enable(crtc
);
3395 mutex_lock(&dev
->struct_mutex
);
3396 intel_update_fbc(dev
);
3397 mutex_unlock(&dev
->struct_mutex
);
3399 intel_crtc_update_cursor(crtc
, true);
3401 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3402 encoder
->enable(encoder
);
3404 if (HAS_PCH_CPT(dev
))
3405 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3408 * There seems to be a race in PCH platform hw (at least on some
3409 * outputs) where an enabled pipe still completes any pageflip right
3410 * away (as if the pipe is off) instead of waiting for vblank. As soon
3411 * as the first vblank happend, everything works as expected. Hence just
3412 * wait for one vblank before returning to avoid strange things
3415 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3418 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3420 struct drm_device
*dev
= crtc
->dev
;
3421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3423 struct intel_encoder
*encoder
;
3424 int pipe
= intel_crtc
->pipe
;
3425 int plane
= intel_crtc
->plane
;
3427 WARN_ON(!crtc
->enabled
);
3429 if (intel_crtc
->active
)
3432 intel_crtc
->active
= true;
3433 intel_update_watermarks(dev
);
3435 if (intel_crtc
->config
.has_pch_encoder
)
3436 dev_priv
->display
.fdi_link_train(crtc
);
3438 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3439 if (encoder
->pre_enable
)
3440 encoder
->pre_enable(encoder
);
3442 intel_ddi_enable_pipe_clock(intel_crtc
);
3444 /* Enable panel fitting for eDP */
3445 if (dev_priv
->pch_pf_size
&&
3446 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3447 /* Force use of hard-coded filter coefficients
3448 * as some pre-programmed values are broken,
3451 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3452 PF_PIPE_SEL_IVB(pipe
));
3453 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3454 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3458 * On ILK+ LUT must be loaded before the pipe is running but with
3461 intel_crtc_load_lut(crtc
);
3463 intel_ddi_set_pipe_settings(crtc
);
3464 intel_ddi_enable_transcoder_func(crtc
);
3466 intel_enable_pipe(dev_priv
, pipe
,
3467 intel_crtc
->config
.has_pch_encoder
);
3468 intel_enable_plane(dev_priv
, plane
, pipe
);
3470 if (intel_crtc
->config
.has_pch_encoder
)
3471 lpt_pch_enable(crtc
);
3473 mutex_lock(&dev
->struct_mutex
);
3474 intel_update_fbc(dev
);
3475 mutex_unlock(&dev
->struct_mutex
);
3477 intel_crtc_update_cursor(crtc
, true);
3479 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3480 encoder
->enable(encoder
);
3483 * There seems to be a race in PCH platform hw (at least on some
3484 * outputs) where an enabled pipe still completes any pageflip right
3485 * away (as if the pipe is off) instead of waiting for vblank. As soon
3486 * as the first vblank happend, everything works as expected. Hence just
3487 * wait for one vblank before returning to avoid strange things
3490 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3493 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3495 struct drm_device
*dev
= crtc
->dev
;
3496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3497 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3498 struct intel_encoder
*encoder
;
3499 int pipe
= intel_crtc
->pipe
;
3500 int plane
= intel_crtc
->plane
;
3504 if (!intel_crtc
->active
)
3507 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3508 encoder
->disable(encoder
);
3510 intel_crtc_wait_for_pending_flips(crtc
);
3511 drm_vblank_off(dev
, pipe
);
3512 intel_crtc_update_cursor(crtc
, false);
3514 intel_disable_plane(dev_priv
, plane
, pipe
);
3516 if (dev_priv
->cfb_plane
== plane
)
3517 intel_disable_fbc(dev
);
3519 intel_disable_pipe(dev_priv
, pipe
);
3522 I915_WRITE(PF_CTL(pipe
), 0);
3523 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3525 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3526 if (encoder
->post_disable
)
3527 encoder
->post_disable(encoder
);
3529 ironlake_fdi_disable(crtc
);
3531 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3533 if (HAS_PCH_CPT(dev
)) {
3534 /* disable TRANS_DP_CTL */
3535 reg
= TRANS_DP_CTL(pipe
);
3536 temp
= I915_READ(reg
);
3537 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3538 temp
|= TRANS_DP_PORT_SEL_NONE
;
3539 I915_WRITE(reg
, temp
);
3541 /* disable DPLL_SEL */
3542 temp
= I915_READ(PCH_DPLL_SEL
);
3545 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3548 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3551 /* C shares PLL A or B */
3552 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3557 I915_WRITE(PCH_DPLL_SEL
, temp
);
3560 /* disable PCH DPLL */
3561 intel_disable_pch_pll(intel_crtc
);
3563 ironlake_fdi_pll_disable(intel_crtc
);
3565 intel_crtc
->active
= false;
3566 intel_update_watermarks(dev
);
3568 mutex_lock(&dev
->struct_mutex
);
3569 intel_update_fbc(dev
);
3570 mutex_unlock(&dev
->struct_mutex
);
3573 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3575 struct drm_device
*dev
= crtc
->dev
;
3576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3577 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3578 struct intel_encoder
*encoder
;
3579 int pipe
= intel_crtc
->pipe
;
3580 int plane
= intel_crtc
->plane
;
3581 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3583 if (!intel_crtc
->active
)
3586 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3587 encoder
->disable(encoder
);
3589 intel_crtc_wait_for_pending_flips(crtc
);
3590 drm_vblank_off(dev
, pipe
);
3591 intel_crtc_update_cursor(crtc
, false);
3593 intel_disable_plane(dev_priv
, plane
, pipe
);
3595 if (dev_priv
->cfb_plane
== plane
)
3596 intel_disable_fbc(dev
);
3598 intel_disable_pipe(dev_priv
, pipe
);
3600 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3602 /* XXX: Once we have proper panel fitter state tracking implemented with
3603 * hardware state read/check support we should switch to only disable
3604 * the panel fitter when we know it's used. */
3605 if (intel_using_power_well(dev
)) {
3606 I915_WRITE(PF_CTL(pipe
), 0);
3607 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3610 intel_ddi_disable_pipe_clock(intel_crtc
);
3612 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3613 if (encoder
->post_disable
)
3614 encoder
->post_disable(encoder
);
3616 if (intel_crtc
->config
.has_pch_encoder
) {
3617 lpt_disable_pch_transcoder(dev_priv
);
3618 intel_ddi_fdi_disable(crtc
);
3621 intel_crtc
->active
= false;
3622 intel_update_watermarks(dev
);
3624 mutex_lock(&dev
->struct_mutex
);
3625 intel_update_fbc(dev
);
3626 mutex_unlock(&dev
->struct_mutex
);
3629 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3631 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3632 intel_put_pch_pll(intel_crtc
);
3635 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3637 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3639 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3640 * start using it. */
3641 intel_crtc
->config
.cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3643 intel_ddi_put_crtc_pll(crtc
);
3646 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3648 if (!enable
&& intel_crtc
->overlay
) {
3649 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3652 mutex_lock(&dev
->struct_mutex
);
3653 dev_priv
->mm
.interruptible
= false;
3654 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3655 dev_priv
->mm
.interruptible
= true;
3656 mutex_unlock(&dev
->struct_mutex
);
3659 /* Let userspace switch the overlay on again. In most cases userspace
3660 * has to recompute where to put it anyway.
3665 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3666 * cursor plane briefly if not already running after enabling the display
3668 * This workaround avoids occasional blank screens when self refresh is
3672 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3674 u32 cntl
= I915_READ(CURCNTR(pipe
));
3676 if ((cntl
& CURSOR_MODE
) == 0) {
3677 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3679 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3680 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3681 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3682 I915_WRITE(CURCNTR(pipe
), cntl
);
3683 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3684 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3688 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3690 struct drm_device
*dev
= crtc
->dev
;
3691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3692 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3693 struct intel_encoder
*encoder
;
3694 int pipe
= intel_crtc
->pipe
;
3695 int plane
= intel_crtc
->plane
;
3697 WARN_ON(!crtc
->enabled
);
3699 if (intel_crtc
->active
)
3702 intel_crtc
->active
= true;
3703 intel_update_watermarks(dev
);
3705 intel_enable_pll(dev_priv
, pipe
);
3707 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3708 if (encoder
->pre_enable
)
3709 encoder
->pre_enable(encoder
);
3711 intel_enable_pipe(dev_priv
, pipe
, false);
3712 intel_enable_plane(dev_priv
, plane
, pipe
);
3714 g4x_fixup_plane(dev_priv
, pipe
);
3716 intel_crtc_load_lut(crtc
);
3717 intel_update_fbc(dev
);
3719 /* Give the overlay scaler a chance to enable if it's on this pipe */
3720 intel_crtc_dpms_overlay(intel_crtc
, true);
3721 intel_crtc_update_cursor(crtc
, true);
3723 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3724 encoder
->enable(encoder
);
3727 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3729 struct drm_device
*dev
= crtc
->base
.dev
;
3730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3732 uint32_t pctl
= I915_READ(PFIT_CONTROL
);
3734 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3736 if (INTEL_INFO(dev
)->gen
>= 4)
3737 pipe
= (pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
;
3741 if (pipe
== crtc
->pipe
) {
3742 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl
);
3743 I915_WRITE(PFIT_CONTROL
, 0);
3747 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3749 struct drm_device
*dev
= crtc
->dev
;
3750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3752 struct intel_encoder
*encoder
;
3753 int pipe
= intel_crtc
->pipe
;
3754 int plane
= intel_crtc
->plane
;
3756 if (!intel_crtc
->active
)
3759 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3760 encoder
->disable(encoder
);
3762 /* Give the overlay scaler a chance to disable if it's on this pipe */
3763 intel_crtc_wait_for_pending_flips(crtc
);
3764 drm_vblank_off(dev
, pipe
);
3765 intel_crtc_dpms_overlay(intel_crtc
, false);
3766 intel_crtc_update_cursor(crtc
, false);
3768 if (dev_priv
->cfb_plane
== plane
)
3769 intel_disable_fbc(dev
);
3771 intel_disable_plane(dev_priv
, plane
, pipe
);
3772 intel_disable_pipe(dev_priv
, pipe
);
3774 i9xx_pfit_disable(intel_crtc
);
3776 intel_disable_pll(dev_priv
, pipe
);
3778 intel_crtc
->active
= false;
3779 intel_update_fbc(dev
);
3780 intel_update_watermarks(dev
);
3783 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3787 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3790 struct drm_device
*dev
= crtc
->dev
;
3791 struct drm_i915_master_private
*master_priv
;
3792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3793 int pipe
= intel_crtc
->pipe
;
3795 if (!dev
->primary
->master
)
3798 master_priv
= dev
->primary
->master
->driver_priv
;
3799 if (!master_priv
->sarea_priv
)
3804 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3805 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3808 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3809 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3812 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3818 * Sets the power management mode of the pipe and plane.
3820 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3822 struct drm_device
*dev
= crtc
->dev
;
3823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 struct intel_encoder
*intel_encoder
;
3825 bool enable
= false;
3827 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3828 enable
|= intel_encoder
->connectors_active
;
3831 dev_priv
->display
.crtc_enable(crtc
);
3833 dev_priv
->display
.crtc_disable(crtc
);
3835 intel_crtc_update_sarea(crtc
, enable
);
3838 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3840 struct drm_device
*dev
= crtc
->dev
;
3841 struct drm_connector
*connector
;
3842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3843 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3845 /* crtc should still be enabled when we disable it. */
3846 WARN_ON(!crtc
->enabled
);
3848 intel_crtc
->eld_vld
= false;
3849 dev_priv
->display
.crtc_disable(crtc
);
3850 intel_crtc_update_sarea(crtc
, false);
3851 dev_priv
->display
.off(crtc
);
3853 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3854 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3857 mutex_lock(&dev
->struct_mutex
);
3858 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3859 mutex_unlock(&dev
->struct_mutex
);
3863 /* Update computed state. */
3864 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3865 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3868 if (connector
->encoder
->crtc
!= crtc
)
3871 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3872 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3876 void intel_modeset_disable(struct drm_device
*dev
)
3878 struct drm_crtc
*crtc
;
3880 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3882 intel_crtc_disable(crtc
);
3886 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3888 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3890 drm_encoder_cleanup(encoder
);
3891 kfree(intel_encoder
);
3894 /* Simple dpms helper for encodres with just one connector, no cloning and only
3895 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3896 * state of the entire output pipe. */
3897 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3899 if (mode
== DRM_MODE_DPMS_ON
) {
3900 encoder
->connectors_active
= true;
3902 intel_crtc_update_dpms(encoder
->base
.crtc
);
3904 encoder
->connectors_active
= false;
3906 intel_crtc_update_dpms(encoder
->base
.crtc
);
3910 /* Cross check the actual hw state with our own modeset state tracking (and it's
3911 * internal consistency). */
3912 static void intel_connector_check_state(struct intel_connector
*connector
)
3914 if (connector
->get_hw_state(connector
)) {
3915 struct intel_encoder
*encoder
= connector
->encoder
;
3916 struct drm_crtc
*crtc
;
3917 bool encoder_enabled
;
3920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3921 connector
->base
.base
.id
,
3922 drm_get_connector_name(&connector
->base
));
3924 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3925 "wrong connector dpms state\n");
3926 WARN(connector
->base
.encoder
!= &encoder
->base
,
3927 "active connector not linked to encoder\n");
3928 WARN(!encoder
->connectors_active
,
3929 "encoder->connectors_active not set\n");
3931 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3932 WARN(!encoder_enabled
, "encoder not enabled\n");
3933 if (WARN_ON(!encoder
->base
.crtc
))
3936 crtc
= encoder
->base
.crtc
;
3938 WARN(!crtc
->enabled
, "crtc not enabled\n");
3939 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3940 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3941 "encoder active on the wrong pipe\n");
3945 /* Even simpler default implementation, if there's really no special case to
3947 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3949 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3951 /* All the simple cases only support two dpms states. */
3952 if (mode
!= DRM_MODE_DPMS_ON
)
3953 mode
= DRM_MODE_DPMS_OFF
;
3955 if (mode
== connector
->dpms
)
3958 connector
->dpms
= mode
;
3960 /* Only need to change hw state when actually enabled */
3961 if (encoder
->base
.crtc
)
3962 intel_encoder_dpms(encoder
, mode
);
3964 WARN_ON(encoder
->connectors_active
!= false);
3966 intel_modeset_check_state(connector
->dev
);
3969 /* Simple connector->get_hw_state implementation for encoders that support only
3970 * one connector and no cloning and hence the encoder state determines the state
3971 * of the connector. */
3972 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3975 struct intel_encoder
*encoder
= connector
->encoder
;
3977 return encoder
->get_hw_state(encoder
, &pipe
);
3980 static bool intel_crtc_compute_config(struct drm_crtc
*crtc
,
3981 struct intel_crtc_config
*pipe_config
)
3983 struct drm_device
*dev
= crtc
->dev
;
3984 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
3986 if (HAS_PCH_SPLIT(dev
)) {
3987 /* FDI link clock is fixed at 2.7G */
3988 if (pipe_config
->requested_mode
.clock
* 3
3989 > IRONLAKE_FDI_FREQ
* 4)
3993 /* All interlaced capable intel hw wants timings in frames. Note though
3994 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3995 * timings, so we need to be careful not to clobber these.*/
3996 if (!pipe_config
->timings_set
)
3997 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3999 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4000 * with a hsync front porch of 0.
4002 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4003 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4006 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4007 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4008 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4009 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4011 pipe_config
->pipe_bpp
= 8*3;
4017 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4019 return 400000; /* FIXME */
4022 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4027 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4032 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4037 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4041 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4043 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4046 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4047 case GC_DISPLAY_CLOCK_333_MHZ
:
4050 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4056 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4061 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4064 /* Assume that the hardware is in the high speed state. This
4065 * should be the default.
4067 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4068 case GC_CLOCK_133_200
:
4069 case GC_CLOCK_100_200
:
4071 case GC_CLOCK_166_250
:
4073 case GC_CLOCK_100_133
:
4077 /* Shouldn't happen */
4081 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4087 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4089 while (*num
> DATA_LINK_M_N_MASK
||
4090 *den
> DATA_LINK_M_N_MASK
) {
4096 static void compute_m_n(unsigned int m
, unsigned int n
,
4097 uint32_t *ret_m
, uint32_t *ret_n
)
4099 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4100 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4101 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4105 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4106 int pixel_clock
, int link_clock
,
4107 struct intel_link_m_n
*m_n
)
4111 compute_m_n(bits_per_pixel
* pixel_clock
,
4112 link_clock
* nlanes
* 8,
4113 &m_n
->gmch_m
, &m_n
->gmch_n
);
4115 compute_m_n(pixel_clock
, link_clock
,
4116 &m_n
->link_m
, &m_n
->link_n
);
4119 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4121 if (i915_panel_use_ssc
>= 0)
4122 return i915_panel_use_ssc
!= 0;
4123 return dev_priv
->lvds_use_ssc
4124 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4127 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4129 struct drm_device
*dev
= crtc
->dev
;
4130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4131 int refclk
= 27000; /* for DP & HDMI */
4133 return 100000; /* only one validated so far */
4135 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4137 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4138 if (intel_panel_use_ssc(dev_priv
))
4142 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4149 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4151 struct drm_device
*dev
= crtc
->dev
;
4152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4155 if (IS_VALLEYVIEW(dev
)) {
4156 refclk
= vlv_get_refclk(crtc
);
4157 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4158 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4159 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4160 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4162 } else if (!IS_GEN2(dev
)) {
4171 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc
*crtc
)
4173 unsigned dotclock
= crtc
->config
.adjusted_mode
.clock
;
4174 struct dpll
*clock
= &crtc
->config
.dpll
;
4176 /* SDVO TV has fixed PLL values depend on its clock range,
4177 this mirrors vbios setting. */
4178 if (dotclock
>= 100000 && dotclock
< 140500) {
4184 } else if (dotclock
>= 140500 && dotclock
<= 200000) {
4192 crtc
->config
.clock_set
= true;
4195 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4196 intel_clock_t
*reduced_clock
)
4198 struct drm_device
*dev
= crtc
->base
.dev
;
4199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4200 int pipe
= crtc
->pipe
;
4202 struct dpll
*clock
= &crtc
->config
.dpll
;
4204 if (IS_PINEVIEW(dev
)) {
4205 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4207 fp2
= (1 << reduced_clock
->n
) << 16 |
4208 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4210 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4212 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4216 I915_WRITE(FP0(pipe
), fp
);
4218 crtc
->lowfreq_avail
= false;
4219 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4220 reduced_clock
&& i915_powersave
) {
4221 I915_WRITE(FP1(pipe
), fp2
);
4222 crtc
->lowfreq_avail
= true;
4224 I915_WRITE(FP1(pipe
), fp
);
4228 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4230 if (crtc
->config
.has_pch_encoder
)
4231 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4233 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4236 static void vlv_update_pll(struct intel_crtc
*crtc
)
4238 struct drm_device
*dev
= crtc
->base
.dev
;
4239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4240 int pipe
= crtc
->pipe
;
4241 u32 dpll
, mdiv
, pdiv
;
4242 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4246 mutex_lock(&dev_priv
->dpio_lock
);
4248 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4249 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4251 dpll
= DPLL_VGA_MODE_DIS
;
4252 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4253 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4254 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4256 I915_WRITE(DPLL(pipe
), dpll
);
4257 POSTING_READ(DPLL(pipe
));
4259 bestn
= crtc
->config
.dpll
.n
;
4260 bestm1
= crtc
->config
.dpll
.m1
;
4261 bestm2
= crtc
->config
.dpll
.m2
;
4262 bestp1
= crtc
->config
.dpll
.p1
;
4263 bestp2
= crtc
->config
.dpll
.p2
;
4266 * In Valleyview PLL and program lane counter registers are exposed
4267 * through DPIO interface
4269 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4270 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4271 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4272 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4273 mdiv
|= (1 << DPIO_K_SHIFT
);
4274 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4275 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4277 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4279 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4280 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4281 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4282 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4283 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4285 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4287 dpll
|= DPLL_VCO_ENABLE
;
4288 I915_WRITE(DPLL(pipe
), dpll
);
4289 POSTING_READ(DPLL(pipe
));
4290 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4291 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4293 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4295 if (crtc
->config
.has_dp_encoder
)
4296 intel_dp_set_m_n(crtc
);
4298 I915_WRITE(DPLL(pipe
), dpll
);
4300 /* Wait for the clocks to stabilize. */
4301 POSTING_READ(DPLL(pipe
));
4307 if (crtc
->config
.pixel_multiplier
> 1) {
4308 temp
= (crtc
->config
.pixel_multiplier
- 1)
4309 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4312 I915_WRITE(DPLL_MD(pipe
), temp
);
4313 POSTING_READ(DPLL_MD(pipe
));
4315 /* Now program lane control registers */
4316 if(intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)
4317 || intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
4321 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4324 if(intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
)) {
4328 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4331 mutex_unlock(&dev_priv
->dpio_lock
);
4334 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4335 intel_clock_t
*reduced_clock
,
4338 struct drm_device
*dev
= crtc
->base
.dev
;
4339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4340 struct intel_encoder
*encoder
;
4341 int pipe
= crtc
->pipe
;
4344 struct dpll
*clock
= &crtc
->config
.dpll
;
4346 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4348 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4349 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4351 dpll
= DPLL_VGA_MODE_DIS
;
4353 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4354 dpll
|= DPLLB_MODE_LVDS
;
4356 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4359 if ((crtc
->config
.pixel_multiplier
> 1) &&
4360 (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))) {
4361 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4362 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4364 dpll
|= DPLL_DVO_HIGH_SPEED
;
4366 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4367 dpll
|= DPLL_DVO_HIGH_SPEED
;
4369 /* compute bitmask from p1 value */
4370 if (IS_PINEVIEW(dev
))
4371 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4373 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4374 if (IS_G4X(dev
) && reduced_clock
)
4375 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4377 switch (clock
->p2
) {
4379 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4382 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4385 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4388 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4391 if (INTEL_INFO(dev
)->gen
>= 4)
4392 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4394 if (is_sdvo
&& intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4395 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4396 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_TVOUT
))
4397 /* XXX: just matching BIOS for now */
4398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4400 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4401 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4402 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4404 dpll
|= PLL_REF_INPUT_DREFCLK
;
4406 dpll
|= DPLL_VCO_ENABLE
;
4407 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4408 POSTING_READ(DPLL(pipe
));
4411 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4412 if (encoder
->pre_pll_enable
)
4413 encoder
->pre_pll_enable(encoder
);
4415 if (crtc
->config
.has_dp_encoder
)
4416 intel_dp_set_m_n(crtc
);
4418 I915_WRITE(DPLL(pipe
), dpll
);
4420 /* Wait for the clocks to stabilize. */
4421 POSTING_READ(DPLL(pipe
));
4424 if (INTEL_INFO(dev
)->gen
>= 4) {
4428 if (crtc
->config
.pixel_multiplier
> 1) {
4429 temp
= (crtc
->config
.pixel_multiplier
- 1)
4430 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4433 I915_WRITE(DPLL_MD(pipe
), temp
);
4435 /* The pixel multiplier can only be updated once the
4436 * DPLL is enabled and the clocks are stable.
4438 * So write it again.
4440 I915_WRITE(DPLL(pipe
), dpll
);
4444 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4445 struct drm_display_mode
*adjusted_mode
,
4446 intel_clock_t
*reduced_clock
,
4449 struct drm_device
*dev
= crtc
->base
.dev
;
4450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4451 struct intel_encoder
*encoder
;
4452 int pipe
= crtc
->pipe
;
4454 struct dpll
*clock
= &crtc
->config
.dpll
;
4456 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4458 dpll
= DPLL_VGA_MODE_DIS
;
4460 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4461 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4464 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4466 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4468 dpll
|= PLL_P2_DIVIDE_BY_4
;
4471 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4472 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4473 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4475 dpll
|= PLL_REF_INPUT_DREFCLK
;
4477 dpll
|= DPLL_VCO_ENABLE
;
4478 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4479 POSTING_READ(DPLL(pipe
));
4482 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4483 if (encoder
->pre_pll_enable
)
4484 encoder
->pre_pll_enable(encoder
);
4486 I915_WRITE(DPLL(pipe
), dpll
);
4488 /* Wait for the clocks to stabilize. */
4489 POSTING_READ(DPLL(pipe
));
4492 /* The pixel multiplier can only be updated once the
4493 * DPLL is enabled and the clocks are stable.
4495 * So write it again.
4497 I915_WRITE(DPLL(pipe
), dpll
);
4500 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4501 struct drm_display_mode
*mode
,
4502 struct drm_display_mode
*adjusted_mode
)
4504 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4506 enum pipe pipe
= intel_crtc
->pipe
;
4507 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4508 uint32_t vsyncshift
;
4510 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4511 /* the chip adds 2 halflines automatically */
4512 adjusted_mode
->crtc_vtotal
-= 1;
4513 adjusted_mode
->crtc_vblank_end
-= 1;
4514 vsyncshift
= adjusted_mode
->crtc_hsync_start
4515 - adjusted_mode
->crtc_htotal
/ 2;
4520 if (INTEL_INFO(dev
)->gen
> 3)
4521 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4523 I915_WRITE(HTOTAL(cpu_transcoder
),
4524 (adjusted_mode
->crtc_hdisplay
- 1) |
4525 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4526 I915_WRITE(HBLANK(cpu_transcoder
),
4527 (adjusted_mode
->crtc_hblank_start
- 1) |
4528 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4529 I915_WRITE(HSYNC(cpu_transcoder
),
4530 (adjusted_mode
->crtc_hsync_start
- 1) |
4531 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4533 I915_WRITE(VTOTAL(cpu_transcoder
),
4534 (adjusted_mode
->crtc_vdisplay
- 1) |
4535 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4536 I915_WRITE(VBLANK(cpu_transcoder
),
4537 (adjusted_mode
->crtc_vblank_start
- 1) |
4538 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4539 I915_WRITE(VSYNC(cpu_transcoder
),
4540 (adjusted_mode
->crtc_vsync_start
- 1) |
4541 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4543 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4544 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4545 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4547 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4548 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4549 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4551 /* pipesrc controls the size that is scaled from, which should
4552 * always be the user's requested size.
4554 I915_WRITE(PIPESRC(pipe
),
4555 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4558 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4560 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 pipeconf
= I915_READ(PIPECONF(intel_crtc
->pipe
));
4566 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4567 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4570 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4573 if (intel_crtc
->config
.requested_mode
.clock
>
4574 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4575 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4577 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4580 /* default to 8bpc */
4581 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4582 if (intel_crtc
->config
.has_dp_encoder
) {
4583 if (intel_crtc
->config
.dither
) {
4584 pipeconf
|= PIPECONF_6BPC
|
4585 PIPECONF_DITHER_EN
|
4586 PIPECONF_DITHER_TYPE_SP
;
4590 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(&intel_crtc
->base
,
4591 INTEL_OUTPUT_EDP
)) {
4592 if (intel_crtc
->config
.dither
) {
4593 pipeconf
|= PIPECONF_6BPC
|
4595 I965_PIPECONF_ACTIVE
;
4599 if (HAS_PIPE_CXSR(dev
)) {
4600 if (intel_crtc
->lowfreq_avail
) {
4601 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4602 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4604 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4605 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4609 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4610 if (!IS_GEN2(dev
) &&
4611 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4612 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4614 pipeconf
|= PIPECONF_PROGRESSIVE
;
4616 if (IS_VALLEYVIEW(dev
)) {
4617 if (intel_crtc
->config
.limited_color_range
)
4618 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4620 pipeconf
&= ~PIPECONF_COLOR_RANGE_SELECT
;
4623 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4624 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4627 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4629 struct drm_framebuffer
*fb
)
4631 struct drm_device
*dev
= crtc
->dev
;
4632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4633 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4634 struct drm_display_mode
*adjusted_mode
=
4635 &intel_crtc
->config
.adjusted_mode
;
4636 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4637 int pipe
= intel_crtc
->pipe
;
4638 int plane
= intel_crtc
->plane
;
4639 int refclk
, num_connectors
= 0;
4640 intel_clock_t clock
, reduced_clock
;
4642 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4643 bool is_lvds
= false, is_tv
= false;
4644 struct intel_encoder
*encoder
;
4645 const intel_limit_t
*limit
;
4648 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4649 switch (encoder
->type
) {
4650 case INTEL_OUTPUT_LVDS
:
4653 case INTEL_OUTPUT_SDVO
:
4654 case INTEL_OUTPUT_HDMI
:
4656 if (encoder
->needs_tv_clock
)
4659 case INTEL_OUTPUT_TVOUT
:
4667 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4670 * Returns a set of divisors for the desired target clock with the given
4671 * refclk, or FALSE. The returned values represent the clock equation:
4672 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4674 limit
= intel_limit(crtc
, refclk
);
4675 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4678 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4682 /* Ensure that the cursor is valid for the new mode before changing... */
4683 intel_crtc_update_cursor(crtc
, true);
4685 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4687 * Ensure we match the reduced clock's P to the target clock.
4688 * If the clocks don't match, we can't switch the display clock
4689 * by using the FP0/FP1. In such case we will disable the LVDS
4690 * downclock feature.
4692 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4693 dev_priv
->lvds_downclock
,
4698 /* Compat-code for transition, will disappear. */
4699 if (!intel_crtc
->config
.clock_set
) {
4700 intel_crtc
->config
.dpll
.n
= clock
.n
;
4701 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4702 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4703 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4704 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4707 if (is_sdvo
&& is_tv
)
4708 i9xx_adjust_sdvo_tv_clock(intel_crtc
);
4711 i8xx_update_pll(intel_crtc
, adjusted_mode
,
4712 has_reduced_clock
? &reduced_clock
: NULL
,
4714 else if (IS_VALLEYVIEW(dev
))
4715 vlv_update_pll(intel_crtc
);
4717 i9xx_update_pll(intel_crtc
,
4718 has_reduced_clock
? &reduced_clock
: NULL
,
4721 /* Set up the display plane register */
4722 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4724 if (!IS_VALLEYVIEW(dev
)) {
4726 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4728 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4731 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4732 drm_mode_debug_printmodeline(mode
);
4734 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4736 /* pipesrc and dspsize control the size that is scaled from,
4737 * which should always be the user's requested size.
4739 I915_WRITE(DSPSIZE(plane
),
4740 ((mode
->vdisplay
- 1) << 16) |
4741 (mode
->hdisplay
- 1));
4742 I915_WRITE(DSPPOS(plane
), 0);
4744 i9xx_set_pipeconf(intel_crtc
);
4746 intel_enable_pipe(dev_priv
, pipe
, false);
4748 intel_wait_for_vblank(dev
, pipe
);
4750 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4751 POSTING_READ(DSPCNTR(plane
));
4753 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4755 intel_update_watermarks(dev
);
4760 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4761 struct intel_crtc_config
*pipe_config
)
4763 struct drm_device
*dev
= crtc
->base
.dev
;
4764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4767 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4768 if (!(tmp
& PIPECONF_ENABLE
))
4774 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4777 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4778 struct intel_encoder
*encoder
;
4780 bool has_lvds
= false;
4781 bool has_cpu_edp
= false;
4782 bool has_pch_edp
= false;
4783 bool has_panel
= false;
4784 bool has_ck505
= false;
4785 bool can_ssc
= false;
4787 /* We need to take the global config into account */
4788 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4790 switch (encoder
->type
) {
4791 case INTEL_OUTPUT_LVDS
:
4795 case INTEL_OUTPUT_EDP
:
4797 if (intel_encoder_is_pch_edp(&encoder
->base
))
4805 if (HAS_PCH_IBX(dev
)) {
4806 has_ck505
= dev_priv
->display_clock_mode
;
4807 can_ssc
= has_ck505
;
4813 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4814 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4817 /* Ironlake: try to setup display ref clock before DPLL
4818 * enabling. This is only under driver's control after
4819 * PCH B stepping, previous chipset stepping should be
4820 * ignoring this setting.
4822 val
= I915_READ(PCH_DREF_CONTROL
);
4824 /* As we must carefully and slowly disable/enable each source in turn,
4825 * compute the final state we want first and check if we need to
4826 * make any changes at all.
4829 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4831 final
|= DREF_NONSPREAD_CK505_ENABLE
;
4833 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4835 final
&= ~DREF_SSC_SOURCE_MASK
;
4836 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4837 final
&= ~DREF_SSC1_ENABLE
;
4840 final
|= DREF_SSC_SOURCE_ENABLE
;
4842 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4843 final
|= DREF_SSC1_ENABLE
;
4846 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
4847 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4849 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4851 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4853 final
|= DREF_SSC_SOURCE_DISABLE
;
4854 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4860 /* Always enable nonspread source */
4861 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4864 val
|= DREF_NONSPREAD_CK505_ENABLE
;
4866 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4869 val
&= ~DREF_SSC_SOURCE_MASK
;
4870 val
|= DREF_SSC_SOURCE_ENABLE
;
4872 /* SSC must be turned on before enabling the CPU output */
4873 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4874 DRM_DEBUG_KMS("Using SSC on panel\n");
4875 val
|= DREF_SSC1_ENABLE
;
4877 val
&= ~DREF_SSC1_ENABLE
;
4879 /* Get SSC going before enabling the outputs */
4880 I915_WRITE(PCH_DREF_CONTROL
, val
);
4881 POSTING_READ(PCH_DREF_CONTROL
);
4884 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4886 /* Enable CPU source on CPU attached eDP */
4888 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4889 DRM_DEBUG_KMS("Using SSC on eDP\n");
4890 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4893 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4895 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4897 I915_WRITE(PCH_DREF_CONTROL
, val
);
4898 POSTING_READ(PCH_DREF_CONTROL
);
4901 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4903 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4905 /* Turn off CPU output */
4906 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4908 I915_WRITE(PCH_DREF_CONTROL
, val
);
4909 POSTING_READ(PCH_DREF_CONTROL
);
4912 /* Turn off the SSC source */
4913 val
&= ~DREF_SSC_SOURCE_MASK
;
4914 val
|= DREF_SSC_SOURCE_DISABLE
;
4917 val
&= ~DREF_SSC1_ENABLE
;
4919 I915_WRITE(PCH_DREF_CONTROL
, val
);
4920 POSTING_READ(PCH_DREF_CONTROL
);
4924 BUG_ON(val
!= final
);
4927 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4928 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4931 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4932 struct intel_encoder
*encoder
;
4933 bool has_vga
= false;
4934 bool is_sdv
= false;
4937 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4938 switch (encoder
->type
) {
4939 case INTEL_OUTPUT_ANALOG
:
4948 mutex_lock(&dev_priv
->dpio_lock
);
4950 /* XXX: Rip out SDV support once Haswell ships for real. */
4951 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4954 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4955 tmp
&= ~SBI_SSCCTL_DISABLE
;
4956 tmp
|= SBI_SSCCTL_PATHALT
;
4957 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4961 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4962 tmp
&= ~SBI_SSCCTL_PATHALT
;
4963 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4966 tmp
= I915_READ(SOUTH_CHICKEN2
);
4967 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4968 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4970 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4971 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4972 DRM_ERROR("FDI mPHY reset assert timeout\n");
4974 tmp
= I915_READ(SOUTH_CHICKEN2
);
4975 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4976 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4978 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4979 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4981 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4984 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
4985 tmp
&= ~(0xFF << 24);
4986 tmp
|= (0x12 << 24);
4987 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
4990 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
4992 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
4995 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
4997 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
4999 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5001 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5004 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5005 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5006 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5008 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5009 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5010 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5012 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5014 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5016 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5018 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5021 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5022 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5023 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5025 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5026 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5027 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5030 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5033 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5035 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5038 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5041 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5044 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5046 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5049 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5051 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5052 tmp
&= ~(0xFF << 16);
5053 tmp
|= (0x1C << 16);
5054 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5056 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5057 tmp
&= ~(0xFF << 16);
5058 tmp
|= (0x1C << 16);
5059 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5062 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5064 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5066 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5068 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5070 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5071 tmp
&= ~(0xF << 28);
5073 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5075 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5076 tmp
&= ~(0xF << 28);
5078 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5081 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5082 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5083 tmp
|= SBI_DBUFF0_ENABLE
;
5084 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5086 mutex_unlock(&dev_priv
->dpio_lock
);
5090 * Initialize reference clocks when the driver loads
5092 void intel_init_pch_refclk(struct drm_device
*dev
)
5094 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5095 ironlake_init_pch_refclk(dev
);
5096 else if (HAS_PCH_LPT(dev
))
5097 lpt_init_pch_refclk(dev
);
5100 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5102 struct drm_device
*dev
= crtc
->dev
;
5103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5104 struct intel_encoder
*encoder
;
5105 struct intel_encoder
*edp_encoder
= NULL
;
5106 int num_connectors
= 0;
5107 bool is_lvds
= false;
5109 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5110 switch (encoder
->type
) {
5111 case INTEL_OUTPUT_LVDS
:
5114 case INTEL_OUTPUT_EDP
:
5115 edp_encoder
= encoder
;
5121 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5122 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5123 dev_priv
->lvds_ssc_freq
);
5124 return dev_priv
->lvds_ssc_freq
* 1000;
5130 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5131 struct drm_display_mode
*adjusted_mode
,
5134 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5136 int pipe
= intel_crtc
->pipe
;
5139 val
= I915_READ(PIPECONF(pipe
));
5141 val
&= ~PIPECONF_BPC_MASK
;
5142 switch (intel_crtc
->config
.pipe_bpp
) {
5144 val
|= PIPECONF_6BPC
;
5147 val
|= PIPECONF_8BPC
;
5150 val
|= PIPECONF_10BPC
;
5153 val
|= PIPECONF_12BPC
;
5156 /* Case prevented by intel_choose_pipe_bpp_dither. */
5160 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5162 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5164 val
&= ~PIPECONF_INTERLACE_MASK
;
5165 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5166 val
|= PIPECONF_INTERLACED_ILK
;
5168 val
|= PIPECONF_PROGRESSIVE
;
5170 if (intel_crtc
->config
.limited_color_range
)
5171 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5173 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5175 I915_WRITE(PIPECONF(pipe
), val
);
5176 POSTING_READ(PIPECONF(pipe
));
5180 * Set up the pipe CSC unit.
5182 * Currently only full range RGB to limited range RGB conversion
5183 * is supported, but eventually this should handle various
5184 * RGB<->YCbCr scenarios as well.
5186 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5188 struct drm_device
*dev
= crtc
->dev
;
5189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5190 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5191 int pipe
= intel_crtc
->pipe
;
5192 uint16_t coeff
= 0x7800; /* 1.0 */
5195 * TODO: Check what kind of values actually come out of the pipe
5196 * with these coeff/postoff values and adjust to get the best
5197 * accuracy. Perhaps we even need to take the bpc value into
5201 if (intel_crtc
->config
.limited_color_range
)
5202 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5205 * GY/GU and RY/RU should be the other way around according
5206 * to BSpec, but reality doesn't agree. Just set them up in
5207 * a way that results in the correct picture.
5209 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5210 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5212 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5213 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5215 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5216 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5218 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5219 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5220 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5222 if (INTEL_INFO(dev
)->gen
> 6) {
5223 uint16_t postoff
= 0;
5225 if (intel_crtc
->config
.limited_color_range
)
5226 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5228 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5229 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5230 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5232 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5234 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5236 if (intel_crtc
->config
.limited_color_range
)
5237 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5239 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5243 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5244 struct drm_display_mode
*adjusted_mode
,
5247 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5249 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5252 val
= I915_READ(PIPECONF(cpu_transcoder
));
5254 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5256 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5258 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5259 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5260 val
|= PIPECONF_INTERLACED_ILK
;
5262 val
|= PIPECONF_PROGRESSIVE
;
5264 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5265 POSTING_READ(PIPECONF(cpu_transcoder
));
5268 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5269 struct drm_display_mode
*adjusted_mode
,
5270 intel_clock_t
*clock
,
5271 bool *has_reduced_clock
,
5272 intel_clock_t
*reduced_clock
)
5274 struct drm_device
*dev
= crtc
->dev
;
5275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5276 struct intel_encoder
*intel_encoder
;
5278 const intel_limit_t
*limit
;
5279 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5281 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5282 switch (intel_encoder
->type
) {
5283 case INTEL_OUTPUT_LVDS
:
5286 case INTEL_OUTPUT_SDVO
:
5287 case INTEL_OUTPUT_HDMI
:
5289 if (intel_encoder
->needs_tv_clock
)
5292 case INTEL_OUTPUT_TVOUT
:
5298 refclk
= ironlake_get_refclk(crtc
);
5301 * Returns a set of divisors for the desired target clock with the given
5302 * refclk, or FALSE. The returned values represent the clock equation:
5303 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5305 limit
= intel_limit(crtc
, refclk
);
5306 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5311 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5313 * Ensure we match the reduced clock's P to the target clock.
5314 * If the clocks don't match, we can't switch the display clock
5315 * by using the FP0/FP1. In such case we will disable the LVDS
5316 * downclock feature.
5318 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5319 dev_priv
->lvds_downclock
,
5325 if (is_sdvo
&& is_tv
)
5326 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc
));
5331 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5336 temp
= I915_READ(SOUTH_CHICKEN1
);
5337 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5340 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5341 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5343 temp
|= FDI_BC_BIFURCATION_SELECT
;
5344 DRM_DEBUG_KMS("enabling fdi C rx\n");
5345 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5346 POSTING_READ(SOUTH_CHICKEN1
);
5349 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5351 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5353 struct intel_crtc
*pipe_B_crtc
=
5354 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5356 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5357 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5358 if (intel_crtc
->fdi_lanes
> 4) {
5359 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5360 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5361 /* Clamp lanes to avoid programming the hw with bogus values. */
5362 intel_crtc
->fdi_lanes
= 4;
5367 if (INTEL_INFO(dev
)->num_pipes
== 2)
5370 switch (intel_crtc
->pipe
) {
5374 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5375 intel_crtc
->fdi_lanes
> 2) {
5376 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5377 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5378 /* Clamp lanes to avoid programming the hw with bogus values. */
5379 intel_crtc
->fdi_lanes
= 2;
5384 if (intel_crtc
->fdi_lanes
> 2)
5385 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5387 cpt_enable_fdi_bc_bifurcation(dev
);
5391 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5392 if (intel_crtc
->fdi_lanes
> 2) {
5393 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5394 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5395 /* Clamp lanes to avoid programming the hw with bogus values. */
5396 intel_crtc
->fdi_lanes
= 2;
5401 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5405 cpt_enable_fdi_bc_bifurcation(dev
);
5413 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5416 * Account for spread spectrum to avoid
5417 * oversubscribing the link. Max center spread
5418 * is 2.5%; use 5% for safety's sake.
5420 u32 bps
= target_clock
* bpp
* 21 / 20;
5421 return bps
/ (link_bw
* 8) + 1;
5424 void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5425 struct intel_link_m_n
*m_n
)
5427 struct drm_device
*dev
= crtc
->base
.dev
;
5428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5429 int pipe
= crtc
->pipe
;
5431 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5432 I915_WRITE(TRANSDATA_N1(pipe
), m_n
->gmch_n
);
5433 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
->link_m
);
5434 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
->link_n
);
5437 void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5438 struct intel_link_m_n
*m_n
)
5440 struct drm_device
*dev
= crtc
->base
.dev
;
5441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5442 int pipe
= crtc
->pipe
;
5443 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5445 if (INTEL_INFO(dev
)->gen
>= 5) {
5446 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5447 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5448 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5449 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5451 I915_WRITE(PIPE_GMCH_DATA_M(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5452 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
->gmch_n
);
5453 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
->link_m
);
5454 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
->link_n
);
5458 static void ironlake_fdi_set_m_n(struct drm_crtc
*crtc
)
5460 struct drm_device
*dev
= crtc
->dev
;
5461 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5462 struct drm_display_mode
*adjusted_mode
=
5463 &intel_crtc
->config
.adjusted_mode
;
5464 struct intel_link_m_n m_n
= {0};
5465 int target_clock
, lane
, link_bw
;
5467 /* FDI is a binary signal running at ~2.7GHz, encoding
5468 * each output octet as 10 bits. The actual frequency
5469 * is stored as a divider into a 100MHz clock, and the
5470 * mode pixel clock is stored in units of 1KHz.
5471 * Hence the bw of each lane in terms of the mode signal
5474 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5476 if (intel_crtc
->config
.pixel_target_clock
)
5477 target_clock
= intel_crtc
->config
.pixel_target_clock
;
5479 target_clock
= adjusted_mode
->clock
;
5481 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5482 intel_crtc
->config
.pipe_bpp
);
5484 intel_crtc
->fdi_lanes
= lane
;
5486 if (intel_crtc
->config
.pixel_multiplier
> 1)
5487 link_bw
*= intel_crtc
->config
.pixel_multiplier
;
5488 intel_link_compute_m_n(intel_crtc
->config
.pipe_bpp
, lane
, target_clock
,
5491 intel_cpu_transcoder_set_m_n(intel_crtc
, &m_n
);
5494 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5495 intel_clock_t
*clock
, u32
*fp
,
5496 intel_clock_t
*reduced_clock
, u32
*fp2
)
5498 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5499 struct drm_device
*dev
= crtc
->dev
;
5500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5501 struct intel_encoder
*intel_encoder
;
5503 int factor
, num_connectors
= 0;
5504 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5506 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5507 switch (intel_encoder
->type
) {
5508 case INTEL_OUTPUT_LVDS
:
5511 case INTEL_OUTPUT_SDVO
:
5512 case INTEL_OUTPUT_HDMI
:
5514 if (intel_encoder
->needs_tv_clock
)
5517 case INTEL_OUTPUT_TVOUT
:
5525 /* Enable autotuning of the PLL clock (if permissible) */
5528 if ((intel_panel_use_ssc(dev_priv
) &&
5529 dev_priv
->lvds_ssc_freq
== 100) ||
5530 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5532 } else if (is_sdvo
&& is_tv
)
5535 if (clock
->m
< factor
* clock
->n
)
5538 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5544 dpll
|= DPLLB_MODE_LVDS
;
5546 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5548 if (intel_crtc
->config
.pixel_multiplier
> 1) {
5549 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5550 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5552 dpll
|= DPLL_DVO_HIGH_SPEED
;
5554 if (intel_crtc
->config
.has_dp_encoder
&&
5555 intel_crtc
->config
.has_pch_encoder
)
5556 dpll
|= DPLL_DVO_HIGH_SPEED
;
5558 /* compute bitmask from p1 value */
5559 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5561 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5563 switch (clock
->p2
) {
5565 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5568 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5571 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5574 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5578 if (is_sdvo
&& is_tv
)
5579 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5581 /* XXX: just matching BIOS for now */
5582 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5584 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5585 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5587 dpll
|= PLL_REF_INPUT_DREFCLK
;
5592 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5594 struct drm_framebuffer
*fb
)
5596 struct drm_device
*dev
= crtc
->dev
;
5597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5599 struct drm_display_mode
*adjusted_mode
=
5600 &intel_crtc
->config
.adjusted_mode
;
5601 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5602 int pipe
= intel_crtc
->pipe
;
5603 int plane
= intel_crtc
->plane
;
5604 int num_connectors
= 0;
5605 intel_clock_t clock
, reduced_clock
;
5606 u32 dpll
, fp
= 0, fp2
= 0;
5607 bool ok
, has_reduced_clock
= false;
5608 bool is_lvds
= false;
5609 struct intel_encoder
*encoder
;
5611 bool dither
, fdi_config_ok
;
5613 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5614 switch (encoder
->type
) {
5615 case INTEL_OUTPUT_LVDS
:
5623 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5624 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5626 intel_crtc
->config
.cpu_transcoder
= pipe
;
5628 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5629 &has_reduced_clock
, &reduced_clock
);
5631 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5634 /* Compat-code for transition, will disappear. */
5635 if (!intel_crtc
->config
.clock_set
) {
5636 intel_crtc
->config
.dpll
.n
= clock
.n
;
5637 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5638 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5639 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5640 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5643 /* Ensure that the cursor is valid for the new mode before changing... */
5644 intel_crtc_update_cursor(crtc
, true);
5646 /* determine panel color depth */
5647 dither
= intel_crtc
->config
.dither
;
5648 if (is_lvds
&& dev_priv
->lvds_dither
)
5651 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5652 if (has_reduced_clock
)
5653 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5656 dpll
= ironlake_compute_dpll(intel_crtc
, &clock
, &fp
, &reduced_clock
,
5657 has_reduced_clock
? &fp2
: NULL
);
5659 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5660 drm_mode_debug_printmodeline(mode
);
5662 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5663 if (intel_crtc
->config
.has_pch_encoder
) {
5664 struct intel_pch_pll
*pll
;
5666 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5668 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5673 intel_put_pch_pll(intel_crtc
);
5675 if (intel_crtc
->config
.has_dp_encoder
)
5676 intel_dp_set_m_n(intel_crtc
);
5678 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5679 if (encoder
->pre_pll_enable
)
5680 encoder
->pre_pll_enable(encoder
);
5682 if (intel_crtc
->pch_pll
) {
5683 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5685 /* Wait for the clocks to stabilize. */
5686 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5689 /* The pixel multiplier can only be updated once the
5690 * DPLL is enabled and the clocks are stable.
5692 * So write it again.
5694 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5697 intel_crtc
->lowfreq_avail
= false;
5698 if (intel_crtc
->pch_pll
) {
5699 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5700 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5701 intel_crtc
->lowfreq_avail
= true;
5703 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5707 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5709 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5710 * ironlake_check_fdi_lanes. */
5711 intel_crtc
->fdi_lanes
= 0;
5712 if (intel_crtc
->config
.has_pch_encoder
)
5713 ironlake_fdi_set_m_n(crtc
);
5715 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5717 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5719 intel_wait_for_vblank(dev
, pipe
);
5721 /* Set up the display plane register */
5722 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5723 POSTING_READ(DSPCNTR(plane
));
5725 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5727 intel_update_watermarks(dev
);
5729 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5731 return fdi_config_ok
? ret
: -EINVAL
;
5734 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5735 struct intel_crtc_config
*pipe_config
)
5737 struct drm_device
*dev
= crtc
->base
.dev
;
5738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5741 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5742 if (!(tmp
& PIPECONF_ENABLE
))
5745 if (I915_READ(TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
)
5746 pipe_config
->has_pch_encoder
= true;
5751 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5754 bool enable
= false;
5755 struct intel_crtc
*crtc
;
5756 struct intel_encoder
*encoder
;
5758 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5759 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5761 /* XXX: Should check for edp transcoder here, but thanks to init
5762 * sequence that's not yet available. Just in case desktop eDP
5763 * on PORT D is possible on haswell, too. */
5766 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5768 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5769 encoder
->connectors_active
)
5773 /* Even the eDP panel fitter is outside the always-on well. */
5774 if (dev_priv
->pch_pf_size
)
5777 intel_set_power_well(dev
, enable
);
5780 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5782 struct drm_framebuffer
*fb
)
5784 struct drm_device
*dev
= crtc
->dev
;
5785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5786 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5787 struct drm_display_mode
*adjusted_mode
=
5788 &intel_crtc
->config
.adjusted_mode
;
5789 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5790 int pipe
= intel_crtc
->pipe
;
5791 int plane
= intel_crtc
->plane
;
5792 int num_connectors
= 0;
5793 bool is_cpu_edp
= false;
5794 struct intel_encoder
*encoder
;
5798 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5799 switch (encoder
->type
) {
5800 case INTEL_OUTPUT_EDP
:
5801 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5810 intel_crtc
->config
.cpu_transcoder
= TRANSCODER_EDP
;
5812 intel_crtc
->config
.cpu_transcoder
= pipe
;
5814 /* We are not sure yet this won't happen. */
5815 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5816 INTEL_PCH_TYPE(dev
));
5818 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5819 num_connectors
, pipe_name(pipe
));
5821 WARN_ON(I915_READ(PIPECONF(intel_crtc
->config
.cpu_transcoder
)) &
5822 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5824 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5826 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5829 /* Ensure that the cursor is valid for the new mode before changing... */
5830 intel_crtc_update_cursor(crtc
, true);
5832 /* determine panel color depth */
5833 dither
= intel_crtc
->config
.dither
;
5835 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5836 drm_mode_debug_printmodeline(mode
);
5838 if (intel_crtc
->config
.has_dp_encoder
)
5839 intel_dp_set_m_n(intel_crtc
);
5841 intel_crtc
->lowfreq_avail
= false;
5843 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5845 if (intel_crtc
->config
.has_pch_encoder
)
5846 ironlake_fdi_set_m_n(crtc
);
5848 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5850 intel_set_pipe_csc(crtc
);
5852 /* Set up the display plane register */
5853 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5854 POSTING_READ(DSPCNTR(plane
));
5856 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5858 intel_update_watermarks(dev
);
5860 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5865 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5866 struct intel_crtc_config
*pipe_config
)
5868 struct drm_device
*dev
= crtc
->base
.dev
;
5869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5872 tmp
= I915_READ(PIPECONF(crtc
->config
.cpu_transcoder
));
5873 if (!(tmp
& PIPECONF_ENABLE
))
5877 * aswell has only FDI/PCH transcoder A. It is which is connected to
5878 * DDI E. So just check whether this pipe is wired to DDI E and whether
5879 * the PCH transcoder is on.
5881 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(crtc
->pipe
));
5882 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
5883 I915_READ(TRANSCONF(PIPE_A
)) & TRANS_ENABLE
)
5884 pipe_config
->has_pch_encoder
= true;
5890 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5892 struct drm_framebuffer
*fb
)
5894 struct drm_device
*dev
= crtc
->dev
;
5895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5896 struct drm_encoder_helper_funcs
*encoder_funcs
;
5897 struct intel_encoder
*encoder
;
5898 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5899 struct drm_display_mode
*adjusted_mode
=
5900 &intel_crtc
->config
.adjusted_mode
;
5901 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5902 int pipe
= intel_crtc
->pipe
;
5905 drm_vblank_pre_modeset(dev
, pipe
);
5907 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
5909 drm_vblank_post_modeset(dev
, pipe
);
5914 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5915 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5916 encoder
->base
.base
.id
,
5917 drm_get_encoder_name(&encoder
->base
),
5918 mode
->base
.id
, mode
->name
);
5919 if (encoder
->mode_set
) {
5920 encoder
->mode_set(encoder
);
5922 encoder_funcs
= encoder
->base
.helper_private
;
5923 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5930 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5931 int reg_eldv
, uint32_t bits_eldv
,
5932 int reg_elda
, uint32_t bits_elda
,
5935 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5936 uint8_t *eld
= connector
->eld
;
5939 i
= I915_READ(reg_eldv
);
5948 i
= I915_READ(reg_elda
);
5950 I915_WRITE(reg_elda
, i
);
5952 for (i
= 0; i
< eld
[2]; i
++)
5953 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5959 static void g4x_write_eld(struct drm_connector
*connector
,
5960 struct drm_crtc
*crtc
)
5962 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5963 uint8_t *eld
= connector
->eld
;
5968 i
= I915_READ(G4X_AUD_VID_DID
);
5970 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5971 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5973 eldv
= G4X_ELDV_DEVCTG
;
5975 if (intel_eld_uptodate(connector
,
5976 G4X_AUD_CNTL_ST
, eldv
,
5977 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5978 G4X_HDMIW_HDMIEDID
))
5981 i
= I915_READ(G4X_AUD_CNTL_ST
);
5982 i
&= ~(eldv
| G4X_ELD_ADDR
);
5983 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5984 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5989 len
= min_t(uint8_t, eld
[2], len
);
5990 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5991 for (i
= 0; i
< len
; i
++)
5992 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5994 i
= I915_READ(G4X_AUD_CNTL_ST
);
5996 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5999 static void haswell_write_eld(struct drm_connector
*connector
,
6000 struct drm_crtc
*crtc
)
6002 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6003 uint8_t *eld
= connector
->eld
;
6004 struct drm_device
*dev
= crtc
->dev
;
6005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6009 int pipe
= to_intel_crtc(crtc
)->pipe
;
6012 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6013 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6014 int aud_config
= HSW_AUD_CFG(pipe
);
6015 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6018 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6020 /* Audio output enable */
6021 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6022 tmp
= I915_READ(aud_cntrl_st2
);
6023 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6024 I915_WRITE(aud_cntrl_st2
, tmp
);
6026 /* Wait for 1 vertical blank */
6027 intel_wait_for_vblank(dev
, pipe
);
6029 /* Set ELD valid state */
6030 tmp
= I915_READ(aud_cntrl_st2
);
6031 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6032 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6033 I915_WRITE(aud_cntrl_st2
, tmp
);
6034 tmp
= I915_READ(aud_cntrl_st2
);
6035 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6037 /* Enable HDMI mode */
6038 tmp
= I915_READ(aud_config
);
6039 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6040 /* clear N_programing_enable and N_value_index */
6041 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6042 I915_WRITE(aud_config
, tmp
);
6044 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6046 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6047 intel_crtc
->eld_vld
= true;
6049 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6050 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6051 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6052 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6054 I915_WRITE(aud_config
, 0);
6056 if (intel_eld_uptodate(connector
,
6057 aud_cntrl_st2
, eldv
,
6058 aud_cntl_st
, IBX_ELD_ADDRESS
,
6062 i
= I915_READ(aud_cntrl_st2
);
6064 I915_WRITE(aud_cntrl_st2
, i
);
6069 i
= I915_READ(aud_cntl_st
);
6070 i
&= ~IBX_ELD_ADDRESS
;
6071 I915_WRITE(aud_cntl_st
, i
);
6072 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6073 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6075 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6076 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6077 for (i
= 0; i
< len
; i
++)
6078 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6080 i
= I915_READ(aud_cntrl_st2
);
6082 I915_WRITE(aud_cntrl_st2
, i
);
6086 static void ironlake_write_eld(struct drm_connector
*connector
,
6087 struct drm_crtc
*crtc
)
6089 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6090 uint8_t *eld
= connector
->eld
;
6098 int pipe
= to_intel_crtc(crtc
)->pipe
;
6100 if (HAS_PCH_IBX(connector
->dev
)) {
6101 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6102 aud_config
= IBX_AUD_CFG(pipe
);
6103 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6104 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6106 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6107 aud_config
= CPT_AUD_CFG(pipe
);
6108 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6109 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6112 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6114 i
= I915_READ(aud_cntl_st
);
6115 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6117 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6118 /* operate blindly on all ports */
6119 eldv
= IBX_ELD_VALIDB
;
6120 eldv
|= IBX_ELD_VALIDB
<< 4;
6121 eldv
|= IBX_ELD_VALIDB
<< 8;
6123 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6124 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6127 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6128 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6129 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6130 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6132 I915_WRITE(aud_config
, 0);
6134 if (intel_eld_uptodate(connector
,
6135 aud_cntrl_st2
, eldv
,
6136 aud_cntl_st
, IBX_ELD_ADDRESS
,
6140 i
= I915_READ(aud_cntrl_st2
);
6142 I915_WRITE(aud_cntrl_st2
, i
);
6147 i
= I915_READ(aud_cntl_st
);
6148 i
&= ~IBX_ELD_ADDRESS
;
6149 I915_WRITE(aud_cntl_st
, i
);
6151 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6152 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6153 for (i
= 0; i
< len
; i
++)
6154 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6156 i
= I915_READ(aud_cntrl_st2
);
6158 I915_WRITE(aud_cntrl_st2
, i
);
6161 void intel_write_eld(struct drm_encoder
*encoder
,
6162 struct drm_display_mode
*mode
)
6164 struct drm_crtc
*crtc
= encoder
->crtc
;
6165 struct drm_connector
*connector
;
6166 struct drm_device
*dev
= encoder
->dev
;
6167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6169 connector
= drm_select_eld(encoder
, mode
);
6173 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6175 drm_get_connector_name(connector
),
6176 connector
->encoder
->base
.id
,
6177 drm_get_encoder_name(connector
->encoder
));
6179 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6181 if (dev_priv
->display
.write_eld
)
6182 dev_priv
->display
.write_eld(connector
, crtc
);
6185 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6186 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6188 struct drm_device
*dev
= crtc
->dev
;
6189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6190 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6191 int palreg
= PALETTE(intel_crtc
->pipe
);
6194 /* The clocks have to be on to load the palette. */
6195 if (!crtc
->enabled
|| !intel_crtc
->active
)
6198 /* use legacy palette for Ironlake */
6199 if (HAS_PCH_SPLIT(dev
))
6200 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6202 for (i
= 0; i
< 256; i
++) {
6203 I915_WRITE(palreg
+ 4 * i
,
6204 (intel_crtc
->lut_r
[i
] << 16) |
6205 (intel_crtc
->lut_g
[i
] << 8) |
6206 intel_crtc
->lut_b
[i
]);
6210 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6212 struct drm_device
*dev
= crtc
->dev
;
6213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6215 bool visible
= base
!= 0;
6218 if (intel_crtc
->cursor_visible
== visible
)
6221 cntl
= I915_READ(_CURACNTR
);
6223 /* On these chipsets we can only modify the base whilst
6224 * the cursor is disabled.
6226 I915_WRITE(_CURABASE
, base
);
6228 cntl
&= ~(CURSOR_FORMAT_MASK
);
6229 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6230 cntl
|= CURSOR_ENABLE
|
6231 CURSOR_GAMMA_ENABLE
|
6234 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6235 I915_WRITE(_CURACNTR
, cntl
);
6237 intel_crtc
->cursor_visible
= visible
;
6240 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6242 struct drm_device
*dev
= crtc
->dev
;
6243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6244 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6245 int pipe
= intel_crtc
->pipe
;
6246 bool visible
= base
!= 0;
6248 if (intel_crtc
->cursor_visible
!= visible
) {
6249 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6251 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6252 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6253 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6255 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6256 cntl
|= CURSOR_MODE_DISABLE
;
6258 I915_WRITE(CURCNTR(pipe
), cntl
);
6260 intel_crtc
->cursor_visible
= visible
;
6262 /* and commit changes on next vblank */
6263 I915_WRITE(CURBASE(pipe
), base
);
6266 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6268 struct drm_device
*dev
= crtc
->dev
;
6269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6271 int pipe
= intel_crtc
->pipe
;
6272 bool visible
= base
!= 0;
6274 if (intel_crtc
->cursor_visible
!= visible
) {
6275 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6277 cntl
&= ~CURSOR_MODE
;
6278 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6280 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6281 cntl
|= CURSOR_MODE_DISABLE
;
6283 if (IS_HASWELL(dev
))
6284 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6285 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6287 intel_crtc
->cursor_visible
= visible
;
6289 /* and commit changes on next vblank */
6290 I915_WRITE(CURBASE_IVB(pipe
), base
);
6293 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6294 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6297 struct drm_device
*dev
= crtc
->dev
;
6298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6300 int pipe
= intel_crtc
->pipe
;
6301 int x
= intel_crtc
->cursor_x
;
6302 int y
= intel_crtc
->cursor_y
;
6308 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6309 base
= intel_crtc
->cursor_addr
;
6310 if (x
> (int) crtc
->fb
->width
)
6313 if (y
> (int) crtc
->fb
->height
)
6319 if (x
+ intel_crtc
->cursor_width
< 0)
6322 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6325 pos
|= x
<< CURSOR_X_SHIFT
;
6328 if (y
+ intel_crtc
->cursor_height
< 0)
6331 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6334 pos
|= y
<< CURSOR_Y_SHIFT
;
6336 visible
= base
!= 0;
6337 if (!visible
&& !intel_crtc
->cursor_visible
)
6340 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6341 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6342 ivb_update_cursor(crtc
, base
);
6344 I915_WRITE(CURPOS(pipe
), pos
);
6345 if (IS_845G(dev
) || IS_I865G(dev
))
6346 i845_update_cursor(crtc
, base
);
6348 i9xx_update_cursor(crtc
, base
);
6352 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6353 struct drm_file
*file
,
6355 uint32_t width
, uint32_t height
)
6357 struct drm_device
*dev
= crtc
->dev
;
6358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6360 struct drm_i915_gem_object
*obj
;
6364 /* if we want to turn off the cursor ignore width and height */
6366 DRM_DEBUG_KMS("cursor off\n");
6369 mutex_lock(&dev
->struct_mutex
);
6373 /* Currently we only support 64x64 cursors */
6374 if (width
!= 64 || height
!= 64) {
6375 DRM_ERROR("we currently only support 64x64 cursors\n");
6379 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6380 if (&obj
->base
== NULL
)
6383 if (obj
->base
.size
< width
* height
* 4) {
6384 DRM_ERROR("buffer is to small\n");
6389 /* we only need to pin inside GTT if cursor is non-phy */
6390 mutex_lock(&dev
->struct_mutex
);
6391 if (!dev_priv
->info
->cursor_needs_physical
) {
6394 if (obj
->tiling_mode
) {
6395 DRM_ERROR("cursor cannot be tiled\n");
6400 /* Note that the w/a also requires 2 PTE of padding following
6401 * the bo. We currently fill all unused PTE with the shadow
6402 * page and so we should always have valid PTE following the
6403 * cursor preventing the VT-d warning.
6406 if (need_vtd_wa(dev
))
6407 alignment
= 64*1024;
6409 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6411 DRM_ERROR("failed to move cursor bo into the GTT\n");
6415 ret
= i915_gem_object_put_fence(obj
);
6417 DRM_ERROR("failed to release fence for cursor");
6421 addr
= obj
->gtt_offset
;
6423 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6424 ret
= i915_gem_attach_phys_object(dev
, obj
,
6425 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6428 DRM_ERROR("failed to attach phys object\n");
6431 addr
= obj
->phys_obj
->handle
->busaddr
;
6435 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6438 if (intel_crtc
->cursor_bo
) {
6439 if (dev_priv
->info
->cursor_needs_physical
) {
6440 if (intel_crtc
->cursor_bo
!= obj
)
6441 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6443 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6444 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6447 mutex_unlock(&dev
->struct_mutex
);
6449 intel_crtc
->cursor_addr
= addr
;
6450 intel_crtc
->cursor_bo
= obj
;
6451 intel_crtc
->cursor_width
= width
;
6452 intel_crtc
->cursor_height
= height
;
6454 intel_crtc_update_cursor(crtc
, true);
6458 i915_gem_object_unpin(obj
);
6460 mutex_unlock(&dev
->struct_mutex
);
6462 drm_gem_object_unreference_unlocked(&obj
->base
);
6466 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6470 intel_crtc
->cursor_x
= x
;
6471 intel_crtc
->cursor_y
= y
;
6473 intel_crtc_update_cursor(crtc
, true);
6478 /** Sets the color ramps on behalf of RandR */
6479 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6480 u16 blue
, int regno
)
6482 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6484 intel_crtc
->lut_r
[regno
] = red
>> 8;
6485 intel_crtc
->lut_g
[regno
] = green
>> 8;
6486 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6489 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6490 u16
*blue
, int regno
)
6492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6494 *red
= intel_crtc
->lut_r
[regno
] << 8;
6495 *green
= intel_crtc
->lut_g
[regno
] << 8;
6496 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6499 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6500 u16
*blue
, uint32_t start
, uint32_t size
)
6502 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6505 for (i
= start
; i
< end
; i
++) {
6506 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6507 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6508 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6511 intel_crtc_load_lut(crtc
);
6514 /* VESA 640x480x72Hz mode to set on the pipe */
6515 static struct drm_display_mode load_detect_mode
= {
6516 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6517 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6520 static struct drm_framebuffer
*
6521 intel_framebuffer_create(struct drm_device
*dev
,
6522 struct drm_mode_fb_cmd2
*mode_cmd
,
6523 struct drm_i915_gem_object
*obj
)
6525 struct intel_framebuffer
*intel_fb
;
6528 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6530 drm_gem_object_unreference_unlocked(&obj
->base
);
6531 return ERR_PTR(-ENOMEM
);
6534 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6536 drm_gem_object_unreference_unlocked(&obj
->base
);
6538 return ERR_PTR(ret
);
6541 return &intel_fb
->base
;
6545 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6547 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6548 return ALIGN(pitch
, 64);
6552 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6554 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6555 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6558 static struct drm_framebuffer
*
6559 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6560 struct drm_display_mode
*mode
,
6563 struct drm_i915_gem_object
*obj
;
6564 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6566 obj
= i915_gem_alloc_object(dev
,
6567 intel_framebuffer_size_for_mode(mode
, bpp
));
6569 return ERR_PTR(-ENOMEM
);
6571 mode_cmd
.width
= mode
->hdisplay
;
6572 mode_cmd
.height
= mode
->vdisplay
;
6573 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6575 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6577 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6580 static struct drm_framebuffer
*
6581 mode_fits_in_fbdev(struct drm_device
*dev
,
6582 struct drm_display_mode
*mode
)
6584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6585 struct drm_i915_gem_object
*obj
;
6586 struct drm_framebuffer
*fb
;
6588 if (dev_priv
->fbdev
== NULL
)
6591 obj
= dev_priv
->fbdev
->ifb
.obj
;
6595 fb
= &dev_priv
->fbdev
->ifb
.base
;
6596 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6597 fb
->bits_per_pixel
))
6600 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6606 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6607 struct drm_display_mode
*mode
,
6608 struct intel_load_detect_pipe
*old
)
6610 struct intel_crtc
*intel_crtc
;
6611 struct intel_encoder
*intel_encoder
=
6612 intel_attached_encoder(connector
);
6613 struct drm_crtc
*possible_crtc
;
6614 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6615 struct drm_crtc
*crtc
= NULL
;
6616 struct drm_device
*dev
= encoder
->dev
;
6617 struct drm_framebuffer
*fb
;
6620 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6621 connector
->base
.id
, drm_get_connector_name(connector
),
6622 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6625 * Algorithm gets a little messy:
6627 * - if the connector already has an assigned crtc, use it (but make
6628 * sure it's on first)
6630 * - try to find the first unused crtc that can drive this connector,
6631 * and use that if we find one
6634 /* See if we already have a CRTC for this connector */
6635 if (encoder
->crtc
) {
6636 crtc
= encoder
->crtc
;
6638 mutex_lock(&crtc
->mutex
);
6640 old
->dpms_mode
= connector
->dpms
;
6641 old
->load_detect_temp
= false;
6643 /* Make sure the crtc and connector are running */
6644 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6645 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6650 /* Find an unused one (if possible) */
6651 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6653 if (!(encoder
->possible_crtcs
& (1 << i
)))
6655 if (!possible_crtc
->enabled
) {
6656 crtc
= possible_crtc
;
6662 * If we didn't find an unused CRTC, don't use any.
6665 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6669 mutex_lock(&crtc
->mutex
);
6670 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6671 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6673 intel_crtc
= to_intel_crtc(crtc
);
6674 old
->dpms_mode
= connector
->dpms
;
6675 old
->load_detect_temp
= true;
6676 old
->release_fb
= NULL
;
6679 mode
= &load_detect_mode
;
6681 /* We need a framebuffer large enough to accommodate all accesses
6682 * that the plane may generate whilst we perform load detection.
6683 * We can not rely on the fbcon either being present (we get called
6684 * during its initialisation to detect all boot displays, or it may
6685 * not even exist) or that it is large enough to satisfy the
6688 fb
= mode_fits_in_fbdev(dev
, mode
);
6690 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6691 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6692 old
->release_fb
= fb
;
6694 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6696 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6697 mutex_unlock(&crtc
->mutex
);
6701 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6702 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6703 if (old
->release_fb
)
6704 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6705 mutex_unlock(&crtc
->mutex
);
6709 /* let the connector get through one full cycle before testing */
6710 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6714 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6715 struct intel_load_detect_pipe
*old
)
6717 struct intel_encoder
*intel_encoder
=
6718 intel_attached_encoder(connector
);
6719 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6720 struct drm_crtc
*crtc
= encoder
->crtc
;
6722 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6723 connector
->base
.id
, drm_get_connector_name(connector
),
6724 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6726 if (old
->load_detect_temp
) {
6727 to_intel_connector(connector
)->new_encoder
= NULL
;
6728 intel_encoder
->new_crtc
= NULL
;
6729 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6731 if (old
->release_fb
) {
6732 drm_framebuffer_unregister_private(old
->release_fb
);
6733 drm_framebuffer_unreference(old
->release_fb
);
6736 mutex_unlock(&crtc
->mutex
);
6740 /* Switch crtc and encoder back off if necessary */
6741 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6742 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6744 mutex_unlock(&crtc
->mutex
);
6747 /* Returns the clock of the currently programmed mode of the given pipe. */
6748 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6752 int pipe
= intel_crtc
->pipe
;
6753 u32 dpll
= I915_READ(DPLL(pipe
));
6755 intel_clock_t clock
;
6757 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6758 fp
= I915_READ(FP0(pipe
));
6760 fp
= I915_READ(FP1(pipe
));
6762 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6763 if (IS_PINEVIEW(dev
)) {
6764 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6765 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6767 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6768 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6771 if (!IS_GEN2(dev
)) {
6772 if (IS_PINEVIEW(dev
))
6773 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6774 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6776 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6777 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6779 switch (dpll
& DPLL_MODE_MASK
) {
6780 case DPLLB_MODE_DAC_SERIAL
:
6781 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6784 case DPLLB_MODE_LVDS
:
6785 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6789 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6790 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6794 /* XXX: Handle the 100Mhz refclk */
6795 intel_clock(dev
, 96000, &clock
);
6797 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6800 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6801 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6804 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6805 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6806 /* XXX: might not be 66MHz */
6807 intel_clock(dev
, 66000, &clock
);
6809 intel_clock(dev
, 48000, &clock
);
6811 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6814 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6815 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6817 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6822 intel_clock(dev
, 48000, &clock
);
6826 /* XXX: It would be nice to validate the clocks, but we can't reuse
6827 * i830PllIsValid() because it relies on the xf86_config connector
6828 * configuration being accurate, which it isn't necessarily.
6834 /** Returns the currently programmed mode of the given pipe. */
6835 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6836 struct drm_crtc
*crtc
)
6838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6840 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6841 struct drm_display_mode
*mode
;
6842 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6843 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6844 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6845 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6847 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6851 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6852 mode
->hdisplay
= (htot
& 0xffff) + 1;
6853 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6854 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6855 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6856 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6857 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6858 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6859 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6861 drm_mode_set_name(mode
);
6866 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6868 struct drm_device
*dev
= crtc
->dev
;
6869 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6871 int pipe
= intel_crtc
->pipe
;
6872 int dpll_reg
= DPLL(pipe
);
6875 if (HAS_PCH_SPLIT(dev
))
6878 if (!dev_priv
->lvds_downclock_avail
)
6881 dpll
= I915_READ(dpll_reg
);
6882 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6883 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6885 assert_panel_unlocked(dev_priv
, pipe
);
6887 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6888 I915_WRITE(dpll_reg
, dpll
);
6889 intel_wait_for_vblank(dev
, pipe
);
6891 dpll
= I915_READ(dpll_reg
);
6892 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6893 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6897 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6899 struct drm_device
*dev
= crtc
->dev
;
6900 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6903 if (HAS_PCH_SPLIT(dev
))
6906 if (!dev_priv
->lvds_downclock_avail
)
6910 * Since this is called by a timer, we should never get here in
6913 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6914 int pipe
= intel_crtc
->pipe
;
6915 int dpll_reg
= DPLL(pipe
);
6918 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6920 assert_panel_unlocked(dev_priv
, pipe
);
6922 dpll
= I915_READ(dpll_reg
);
6923 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6924 I915_WRITE(dpll_reg
, dpll
);
6925 intel_wait_for_vblank(dev
, pipe
);
6926 dpll
= I915_READ(dpll_reg
);
6927 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6928 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6933 void intel_mark_busy(struct drm_device
*dev
)
6935 i915_update_gfx_val(dev
->dev_private
);
6938 void intel_mark_idle(struct drm_device
*dev
)
6940 struct drm_crtc
*crtc
;
6942 if (!i915_powersave
)
6945 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6949 intel_decrease_pllclock(crtc
);
6953 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6955 struct drm_device
*dev
= obj
->base
.dev
;
6956 struct drm_crtc
*crtc
;
6958 if (!i915_powersave
)
6961 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6965 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6966 intel_increase_pllclock(crtc
);
6970 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6972 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6973 struct drm_device
*dev
= crtc
->dev
;
6974 struct intel_unpin_work
*work
;
6975 unsigned long flags
;
6977 spin_lock_irqsave(&dev
->event_lock
, flags
);
6978 work
= intel_crtc
->unpin_work
;
6979 intel_crtc
->unpin_work
= NULL
;
6980 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6983 cancel_work_sync(&work
->work
);
6987 drm_crtc_cleanup(crtc
);
6992 static void intel_unpin_work_fn(struct work_struct
*__work
)
6994 struct intel_unpin_work
*work
=
6995 container_of(__work
, struct intel_unpin_work
, work
);
6996 struct drm_device
*dev
= work
->crtc
->dev
;
6998 mutex_lock(&dev
->struct_mutex
);
6999 intel_unpin_fb_obj(work
->old_fb_obj
);
7000 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7001 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7003 intel_update_fbc(dev
);
7004 mutex_unlock(&dev
->struct_mutex
);
7006 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7007 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7012 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7013 struct drm_crtc
*crtc
)
7015 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7016 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7017 struct intel_unpin_work
*work
;
7018 unsigned long flags
;
7020 /* Ignore early vblank irqs */
7021 if (intel_crtc
== NULL
)
7024 spin_lock_irqsave(&dev
->event_lock
, flags
);
7025 work
= intel_crtc
->unpin_work
;
7027 /* Ensure we don't miss a work->pending update ... */
7030 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7031 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7035 /* and that the unpin work is consistent wrt ->pending. */
7038 intel_crtc
->unpin_work
= NULL
;
7041 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7043 drm_vblank_put(dev
, intel_crtc
->pipe
);
7045 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7047 wake_up_all(&dev_priv
->pending_flip_queue
);
7049 queue_work(dev_priv
->wq
, &work
->work
);
7051 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7054 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7056 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7057 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7059 do_intel_finish_page_flip(dev
, crtc
);
7062 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7064 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7065 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7067 do_intel_finish_page_flip(dev
, crtc
);
7070 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7072 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7073 struct intel_crtc
*intel_crtc
=
7074 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7075 unsigned long flags
;
7077 /* NB: An MMIO update of the plane base pointer will also
7078 * generate a page-flip completion irq, i.e. every modeset
7079 * is also accompanied by a spurious intel_prepare_page_flip().
7081 spin_lock_irqsave(&dev
->event_lock
, flags
);
7082 if (intel_crtc
->unpin_work
)
7083 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7084 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7087 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7089 /* Ensure that the work item is consistent when activating it ... */
7091 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7092 /* and that it is marked active as soon as the irq could fire. */
7096 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7097 struct drm_crtc
*crtc
,
7098 struct drm_framebuffer
*fb
,
7099 struct drm_i915_gem_object
*obj
)
7101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7102 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7104 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7107 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7111 ret
= intel_ring_begin(ring
, 6);
7115 /* Can't queue multiple flips, so wait for the previous
7116 * one to finish before executing the next.
7118 if (intel_crtc
->plane
)
7119 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7121 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7122 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7123 intel_ring_emit(ring
, MI_NOOP
);
7124 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7125 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7126 intel_ring_emit(ring
, fb
->pitches
[0]);
7127 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7128 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7130 intel_mark_page_flip_active(intel_crtc
);
7131 intel_ring_advance(ring
);
7135 intel_unpin_fb_obj(obj
);
7140 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7141 struct drm_crtc
*crtc
,
7142 struct drm_framebuffer
*fb
,
7143 struct drm_i915_gem_object
*obj
)
7145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7148 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7151 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7155 ret
= intel_ring_begin(ring
, 6);
7159 if (intel_crtc
->plane
)
7160 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7162 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7163 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7164 intel_ring_emit(ring
, MI_NOOP
);
7165 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7166 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7167 intel_ring_emit(ring
, fb
->pitches
[0]);
7168 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7169 intel_ring_emit(ring
, MI_NOOP
);
7171 intel_mark_page_flip_active(intel_crtc
);
7172 intel_ring_advance(ring
);
7176 intel_unpin_fb_obj(obj
);
7181 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7182 struct drm_crtc
*crtc
,
7183 struct drm_framebuffer
*fb
,
7184 struct drm_i915_gem_object
*obj
)
7186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7188 uint32_t pf
, pipesrc
;
7189 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7192 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7196 ret
= intel_ring_begin(ring
, 4);
7200 /* i965+ uses the linear or tiled offsets from the
7201 * Display Registers (which do not change across a page-flip)
7202 * so we need only reprogram the base address.
7204 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7205 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7206 intel_ring_emit(ring
, fb
->pitches
[0]);
7207 intel_ring_emit(ring
,
7208 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7211 /* XXX Enabling the panel-fitter across page-flip is so far
7212 * untested on non-native modes, so ignore it for now.
7213 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7216 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7217 intel_ring_emit(ring
, pf
| pipesrc
);
7219 intel_mark_page_flip_active(intel_crtc
);
7220 intel_ring_advance(ring
);
7224 intel_unpin_fb_obj(obj
);
7229 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7230 struct drm_crtc
*crtc
,
7231 struct drm_framebuffer
*fb
,
7232 struct drm_i915_gem_object
*obj
)
7234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7235 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7236 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7237 uint32_t pf
, pipesrc
;
7240 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7244 ret
= intel_ring_begin(ring
, 4);
7248 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7249 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7250 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7251 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7253 /* Contrary to the suggestions in the documentation,
7254 * "Enable Panel Fitter" does not seem to be required when page
7255 * flipping with a non-native mode, and worse causes a normal
7257 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7260 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7261 intel_ring_emit(ring
, pf
| pipesrc
);
7263 intel_mark_page_flip_active(intel_crtc
);
7264 intel_ring_advance(ring
);
7268 intel_unpin_fb_obj(obj
);
7274 * On gen7 we currently use the blit ring because (in early silicon at least)
7275 * the render ring doesn't give us interrpts for page flip completion, which
7276 * means clients will hang after the first flip is queued. Fortunately the
7277 * blit ring generates interrupts properly, so use it instead.
7279 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7280 struct drm_crtc
*crtc
,
7281 struct drm_framebuffer
*fb
,
7282 struct drm_i915_gem_object
*obj
)
7284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7285 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7286 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7287 uint32_t plane_bit
= 0;
7290 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7294 switch(intel_crtc
->plane
) {
7296 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7299 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7302 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7305 WARN_ONCE(1, "unknown plane in flip command\n");
7310 ret
= intel_ring_begin(ring
, 4);
7314 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7315 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7316 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7317 intel_ring_emit(ring
, (MI_NOOP
));
7319 intel_mark_page_flip_active(intel_crtc
);
7320 intel_ring_advance(ring
);
7324 intel_unpin_fb_obj(obj
);
7329 static int intel_default_queue_flip(struct drm_device
*dev
,
7330 struct drm_crtc
*crtc
,
7331 struct drm_framebuffer
*fb
,
7332 struct drm_i915_gem_object
*obj
)
7337 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7338 struct drm_framebuffer
*fb
,
7339 struct drm_pending_vblank_event
*event
)
7341 struct drm_device
*dev
= crtc
->dev
;
7342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7343 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7344 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7346 struct intel_unpin_work
*work
;
7347 unsigned long flags
;
7350 /* Can't change pixel format via MI display flips. */
7351 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7355 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7356 * Note that pitch changes could also affect these register.
7358 if (INTEL_INFO(dev
)->gen
> 3 &&
7359 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7360 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7363 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7367 work
->event
= event
;
7369 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7370 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7372 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7376 /* We borrow the event spin lock for protecting unpin_work */
7377 spin_lock_irqsave(&dev
->event_lock
, flags
);
7378 if (intel_crtc
->unpin_work
) {
7379 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7381 drm_vblank_put(dev
, intel_crtc
->pipe
);
7383 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7386 intel_crtc
->unpin_work
= work
;
7387 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7389 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7390 flush_workqueue(dev_priv
->wq
);
7392 ret
= i915_mutex_lock_interruptible(dev
);
7396 /* Reference the objects for the scheduled work. */
7397 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7398 drm_gem_object_reference(&obj
->base
);
7402 work
->pending_flip_obj
= obj
;
7404 work
->enable_stall_check
= true;
7406 atomic_inc(&intel_crtc
->unpin_work_count
);
7407 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7409 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7411 goto cleanup_pending
;
7413 intel_disable_fbc(dev
);
7414 intel_mark_fb_busy(obj
);
7415 mutex_unlock(&dev
->struct_mutex
);
7417 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7422 atomic_dec(&intel_crtc
->unpin_work_count
);
7424 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7425 drm_gem_object_unreference(&obj
->base
);
7426 mutex_unlock(&dev
->struct_mutex
);
7429 spin_lock_irqsave(&dev
->event_lock
, flags
);
7430 intel_crtc
->unpin_work
= NULL
;
7431 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7433 drm_vblank_put(dev
, intel_crtc
->pipe
);
7440 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7441 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7442 .load_lut
= intel_crtc_load_lut
,
7445 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7447 struct intel_encoder
*other_encoder
;
7448 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7453 list_for_each_entry(other_encoder
,
7454 &crtc
->dev
->mode_config
.encoder_list
,
7457 if (&other_encoder
->new_crtc
->base
!= crtc
||
7458 encoder
== other_encoder
)
7467 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7468 struct drm_crtc
*crtc
)
7470 struct drm_device
*dev
;
7471 struct drm_crtc
*tmp
;
7474 WARN(!crtc
, "checking null crtc?\n");
7478 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7484 if (encoder
->possible_crtcs
& crtc_mask
)
7490 * intel_modeset_update_staged_output_state
7492 * Updates the staged output configuration state, e.g. after we've read out the
7495 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7497 struct intel_encoder
*encoder
;
7498 struct intel_connector
*connector
;
7500 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7502 connector
->new_encoder
=
7503 to_intel_encoder(connector
->base
.encoder
);
7506 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7509 to_intel_crtc(encoder
->base
.crtc
);
7514 * intel_modeset_commit_output_state
7516 * This function copies the stage display pipe configuration to the real one.
7518 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7520 struct intel_encoder
*encoder
;
7521 struct intel_connector
*connector
;
7523 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7525 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7528 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7530 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7535 pipe_config_set_bpp(struct drm_crtc
*crtc
,
7536 struct drm_framebuffer
*fb
,
7537 struct intel_crtc_config
*pipe_config
)
7539 struct drm_device
*dev
= crtc
->dev
;
7540 struct drm_connector
*connector
;
7543 switch (fb
->pixel_format
) {
7545 bpp
= 8*3; /* since we go through a colormap */
7547 case DRM_FORMAT_XRGB1555
:
7548 case DRM_FORMAT_ARGB1555
:
7549 /* checked in intel_framebuffer_init already */
7550 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7552 case DRM_FORMAT_RGB565
:
7553 bpp
= 6*3; /* min is 18bpp */
7555 case DRM_FORMAT_XBGR8888
:
7556 case DRM_FORMAT_ABGR8888
:
7557 /* checked in intel_framebuffer_init already */
7558 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7560 case DRM_FORMAT_XRGB8888
:
7561 case DRM_FORMAT_ARGB8888
:
7564 case DRM_FORMAT_XRGB2101010
:
7565 case DRM_FORMAT_ARGB2101010
:
7566 case DRM_FORMAT_XBGR2101010
:
7567 case DRM_FORMAT_ABGR2101010
:
7568 /* checked in intel_framebuffer_init already */
7569 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7573 /* TODO: gen4+ supports 16 bpc floating point, too. */
7575 DRM_DEBUG_KMS("unsupported depth\n");
7579 pipe_config
->pipe_bpp
= bpp
;
7581 /* Clamp display bpp to EDID value */
7582 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7584 if (connector
->encoder
&& connector
->encoder
->crtc
!= crtc
)
7587 /* Don't use an invalid EDID bpc value */
7588 if (connector
->display_info
.bpc
&&
7589 connector
->display_info
.bpc
* 3 < bpp
) {
7590 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7591 bpp
, connector
->display_info
.bpc
*3);
7592 pipe_config
->pipe_bpp
= connector
->display_info
.bpc
*3;
7599 static struct intel_crtc_config
*
7600 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7601 struct drm_framebuffer
*fb
,
7602 struct drm_display_mode
*mode
)
7604 struct drm_device
*dev
= crtc
->dev
;
7605 struct drm_encoder_helper_funcs
*encoder_funcs
;
7606 struct intel_encoder
*encoder
;
7607 struct intel_crtc_config
*pipe_config
;
7610 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7612 return ERR_PTR(-ENOMEM
);
7614 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7615 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7617 plane_bpp
= pipe_config_set_bpp(crtc
, fb
, pipe_config
);
7621 /* Pass our mode to the connectors and the CRTC to give them a chance to
7622 * adjust it according to limitations or connector properties, and also
7623 * a chance to reject the mode entirely.
7625 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7628 if (&encoder
->new_crtc
->base
!= crtc
)
7631 if (encoder
->compute_config
) {
7632 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7633 DRM_DEBUG_KMS("Encoder config failure\n");
7640 encoder_funcs
= encoder
->base
.helper_private
;
7641 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7642 &pipe_config
->requested_mode
,
7643 &pipe_config
->adjusted_mode
))) {
7644 DRM_DEBUG_KMS("Encoder fixup failed\n");
7649 if (!(intel_crtc_compute_config(crtc
, pipe_config
))) {
7650 DRM_DEBUG_KMS("CRTC fixup failed\n");
7653 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7655 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7656 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7657 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7662 return ERR_PTR(-EINVAL
);
7665 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7666 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7668 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7669 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7671 struct intel_crtc
*intel_crtc
;
7672 struct drm_device
*dev
= crtc
->dev
;
7673 struct intel_encoder
*encoder
;
7674 struct intel_connector
*connector
;
7675 struct drm_crtc
*tmp_crtc
;
7677 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7679 /* Check which crtcs have changed outputs connected to them, these need
7680 * to be part of the prepare_pipes mask. We don't (yet) support global
7681 * modeset across multiple crtcs, so modeset_pipes will only have one
7682 * bit set at most. */
7683 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7685 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7688 if (connector
->base
.encoder
) {
7689 tmp_crtc
= connector
->base
.encoder
->crtc
;
7691 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7694 if (connector
->new_encoder
)
7696 1 << connector
->new_encoder
->new_crtc
->pipe
;
7699 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7701 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7704 if (encoder
->base
.crtc
) {
7705 tmp_crtc
= encoder
->base
.crtc
;
7707 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7710 if (encoder
->new_crtc
)
7711 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7714 /* Check for any pipes that will be fully disabled ... */
7715 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7719 /* Don't try to disable disabled crtcs. */
7720 if (!intel_crtc
->base
.enabled
)
7723 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7725 if (encoder
->new_crtc
== intel_crtc
)
7730 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7734 /* set_mode is also used to update properties on life display pipes. */
7735 intel_crtc
= to_intel_crtc(crtc
);
7737 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7740 * For simplicity do a full modeset on any pipe where the output routing
7741 * changed. We could be more clever, but that would require us to be
7742 * more careful with calling the relevant encoder->mode_set functions.
7745 *modeset_pipes
= *prepare_pipes
;
7747 /* ... and mask these out. */
7748 *modeset_pipes
&= ~(*disable_pipes
);
7749 *prepare_pipes
&= ~(*disable_pipes
);
7752 * HACK: We don't (yet) fully support global modesets. intel_set_config
7753 * obies this rule, but the modeset restore mode of
7754 * intel_modeset_setup_hw_state does not.
7756 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
7757 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
7760 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7762 struct drm_encoder
*encoder
;
7763 struct drm_device
*dev
= crtc
->dev
;
7765 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7766 if (encoder
->crtc
== crtc
)
7773 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7775 struct intel_encoder
*intel_encoder
;
7776 struct intel_crtc
*intel_crtc
;
7777 struct drm_connector
*connector
;
7779 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7781 if (!intel_encoder
->base
.crtc
)
7784 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7786 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7787 intel_encoder
->connectors_active
= false;
7790 intel_modeset_commit_output_state(dev
);
7792 /* Update computed state. */
7793 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7795 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7798 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7799 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7802 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7804 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7805 struct drm_property
*dpms_property
=
7806 dev
->mode_config
.dpms_property
;
7808 connector
->dpms
= DRM_MODE_DPMS_ON
;
7809 drm_object_property_set_value(&connector
->base
,
7813 intel_encoder
= to_intel_encoder(connector
->encoder
);
7814 intel_encoder
->connectors_active
= true;
7820 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7821 list_for_each_entry((intel_crtc), \
7822 &(dev)->mode_config.crtc_list, \
7824 if (mask & (1 <<(intel_crtc)->pipe)) \
7827 intel_pipe_config_compare(struct intel_crtc_config
*current_config
,
7828 struct intel_crtc_config
*pipe_config
)
7830 if (current_config
->has_pch_encoder
!= pipe_config
->has_pch_encoder
) {
7831 DRM_ERROR("mismatch in has_pch_encoder "
7832 "(expected %i, found %i)\n",
7833 current_config
->has_pch_encoder
,
7834 pipe_config
->has_pch_encoder
);
7842 intel_modeset_check_state(struct drm_device
*dev
)
7844 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7845 struct intel_crtc
*crtc
;
7846 struct intel_encoder
*encoder
;
7847 struct intel_connector
*connector
;
7848 struct intel_crtc_config pipe_config
;
7850 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7852 /* This also checks the encoder/connector hw state with the
7853 * ->get_hw_state callbacks. */
7854 intel_connector_check_state(connector
);
7856 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7857 "connector's staged encoder doesn't match current encoder\n");
7860 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7862 bool enabled
= false;
7863 bool active
= false;
7864 enum pipe pipe
, tracked_pipe
;
7866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7867 encoder
->base
.base
.id
,
7868 drm_get_encoder_name(&encoder
->base
));
7870 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7871 "encoder's stage crtc doesn't match current crtc\n");
7872 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7873 "encoder's active_connectors set, but no crtc\n");
7875 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7877 if (connector
->base
.encoder
!= &encoder
->base
)
7880 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7883 WARN(!!encoder
->base
.crtc
!= enabled
,
7884 "encoder's enabled state mismatch "
7885 "(expected %i, found %i)\n",
7886 !!encoder
->base
.crtc
, enabled
);
7887 WARN(active
&& !encoder
->base
.crtc
,
7888 "active encoder with no crtc\n");
7890 WARN(encoder
->connectors_active
!= active
,
7891 "encoder's computed active state doesn't match tracked active state "
7892 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7894 active
= encoder
->get_hw_state(encoder
, &pipe
);
7895 WARN(active
!= encoder
->connectors_active
,
7896 "encoder's hw state doesn't match sw tracking "
7897 "(expected %i, found %i)\n",
7898 encoder
->connectors_active
, active
);
7900 if (!encoder
->base
.crtc
)
7903 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7904 WARN(active
&& pipe
!= tracked_pipe
,
7905 "active encoder's pipe doesn't match"
7906 "(expected %i, found %i)\n",
7907 tracked_pipe
, pipe
);
7911 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7913 bool enabled
= false;
7914 bool active
= false;
7916 DRM_DEBUG_KMS("[CRTC:%d]\n",
7917 crtc
->base
.base
.id
);
7919 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7920 "active crtc, but not enabled in sw tracking\n");
7922 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7924 if (encoder
->base
.crtc
!= &crtc
->base
)
7927 if (encoder
->connectors_active
)
7930 WARN(active
!= crtc
->active
,
7931 "crtc's computed active state doesn't match tracked active state "
7932 "(expected %i, found %i)\n", active
, crtc
->active
);
7933 WARN(enabled
!= crtc
->base
.enabled
,
7934 "crtc's computed enabled state doesn't match tracked enabled state "
7935 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7937 memset(&pipe_config
, 0, sizeof(pipe_config
));
7938 active
= dev_priv
->display
.get_pipe_config(crtc
,
7940 WARN(crtc
->active
!= active
,
7941 "crtc active state doesn't match with hw state "
7942 "(expected %i, found %i)\n", crtc
->active
, active
);
7945 !intel_pipe_config_compare(&crtc
->config
, &pipe_config
),
7946 "pipe state doesn't match!\n");
7950 static int __intel_set_mode(struct drm_crtc
*crtc
,
7951 struct drm_display_mode
*mode
,
7952 int x
, int y
, struct drm_framebuffer
*fb
)
7954 struct drm_device
*dev
= crtc
->dev
;
7955 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7956 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
7957 struct intel_crtc_config
*pipe_config
= NULL
;
7958 struct intel_crtc
*intel_crtc
;
7959 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7962 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7965 saved_hwmode
= saved_mode
+ 1;
7967 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7968 &prepare_pipes
, &disable_pipes
);
7970 *saved_hwmode
= crtc
->hwmode
;
7971 *saved_mode
= crtc
->mode
;
7973 /* Hack: Because we don't (yet) support global modeset on multiple
7974 * crtcs, we don't keep track of the new mode for more than one crtc.
7975 * Hence simply check whether any bit is set in modeset_pipes in all the
7976 * pieces of code that are not yet converted to deal with mutliple crtcs
7977 * changing their mode at the same time. */
7978 if (modeset_pipes
) {
7979 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
7980 if (IS_ERR(pipe_config
)) {
7981 ret
= PTR_ERR(pipe_config
);
7988 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7989 modeset_pipes
, prepare_pipes
, disable_pipes
);
7991 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7992 intel_crtc_disable(&intel_crtc
->base
);
7994 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7995 if (intel_crtc
->base
.enabled
)
7996 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7999 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8000 * to set it here already despite that we pass it down the callchain.
8002 if (modeset_pipes
) {
8003 enum transcoder tmp
= to_intel_crtc(crtc
)->config
.cpu_transcoder
;
8005 /* mode_set/enable/disable functions rely on a correct pipe
8007 to_intel_crtc(crtc
)->config
= *pipe_config
;
8008 to_intel_crtc(crtc
)->config
.cpu_transcoder
= tmp
;
8011 /* Only after disabling all output pipelines that will be changed can we
8012 * update the the output configuration. */
8013 intel_modeset_update_state(dev
, prepare_pipes
);
8015 if (dev_priv
->display
.modeset_global_resources
)
8016 dev_priv
->display
.modeset_global_resources(dev
);
8018 /* Set up the DPLL and any encoders state that needs to adjust or depend
8021 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8022 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8028 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8029 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8030 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8032 if (modeset_pipes
) {
8033 /* Store real post-adjustment hardware mode. */
8034 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8036 /* Calculate and store various constants which
8037 * are later needed by vblank and swap-completion
8038 * timestamping. They are derived from true hwmode.
8040 drm_calc_timestamping_constants(crtc
);
8043 /* FIXME: add subpixel order */
8045 if (ret
&& crtc
->enabled
) {
8046 crtc
->hwmode
= *saved_hwmode
;
8047 crtc
->mode
= *saved_mode
;
8056 int intel_set_mode(struct drm_crtc
*crtc
,
8057 struct drm_display_mode
*mode
,
8058 int x
, int y
, struct drm_framebuffer
*fb
)
8062 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8065 intel_modeset_check_state(crtc
->dev
);
8070 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8072 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8075 #undef for_each_intel_crtc_masked
8077 static void intel_set_config_free(struct intel_set_config
*config
)
8082 kfree(config
->save_connector_encoders
);
8083 kfree(config
->save_encoder_crtcs
);
8087 static int intel_set_config_save_state(struct drm_device
*dev
,
8088 struct intel_set_config
*config
)
8090 struct drm_encoder
*encoder
;
8091 struct drm_connector
*connector
;
8094 config
->save_encoder_crtcs
=
8095 kcalloc(dev
->mode_config
.num_encoder
,
8096 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8097 if (!config
->save_encoder_crtcs
)
8100 config
->save_connector_encoders
=
8101 kcalloc(dev
->mode_config
.num_connector
,
8102 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8103 if (!config
->save_connector_encoders
)
8106 /* Copy data. Note that driver private data is not affected.
8107 * Should anything bad happen only the expected state is
8108 * restored, not the drivers personal bookkeeping.
8111 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8112 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8116 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8117 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8123 static void intel_set_config_restore_state(struct drm_device
*dev
,
8124 struct intel_set_config
*config
)
8126 struct intel_encoder
*encoder
;
8127 struct intel_connector
*connector
;
8131 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8133 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8137 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8138 connector
->new_encoder
=
8139 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8144 is_crtc_connector_off(struct drm_crtc
*crtc
, struct drm_connector
*connectors
,
8149 for (i
= 0; i
< num_connectors
; i
++)
8150 if (connectors
[i
].encoder
&&
8151 connectors
[i
].encoder
->crtc
== crtc
&&
8152 connectors
[i
].dpms
!= DRM_MODE_DPMS_ON
)
8159 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8160 struct intel_set_config
*config
)
8163 /* We should be able to check here if the fb has the same properties
8164 * and then just flip_or_move it */
8165 if (set
->connectors
!= NULL
&&
8166 is_crtc_connector_off(set
->crtc
, *set
->connectors
,
8167 set
->num_connectors
)) {
8168 config
->mode_changed
= true;
8169 } else if (set
->crtc
->fb
!= set
->fb
) {
8170 /* If we have no fb then treat it as a full mode set */
8171 if (set
->crtc
->fb
== NULL
) {
8172 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8173 config
->mode_changed
= true;
8174 } else if (set
->fb
== NULL
) {
8175 config
->mode_changed
= true;
8176 } else if (set
->fb
->pixel_format
!=
8177 set
->crtc
->fb
->pixel_format
) {
8178 config
->mode_changed
= true;
8180 config
->fb_changed
= true;
8184 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8185 config
->fb_changed
= true;
8187 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8188 DRM_DEBUG_KMS("modes are different, full mode set\n");
8189 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8190 drm_mode_debug_printmodeline(set
->mode
);
8191 config
->mode_changed
= true;
8196 intel_modeset_stage_output_state(struct drm_device
*dev
,
8197 struct drm_mode_set
*set
,
8198 struct intel_set_config
*config
)
8200 struct drm_crtc
*new_crtc
;
8201 struct intel_connector
*connector
;
8202 struct intel_encoder
*encoder
;
8205 /* The upper layers ensure that we either disable a crtc or have a list
8206 * of connectors. For paranoia, double-check this. */
8207 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8208 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8211 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8213 /* Otherwise traverse passed in connector list and get encoders
8215 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8216 if (set
->connectors
[ro
] == &connector
->base
) {
8217 connector
->new_encoder
= connector
->encoder
;
8222 /* If we disable the crtc, disable all its connectors. Also, if
8223 * the connector is on the changing crtc but not on the new
8224 * connector list, disable it. */
8225 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8226 connector
->base
.encoder
&&
8227 connector
->base
.encoder
->crtc
== set
->crtc
) {
8228 connector
->new_encoder
= NULL
;
8230 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8231 connector
->base
.base
.id
,
8232 drm_get_connector_name(&connector
->base
));
8236 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8237 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8238 config
->mode_changed
= true;
8241 /* connector->new_encoder is now updated for all connectors. */
8243 /* Update crtc of enabled connectors. */
8245 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8247 if (!connector
->new_encoder
)
8250 new_crtc
= connector
->new_encoder
->base
.crtc
;
8252 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8253 if (set
->connectors
[ro
] == &connector
->base
)
8254 new_crtc
= set
->crtc
;
8257 /* Make sure the new CRTC will work with the encoder */
8258 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8262 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8264 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8265 connector
->base
.base
.id
,
8266 drm_get_connector_name(&connector
->base
),
8270 /* Check for any encoders that needs to be disabled. */
8271 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8273 list_for_each_entry(connector
,
8274 &dev
->mode_config
.connector_list
,
8276 if (connector
->new_encoder
== encoder
) {
8277 WARN_ON(!connector
->new_encoder
->new_crtc
);
8282 encoder
->new_crtc
= NULL
;
8284 /* Only now check for crtc changes so we don't miss encoders
8285 * that will be disabled. */
8286 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8287 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8288 config
->mode_changed
= true;
8291 /* Now we've also updated encoder->new_crtc for all encoders. */
8296 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8298 struct drm_device
*dev
;
8299 struct drm_mode_set save_set
;
8300 struct intel_set_config
*config
;
8305 BUG_ON(!set
->crtc
->helper_private
);
8307 /* Enforce sane interface api - has been abused by the fb helper. */
8308 BUG_ON(!set
->mode
&& set
->fb
);
8309 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8312 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8313 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8314 (int)set
->num_connectors
, set
->x
, set
->y
);
8316 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8319 dev
= set
->crtc
->dev
;
8322 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8326 ret
= intel_set_config_save_state(dev
, config
);
8330 save_set
.crtc
= set
->crtc
;
8331 save_set
.mode
= &set
->crtc
->mode
;
8332 save_set
.x
= set
->crtc
->x
;
8333 save_set
.y
= set
->crtc
->y
;
8334 save_set
.fb
= set
->crtc
->fb
;
8336 /* Compute whether we need a full modeset, only an fb base update or no
8337 * change at all. In the future we might also check whether only the
8338 * mode changed, e.g. for LVDS where we only change the panel fitter in
8340 intel_set_config_compute_mode_changes(set
, config
);
8342 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8346 if (config
->mode_changed
) {
8348 DRM_DEBUG_KMS("attempting to set mode from"
8350 drm_mode_debug_printmodeline(set
->mode
);
8353 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8354 set
->x
, set
->y
, set
->fb
);
8355 } else if (config
->fb_changed
) {
8356 intel_crtc_wait_for_pending_flips(set
->crtc
);
8358 ret
= intel_pipe_set_base(set
->crtc
,
8359 set
->x
, set
->y
, set
->fb
);
8363 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8364 set
->crtc
->base
.id
, ret
);
8366 intel_set_config_restore_state(dev
, config
);
8368 /* Try to restore the config */
8369 if (config
->mode_changed
&&
8370 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8371 save_set
.x
, save_set
.y
, save_set
.fb
))
8372 DRM_ERROR("failed to restore config after modeset failure\n");
8376 intel_set_config_free(config
);
8380 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8381 .cursor_set
= intel_crtc_cursor_set
,
8382 .cursor_move
= intel_crtc_cursor_move
,
8383 .gamma_set
= intel_crtc_gamma_set
,
8384 .set_config
= intel_crtc_set_config
,
8385 .destroy
= intel_crtc_destroy
,
8386 .page_flip
= intel_crtc_page_flip
,
8389 static void intel_cpu_pll_init(struct drm_device
*dev
)
8392 intel_ddi_pll_init(dev
);
8395 static void intel_pch_pll_init(struct drm_device
*dev
)
8397 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8400 if (dev_priv
->num_pch_pll
== 0) {
8401 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8405 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8406 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8407 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8408 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8412 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8414 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8415 struct intel_crtc
*intel_crtc
;
8418 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8419 if (intel_crtc
== NULL
)
8422 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8424 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8425 for (i
= 0; i
< 256; i
++) {
8426 intel_crtc
->lut_r
[i
] = i
;
8427 intel_crtc
->lut_g
[i
] = i
;
8428 intel_crtc
->lut_b
[i
] = i
;
8431 /* Swap pipes & planes for FBC on pre-965 */
8432 intel_crtc
->pipe
= pipe
;
8433 intel_crtc
->plane
= pipe
;
8434 intel_crtc
->config
.cpu_transcoder
= pipe
;
8435 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8436 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8437 intel_crtc
->plane
= !pipe
;
8440 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8441 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8442 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8443 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8445 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8448 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8449 struct drm_file
*file
)
8451 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8452 struct drm_mode_object
*drmmode_obj
;
8453 struct intel_crtc
*crtc
;
8455 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8458 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8459 DRM_MODE_OBJECT_CRTC
);
8462 DRM_ERROR("no such CRTC id\n");
8466 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8467 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8472 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8474 struct drm_device
*dev
= encoder
->base
.dev
;
8475 struct intel_encoder
*source_encoder
;
8479 list_for_each_entry(source_encoder
,
8480 &dev
->mode_config
.encoder_list
, base
.head
) {
8482 if (encoder
== source_encoder
)
8483 index_mask
|= (1 << entry
);
8485 /* Intel hw has only one MUX where enocoders could be cloned. */
8486 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8487 index_mask
|= (1 << entry
);
8495 static bool has_edp_a(struct drm_device
*dev
)
8497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8499 if (!IS_MOBILE(dev
))
8502 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8506 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8512 static void intel_setup_outputs(struct drm_device
*dev
)
8514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8515 struct intel_encoder
*encoder
;
8516 bool dpd_is_edp
= false;
8519 has_lvds
= intel_lvds_init(dev
);
8520 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8521 /* disable the panel fitter on everything but LVDS */
8522 I915_WRITE(PFIT_CONTROL
, 0);
8526 intel_crt_init(dev
);
8531 /* Haswell uses DDI functions to detect digital outputs */
8532 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8533 /* DDI A only supports eDP */
8535 intel_ddi_init(dev
, PORT_A
);
8537 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8539 found
= I915_READ(SFUSE_STRAP
);
8541 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8542 intel_ddi_init(dev
, PORT_B
);
8543 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8544 intel_ddi_init(dev
, PORT_C
);
8545 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8546 intel_ddi_init(dev
, PORT_D
);
8547 } else if (HAS_PCH_SPLIT(dev
)) {
8549 dpd_is_edp
= intel_dpd_is_edp(dev
);
8552 intel_dp_init(dev
, DP_A
, PORT_A
);
8554 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8555 /* PCH SDVOB multiplex with HDMIB */
8556 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8558 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8559 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8560 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8563 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8564 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8566 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8567 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8569 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8570 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8572 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8573 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8574 } else if (IS_VALLEYVIEW(dev
)) {
8575 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8576 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8577 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8579 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8580 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8582 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8583 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8585 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8588 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8589 DRM_DEBUG_KMS("probing SDVOB\n");
8590 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8591 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8592 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8593 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8596 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8597 DRM_DEBUG_KMS("probing DP_B\n");
8598 intel_dp_init(dev
, DP_B
, PORT_B
);
8602 /* Before G4X SDVOC doesn't have its own detect register */
8604 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8605 DRM_DEBUG_KMS("probing SDVOC\n");
8606 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8609 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8611 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8612 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8613 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8615 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8616 DRM_DEBUG_KMS("probing DP_C\n");
8617 intel_dp_init(dev
, DP_C
, PORT_C
);
8621 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8622 (I915_READ(DP_D
) & DP_DETECTED
)) {
8623 DRM_DEBUG_KMS("probing DP_D\n");
8624 intel_dp_init(dev
, DP_D
, PORT_D
);
8626 } else if (IS_GEN2(dev
))
8627 intel_dvo_init(dev
);
8629 if (SUPPORTS_TV(dev
))
8632 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8633 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8634 encoder
->base
.possible_clones
=
8635 intel_encoder_clones(encoder
);
8638 intel_init_pch_refclk(dev
);
8640 drm_helper_move_panel_connectors_to_head(dev
);
8643 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8645 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8647 drm_framebuffer_cleanup(fb
);
8648 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8653 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8654 struct drm_file
*file
,
8655 unsigned int *handle
)
8657 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8658 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8660 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8663 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8664 .destroy
= intel_user_framebuffer_destroy
,
8665 .create_handle
= intel_user_framebuffer_create_handle
,
8668 int intel_framebuffer_init(struct drm_device
*dev
,
8669 struct intel_framebuffer
*intel_fb
,
8670 struct drm_mode_fb_cmd2
*mode_cmd
,
8671 struct drm_i915_gem_object
*obj
)
8675 if (obj
->tiling_mode
== I915_TILING_Y
) {
8676 DRM_DEBUG("hardware does not support tiling Y\n");
8680 if (mode_cmd
->pitches
[0] & 63) {
8681 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8682 mode_cmd
->pitches
[0]);
8686 /* FIXME <= Gen4 stride limits are bit unclear */
8687 if (mode_cmd
->pitches
[0] > 32768) {
8688 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8689 mode_cmd
->pitches
[0]);
8693 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8694 mode_cmd
->pitches
[0] != obj
->stride
) {
8695 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8696 mode_cmd
->pitches
[0], obj
->stride
);
8700 /* Reject formats not supported by any plane early. */
8701 switch (mode_cmd
->pixel_format
) {
8703 case DRM_FORMAT_RGB565
:
8704 case DRM_FORMAT_XRGB8888
:
8705 case DRM_FORMAT_ARGB8888
:
8707 case DRM_FORMAT_XRGB1555
:
8708 case DRM_FORMAT_ARGB1555
:
8709 if (INTEL_INFO(dev
)->gen
> 3) {
8710 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8714 case DRM_FORMAT_XBGR8888
:
8715 case DRM_FORMAT_ABGR8888
:
8716 case DRM_FORMAT_XRGB2101010
:
8717 case DRM_FORMAT_ARGB2101010
:
8718 case DRM_FORMAT_XBGR2101010
:
8719 case DRM_FORMAT_ABGR2101010
:
8720 if (INTEL_INFO(dev
)->gen
< 4) {
8721 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8725 case DRM_FORMAT_YUYV
:
8726 case DRM_FORMAT_UYVY
:
8727 case DRM_FORMAT_YVYU
:
8728 case DRM_FORMAT_VYUY
:
8729 if (INTEL_INFO(dev
)->gen
< 5) {
8730 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8735 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8739 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8740 if (mode_cmd
->offsets
[0] != 0)
8743 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8744 intel_fb
->obj
= obj
;
8746 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8748 DRM_ERROR("framebuffer init failed %d\n", ret
);
8755 static struct drm_framebuffer
*
8756 intel_user_framebuffer_create(struct drm_device
*dev
,
8757 struct drm_file
*filp
,
8758 struct drm_mode_fb_cmd2
*mode_cmd
)
8760 struct drm_i915_gem_object
*obj
;
8762 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8763 mode_cmd
->handles
[0]));
8764 if (&obj
->base
== NULL
)
8765 return ERR_PTR(-ENOENT
);
8767 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8770 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8771 .fb_create
= intel_user_framebuffer_create
,
8772 .output_poll_changed
= intel_fb_output_poll_changed
,
8775 /* Set up chip specific display functions */
8776 static void intel_init_display(struct drm_device
*dev
)
8778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8781 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
8782 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8783 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8784 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8785 dev_priv
->display
.off
= haswell_crtc_off
;
8786 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8787 } else if (HAS_PCH_SPLIT(dev
)) {
8788 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
8789 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8790 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8791 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8792 dev_priv
->display
.off
= ironlake_crtc_off
;
8793 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8795 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
8796 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8797 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8798 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8799 dev_priv
->display
.off
= i9xx_crtc_off
;
8800 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8803 /* Returns the core display clock speed */
8804 if (IS_VALLEYVIEW(dev
))
8805 dev_priv
->display
.get_display_clock_speed
=
8806 valleyview_get_display_clock_speed
;
8807 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8808 dev_priv
->display
.get_display_clock_speed
=
8809 i945_get_display_clock_speed
;
8810 else if (IS_I915G(dev
))
8811 dev_priv
->display
.get_display_clock_speed
=
8812 i915_get_display_clock_speed
;
8813 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8814 dev_priv
->display
.get_display_clock_speed
=
8815 i9xx_misc_get_display_clock_speed
;
8816 else if (IS_I915GM(dev
))
8817 dev_priv
->display
.get_display_clock_speed
=
8818 i915gm_get_display_clock_speed
;
8819 else if (IS_I865G(dev
))
8820 dev_priv
->display
.get_display_clock_speed
=
8821 i865_get_display_clock_speed
;
8822 else if (IS_I85X(dev
))
8823 dev_priv
->display
.get_display_clock_speed
=
8824 i855_get_display_clock_speed
;
8826 dev_priv
->display
.get_display_clock_speed
=
8827 i830_get_display_clock_speed
;
8829 if (HAS_PCH_SPLIT(dev
)) {
8831 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8832 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8833 } else if (IS_GEN6(dev
)) {
8834 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8835 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8836 } else if (IS_IVYBRIDGE(dev
)) {
8837 /* FIXME: detect B0+ stepping and use auto training */
8838 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8839 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8840 dev_priv
->display
.modeset_global_resources
=
8841 ivb_modeset_global_resources
;
8842 } else if (IS_HASWELL(dev
)) {
8843 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8844 dev_priv
->display
.write_eld
= haswell_write_eld
;
8845 dev_priv
->display
.modeset_global_resources
=
8846 haswell_modeset_global_resources
;
8848 } else if (IS_G4X(dev
)) {
8849 dev_priv
->display
.write_eld
= g4x_write_eld
;
8852 /* Default just returns -ENODEV to indicate unsupported */
8853 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8855 switch (INTEL_INFO(dev
)->gen
) {
8857 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8861 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8866 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8870 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8873 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8879 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8880 * resume, or other times. This quirk makes sure that's the case for
8883 static void quirk_pipea_force(struct drm_device
*dev
)
8885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8887 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8888 DRM_INFO("applying pipe a force quirk\n");
8892 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8894 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8897 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8898 DRM_INFO("applying lvds SSC disable quirk\n");
8902 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8905 static void quirk_invert_brightness(struct drm_device
*dev
)
8907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8908 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8909 DRM_INFO("applying inverted panel brightness quirk\n");
8912 struct intel_quirk
{
8914 int subsystem_vendor
;
8915 int subsystem_device
;
8916 void (*hook
)(struct drm_device
*dev
);
8919 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8920 struct intel_dmi_quirk
{
8921 void (*hook
)(struct drm_device
*dev
);
8922 const struct dmi_system_id (*dmi_id_list
)[];
8925 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8927 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8931 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8933 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8935 .callback
= intel_dmi_reverse_brightness
,
8936 .ident
= "NCR Corporation",
8937 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8938 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8941 { } /* terminating entry */
8943 .hook
= quirk_invert_brightness
,
8947 static struct intel_quirk intel_quirks
[] = {
8948 /* HP Mini needs pipe A force quirk (LP: #322104) */
8949 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8951 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8952 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8954 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8955 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8957 /* 830/845 need to leave pipe A & dpll A up */
8958 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8959 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8961 /* Lenovo U160 cannot use SSC on LVDS */
8962 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8964 /* Sony Vaio Y cannot use SSC on LVDS */
8965 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8967 /* Acer Aspire 5734Z must invert backlight brightness */
8968 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8970 /* Acer/eMachines G725 */
8971 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
8973 /* Acer/eMachines e725 */
8974 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
8976 /* Acer/Packard Bell NCL20 */
8977 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
8979 /* Acer Aspire 4736Z */
8980 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
8983 static void intel_init_quirks(struct drm_device
*dev
)
8985 struct pci_dev
*d
= dev
->pdev
;
8988 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8989 struct intel_quirk
*q
= &intel_quirks
[i
];
8991 if (d
->device
== q
->device
&&
8992 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8993 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8994 (d
->subsystem_device
== q
->subsystem_device
||
8995 q
->subsystem_device
== PCI_ANY_ID
))
8998 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8999 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9000 intel_dmi_quirks
[i
].hook(dev
);
9004 /* Disable the VGA plane that we never use */
9005 static void i915_disable_vga(struct drm_device
*dev
)
9007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9009 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9011 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9012 outb(SR01
, VGA_SR_INDEX
);
9013 sr1
= inb(VGA_SR_DATA
);
9014 outb(sr1
| 1<<5, VGA_SR_DATA
);
9015 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9018 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9019 POSTING_READ(vga_reg
);
9022 void intel_modeset_init_hw(struct drm_device
*dev
)
9024 intel_init_power_well(dev
);
9026 intel_prepare_ddi(dev
);
9028 intel_init_clock_gating(dev
);
9030 mutex_lock(&dev
->struct_mutex
);
9031 intel_enable_gt_powersave(dev
);
9032 mutex_unlock(&dev
->struct_mutex
);
9035 void intel_modeset_init(struct drm_device
*dev
)
9037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9040 drm_mode_config_init(dev
);
9042 dev
->mode_config
.min_width
= 0;
9043 dev
->mode_config
.min_height
= 0;
9045 dev
->mode_config
.preferred_depth
= 24;
9046 dev
->mode_config
.prefer_shadow
= 1;
9048 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9050 intel_init_quirks(dev
);
9054 if (INTEL_INFO(dev
)->num_pipes
== 0)
9057 intel_init_display(dev
);
9060 dev
->mode_config
.max_width
= 2048;
9061 dev
->mode_config
.max_height
= 2048;
9062 } else if (IS_GEN3(dev
)) {
9063 dev
->mode_config
.max_width
= 4096;
9064 dev
->mode_config
.max_height
= 4096;
9066 dev
->mode_config
.max_width
= 8192;
9067 dev
->mode_config
.max_height
= 8192;
9069 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9071 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9072 INTEL_INFO(dev
)->num_pipes
,
9073 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9075 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
9076 intel_crtc_init(dev
, i
);
9077 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9078 ret
= intel_plane_init(dev
, i
, j
);
9080 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9085 intel_cpu_pll_init(dev
);
9086 intel_pch_pll_init(dev
);
9088 /* Just disable it once at startup */
9089 i915_disable_vga(dev
);
9090 intel_setup_outputs(dev
);
9092 /* Just in case the BIOS is doing something questionable. */
9093 intel_disable_fbc(dev
);
9097 intel_connector_break_all_links(struct intel_connector
*connector
)
9099 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9100 connector
->base
.encoder
= NULL
;
9101 connector
->encoder
->connectors_active
= false;
9102 connector
->encoder
->base
.crtc
= NULL
;
9105 static void intel_enable_pipe_a(struct drm_device
*dev
)
9107 struct intel_connector
*connector
;
9108 struct drm_connector
*crt
= NULL
;
9109 struct intel_load_detect_pipe load_detect_temp
;
9111 /* We can't just switch on the pipe A, we need to set things up with a
9112 * proper mode and output configuration. As a gross hack, enable pipe A
9113 * by enabling the load detect pipe once. */
9114 list_for_each_entry(connector
,
9115 &dev
->mode_config
.connector_list
,
9117 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9118 crt
= &connector
->base
;
9126 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9127 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9133 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9135 struct drm_device
*dev
= crtc
->base
.dev
;
9136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9139 if (INTEL_INFO(dev
)->num_pipes
== 1)
9142 reg
= DSPCNTR(!crtc
->plane
);
9143 val
= I915_READ(reg
);
9145 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9146 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9152 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9154 struct drm_device
*dev
= crtc
->base
.dev
;
9155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9158 /* Clear any frame start delays used for debugging left by the BIOS */
9159 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
9160 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9162 /* We need to sanitize the plane -> pipe mapping first because this will
9163 * disable the crtc (and hence change the state) if it is wrong. Note
9164 * that gen4+ has a fixed plane -> pipe mapping. */
9165 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9166 struct intel_connector
*connector
;
9169 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9170 crtc
->base
.base
.id
);
9172 /* Pipe has the wrong plane attached and the plane is active.
9173 * Temporarily change the plane mapping and disable everything
9175 plane
= crtc
->plane
;
9176 crtc
->plane
= !plane
;
9177 dev_priv
->display
.crtc_disable(&crtc
->base
);
9178 crtc
->plane
= plane
;
9180 /* ... and break all links. */
9181 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9183 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9186 intel_connector_break_all_links(connector
);
9189 WARN_ON(crtc
->active
);
9190 crtc
->base
.enabled
= false;
9193 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9194 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9195 /* BIOS forgot to enable pipe A, this mostly happens after
9196 * resume. Force-enable the pipe to fix this, the update_dpms
9197 * call below we restore the pipe to the right state, but leave
9198 * the required bits on. */
9199 intel_enable_pipe_a(dev
);
9202 /* Adjust the state of the output pipe according to whether we
9203 * have active connectors/encoders. */
9204 intel_crtc_update_dpms(&crtc
->base
);
9206 if (crtc
->active
!= crtc
->base
.enabled
) {
9207 struct intel_encoder
*encoder
;
9209 /* This can happen either due to bugs in the get_hw_state
9210 * functions or because the pipe is force-enabled due to the
9212 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9214 crtc
->base
.enabled
? "enabled" : "disabled",
9215 crtc
->active
? "enabled" : "disabled");
9217 crtc
->base
.enabled
= crtc
->active
;
9219 /* Because we only establish the connector -> encoder ->
9220 * crtc links if something is active, this means the
9221 * crtc is now deactivated. Break the links. connector
9222 * -> encoder links are only establish when things are
9223 * actually up, hence no need to break them. */
9224 WARN_ON(crtc
->active
);
9226 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9227 WARN_ON(encoder
->connectors_active
);
9228 encoder
->base
.crtc
= NULL
;
9233 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9235 struct intel_connector
*connector
;
9236 struct drm_device
*dev
= encoder
->base
.dev
;
9238 /* We need to check both for a crtc link (meaning that the
9239 * encoder is active and trying to read from a pipe) and the
9240 * pipe itself being active. */
9241 bool has_active_crtc
= encoder
->base
.crtc
&&
9242 to_intel_crtc(encoder
->base
.crtc
)->active
;
9244 if (encoder
->connectors_active
&& !has_active_crtc
) {
9245 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9246 encoder
->base
.base
.id
,
9247 drm_get_encoder_name(&encoder
->base
));
9249 /* Connector is active, but has no active pipe. This is
9250 * fallout from our resume register restoring. Disable
9251 * the encoder manually again. */
9252 if (encoder
->base
.crtc
) {
9253 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9254 encoder
->base
.base
.id
,
9255 drm_get_encoder_name(&encoder
->base
));
9256 encoder
->disable(encoder
);
9259 /* Inconsistent output/port/pipe state happens presumably due to
9260 * a bug in one of the get_hw_state functions. Or someplace else
9261 * in our code, like the register restore mess on resume. Clamp
9262 * things to off as a safer default. */
9263 list_for_each_entry(connector
,
9264 &dev
->mode_config
.connector_list
,
9266 if (connector
->encoder
!= encoder
)
9269 intel_connector_break_all_links(connector
);
9272 /* Enabled encoders without active connectors will be fixed in
9273 * the crtc fixup. */
9276 void i915_redisable_vga(struct drm_device
*dev
)
9278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9279 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9281 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9282 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9283 i915_disable_vga(dev
);
9287 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9288 * and i915 state tracking structures. */
9289 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9295 struct drm_plane
*plane
;
9296 struct intel_crtc
*crtc
;
9297 struct intel_encoder
*encoder
;
9298 struct intel_connector
*connector
;
9301 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9303 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9304 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9305 case TRANS_DDI_EDP_INPUT_A_ON
:
9306 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9309 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9312 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9316 /* A bogus value has been programmed, disable
9318 WARN(1, "Bogus eDP source %08x\n", tmp
);
9319 intel_ddi_disable_transcoder_func(dev_priv
,
9324 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9325 crtc
->config
.cpu_transcoder
= TRANSCODER_EDP
;
9327 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9333 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9335 enum transcoder tmp
= crtc
->config
.cpu_transcoder
;
9336 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9337 crtc
->config
.cpu_transcoder
= tmp
;
9339 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9342 crtc
->base
.enabled
= crtc
->active
;
9344 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9346 crtc
->active
? "enabled" : "disabled");
9350 intel_ddi_setup_hw_pll_state(dev
);
9352 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9356 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9357 encoder
->base
.crtc
=
9358 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9360 encoder
->base
.crtc
= NULL
;
9363 encoder
->connectors_active
= false;
9364 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9365 encoder
->base
.base
.id
,
9366 drm_get_encoder_name(&encoder
->base
),
9367 encoder
->base
.crtc
? "enabled" : "disabled",
9371 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9373 if (connector
->get_hw_state(connector
)) {
9374 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9375 connector
->encoder
->connectors_active
= true;
9376 connector
->base
.encoder
= &connector
->encoder
->base
;
9378 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9379 connector
->base
.encoder
= NULL
;
9381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9382 connector
->base
.base
.id
,
9383 drm_get_connector_name(&connector
->base
),
9384 connector
->base
.encoder
? "enabled" : "disabled");
9387 /* HW state is read out, now we need to sanitize this mess. */
9388 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9390 intel_sanitize_encoder(encoder
);
9393 for_each_pipe(pipe
) {
9394 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9395 intel_sanitize_crtc(crtc
);
9398 if (force_restore
) {
9400 * We need to use raw interfaces for restoring state to avoid
9401 * checking (bogus) intermediate states.
9403 for_each_pipe(pipe
) {
9404 struct drm_crtc
*crtc
=
9405 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9407 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
9410 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9411 intel_plane_restore(plane
);
9413 i915_redisable_vga(dev
);
9415 intel_modeset_update_staged_output_state(dev
);
9418 intel_modeset_check_state(dev
);
9420 drm_mode_config_reset(dev
);
9423 void intel_modeset_gem_init(struct drm_device
*dev
)
9425 intel_modeset_init_hw(dev
);
9427 intel_setup_overlay(dev
);
9429 intel_modeset_setup_hw_state(dev
, false);
9432 void intel_modeset_cleanup(struct drm_device
*dev
)
9434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9435 struct drm_crtc
*crtc
;
9436 struct intel_crtc
*intel_crtc
;
9438 drm_kms_helper_poll_fini(dev
);
9439 mutex_lock(&dev
->struct_mutex
);
9441 intel_unregister_dsm_handler();
9444 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9445 /* Skip inactive CRTCs */
9449 intel_crtc
= to_intel_crtc(crtc
);
9450 intel_increase_pllclock(crtc
);
9453 intel_disable_fbc(dev
);
9455 intel_disable_gt_powersave(dev
);
9457 ironlake_teardown_rc6(dev
);
9459 if (IS_VALLEYVIEW(dev
))
9462 mutex_unlock(&dev
->struct_mutex
);
9464 /* Disable the irq before mode object teardown, for the irq might
9465 * enqueue unpin/hotplug work. */
9466 drm_irq_uninstall(dev
);
9467 cancel_work_sync(&dev_priv
->hotplug_work
);
9468 cancel_work_sync(&dev_priv
->rps
.work
);
9470 /* flush any delayed tasks or pending work */
9471 flush_scheduled_work();
9473 /* destroy backlight, if any, before the connectors */
9474 intel_panel_destroy_backlight(dev
);
9476 drm_mode_config_cleanup(dev
);
9478 intel_cleanup_overlay(dev
);
9482 * Return which encoder is currently attached for connector.
9484 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9486 return &intel_attached_encoder(connector
)->base
;
9489 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9490 struct intel_encoder
*encoder
)
9492 connector
->encoder
= encoder
;
9493 drm_mode_connector_attach_encoder(&connector
->base
,
9498 * set vga decode state - true == enable VGA decode
9500 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9505 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9507 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9509 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9510 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9514 #ifdef CONFIG_DEBUG_FS
9515 #include <linux/seq_file.h>
9517 struct intel_display_error_state
{
9518 struct intel_cursor_error_state
{
9523 } cursor
[I915_MAX_PIPES
];
9525 struct intel_pipe_error_state
{
9535 } pipe
[I915_MAX_PIPES
];
9537 struct intel_plane_error_state
{
9545 } plane
[I915_MAX_PIPES
];
9548 struct intel_display_error_state
*
9549 intel_display_capture_error_state(struct drm_device
*dev
)
9551 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9552 struct intel_display_error_state
*error
;
9553 enum transcoder cpu_transcoder
;
9556 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9561 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9563 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9564 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9565 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9566 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9568 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9569 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9570 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9573 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9574 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9575 if (INTEL_INFO(dev
)->gen
<= 3) {
9576 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9577 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9579 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9580 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9581 if (INTEL_INFO(dev
)->gen
>= 4) {
9582 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9583 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9586 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9587 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9588 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9589 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9590 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9591 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9592 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9593 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9600 intel_display_print_error_state(struct seq_file
*m
,
9601 struct drm_device
*dev
,
9602 struct intel_display_error_state
*error
)
9606 seq_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9608 seq_printf(m
, "Pipe [%d]:\n", i
);
9609 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9610 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9611 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9612 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9613 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9614 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9615 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9616 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9618 seq_printf(m
, "Plane [%d]:\n", i
);
9619 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9620 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9621 if (INTEL_INFO(dev
)->gen
<= 3) {
9622 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9623 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9625 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9626 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9627 if (INTEL_INFO(dev
)->gen
>= 4) {
9628 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9629 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9632 seq_printf(m
, "Cursor [%d]:\n", i
);
9633 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9634 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9635 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);